Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device. According to the method for manufacturing a semiconductor device of the present invention, a damascene structure can be realized by forming a first etch stop layer, a first target dielectric layer, a second etch stop layer, and a second target dielectric layer on a semiconductor substrate; and a first hard mask layer and a second mask layer stacked with different opening sizes on the second target dielectric layer. According to the method of the present invention, only one photolithography process is required to realize the dual damascene structure in the dual damascene process, without the need for expensive photolithography equipment support, and the equipment cost is lower; the formed damascene structure is easy to fill, and seamless filling can be achieved; at the same time, the method for manufacturing a semiconductor device of the present invention has wide applicability and can also be used for etching conventional through holes, and has a broader application prospect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] In the metal interconnect strategy of semiconductor IC manufacturing, copper is used as the primary chip interconnect conductor. Because copper is difficult to etch, early researchers engaged in copper etching were forced to consider alternative methods to produce metal lines. The dual damascene method became the consensus method for copper metallization.

[0003] Compared to traditional aluminum interconnect processes, the dual damascene method, in addition to using a metal line interconnect trench process, also employs a metal inlay process to connect two lines together, using contact holes or vias. This means that both the vias and the metal lines are filled simultaneously, saving process steps and eliminating the interface between the vias and the metal lines. Consequently, the dual damascene method reduces process steps by 0% to 30%. 2 The dual damascene method not only has fewer manufacturing steps but also eliminates or reduces the most difficult steps in traditional aluminum interconnect metallization: aluminum etching and numerous chemical mechanical polishing steps for tungsten and dielectric materials.

[0004] There are two types of dual damascene processes: via first, trench last (Via First, Trench Last) and trench first, via last (Trench First, Via Last). Both processes require two or more coats of photoresist, exposure, and dry etching to achieve their desired results. The difference in CD between the two photolithography steps results in the formation of trench or via patterns. The need for multiple coats of photoresist, exposure, and other processes results in a high process cost. Furthermore, multiple exposures are required on the same film layer, placing high demands on the performance of the photolithography machine. Consequently, the cost of the photoresist is also high. Furthermore, the second coat of photoresist currently has a certain step, resulting in defects such as unclean development. Exposure and development require sufficient windows to address these defects, and problems such as a small process window are also prominent.

[0005] In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device. Summary of the Invention

[0006] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0008] providing a semiconductor substrate;

[0009] forming a first etch stop layer, a first target dielectric layer, a second etch stop layer, and a second target dielectric layer in sequence on the semiconductor substrate;

[0010] forming a first hard mask layer and a patterned second mask layer in sequence on the second target dielectric layer, wherein the second mask layer has a first opening, and the first opening exposes a portion of the first hard mask layer;

[0011] Etching the first hard mask layer using the second mask layer as a mask to form a second opening in the first hard mask layer, wherein the second opening exposes a portion of the second target dielectric layer and is larger than the first opening;

[0012] etching the second target dielectric layer using the second mask layer as a mask to form a third opening in the second target dielectric layer, wherein the third opening exposes a portion of the second etch stop layer;

[0013] etching the second etch stop layer using the second mask layer as a mask to form a fourth opening in the first etch stop layer, wherein the fourth opening exposes a portion of the first target dielectric layer;

[0014] removing the second mask layer;

[0015] Using the first hard mask layer as a mask, etching the first target dielectric layer and the second target dielectric layer to form a fifth opening in the first target dielectric layer and expanding the third opening into a sixth opening;

[0016] Using the first hard mask layer as a mask, the second etch stop layer and the first etch stop layer are etched to form a seventh opening in the first etch stop layer, and the fourth opening is expanded into an eighth opening, wherein a size of the eighth opening is equal to a size of the sixth opening.

[0017] Illustratively, the method of etching the first hard mask layer using the second mask layer as a mask includes using a dry etching process to retreat the first hard mask layer to form the second opening.

[0018] Exemplarily, the first hard mask layer includes a polysilicon layer.

[0019] Exemplarily, in the step of using a dry etching process to make the first hard mask layer retreat to form the second opening, the etching gas of the dry etching process includes SF6, O2 and CF4, the flow adjustment range of SF6 is 15 to 40 sccm, the flow adjustment range of O2 is 5 to 55 sccm, the flow adjustment range of CF4 is 10 to 30 sccm, the process pressure range of the dry etching process is 10 to 20 mT, the upper RF source power range of the dry etching process is 300 to 500 W, and the lower RF source power adjustment range of the dry etching process is 30 to 60 W.

[0020] Illustratively, the second mask layer includes a photoresist layer, or a composite layer consisting of a photoresist, an anti-reflective layer, and a hard mask layer.

[0021] Exemplarily, the first etch stop layer and the second etch stop layer are made of the same material.

[0022] Exemplarily, the thickness of the first etch stop layer is equal to the thickness of the second etch stop layer.

[0023] Exemplarily, a size of the sixth opening is equal to a size of the second opening.

[0024] Exemplarily, the first target dielectric layer and the second target dielectric layer are layers of the same material.

[0025] Exemplarily, the method further includes removing the first hard mask layer.

[0026] According to the manufacturing method of the semiconductor device of the present invention, only one photolithography process is required to realize the dual damascene structure in the dual damascene process, without the need for expensive photolithography equipment support, and the equipment cost is lower; the formed damascene structure is easy to fill, and seamless filling can be achieved; at the same time, the manufacturing method of the semiconductor device of the present invention has wide applicability and can also be used for etching conventional through holes, and has a broader application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0028] In the attached figure:

[0029] Figure 1A-1G is a schematic structural diagram of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Figure 2The flowchart is an exemplary method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0032] To provide a thorough understanding of the present invention, a detailed description will be provided below to illustrate the semiconductor device manufacturing method of the present invention. Obviously, the practice of the present invention is not limited to the specific details familiar to those skilled in the semiconductor field. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other embodiments.

[0033] It should be noted that the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0034] Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete and to fully convey the concepts of these exemplary embodiments to those skilled in the art. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity, and identical reference numerals are used to represent identical elements, and their descriptions will be omitted.

[0035] In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0036] providing a semiconductor substrate;

[0037] forming a first etch stop layer, a first target dielectric layer, a second etch stop layer, and a second target dielectric layer in sequence on the semiconductor substrate;

[0038] forming a first hard mask layer and a patterned second mask layer in sequence on the second target dielectric layer, wherein the second mask layer has a first opening, and the first opening exposes a portion of the first hard mask layer;

[0039] Etching the first hard mask layer using the second mask layer as a mask to form a second opening in the first hard mask layer, wherein the second opening exposes a portion of the second target dielectric layer and is larger than the first opening;

[0040] etching the second target dielectric layer using the second mask layer as a mask to form a third opening in the second target dielectric layer, wherein the third opening exposes a portion of the second etch stop layer;

[0041] etching the second etch stop layer using the second mask layer as a mask to form a fourth opening in the first etch stop layer, wherein the fourth opening exposes a portion of the first target dielectric layer;

[0042] removing the second mask layer;

[0043] Using the first hard mask layer as a mask, etching the first target dielectric layer and the second target dielectric layer to form a fifth opening in the first target dielectric layer and expanding the third opening into a sixth opening;

[0044] Using the first hard mask layer as a mask, the second etch stop layer and the first etch stop layer are etched to form a seventh opening in the first etch stop layer, and the fourth opening is expanded into an eighth opening, wherein a size of the eighth opening is equal to a size of the sixth opening.

[0045] See below Figure 1A-1G and Figure 2 A chemical mechanical polishing method according to the present invention is exemplified. Figure 1A-1G is a schematic structural diagram of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention; Figure 2 The flowchart is an exemplary method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0046] First, see Figure 1A , providing a semiconductor substrate 100.

[0047] The semiconductor substrate 100 can specifically be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, including a multilayer structure composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0048] In this embodiment, the semiconductor substrate 100 is a silicon wafer on which core devices are formed, and a dual damascene structure is formed through subsequent steps to form an interconnection structure.

[0049] Next, continue to see Figure 1A A first etch stop layer 101 , a first target dielectric layer 102 , a second etch stop layer 103 and a second target dielectric layer 104 are sequentially formed on a semiconductor substrate 100 .

[0050] The first target dielectric layer 102 and the second target dielectric layer 104 are used to form a dual damascene structure therein, and the second etch stop layer 103 is formed between the first target dielectric layer 102 and the second target dielectric layer 104 in order to effectively protect the first target dielectric layer 102 during the subsequent etching of the first target dielectric layer 102 and the second target dielectric layer 104 using the first hard mask layer as a mask, thereby preventing the opening in the first target dielectric layer 102 from expanding outward, thereby forming openings of different sizes in the first target dielectric layer 102 and the second target dielectric layer 104 to form a dual damascene structure.

[0051] At the same time, the etch stop layer 101 is formed below the first target dielectric layer 102 to avoid over-etching and damaging the semiconductor substrate during the process of etching the first target dielectric layer 102 to form an opening in the first target dielectric layer 102, and also to avoid damage to the semiconductor substrate during the process of removing the second etch stop layer 103.

[0052] Exemplarily, the material of the first etch stop layer 101 may be silicon nitride, silicon oxide, etc. In this embodiment, the first etch stop layer 101 is a silicon nitride layer.

[0053] For example, the material of the first target dielectric layer 102 can be various types of insulating silicon dioxide materials grown, such as BPSG, PSG, FSG, USG, TEOS, thermally oxidized silicon dioxide, wet oxidized silicon dioxide, or a combination of these multilayer films. In this embodiment, BPSG is selected for the first target dielectric layer 102.

[0054] For example, the material of the second etch stop layer 103 may be silicon nitride, silicon oxide, or the like.

[0055] Furthermore, illustratively, the second etch stop layer 103 is made of the same material layer 101 as the first etch stop layer.

[0056] Furthermore, the second etch stop layer 103 is made of the same material layer 101 as the first etch stop layer, and the second etch stop layer 103 has the same thickness as the first etch stop layer 101 .

[0057] The second etch-stop layer 103 is made of the same material as the first etch-stop layer 101. When the first etch-stop layer 101 is subsequently etched to expose the semiconductor substrate, the exposed second etch-stop layer 103 can be etched simultaneously, thereby simplifying the process flow. The second etch-stop layer 103 is made of the same thickness as the first etch-stop layer 101. This allows the first etch-stop layer exposed by the opening in the first target dielectric layer to be removed simultaneously with the second etch-stop layer exposed by the opening in the second target dielectric layer, thereby forming a dual damascene structure with smooth sidewall connections.

[0058] At the same time, the second etch stop layer 103 is selected to be a material layer of the same material as the first etch stop layer 101. Since the second etch stop layer 103 is located above the first target dielectric layer 101, when the same etching process is used, the etching rate of the second etch stop layer 103 is greater than the etching rate of the first etch stop layer 101 during the etching process. Therefore, in the process of etching the first etch stop layer 101 to form an opening, the second etch stop layer 103 can be completely removed, thereby avoiding the second etch stop layer 103 remaining above the first target dielectric layer, which is not conducive to subsequent metal filling.

[0059] For example, the material of the second target dielectric layer 104 may be insulating silicon dioxide materials grown in various forms, such as BPSG, PSG, FSG, USG, TEOS, thermally oxidized silicon dioxide, wet oxidized silicon dioxide, or a combination of multiple layers thereof.

[0060] For example, the second target dielectric layer 104 is made of the same material as the first target dielectric layer 102. Since the second target dielectric layer 104 is located above the first target dielectric layer 102, the etching rate of the second target dielectric layer 104 is greater than the etching rate of the first target dielectric layer 102 during the etching process using the same etching process. Therefore, during the process of etching the first target dielectric layer 101 to form an opening, the opening in the second target dielectric layer 104 can expand outward at a faster rate, ultimately reaching the desired opening size.

[0061] In this embodiment, the first target dielectric layer 102 is made of BPSG, and the second target dielectric layer 104 is made of BPSG.

[0062] The second target dielectric layer 104 is made of the same material as the first target dielectric layer 102. During the subsequent etching process to form an opening in the first target dielectric layer 102, the second target dielectric layer 104 is correspondingly etched to expand the opening in the second target dielectric layer 104, thereby forming a dual-damascene damascene structure. This dual-damascene damascene structure is achieved in a single photolithography process, effectively reducing process steps and costs. The specific process described above will be further described in subsequent steps.

[0063] Methods for forming the first etch stop layer, the first target dielectric layer, the second etch stop layer and the second target dielectric layer include high temperature thermal oxidation or chemical vapor deposition or physical vapor deposition and other methods well known to those skilled in the art.

[0064] It should be understood that, in this embodiment, setting the first etch stop layer and the second etch stop layer to be the same material layer, the thickness of the first etch stop layer is equal to the thickness of the second etch stop layer, or the first target dielectric layer and the second target dielectric layer to be the same material layer is merely exemplary. Those skilled in the art should understand that the first etch stop layer and the second etch stop layer can be different material layers, different thicknesses, or the first target dielectric layer and the second target dielectric layer can be different material layers, and the technical effects of the present invention can be achieved.

[0065] Continue to read Figure 1A A first hard mask layer 105 and a patterned second mask layer 106 are sequentially formed on the second target dielectric layer 104 . The second mask layer 106 has a first opening 1061 , which exposes the first hard mask layer 105 .

[0066] Illustratively, the method of etching the first hard mask layer using the second mask layer as a mask includes using a dry etching process to retreat the first hard mask layer to form the second opening.

[0067] The first hard mask layer is etched through a dry etching process to form an opening in the first hard mask layer (the size of the opening is the same as the size of the first opening in the second mask layer), and then the first hard mask layer is retreated to form a second opening. The amount of retreat of the first hard mask layer can be precisely controlled, thereby precisely controlling the size of the second opening. The entire process is processed using a self-alignment process, and there is no obvious defect problem. This can greatly reduce the occurrence of online anomalies and is more conducive to the needs of industrial mass production.

[0068] A mask layer in which a first hard mask layer 105 and a second mask layer 106 are stacked is formed on the second target dielectric layer 104. In a subsequent process of forming an opening, an opening having a size different from that of a first opening 1061 in the second mask layer 106 can be formed in the first hard mask layer 105 during a process of etching the first hard mask layer 105 through the second mask layer 106. An opening having a size larger than that of the first opening 1061 is formed in the first hard mask layer 105, so that dual damascene structures having different sizes can be formed in a subsequent process of etching the first target dielectric layer 102 and the second target dielectric layer 104.

[0069] For example, the material of the first hard mask layer may be titanium nitride, silicon nitride, silicon dioxide, or polysilicon.

[0070] In one embodiment of the present invention, polysilicon is used as the material of the first hard mask layer. The material of the polysilicon can be ultra-high purity polysilicon (U-Ploy) or doped polysilicon (Dope-Poly), which is not limited here.

[0071] Polysilicon is used as the material of the first hard mask layer. On the one hand, it is easy to form a pull-back effect during the process of etching it with the second mask layer as a mask to form an opening therein, thereby forming an opening larger than the first opening. On the other hand, it is easy to remove during the process of etching to form the opening and subsequent removal, thereby avoiding contamination of the dual damascene structure.

[0072] Illustratively, the material of the second mask layer includes a photoresist layer, or a composite material layer consisting of a photoresist layer, an anti-reflection layer, and a hard mask layer.

[0073] In this embodiment, the second mask layer is made of a photoresist layer. This, combined with the polysilicon layer of the first hard mask layer, facilitates a pull-back effect during polysilicon etching, thereby forming an opening larger than the first opening. Furthermore, the formation and removal processes are simple, making clean removal easy. Furthermore, the polysilicon pull-back process utilizes a self-aligned process, eliminating significant defects and significantly reducing the occurrence of in-line anomalies, facilitating industrial mass production.

[0074] Illustratively, a method of forming the first hard mask layer includes chemical vapor deposition, physical vapor deposition, and the like.

[0075] Illustratively, the method for forming the second hard mask layer includes process steps such as spin coating of photoresist, exposure, and development.

[0076] Next, see Figure 1BThe first hard mask layer 105 is etched using the second mask layer 106 as a mask to form a second opening 1051 in the first hard mask layer 105 . The second opening 1051 exposes a portion of the second target dielectric layer 104 , and the size of the second opening 1051 is larger than the first opening 1061 .

[0077] Exemplarily, the method of etching the first hard mask layer using the second mask layer as a mask adopts a dry etching method, wherein the first hard mask layer is over-etched during the dry etching process so that the size of the second opening formed in the first hard mask layer is larger than the size of the first opening in the second mask layer.

[0078] In one embodiment of the present invention, the over-etching is achieved by an endpoint detection method, so that the size of the second opening formed in the first hard mask layer reaches a preset size, forming an opening size that meets the requirements.

[0079] In one embodiment of the present invention, the first hard mask layer is a polysilicon layer, and the second mask layer is a photoresist layer. During the dry etching process, the photoresist mask layer is used to block the polysilicon, and a certain pull-back effect is achieved while etching the polysilicon cleanly. As a result, the size of the second opening formed in the polysilicon is larger than the size of the first opening in the photoresist mask layer.

[0080] Exemplarily, the etching gas used in the step of etching the polysilicon layer using the photoresist layer as a mask includes SF6, O2 and CF4.

[0081] Exemplarily, in the step of etching the polysilicon layer using the photoresist layer as a mask, the flow adjustment range of SF6 is 15 to 40 sccm, the flow adjustment range of O2 is 5 to 55 sccm, the flow adjustment range of CF4 is 10 to 30 sccm, the process pressure range is 10 to 20 mT, the upper RF source power range is 300 to 500 W, and the lower RF source power adjustment range is 30 to 60 W.

[0082] It should be understood that the above-mentioned process of etching polysilicon using photoresist as a mask is merely exemplary, and those skilled in the art should understand that any method capable of forming a second opening in the first hard mask layer with a size larger than the size of the first opening in the second mask layer is applicable to the present invention.

[0083] Next, see Figure 1C The second target dielectric layer 104 is etched using the second mask layer 106 as a mask to form a third opening 1041 in the second target dielectric layer 104 . The third opening 1041 exposes a portion of the second etch stop layer 103 .

[0084] In this step, since the second mask layer 106 is used as a mask for etching, the third opening 1041 formed in the second target dielectric layer 104 is the same size as the first opening 1061 (since in actual production it is necessary to consider fluctuations in the previous and subsequent processes such as film thickness and rate fluctuations of the etching machine, a certain amount of over-etching is required in the development of the etching process to ensure that the film layer is etched cleanly. The same size this time means that the size is the same or similar within the range allowed by the process over-etching).

[0085] In this embodiment, the second target dielectric layer is made of BPSG. The gas used to etch the second target dielectric layer includes one of the following gas combinations: CF4 / CHF3 / Ar, CF4 / CHF3 / Ar / O2, C4F8 / O2 / Ar, C4F8 / O2 / CO / Ar, C4F6 / O2 / Ar, C4F6 / O2 / CO / Ar, C5F8 / O2 / Ar, or C5F8 / O2 / CO / Ar.

[0086] Next, see Figure 1D The second etch stop layer 103 is etched using the second mask layer 106 as a mask to form a fourth opening 1031 in the second etch stop layer 103 . The fourth opening 1031 exposes a portion of the first target dielectric layer 102 .

[0087] In this step, since the second mask layer 106 is used as a mask for etching, the fourth opening 1031 formed in the second etch stop layer 103 is the same size as the first opening 1061 (since in actual production it is necessary to consider fluctuations in the previous and subsequent processes such as film thickness and rate fluctuations of the etching machine, a certain amount of over-etching is required in the development of the etching process to ensure that the film layer is etched cleanly. The same size this time means that the size is the same or similar within the range allowed by the process over-etching).

[0088] In this embodiment, the second etch stop layer is a silicon nitride layer, and the gas used to etch the second target dielectric layer includes one of the gas combinations of CHF3 / Ar / O2, CH2F2 / Ar / O2, and CH3F / Ar / O2.

[0089] Next, see Figure 1E , remove the second mask layer 106.

[0090] Exemplarily, the second mask layer 106 is removed by a dry etching process.

[0091] In this embodiment, a photoresist layer is used as the second mask layer 106 , and a gas containing O 2 is used in a dry process to etch and remove the second mask layer.

[0092] Next, see Figure 1F, using the first hard mask layer 105 as a mask, etching the first target dielectric layer 102 and the second target dielectric layer 104 to form a fifth opening 1021 in the first target dielectric layer 102, and expanding the third opening 1041 in the second target dielectric layer 104 into a sixth opening 1042.

[0093] In this step, because a second etch-stop layer 103 is formed between the first target dielectric layer 102 and the second target dielectric layer 104, as the third opening 1041 in the second target dielectric layer 104 expands outward to form the sixth opening 1042, the second etch-stop layer 103 effectively protects the first target dielectric layer 102, preventing the fifth opening 1021 in the first target dielectric layer 102 from expanding outward. As a result, the sixth opening 1042 in the first target dielectric layer 102 and the fifth opening 1021 in the second target dielectric layer 104 have different sizes, forming a dual damascene structure. Furthermore, the top of the first target dielectric layer 103 is effectively protected during the process of the third opening 1041 in the second target dielectric layer 104 expanding outward to form the sixth opening 1042.

[0094] In this process, since the first etch stop layer 101 is provided at the bottom of the first target dielectric layer 102 , the third opening 1041 in the second target dielectric layer 104 can be expanded outward to form the sixth opening 1042 through appropriate over-etching.

[0095] Exemplarily, the size of the sixth opening 1042 is equal to that of the second opening 1051 .

[0096] By controlling the size of the sixth opening 1042 to be equal to the size of the second opening 1051 , the opening size of the entire Damascus structure can be controlled by controlling the retreat amount of the first hard mask layer (the size of the second opening 1051 ), thereby achieving precise control.

[0097] In this embodiment, the second target dielectric layer is made of the same material as the first target dielectric layer: BPSG. The gas used to etch the second target dielectric layer includes one of the following gas combinations: CF4 / CHF3 / Ar, CF4 / CHF3 / Ar / O2, C4F8 / O2 / Ar, C4F8 / O2 / CO / Ar, C4F6 / O2 / Ar, C4F6 / O2 / CO / Ar, C5F8 / O2 / Ar, or C5F8 / O2 / CO / Ar.

[0098] Next, see Figure 1G, using the first hard mask layer 105 as a mask, the second etch stop layer 103 and the first etch stop layer 101 are etched to form a seventh opening 1011 in the first stop layer 101, and the fourth opening 1031 is expanded into an eighth opening 1032, wherein the size of the eighth opening 1032 is equal to that of the sixth opening 1052.

[0099] In this step, the first etch stop layer 101 is removed to form a seventh opening 1011 exposing the semiconductor substrate 100. At the same time, the second etch stop layer 103 located above the first target dielectric layer 101 is removed to achieve seamless filling of the subsequent dual damascene structure.

[0100] In this embodiment, the first etch stop layer 101 uses the same material layer as the second etch stop layer 103: a silicon nitride layer, and the gas for etching the first etch stop layer 101 includes one of the gas combinations of CHF3 / Ar / O2, CH2F2 / Ar / O2, CH3F / Ar / O2, etc.

[0101] Next, continue to see Figure 1G , remove the first hard mask layer 105, and form Figure 1G The Damascus structure shown.

[0102] The method for removing the first hard mask layer 105 includes dry or wet etching processes well known to those skilled in the art. In this embodiment, the first hard mask layer 105 is a polysilicon layer, and the polysilicon layer is removed by wet etching.

[0103] So far, the technical solution of the present invention has been exemplarily described. In one embodiment of the present invention, after completing the aforementioned structure, a step of filling the aforementioned dual damascene structure is also included, which will not be repeated here. According to the method for manufacturing a semiconductor device of the present invention, only one photolithography process is required to realize the dual damascene structure in the dual damascene process, without the need for expensive photolithography equipment support, and the equipment cost is lower; the formed damascene structure is easy to fill, and seamless filling can be achieved; at the same time, the method for manufacturing a semiconductor device of the present invention has a wide range of applicability and can also be used for etching conventional through holes, and has a broader application prospect.

[0104] See Figure 2 , shows a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:

[0105] Step S1: providing a semiconductor substrate;

[0106] Step S2: forming a first etch stop layer, a first target dielectric layer, a second etch stop layer, and a second target dielectric layer in sequence on the semiconductor substrate;

[0107] Step S3: forming a first hard mask layer and a patterned second mask layer in sequence on the second target dielectric layer, wherein the second mask layer has a first opening, and the first opening exposes a portion of the first hard mask layer;

[0108] Step S4: etching the first hard mask layer using the second mask layer as a mask to form a second opening in the first hard mask layer, wherein the second opening exposes a portion of the second target dielectric layer and is larger than the first opening;

[0109] Step S5: etching the second target dielectric layer using the second mask layer as a mask to form a third opening in the second target dielectric layer, wherein the third opening exposes a portion of the second etch stop layer;

[0110] Step S6: etching the second etch stop layer using the second mask layer as a mask to form a fourth opening in the first etch stop layer, wherein the fourth opening exposes a portion of the first target dielectric layer;

[0111] Step S7: removing the second mask layer;

[0112] Step S8: using the first hard mask layer as a mask, etching the first target dielectric layer and the second target dielectric layer to form a fifth opening in the first target dielectric layer, and expanding the third opening into a sixth opening;

[0113] Step S9: Using the first hard mask layer as a mask, etching the second etch stop layer and the first etch stop layer to form a seventh opening in the first etch stop layer, and expanding the fourth opening into an eighth opening, wherein the size of the eighth opening is equal to the sixth opening.

[0114] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; forming a first etch stop layer, a first target dielectric layer, a second etch stop layer, and a second target dielectric layer in sequence on the semiconductor substrate; forming a first hard mask layer and a patterned second mask layer in sequence on the second target dielectric layer, wherein the second mask layer has a first opening, and the first opening exposes a portion of the first hard mask layer; Etching the first hard mask layer using the second mask layer as a mask to form a second opening in the first hard mask layer, wherein the second opening exposes a portion of the second target dielectric layer and is larger than the first opening; etching the second target dielectric layer using the second mask layer as a mask to form a third opening in the second target dielectric layer, wherein the third opening exposes a portion of the second etch stop layer; etching the second etch stop layer using the second mask layer as a mask to form a fourth opening in the second etch stop layer, wherein the fourth opening exposes a portion of the first target dielectric layer; removing the second mask layer; Using the first hard mask layer as a mask, etching the first target dielectric layer and the second target dielectric layer to form a fifth opening in the first target dielectric layer and expanding the third opening into a sixth opening; Using the first hard mask layer as a mask, the second etch stop layer and the first etch stop layer are etched to form a seventh opening in the first etch stop layer, and the fourth opening is expanded into an eighth opening, wherein a size of the eighth opening is equal to a size of the sixth opening.

2. The method according to claim 1, characterized in that The method of etching the first hard mask layer using the second mask layer as a mask includes using a dry etching process to retreat the first hard mask layer to form the second opening.

3. The method according to claim 2, characterized in that The first hard mask layer includes a polysilicon layer.

4. The method according to claim 3, characterized in that In the step of using a dry etching process to make the first hard mask layer retreat to form the second opening, the etching gases of the dry etching process include SF6, O2 and CF4, the flow adjustment range of SF6 is 15 to 40 sccm, the flow adjustment range of O2 is 5 to 55 sccm, the flow adjustment range of CF4 is 10 to 30 sccm, the process pressure range of the dry etching process is 10 to 20 mT, the upper RF source power range of the dry etching process is 300 to 500 W, and the lower RF source power adjustment range of the dry etching process is 30 to 60 W.

5. The method according to claim 1, characterized in that The second mask layer includes a photoresist layer, or a composite layer consisting of a photoresist, an anti-reflection layer and a hard mask layer.

6. The method according to claim 2, characterized in that The first etch stop layer and the second etch stop layer are made of the same material.

7. The method according to claim 6, characterized in that The thickness of the first etch stop layer is equal to the thickness of the second etch stop layer.

8. The method according to claim 1, characterized in that The size of the sixth opening is equal to the size of the second opening.

9. The method according to claim 1, characterized in that The first target dielectric layer and the second target dielectric layer are made of the same material.

10. The method according to claim 1, characterized in that The method further includes removing the first hard mask layer.

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