A full-sea-depth pressure-resistant electronic switch

Abstract

The present invention discloses a full-sea-depth pressure-resistant electronic switch, comprising a base plate in a housing, and a control board, a switch board, a wiring board, and a linear buffer board sequentially arranged on the base plate. The control board comprises a control power supply circuit, a PWM wave generating circuit, and a control drive signal conditioning circuit. The switch board comprises a switch group and a switch board absorption circuit. The linear buffer board comprises a time-delayed opening circuit, a buffer board absorption circuit, and a multi-stage buffer circuit. A soft shutdown mode with gradually increasing impedance is achieved by sequentially shutting off multiple resistors connected in parallel with the main switch. The present invention has the advantages of simple structure, rapid response, anti-interference, and tolerance to ultra-high seawater pressure, and is particularly suitable for full-sea-depth underwater control environments.

Description

Technical Field

[0001] The present invention belongs to the field of control technology in electrical systems, and specifically relates to a full-sea-depth voltage-resistant electronic switch suitable for DC high-voltage and high-current switching applications, and is particularly suitable for automatic electrical control of deep-sea ships. Background Art

[0002] Lithium batteries are widely used in deep-sea vehicles due to their high energy density, ease of use and maintenance, and high efficiency. Deep-sea battery systems often employ direct pressure-bearing structural designs to improve energy density. Under the high-pressure conditions of the deep sea, electronic switches, as a crucial component of the battery management system, must overcome complex external pressures to control the opening and closing of the entire battery pack's discharge circuit. Current electronic switches used in deep-sea batteries are generally only suitable for AC operating conditions or low-voltage (generally no higher than DC24V) DC operating conditions. High-current battery systems suffer from significant energy losses. Furthermore, these electronic switch control circuits are not isolated from the main circuit, resulting in complex drive circuits, which increases system complexity and reduces reliability.

[0003] In order for deep-sea battery systems to operate properly underwater, an electronic switch is required that can withstand the surge current when a DC capacitive load is turned on, or the surge voltage when an inductive load is turned off, and can withstand the pressure. Summary of the Invention

[0004] The object of the present invention is to provide an electronic switch that can be used in a full-sea-depth pressure environment and is suitable for a DC110V system.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a full-sea-depth pressure-resistant electronic switch, comprising a bottom plate in a housing, and a control board, a switch board, a wiring board and a linear buffer board arranged in sequence on the bottom plate;

[0006] The control board includes a control power supply circuit, a PWM wave generating circuit and a control drive signal conditioning circuit; the control power supply circuit converts the control signal within the rated voltage range into a control circuit power supply through an LDO linear voltage regulator circuit, and includes a resistor RE1, a diode DE1 and a three-terminal voltage regulator E1 connected in series, the first pin of the resistor RE1 being connected to the switch control signal positive K+, the second pin of the resistor RE1 being connected to the A pin of the diode DE1, the first pin of the capacitor CE1 being connected between the K pin of the diode DE1 and the Vin pin of the three-terminal voltage regulator E1, the second pin of the capacitor CE1 being connected to the GND pin of the three-terminal voltage regulator E1 and the control signal negative AGND, and the capacitor CE2 being connected between the Vout pin and the GND pin of the three-terminal voltage regulator E1; the PWM wave generating circuit uses a half-bridge driver chip to convert the control circuit power supply into a PWM wave; the control drive signal conditioning circuit uses an isolation transformer T1 to isolate the control signal from the main circuit, the secondary side of the transformer converts the control circuit power supply into the drive circuit power supply through a rectifier composed of diodes and a rectifier and filter circuit composed of capacitors and resistors, and the drive circuit power supply drives the switch group via a push-pull circuit composed of two transistors;

[0007] The switch board includes a switch group and a switch board absorption circuit; the switch group uses two MOS transistors G1 and MOS transistor G2 in series to achieve bidirectional control, and improves switching power through multi-path parallel connection: four resistors RC1 to RC4 are connected in series to form a group, two groups of resistors are connected in parallel, five capacitors C1, C21, C41, C61, and C81 are connected in series to form a group, and twenty groups of capacitors are connected in parallel. The K1 contact is connected to the resistor RS1 through the diode DS1, and the two ends of the resistor RS2 and the capacitor CS1 are connected in parallel to the gate and source of the MOS transistor G1 respectively. The K1 contact is connected to the resistor RS3 through the diode DS2, and the two ends of the resistor RS4 and the capacitor CS2 are connected in parallel to the gate and source of the MOS transistor G2 respectively. The drains of the MOS transistors G1 and MOS transistors G2 are connected to the resistors RC4 / RC8 in the resistor group, and the sources of the MOS transistors G1 and MOS transistors G2 are connected to the analog ground. The input terminal IN is connected to the parallel circuit formed by the resistor group and the capacitor group and connected to the MOS transistors G1 / The drain of G2 is connected to capacitors C100 / 200. The switch board absorption circuit absorbs surge current and shutdown surge voltage during startup and shutdown. It consists of resistors and MOS transistors. Ten resistors RQ1 to RQ10 are connected in series to form a group, which is then connected to the gates of two MOS transistors G11 and G12. The drains of the two MOS transistors G11 and G12 are connected to the input terminal IN and the output terminal OUT, respectively. The two MOS transistors G11 and G12 are connected to each other to form a group, totaling 91 groups with a total of 182. Another ten resistors RG1 to RG10 are connected in series to form a group, which is connected in series to the source connection of the two MOS transistors G11 and G12 to lead to the output terminal OUT. The two groups of resistors are connected in series.

[0008] The linear buffer board realizes a soft shutdown mode with gradually increasing impedance by sequentially shutting off multiple resistors connected in parallel with the main switch, and includes a delayed opening circuit, a buffer board absorption circuit, and multiple multi-stage buffer circuits; the delayed opening circuit is used to withstand the surge current generated when the capacitive load is turned on, and the surge voltage impact generated when the inductive load is turned off, and is composed of a diode DK2, a voltage regulator tube VDK3, transistors PK3~PK4 and QK3~QK4, resistors RK7~11, capacitors CK2 and CP4, resistor RK7 and diode DK2 are connected in parallel and then connected to capacitor CK2, one end of resistor RK7 is connected to voltage regulator tube VDK3, and voltage regulator tube VDK4 is connected to capacitor CK2. K3 is connected to the base of transistor QK3, one end of resistor RK8 is connected to the base of transistor QK3, the other end of resistor RK8 is connected to analog ground, the collector of transistor QK3 is connected to resistor RK9, one end of resistor RK9 is connected to the base of transistor PK3, the emitter of transistor PK3 is connected to the power supply terminal VDD, the collector of transistor PK3 is connected to resistor RK10, the other end of resistor RK10 is connected in series with resistor RK11, one end of resistor RK11 is connected to the base of transistor QK4 and transistor PK4, and the other end is connected to analog ground, the emitter of transistor QK4 is connected to the emitter of transistor PK4, the middle connection line leads to contact K, at the power supply terminal and the ground The ground terminal is connected in series with a capacitor CP4, and the high-level VDD drives the transistor QK3 to turn on through the voltage regulator tube VDK3. The driving circuit power is driven by the push-pull circuit composed of the transistor QK4 and the transistor PK4 to drive the switch group. The buffer board absorption circuit is composed of a resistor RH and a MOS tube GH. One hundred and one resistors RH are connected in series to form a group, and two MOS tubes GH are connected to form a group through the gate and source. The three groups of resistors RH are connected in parallel. One end of the lead wire is connected to the IN contact and the other end is connected to the drain of the MOS tube GH. The source of the MOS tube GH is connected to the analog ground GND. The gate of the MOS tube GH is connected to eleven resistors RQH connected in series in sequence, and then leads to eleven contacts S1 to S2. S11, according to this combination, 10 groups are connected in parallel; the multi-stage buffer circuit is used to withstand high-voltage shocks, and is composed of eleven diodes DKS1~11, voltage regulator tubes VDU1~VDU5, resistor RK12 and capacitor CK3. A diode DKS is connected between each contact K and contact S, that is, eleven diodes DKS1~11 are connected between contacts S~S11, capacitor CK3 is connected between contact S1 and analog ground GND, a resistor RK12 is connected between contact S and analog ground, four voltage regulator tubes VDU2~VDU5 are connected in series between contact S and contact U1, and a voltage regulator tube VDU1 is connected between contact IN and contact U1.

[0009] The full-sea-depth voltage-resistant electronic switch has a PWM wave generating circuit comprising diodes DP1 to DP4, resistors RT1 and RP1, capacitors CT1 and CE3, and a half-bridge driver U1; the first pin of the resistor RT1 is respectively connected to the Vout pin of the three-terminal regulator E1 in the control power supply circuit, the K pin of the diode DP3, the 8th high-side floating power supply pin and the 5th power supply VCC pin of the half-bridge driver U1, the K pin of the diode DP1, and the first pin of the capacitor CE3; the A pin of the diode DP3 is connected to the K pin of the diode DP4 and the 4th low-side output pin Lo of the half-bridge driver U1. pin; the first pin of capacitor CE3 is connected to the second pin of resistor RT1 and the 2nd oscillation pin of half-bridge driver U1, and the second pin of capacitor CE3 is respectively connected to the 1st current detection input pin, the 3rd power supply GND pin, the 6th floating voltage feedback pin of half-bridge driver U1 in the PWM wave generating circuit, as well as the A pin of diode DP4, the A pin of diode DP2, the second pin of capacitor CE3 and AGND in the control power supply circuit; the K pin of diode DP2 is connected to the A pin of diode DP1, the 7th pin Ho high-side output pin of half-bridge driver U1 and the first pin of resistor RE3.

[0010] The full-sea-depth withstand voltage electronic switch has a control drive signal conditioning circuit comprising voltage regulator tubes VDK1-VDK2, PNP transistors PK1-PK2, NPN transistors QK1-QK2, an isolation transformer T1, resistors RK1-RK5 and resistors RP2-RP3, capacitors CP1-CP3 and capacitor CK1, and diodes DP5-DP8; the first pin of the source side of the isolation transformer T1 is connected to the second pin of the resistor RP1 in the PWM wave generating circuit, the second pin of the source side of the isolation transformer T1 is connected to the fourth pin Lo low-side output pin of the half-bridge driver U1 in the PWM wave generating circuit; the third pin of the secondary side of the isolation transformer T1 (the same end as the first pin of the source side of T1) is connected to the diode D Pin A of P7 and pin K of diode DP8; the fourth pin of the secondary side of isolation transformer T1 is connected to pin A of diode DP5 and pin K of diode DP6; the first pin of resistor RP2 is connected to pin K of diode DP5, pin K of diode DP7, the first pin of capacitor CP1, pin K of voltage regulator VDK1, the emitter of transistor PK1 and the collector of transistor QK2; the second pin of resistor RP2 is connected to pin A of diode DP6, pin A of diode DP8, the second pin of capacitor CP1, the first pin of resistor RK1, the emitter of transistor QK1, the first pin of resistor RK5 and the collector of transistor PK2; the A pin of voltage regulator VDK1 is connected to voltage regulator VDK2 The A pin of the resistor RK3 is connected to the base of the transistor PK1, the first pin of the capacitor CK1, the second pin of the resistor RK1 and the first pin of the resistor RK2; the second pin of the resistor RK2 is connected to the base of the transistor QK1; the K pin of the voltage regulator diode VDK2 is respectively connected to the second pin of the capacitor CK1, the collector of the transistor PK1 and the first pin of the resistor RK4; the second pin of the resistor RK4 is respectively connected to the second pin of the resistor RK5, the base of the transistor QK2 and the base of the transistor PK2; the first pin of the resistor RK3 is connected to the base of the transistor PK1, and the second pin is connected to the collector of the transistor QK1, the first pin of the capacitor CP2 is connected to VDD, the second pin of the capacitor CP3 is connected to the analog ground GND, and the resistor RP3 is connected in parallel with the capacitors CP2 and CP3.

[0011] Furthermore, the isolation transformer T1 is an on-board planar isolation transformer.

[0012] Furthermore, the resistors, capacitors, diodes, MOS tubes and triodes are all solid plastic-encapsulated devices.

[0013] The advantages and positive effects of the present invention are as follows:

[0014] 1. There is a very high isolation voltage level between the control circuit and the switch main circuit.

[0015] 2. The switching speed can reach below 0.1mS.

[0016] 3. When the rated working conditions are not exceeded, there is no life limit for the number of switches, and the stability and durability are high.

[0017] 4. Complete anti-turn-on surge current circuit, capable of directly turning on large capacitive loads.

[0018] 5. Complete anti-shutoff surge voltage circuit, with the ability to directly shut down large inductive loads.

[0019] 6. There is no contact spark during the switching process, the interference is much smaller than that of mechanical switches, and the electromagnetic compatibility performance is intact.

[0020] 7. The main switch adopts multi-channel MOS tube parallel connection, which reduces the internal resistance of the switch, reduces energy loss, and dissipates heat on the switch bottom plate, reducing the size of the switch.

[0021] 8. Under oil immersion conditions, it has the ability to work under high pressure conditions and is suitable for use in deep sea environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural block diagram of the composition of the present invention;

[0023] Figure 2 This is a schematic diagram of the control power supply circuit of the present invention;

[0024] Figure 3 Schematic diagram of the PWM wave generating circuit of the present invention;

[0025] Figure 4 This is a schematic diagram of a control drive signal conditioning circuit according to the present invention;

[0026] Figure 5 This is a schematic diagram of the switch group of the present invention;

[0027] Figure 6 This is a schematic diagram of the switch board absorption circuit of the present invention;

[0028] Figure 7 It is a schematic diagram of the delayed opening circuit of the present invention;

[0029] Figure 8 This is a schematic diagram of the buffer board absorption circuit of the present invention;

[0030] Figure 9 Schematic diagram of the multi-stage buffer circuit of the present invention.

[0031] The reference numerals are: 10—base plate, 11—control board, 12—switch board, 13—connection board, 14—linear buffer board. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0033] Reference Figure 1 As shown, the present invention discloses a full-sea-depth voltage-resistant electronic switch, including a base plate 10 in a housing, and a control board 11, a switch board 12, a linear buffer board 14 and a terminal board 13 arranged in sequence on the base plate 10; the control board 11 includes a control power supply circuit, a PWM wave generating circuit, and a control drive signal conditioning circuit; the switch board 12 includes a switch group and a switch board absorption circuit; the linear buffer board 14 realizes a soft shutdown mode with gradually increasing impedance by sequentially shutting off multiple resistors connected in parallel with the main switch, including a delayed opening circuit, multiple buffer board absorption circuits and multiple multi-stage buffer circuits.

[0034] Figure 2 、 Figure 3 、 Figure 4 FIG. 1 is a schematic diagram of the control board 11 of the electronic switch of the present invention.

[0035] Reference Figure 2 As shown, the control power supply circuit converts the control signal within the rated voltage range into a control circuit power supply through an LDO linear voltage regulator circuit, including a resistor RE1, a diode DE1 and a three-terminal voltage regulator E1 connected in series. The first pin of the resistor RE1 is connected to the switch control signal positive K+, the second pin of the resistor RE1 is connected to the A pin of the diode DE1, the first pin of the capacitor CE1 is connected between the K pin of the diode DE1 and the Vin pin of the three-terminal voltage regulator E1, the second pin of the capacitor CE1 is connected to the GND pin of the three-terminal voltage regulator E1 and the control signal negative AGND, and the capacitor CE2 is connected between the Vout pin and the GND pin of the three-terminal voltage regulator E1.

[0036] Reference Figure 3As shown, the PWM wave generating circuit uses a half-bridge driver chip to convert the control circuit power supply into a PWM wave, including diodes DP1 to DP4, resistors RT1 and RP1, capacitors CT1 and CE3, and a half-bridge driver U1; the first pin of the resistor RT1 is respectively connected to the Vout pin of the three-terminal regulator E1 in the control power supply circuit, the K pin of the diode DP3, the 8th pin high-side floating power supply pin and the 5th pin power supply VCC pin of the half-bridge driver U1, the K pin of the diode DP1, and the first pin of the capacitor CE3; the A pin of the diode DP3 is connected to the K pin of the diode DP4 and the L pin 4 of the half-bridge driver U1. o Low-side output pin; the first pin of capacitor CE3 is connected to the second pin of resistor RT1 and the 2nd oscillation pin of half-bridge driver U1, and the second pin of capacitor CE3 is respectively connected to the 1st current detection input pin, the 3rd power supply GND pin, the 6th floating voltage feedback pin of half-bridge driver U1 in the PWM wave generating circuit, as well as the A pin of diode DP4, the A pin of diode DP2, the second pin of capacitor CE3 and AGND in the control power supply circuit; the K pin of diode DP2 is connected to the A pin of diode DP1, the 7th Ho high-side output pin of half-bridge driver U1 and the first pin of resistor RE3.

[0037] Reference Figure 4 As shown, the control drive signal conditioning circuit uses an isolation transformer T1 to isolate the control signal from the main circuit, converting the control circuit power supply into the drive circuit power supply. The drive circuit power supply drives the switch group. The secondary side of the transformer converts the control circuit power supply into the drive circuit power supply through a rectifier composed of diodes and a rectifier filter circuit composed of capacitors and resistors. The drive circuit power supply drives the switch group through a push-pull circuit composed of two transistors. At the same time, two voltage regulator tubes are used to limit the turn-on voltage and the turn-off voltage.

[0038] The control drive signal conditioning circuit includes voltage regulator tubes VDK1~VDK2, PNP transistors PK1~PK2, NPN transistors QK1~QK2, isolation transformer T1, resistors RK1~RK5 and resistors RP2~RP3, capacitors CP1~CP3 and capacitor CK1 and diodes DP5~DP8; the first pin of the source side of the isolation transformer T1 is connected to the second pin of the resistor RP1 in the PWM wave generating circuit, the second pin of the source side of the isolation transformer T1 is connected to the 4th pin Lo low-side output pin of the half-bridge driver U1 in the PWM wave generating circuit; the third pin of the secondary side of the isolation transformer T1 (the same end as the first pin of the source side of T1) is connected to the A pin of the diode DP7 and the diode The K pin of transistor DP8; the fourth pin of the secondary side of isolation transformer T1 is connected to the A pin of diode DP5 and the K pin of diode DP6; the first pin of resistor RP2 is connected to the K pin of diode DP5, the K pin of diode DP7, the first pin of capacitor CP1, the K pin of voltage regulator diode VDK1, the emitter of transistor PK1 and the collector of transistor QK2; the second pin of resistor RP2 is connected to the A pin of diode DP6, the A pin of diode DP8, the second pin of capacitor CP1, the first pin of resistor RK1, the emitter of transistor QK1, the first pin of resistor RK5 and the collector of transistor PK2; the A pin of voltage regulator diode VDK1 is connected to voltage regulator diode VDK2 The A pin of the resistor RK3 is connected to the base of the transistor PK1, the first pin of the capacitor CK1, the second pin of the resistor RK1 and the first pin of the resistor RK2; the second pin of the resistor RK2 is connected to the base of the transistor QK1; the K pin of the voltage regulator diode VDK2 is respectively connected to the second pin of the capacitor CK1, the collector of the transistor PK1 and the first pin of the resistor RK4; the second pin of the resistor RK4 is respectively connected to the second pin of the resistor RK5, the base of the transistor QK2 and the base of the transistor PK2; the first pin of the resistor RK3 is connected to the base of the transistor PK1, and the second pin is connected to the collector of the transistor QK1, the first pin of the capacitor CP2 is connected to VDD, the second pin of the capacitor CP3 is connected to the analog ground GND, and the resistor RP3 is connected in parallel with the capacitors CP2 and CP3.

[0039] The Ho end of the PWM controller is connected in series with a resistor RP2 and then connected to the high end of the transformer T1. The Lo end of the PWM controller is connected to the low end of the transformer. The output end of the transformer T1 is connected to a rectifier bridge composed of four diodes, and then connected in parallel with the resistor RP3 and the capacitor CP1. The voltage regulator VDK1 is connected in series with the resistor RK1 and then connected to the emitter of the transistor PK1. The voltage regulator VDK2 is connected in parallel with the capacitor CK1 and then connected to the collector of the transistor PK1. The resistor RK2 is connected to the base of the transistor QK1. The base of the transistor PK1 is connected to the resistor RK3 and then connected to the collector of the transistor QK1. The collector of the transistor PK1 is connected in series with the two resistors and then connected to the ground end. Diode DK1 is connected to the base of transistor QK2 and the power supply terminal VDD, the emitter of transistor QK2 is connected to the emitter of transistor PK2, and contacts K1 and K2 are led out. A resistor RK6 is connected between the contacts. Two capacitors CP2 and CP3 are connected in series and in parallel with resistor RP3, and one end is connected to the power supply terminal and the other end is grounded.

[0040] Figure 5 、 Figure 6 FIG. 1 is a schematic diagram of the switch board 12 of the present invention.

[0041] Reference Figure 5 As shown, the switch group uses two MOS transistors G1 and G2 connected in series to achieve bidirectional control, and multi-path parallel connection is used to increase switching power: four resistors RC1 to RC4 are connected in series to form a group, two groups of resistors are connected in parallel, five capacitors C1, C21, C41, C61, and C81 are connected in series to form a group, and twenty groups of capacitors are connected in parallel. The contact K1 is connected to the resistor RS1 through the diode DS1. The two ends of the resistor RS2 and capacitor CS1 are connected in parallel to the gate and source of the MOS transistor G1, respectively. The contact K1 is connected to the resistor RS3 through the diode DS2. The two ends of the resistor RS4 and capacitor CS2 are connected in parallel to the gate and source of the MOS transistor G2, respectively. The drains of the MOS transistors G1 and G2 are connected to the resistors RC4 and RC8 in the resistor group. The sources of the MOS transistors G1 and G2 are connected to the analog ground. The input terminal IN is connected to the parallel circuit formed by the resistor group and the capacitor group. The drains of the MOS transistors G1 and G2 are connected to the capacitors C100 and C200.

[0042] Reference Figure 6As shown, the switch board absorption circuit absorbs surge current and shutdown surge voltage during startup and shutdown. It consists of resistors and MOS transistors. Ten resistors RQ1 to RQ10 are connected in series to form a group, which is then connected to the gates of two MOS transistors G11 and G12. The drains of the two MOS transistors G11 and G12 are connected to the input terminal IN and the output terminal OUT, respectively. The two MOS transistors G11 and G12 are connected to each other to form a group, totaling 91 groups with a total of 182. Another ten resistors RG1 to RG10 are connected in series to form a group, which is connected in series to the source connection of the two MOS transistors G11 and G12 to lead to the output terminal OUT. The two groups of resistors are connected in series.

[0043] Figure 7 、 Figure 8 、 Figure 9 This is a schematic diagram of the linear buffer board 14 of the present invention. This board sequentially disconnects multiple resistors connected in parallel with the main switch, achieving a soft shutdown mode with gradually increasing impedance. This multi-stage buffering absorption circuit provides comprehensive protection against turn-on surge current and turn-off surge voltage, making it suitable for direct DC high-voltage, high-current switching applications.

[0044] Reference Figure 7 As shown, the delayed opening circuit is used to withstand the surge current generated when the capacitive load is turned on, and the surge voltage impact generated when the inductive load is turned off. It consists of a diode DK2, a voltage regulator tube VDK3, transistors PK3~PK4 and QK3~QK4, resistors RK7~11, capacitors CK2 and CP4. Resistor RK7 and diode DK2 are connected in parallel and then connected to capacitor CK2. One end of resistor RK7 is connected to the voltage regulator tube VDK3, and the voltage regulator tube VDK3 is connected to the base of the transistor QK3. One end of resistor RK8 is connected to the base of the transistor QK3, and the other end of resistor RK8 is connected to the analog ground. The collector of the transistor QK3 is connected to resistor RK9, and resistor R One end of K9 is connected to the base of transistor PK3, the emitter of transistor PK3 is connected to the power supply terminal VDD, the collector of transistor PK3 is connected to resistor RK10, the other end of resistor RK10 is connected in series with resistor RK11, one end of resistor RK11 is connected to the base of transistor QK4 and transistor PK4, and the other end is connected to analog ground. The emitter of transistor QK4 is connected to the emitter of transistor PK4, and the middle connection leads to contact K2. Capacitor CP4 is connected in series between the power supply terminal and the ground terminal. The high level VDD drives transistor QK3 to turn on through the voltage regulator diode VDK3, and the drive circuit power drives the switch group through the push-pull circuit composed of transistor QK4 and transistor PK4.

[0045] Reference Figure 8As shown, the buffer board absorption circuit is composed of a resistor RH and a MOS transistor GH. Multiple absorption circuits are connected in parallel to form the second part of the linear buffer board 14. One hundred and one resistors RH are connected in series to form a group, and two MOS transistors GH are connected to form a group through the gate and source. One end of the lead wire of the three groups of resistors RH is connected to the IN contact and the other end is connected to the drain of the MOS transistor GH. The source of the MOS transistor GH is connected to the analog ground GND. The gate of the MOS transistor GH is connected to eleven resistors RQH in series and then leads to eleven contacts S1 to S11. In this combination, ten groups are connected in parallel.

[0046] The last part of the circuit is a multi-stage buffer circuit, which is used to withstand high voltage shocks within a certain range. Figure 9 As shown, 11 diodes DKS1~DKS11 are connected between contacts S~S11, a diode DKS12 is connected between contacts S1 and K1, a capacitor CK3 is connected between contact S1 and the analog ground, a resistor RK12 is connected between contact S and the analog ground, 4 voltage regulators VDU2~VDU5 are connected in series between contact S and contact U1, and a voltage regulator VDU1 is connected between contact IN and contact U1.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention, as well as some embodiments of its application. A person skilled in the art may make several modifications and improvements without departing from the inventive concept of the present invention, and all of these modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A full-sea-depth voltage-resistant electronic switch, characterized by: It includes a bottom plate (10) in a housing, and a control board (11), a switch board (12), a wiring board (13), and a linear buffer board (14) arranged in sequence on the bottom plate (10); The control board (11) includes a control power supply circuit, a PWM wave generating circuit and a control drive signal conditioning circuit; the control power supply circuit converts the control signal within the rated voltage range into a control circuit power supply, including a resistor RE1, a diode DE1 and a three-terminal voltage regulator E1 connected in series, the first pin of the resistor RE1 is connected to the switch control signal positive K+, the second pin of the resistor RE1 is connected to the A pin of the diode DE1, the first pin of the capacitor CE1 is connected between the K pin of the diode DE1 and the Vin pin of the three-terminal voltage regulator E1, the second pin of the capacitor CE1 is connected to the GND pin of the three-terminal voltage regulator E1 and the control signal negative AGND, and the capacitor CE2 is connected between the Vout pin and the GND pin of the three-terminal voltage regulator E1; the PWM wave generating circuit uses a half-bridge driver chip to convert the control circuit power supply into a PWM wave; the control drive signal conditioning circuit uses an isolation transformer to achieve isolation between the control signal and the main circuit, converts the control circuit power supply into the drive circuit power supply, and the drive circuit power supply drives the switch group; The switch board (12) includes a switch group and a switch board absorption circuit; the switch group uses MOS tube G1 and MOS tube G2 in series to realize bidirectional control, and improves the switching power by multi-path parallel connection: four resistors are connected in series to form a group, two groups of resistors are connected in parallel, five capacitors are connected in series to form a group, twenty groups of capacitors are connected in parallel, diode DS1 is connected to resistor RS1, resistor RS2 and capacitor CS1 are connected in parallel, both ends are connected to the gate and source of MOS tube G1 respectively, diode DS2 is connected to resistor RS3, resistor RS4 and capacitor CS2 are connected in parallel, both ends are connected to the gate and source of MOS tube G2 respectively, the drains of MOS tube G1 and MOS tube G2 are connected to a group of resistors, and the sources of MOS tube G1 and MOS tube G2 are connected to analog ground; The switch board absorption circuit absorbs surge current and turns off surge voltage. It consists of resistors and MOS transistors. Ten resistors RQ are connected in series to form a group and then connected to the gates of MOS transistors G11 and G12. The drains of the two MOS transistors G11 and G12 are connected to the input terminal IN and the output terminal OUT respectively. Another ten resistors RG are connected in series to form a group and connected to the source connection of MOS transistors G11 and MOS transistors G12 to lead to the output terminal OUT. The two groups of resistors are connected in series. The linear buffer board (14) realizes a gradual increase in impedance by sequentially turning off the resistors, and includes a time-delayed opening circuit, a buffer board absorption circuit, and a multi-stage buffer circuit; the time-delayed opening circuit is composed of a diode DK2, a voltage regulator tube VDK3, transistors PK3-PK4 and QK3-QK4, resistors RK7-11, capacitors CK2 and CP4, the resistor RK7 and the diode DK2 are connected in parallel and then connected to the capacitor CK2, one end of the resistor RK7 is connected to the voltage regulator tube VDK3, and the voltage regulator tube VDK3 is connected to the transistor QK3 The base of transistor QK3 is connected to one end of resistor RK8, and the other end of resistor RK8 is connected to analog ground. The collector of transistor QK3 is connected to resistor RK9, and one end of resistor RK9 is connected to the base of transistor PK3. The emitter of transistor PK3 is connected to the power supply terminal VDD. The collector of transistor PK3 is connected to resistor RK10, and the other end of resistor RK10 is connected in series with resistor RK11. One end of resistor RK11 is connected to the base of transistor QK4 and transistor PK4, and the other end is connected to analog ground. The emitter of the transistor is connected to the emitter of the transistor PK4, and the middle connection leads to the contact K2. The capacitor CP4 is connected in series between the power supply end and the ground end. The high level VDD drives the transistor QK3 through the voltage regulator tube VDK3 to open the drive switch group; the buffer board absorption circuit is composed of a resistor RH and a MOS tube GH. One hundred and one resistors RH are connected in series to form a group. One end of the parallel lead wire of the three groups of resistors RH is connected to the IN contact and the other end is connected to the drain of the MOS tube GH. The source of the MOS tube GH is connected to the analog ground GND. The MOS tube G The gate of H is connected in series with eleven resistors RQH, which lead to eleven contacts S1~S11; the multi-stage buffer circuit is used to withstand high-voltage impacts, and is composed of eleven diodes DKS, voltage-stabilizing diodes VDU1~VDU5, resistor RK12 and capacitor CK3. Eleven diodes DKS1~DKS11 are connected between contacts S~S11, a diode DKS1 is connected between contacts S and S1, a capacitor CK3 is connected between contact S1 and the analog ground, and a resistor RK12 is connected between contact S and the analog ground.

2. The full sea depth withstand voltage electronic switch according to claim 1, characterized in that: The PWM wave generating circuit includes diodes DP1 to DP4, resistors RT1 and RP1, capacitors CT1 and CE3, and a half-bridge driver U1; the first pin of resistor RT1 is respectively connected to the Vout pin of the three-terminal regulator E1, the K pin of diode DP3, the high-side floating power supply pin and the power supply VCC pin of the half-bridge driver U1, the K pin of diode DP1, and the first pin of capacitor CE3; the A pin of diode DP3 is connected to the K pin of diode DP4 and the low-side output pin of the half-bridge driver U1; the first pin of capacitor CE3 is connected to the second pin of resistor RT1 and the oscillation pin of the half-bridge driver U1, and the second pin is respectively connected to the current detection input pin, the power supply GND pin, and the floating voltage feedback pin of the half-bridge driver U1, as well as the A pin of diode DP4, the A pin of diode DP2, the second pin of capacitor CE3, and AGND; the K pin of diode DP2 is connected to the A pin of diode DP1, the high-side output pin of the half-bridge driver U1, and the first pin of resistor RE3.

3. The full-sea-depth voltage-resistant electronic switch according to claim 2, characterized in that: The control drive signal conditioning circuit includes voltage regulator tubes VDK1-VDK2, PNP transistors PK1-PK2, NPN transistors QK1-QK2, isolation transformer T1, resistors RK1-RK5 and resistors RP2-RP3, capacitors CP1-CP3 and capacitor CK1 and diodes DP5-DP8; the first pin of the source side of the isolation transformer T1 is connected to the second pin of the resistor RP1, and the second pin of the source side of the isolation transformer T1 is connected to the low-side output pin of the half-bridge driver U1; The third pin of the secondary side of the isolation transformer T1 is connected to the A pin of the diode DP7 and the K pin of the diode DP8; The fourth pin of the secondary side of the isolation transformer T1 is connected to the A pin of the diode DP5 and the K pin of the diode DP6; the first pin of the resistor RP2 is connected to the K pin of the diode DP5, the K pin of the diode DP7, the first pin of the capacitor CP1, the K pin of the voltage regulator VDK1, the emitter of the transistor PK1 and the collector of the transistor QK2; the second pin of the resistor RP2 is connected to the A pin of the diode DP6, the A pin of the diode DP8, the second pin of the capacitor CP1, the first pin of the resistor RK1, the emitter of the transistor QK1, the first pin of the resistor RK5 and the collector of the transistor PK2; the A pin of the voltage regulator VDK1 is connected to the voltage regulator VDK2 The A pin of the resistor RK3 is connected to the base of the transistor PK1, the first pin of the capacitor CK1, the second pin of the resistor RK1 and the first pin of the resistor RK2; the second pin of the resistor RK2 is connected to the base of the transistor QK1; the K pin of the voltage regulator VDK2 is respectively connected to the second pin of the capacitor CK1, the collector of the transistor PK1 and the first pin of the resistor RK4; the second pin of the resistor RK4 is respectively connected to the second pin of the resistor RK5, the base of the transistor QK2 and the base of the transistor PK2; the first pin of the resistor RK3 is connected to the base of the transistor PK1, and the second pin is connected to the collector of the transistor QK1, the first pin of the capacitor CP2 is connected to VDD, the second pin of the capacitor CP3 is connected to GND, and the resistor RP3 is connected in parallel with the capacitors CP2 and CP3.

4. The full sea depth withstand voltage electronic switch according to claim 3, characterized in that: The isolation transformer T1 is an on-board planar isolation transformer.

5. The full sea depth withstand voltage electronic switch according to claim 1, 2, 3 or 4, characterized in that: The resistors, capacitors, diodes, MOS tubes and triodes are all solid plastic-sealed devices.

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