Drive circuit

Abstract

The purpose is to provide a technology capable of properly driving an IGBT. A drive circuit drives the IGBT by controlling the gate voltage of the IGBT and has a first charging capability and a second charging capability. The first charging capability is the ability to increase the gate voltage to the threshold voltage of the IGBT, while the second charging capability is the ability to increase the gate voltage beyond the threshold voltage. The gate voltage increase per unit time achieved by the first charging capability is greater than the gate voltage increase per unit time achieved by the second charging capability.

Description

Technical Field

[0001] The present invention relates to a driving circuit. Background Art

[0002] Various technologies have been proposed for a drive circuit that drives an IGBT (Insulated Gate Bipolar Transistor) by controlling its gate voltage. For example, Patent Document 1 proposes a technology that causes the gate voltage to rise gradually rather than sharply.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-181973

[0004] However, there is a problem that if the gate voltage is gradually increased from the beginning to the end of the IGBT's conduction, the conduction time becomes longer. Summary of the Invention

[0005] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technology capable of appropriately driving an IGBT.

[0006] The drive circuit according to the present invention is a drive circuit for driving an IGBT by controlling the gate voltage of the IGBT. The drive circuit has a first charging capability for increasing the gate voltage to a threshold voltage of the IGBT and a second charging capability for increasing the gate voltage by exceeding the threshold voltage. The increase in the gate voltage per unit time achieved by the first charging capability is greater than the increase in the gate voltage per unit time achieved by the second charging capability.

[0007] Effects of the Invention

[0008] According to the present invention, the gate voltage rise per unit time achieved by the first charging capability is greater than the gate voltage rise per unit time achieved by the second charging capability. With such a configuration, the IGBT can be driven appropriately. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a diagram showing the structure of a semiconductor device according to the first embodiment.

[0010] Figure 2 This is a diagram for explaining the operation of the IGBT drive circuit according to the first embodiment.

[0011] Figure 3 A diagram showing the structure of a semiconductor device according to a second embodiment.

[0012] Figure 4This is a diagram for explaining the operation of the IGBT drive circuit according to the second embodiment.

[0013] Figure 5 A diagram showing the structure of a semiconductor device according to a third embodiment.

[0014] Figure 6 This is a diagram for explaining the operation of the IGBT drive circuit according to the third embodiment. DETAILED DESCRIPTION

[0015] Below, with reference to the attached Figure 1 The following embodiments are described. The features described in the following embodiments are examples, and not all features are required. In addition, in the following description, the same or similar reference numerals are used for the same structural elements in multiple embodiments, and the different structural elements are mainly described.

[0016] <Implementation Method 1>

[0017] Figure 1 This is a diagram showing the structure of a semiconductor device according to the first embodiment. Figure 1 The semiconductor device includes an IGBT (Insulated Gate Bipolar Transistor) 1 and a gate driver 2. The IGBT 1 and gate driver 2 can be made of conventional silicon (Si) or wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond. When the IGBT 1 and gate driver 2 are made of wide-bandgap semiconductors, stable operation at high temperatures and high voltages and increased switching speed are achieved.

[0018] The IGBT 1 is included in, for example, an inverter (not shown) capable of changing the current frequency.

[0019] 1, when the gate voltage of the IGBT 1 rises sharply, the voltage V between the collector and emitter of the IGBT 1 CE (Hereinafter sometimes referred to as “V CE ”) slowed down.

[0020] The gate driver 2 is, for example, an IC (Integrated Circuit). The gate driver 2 includes an IGBT drive circuit 3. The IGBT drive circuit 3 is a drive circuit that drives the IGBT 1 by controlling the gate voltage of the IGBT 1.

[0021] Figure 2 1 is a diagram for explaining the operation of the IGBT drive circuit 3 according to the first embodiment when the IGBT 1 is turned on. Figure 2The gate charging capability (current) of the IGBT driving circuit 3 for charging the gate of the IGBT 1 and the voltage V between the collector and emitter of the IGBT 1 are shown in FIG. CE and the collector current I of IGBT 1 C (Hereinafter sometimes referred to as “I C ”). In addition, the gate charging capability is substantially equivalent to the gate voltage of IGBT 1.

[0022] The IGBT drive circuit 3 has a first charging capability for increasing the gate voltage of the IGBT 1 to a threshold voltage Vth (hereinafter sometimes simply referred to as "Vth") of the IGBT 1 and a second charging capability for increasing the gate voltage of the IGBT 1 beyond the threshold voltage Vth. Figure 2 As shown in FIG. 1 , the gate voltage rise per unit time achieved by the first charging capability is greater than the gate voltage rise per unit time achieved by the second charging capability. Figure 2 In FIG, the increases in the first charging capacity and the second charging capacity are represented by straight lines, but the present invention is not limited thereto. As long as the above-mentioned relationship is satisfied, the increases may be represented by, for example, curved lines.

[0023] Here, if Figure 2 The gate charging capability is shown by the thin double-dashed line. From the beginning to the end of the conduction of IGBT 1, the gate voltage rises sharply. Figure 2 V CE As shown by the thin double-dashed line, V CE The decline of the conduction loss becomes slower and larger.

[0024] On the other hand, if the gate charging capability is as shown by the thick double-dashed line, the gate voltage rises gently from the beginning to the end of the conduction of the IGBT 1. Figure 2 V CE As shown by the solid line, V CE The fall time becomes faster, but the conduction time becomes longer.

[0025] In contrast, according to the semiconductor device of the first embodiment, the gate voltage rises sharply before the gate voltage exceeds Vth, and after the gate voltage exceeds Vth, the gate voltage rises gently by ramp driving. CE As a result, for example, the dead time of the inverter including the IGBT 1 can be suppressed.

[0026] As a structure that performs an operation opposite to that of the semiconductor device according to the first embodiment, a structure is conceivable in which the gate voltage is gradually increased before the gate voltage exceeds Vth, and the gate voltage is rapidly increased after the gate voltage exceeds Vth. However, compared with this structure, the semiconductor device according to the first embodiment can accelerate the V CE Therefore, according to the first embodiment, for V CE and the on-time, the IGBT 1 can be driven appropriately.

[0027] <Implementation Method 2>

[0028] Figure 3 This figure shows the structure of a semiconductor device according to the second embodiment. Hereinafter, components of the second embodiment that are identical or similar to the components described above are denoted by identical or similar reference numerals, and the description will focus primarily on the different components. In the following description, a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is referred to as "PMOS," and an N-type MOSFET is referred to as "NMOS."

[0029] exist Figure 3 In the example shown in FIG. 1 , the IGBT drive circuit 3 includes an inverter 3a (a NOT gate), a constant current circuit 3b, a first transistor (a PMOS transistor) 3c, and a second transistor (an NMOS transistor) 3d. Furthermore, the IGBT drive circuit 3 includes an internal power supply circuit 3e, a capacitor 3f, a third transistor (an NMOS transistor) 3g, and a fourth transistor (an NMOS transistor) 3h.

[0030] The inverter 3 a outputs L (Low) when the input signal IN is H (High), and outputs H when the input signal IN is L.

[0031] A first terminal of constant current circuit 3b is connected to power supply Vcc. A second terminal of constant current circuit 3b is connected to a first terminal of PMOS 3c. A second terminal of PMOS 3c is connected to a first terminal of NMOS 3d. A second terminal of NMOS 3d is grounded. The gates of PMOS 3c and NMOS 3d are connected to the output of inverter 3a.

[0032] The internal power supply circuit 3e is connected in parallel with the constant current circuit 3b. The internal power supply circuit 3e has a current sourcing function for supplying current to the point B, but does not have a current sinking function for drawing current from the point B.

[0033] A first end of the capacitor 3f is connected to a connection point between the PMOS 3c and the NMOS 3d, and a second end of the capacitor 3f is grounded.

[0034] The first terminal of NMOS 3g is connected to the first terminal of constant current circuit 3b, the second terminal of NMOS 3g is connected to the first terminal of NMOS 3h, and the second terminal of NMOS 3h is grounded. The gate of NMOS 3g is connected to the connection point of PMOS 3c and NMOS 3d and the first terminal of capacitor 3f, and the gate of NMOS 3h is connected to the output of inverter 3a.

[0035] A signal at the connection point between the NMOS 3g and the NMOS 3h is used as the output signal OUT of the IGBT drive circuit 3 . The output signal OUT defines the first charging capability and the second charging capability described in the first embodiment.

[0036] In the above IGBT drive circuit 3, a pair of PMOS 3c and NMOS 3d outputs an intermediate signal ( ) generated by the internal power supply circuit 3e, the constant current circuit 3b and the capacitor 3f based on the output of the inverter 3a corresponding to the input signal IN. Figure 3 The voltage at point C is measured. A pair of NMOS transistors 3g and 3h outputs an output signal OUT based on the output of inverter 3a corresponding to input signal IN and the intermediate signal. While details will be described later, the rise rate per unit time of the intermediate signal implemented by internal power supply circuit 3e is greater than that implemented by constant current circuit 3b and capacitor 3f, and the rise rate ends at an earlier timing.

[0037] A snubber circuit 4 is provided between the IGBT 1 and the IGBT drive circuit 3. The snubber circuit 4 charges the gate of the IGBT 1 based on the output signal OUT. If the NMOS 3g and the NMOS 3h have sufficient charging capacity (current), the snubber circuit 4 is not required.

[0038] Figure 4 This is a diagram for explaining the operation of the IGBT drive circuit 3 according to the second embodiment.

[0039] If at time t1, the input signal IN changes from L to H, then Figure 3 The voltage at point A becomes L, PMOS 3c is turned on, NMOS 3d is turned off, and NMOS 3h is turned off. As a result, the output voltage of the internal power supply circuit 3e makes the intermediate signal ( Figure 3The voltage at point C of the internal power supply circuit 3e rises, and the NMOS 3g is turned on. The output voltage of the internal power supply circuit 3e causes the intermediate signal to rise sharply, so the output signal OUT rises sharply, and the gate voltage of the IGBT 1 also rises sharply to Vth.

[0040] Between time t1 and time t2, Figure 3 At point C, the capacitor 3f is charged at a rate determined by the constant current from constant current circuit 3b and the capacitance of capacitor 3f. The waveform of the intermediate signal becomes a gently rising ramp waveform. Consequently, the waveforms of output signal OUT and the gate voltage of IGBT 1 also become ramp waveforms. At time t2 and thereafter, the intermediate signal, output signal OUT, and the gate voltage of IGBT 1 become H.

[0041] If at time t3, the input signal IN changes from H to L, then Figure 3 The voltage at point A becomes high, PMOS 3c turns off, NMOS 3d turns on, and NMOS 3h turns on. In conjunction with this, NMOS 3g turns off, and the intermediate signal, output signal OUT, and gate voltage of IGBT 1 become low.

[0042] According to the second embodiment as described above, the IGBT drive circuit 3 having the first charging capability and the second charging capability described in the first embodiment can be realized.

[0043] <Implementation Method 3>

[0044] Figure 5 1 is a diagram showing the structure of a semiconductor device according to Embodiment 3. Hereinafter, components according to Embodiment 3 that are identical or similar to the above components are denoted by identical or similar reference numerals, and the description will focus on the different components.

[0045] In the second embodiment, it is somewhat difficult to adjust the voltage when switching from the first charging capability to the second charging capability to the threshold voltage Vth. In contrast, as described below, according to the third embodiment, switching from the first charging capability to the second charging capability can be performed easily and accurately.

[0046] Figure 5 The IGBT drive circuit 3 is to Figure 3 The IGBT drive circuit 3 is further provided with a comparator 3i, a comparison voltage 3j and an NMOS 3k.

[0047] The inverting input (-) of comparator 3i is connected to the output of IGBT drive circuit 3, and the non-inverting input (+) of comparator 3i is connected to comparison voltage 3j. Comparison voltage 3j corresponds to threshold voltage Vth of IGBT 1. One end of NMOS 3k is connected to the output of internal power supply circuit 3e, and the other end of NMOS 3k is connected to the connection point between constant current circuit 3b and PMOS 3c. The gate of NMOS 3k is connected to the output of comparator 3i. With the above structure, comparator 3i is configured to control the output of internal power supply circuit 3e based on the comparison result between output signal OUT of IGBT drive circuit 3 and comparison voltage 3j.

[0048] Figure 6 This is a diagram for explaining the operation of the IGBT drive circuit 3 according to the third embodiment. Figure 6 The actions at time t1, t2, and t3 are respectively Figure 4 The actions at times t1, t2, and t3 are the same.

[0049] When, at time t4, the output signal OUT becomes equal to the comparison voltage 3j, which corresponds to the threshold voltage Vth of the IGBT 1, the comparator 3i turns off the NMOS 3k. Consequently, the waveforms of the intermediate signal, the output signal OUT, and the gate voltage of the IGBT 1 at and after time t4 become ramp waveforms.

[0050] According to the third embodiment described above, the comparator 3i controls the output of the internal power supply circuit 3e based on the output signal OUT of the IGBT drive circuit 3, thereby enabling easy and precise switching from the first charging capability to the second charging capability.

[0051] Furthermore, the embodiments and modifications can be freely combined, or the embodiments and modifications can be appropriately modified or omitted.

[0052] Description of the label

[0053] 1IGBT, 3IGBT drive circuit, 3b constant current circuit, 3c PMOS, 3d, 3g, 3h NMOS, 3e internal power supply circuit, 3f capacitor, 3i comparator.

Claims

1. A driving circuit for driving an IGBT by controlling a gate voltage of the IGBT, wherein: The drive circuit has a first charging capability for increasing the gate voltage to a threshold voltage of the IGBT and a second charging capability for increasing the gate voltage beyond the threshold voltage, wherein an increase in the gate voltage per unit time achieved by the first charging capability is greater than an increase in the gate voltage per unit time achieved by the second charging capability. The driving circuit has: Internal power circuit; constant current circuit; capacitors; a set of a first transistor and a second transistor configured to output an intermediate signal generated by the internal power supply circuit, the constant current circuit, and the capacitor based on an input signal; as well as a set of a third transistor and a fourth transistor that output an output signal that specifies the first charging capacity and the second charging capacity based on the input signal and the intermediate signal; The rise time per unit time of the intermediate signal achieved by the internal power supply circuit is greater than the rise time per unit time of the intermediate signal achieved by the constant current circuit and the capacitor, and ends at an earlier timing.

2. The driving circuit according to claim 1, wherein: A comparator is further provided, which controls the output of the internal power supply circuit based on the output signal.

3. The driving circuit according to claim 1 or 2, wherein: The IGBT is included in an inverter.

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