System-on-Chip and Transaction Processing

Abstract

On-chip system and transaction processing are disclosed. According to one aspect, an on-chip system is provided, which includes: a master device; a slave device; a clock configured to clock-control the operations of the slave device; a clock controller configured to activate or deactivate the clock and / or a power-on controller, the power-on controller being configured to turn on / off the slave device; a control system configured to detect that the clock is deactivated and / or the slave device is powered off when the master device issues an access request to the slave device, the master device being configured to activate the clock when the control system detects that the clock is deactivated and / or power on the slave device when the control system detects that the slave device is powered off, and then issue a new access request to the slave device.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Application No. 2012752, filed on December 7, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to systems-on-chip, and in particular embodiments, to methods for managing transactions between master and slave devices. Background Art

[0004] A system-on-chip (also referred to as a system on a chip) is a complete system embedded on a chip, which may include, for example, one or more processors, memories, interface peripherals, or other components necessary to perform complex functions.

[0005] A system-on-chip typically includes a hierarchical architecture. In particular, a system-on-chip includes devices referred to as "master" and "slave" devices. The master device issues read or write access requests to the slave device.

[0006] For example, the master device is an electronic component such as a processor or a direct memory access controller (also abbreviated as "DMA").

[0007] The slave device can be a storage memory or a network peripheral. The system-on-chip also includes a clock that the slave device can use to operate.

[0008] The interconnection between the host and the slave is typically handled by an internal computer bus compatible with one or more communication protocols.

[0009] In particular, the Advanced Microcontroller Bus Architecture (AMBA) protocol family is known and is a widely used communication standard today, especially by systems-on-chip.

[0010] In the protocol family, a transaction between a master device and a slave device includes an access request from the master device to the slave device, followed by a response from the slave device to the master device.

[0011] In particular, the master device is programmed to wait for a response from the slave device after issuing a request. As long as the master device does not receive a response from the slave device, the code executed by the master device can be paused. If the response does not arrive, the user has no choice but to restart the system-on-chip.

[0012] In addition, a system-on-chip can be used in some applications that require low power consumption. For example, a system-on-chip embedded in an object that can be used in the Internet of Things (IoT) or a mobile phone may require low power consumption.

[0013] Known solutions for reducing the power consumption of a system-on-chip are to deactivate (i.e., turn off) the clock of the slave device and the system-on-chip operating with it when the slave device is not in use. Then, the deactivation and activation of the clock are controlled by software programming by entering the state of each clock in the registers of the clock controller of the system-on-chip. In addition, to reduce the energy consumption, the slave device can also be turned off, especially by resetting the slave device.

[0014] However, for such a solution, a programming error of the master device may lead to the risk of blocking the master device. In particular, there is a risk that the master device will be programmed to issue an access request to the slave device when the clock for the operation of the slave device is deactivated or when the slave device is powered off. Then, it is impossible for the slave device to generate a response to the request from the master device. Then the execution of the code by the master device is blocked and cannot continue. Then the user has to restart the system-on-chip.

[0015] Therefore, it is advantageous to provide a system-on-chip that is configured to avoid blocking the master device when the master device issues an access request to the slave device and the clock for the operation of the slave device is deactivated or when the slave device is powered off. SUMMARY OF THE INVENTION

[0016] According to one aspect, there is provided a system-on-chip including a master device, a slave device, a clock, and a clock controller. The master device is configured to issue an access request to the slave device. The clock is configured to clock the operation of the slave device. The clock controller is configured to activate or deactivate the clock. The system-on-chip may optionally include a power-on controller configured to power on or power off the slave device. The system may further include a control system configured to detect that the clock is deactivated and / or the slave device is powered off when the master device issues an access request to the slave device. The master device is configured to: activate the clock in the clock controller and / or activate the power-on of the slave device in the power-on controller when the control system detects that the clock is deactivated, and then issue a new access request to the slave device.

[0017] Preferably, the system-on-chip includes several slave devices and multiple clocks. Then each slave device operates using its respective clock.

[0018] Such a system-on-chip allows avoiding blocking when waiting for a response from the master device, when the master device issues an access request to a slave device whose clock is deactivated and / or powered off. In fact, such a system-on-chip is configured to activate the clock used by the slave device operation and / or power on the slave device if an access request to the slave device is issued when the clock is deactivated and / or when the slave device is powered off. Then, the master device is configured to issue a new access request to the slave device. Therefore, even if there is a programming error of the master device due to forgetting to activate the clock before issuing an access request to the slave device, a correct response can be generated from the slave device. The user does not have to restart the system-on-chip.

[0019] In an advantageous embodiment, the control system includes: a detection circuit configured to detect whether the clock is deactivated and / or detect whether the slave device is powered off when the master device issues an access request to the slave device; a collector circuit configured to store the slave devices to which the master device has issued an access request when the clock for the operation of the slave device is deactivated and / or the slave device is powered off.

[0020] When the system-on-chip includes several slave devices, the control system may include as many detection circuits as there are slave devices. Then the detection circuits are associated with each slave device. Optionally, it is possible to have one detection circuit for several slave devices, especially when these slave devices are clocked with the same clock and can be powered off, for example, by resetting them with the same signal.

[0021] In an advantageous embodiment, the collector circuit is configured to issue an interruption to the master device when the detection circuit detects that the clock is deactivated.

[0022] Preferably, the master device is configured to access the collector circuit after receiving the interruption issued by the collector circuit in order to know the slave devices to which the master device has issued an access request when the clock for the operation of the slave device is deactivated and / or when the slave device is powered off.

[0023] Advantageously, the master device is connected to the slave device via a bus.

[0024] In an advantageous embodiment, the detection circuit is configured to receive access requests from the master device and, when the clock for the operation of the slave device is activated and the slave device is powered on, send these access requests to the slave device and send the responses from the slave device to the master device. This can be done by the detection circuit without slowing down the frequency used for transactions.

[0025] In particular, the detection circuit can be connected to the master device via a bus and directly connected to the slave device.

[0026] Advantageously, the clock controller includes a register for storing the activation state of the clock and / or the power-on controller includes a register for storing the power-on state of the slave device.

[0027] And wherein, the master device is configured to change the clock activation state in the clock controller register and / or the power-on state of the slave device in the power-on controller.

[0028] Preferably, the detection circuit is configured to receive the clock activation state from the clock controller and / or the power-on state of the slave device from the power-on controller.

[0029] Advantageously, the detection circuit is configured to generate an error message and send it to the master device when it detects that the clock is deactivated and / or the slave device is powered off when the master device issues an access request to the slave device.

[0030] According to another aspect, a method for managing transactions between a master device and a slave device in a system-on-chip is provided, the method comprising: issuing an access request from the master device to the slave device, the slave device operating using a clock, detecting, by a control system, a deactivated state of the clock stored in a clock controller and / or a powered-off state of the slave device stored in a power-on controller, activating, by the master device, the clock in the clock controller if the deactivated state of the clock is detected, and / or activating, by the master device, the power-on of the slave device in the power-on controller if the powered-off state of the slave device is detected, and then issuing a new access request from the master device to the slave device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other advantages and features of the present disclosure will become apparent upon examination of the detailed description of the embodiments and examples, which are in no way limiting, as well as the detailed description of the drawings, wherein:

[0032] Figure 1 is a schematic diagram of an example system-on-chip;

[0033] Figure 2 is a schematic diagram of an example detection circuit;

[0034] Figure 3 is a diagram of an example collector circuit;

[0035] Figure 4 is a flowchart of an example method; and

[0036] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 are schematic diagrams of an example system-on-chip. DETAILED DESCRIPTION

[0037] Figure 1 Illustrates a system-on-chip (SP) according to an embodiment of the present disclosure.

[0038] The system-on-chip (SP) includes a master device (MM). The master device (MM) can be an electronic component such as a processor or a direct memory access controller (DMA). The system-on-chip (SP) also includes several slave devices (ME1), (ME2), (ME3), and (ME4). Each slave device (ME1), (ME2), (ME3), and (ME4) can be, for example, a storage memory or a network peripheral. Here, the system-on-chip (SP) includes four slave devices. However, a system-on-chip with a number of slave devices less than or greater than four can be provided according to the present disclosure. An identifier is associated with each slave device (ME1), (ME2), (ME3), and (ME4).

[0039] Each slave device also includes an input configured to receive power-on signals (RST1), (RST2), (RST3), and (RST4). Each power-on signal allows the slave device to power on or off. The input of each slave device can be an input that resets the slave device according to the received power-on signal. Thus, the power-on signal can be a reset signal. In particular, its power can be turned off while keeping the slave device reset. When the slave device is powered off, the slave devices (ME1), (ME2), (ME3), and (ME4) cannot respond to requests from the master device.

[0040] The system-on-chip (SP) also includes a bus (BS) that allows each slave device (ME1), (ME2), (ME3), and (ME4) to be connected to the master device (MM).

[0041] The master device (MM) is configured to be able to issue access requests to the slave devices (ME1), (ME2), (ME3), and (ME4). These access requests can be sent to the slave devices (ME1), (ME2), (ME3), and (ME4) via the computer bus (BS).

[0042] The access device is further configured to generate responses to the access requests from the master device (MM). These responses can be transmitted to the master device (MM) via the computer bus (BS).

[0043] The system-on-chip is preferably compatible with the Advanced Microcontroller Bus Architecture (AMBA) protocol family.

[0044] The system-on-chip also includes several clocks (CLK1), (CLK2), (CLK3), and (CLK4). Each slave device (ME1), (ME2), (ME3), and (ME4) is connected to its associated clock (CLK1), (CLK2), (CLK3), and (CLK4) to clock-control its operation on that clock.

[0045] In an embodiment, each of the clocks (CLK1), (CLK2), (CLK3), and (CLK4) allows clock control of the operations of the slaves (ME1), (ME2), (ME3), and (ME4), and is associated therewith when the clock is in an active state.

[0046] In addition, when the clock is in an inactive state, each of the clocks (CLK1), (CLK2), (CLK3), and (CLK4) does not allow clock control of the operations of the slaves (ME1), (ME2), (ME3), and (ME4) associated therewith. Then, the slaves (ME1), (ME2), (ME3), and (ME4) cannot generate responses to requests from the master device.

[0047] The system-on-chip (SP) further includes a clock and power-on controller (RCC). In an embodiment, the power-on controller (RCC) includes a plurality of registers, as Figure 1 shown in the form of a table. The registers of the power-on controller (RCC) are configured to store the status (CLKEN) of each of the clocks (CLK1), (CLK2), (CLK3), and (CLK4) associated with the slaves (ME1), (ME2), (ME3), and (ME4).

[0048] The registers of the power-on controller (RCC) are also configured to store the status (RST) of each of the power-on signals (RST1), (RST2), (RST3), and (RST4) associated with each slave.

[0049] Here, the system includes a single power-on controller (RCC) for storing the status of the clocks and the power-on status of the slaves. Optionally, a first controller for storing only the status of the clocks and a second controller for storing only the power-on status of the slaves may be provided.

[0050] In addition, the master device (MM) is configured to write to and change the status (CLKEN) of each of the clocks (CLK1), (CLK2), (CLK3), and (CLK4) in the registers of the power-on controller (RCC), and to write to and change the status (RST) of each of the power-on signals (RST1), (RST2), (RST3), and (RST4) in the registers of the power-on controller (RCC).

[0051] The system-on-chip (SP) further includes a control system (SC). The control system (SC) is used to prevent blocking of the master device (MM) when access requests are issued to the slaves (ME1), (ME2), (ME3) in cases where the clocks (ME1), (ME2), (ME3), and (ME4) for slave operation are deactivated and / or when the slaves are powered off.

[0052] In an embodiment, a control system (SC) is used to prevent blocking of a master device (MM) caused by programming errors of the master device (MM). More specifically, the programming errors include issuing access requests to slave devices whose associated clocks are deactivated and / or to slave devices that are powered off. The master device (MM) waits for a response to each issued access request. If no response arrives at it because the clock associated with the slave device targeted by the access request is deactivated and / or the slave device is powered off, the master device (MM) will not be able to advance the execution of its code. The master device (MM) will be blocked.

[0053] The control system (SC) includes a plurality of detection circuits (DET1), (DET2), (DET3), and (DET4) respectively associated with slave devices (ME1), (ME2), (ME3), and (ME4).

[0054] The detection circuits (DET1), (DET2), (DET3), and (DET4) are respectively inserted between the slave devices (ME1), (ME2), (ME3), and (ME4) and the master device (MM).

[0055] Figure 2 An embodiment detection circuit that can be used, for example, in a Figure 1 system-on-chip is shown. Each detection circuit (DET1), (DET2), (DET3), and (DET4) includes a first input / output (IO1) connected to a computer bus (BS). The first input / output (IO1) is configured to receive an access request (RQ) from the master device (MM) for the slave device associated with the detection circuit and send the response (RE) of the slave device to the master device.

[0056] Each detection circuit (DET1), (DET2), (DET3), and (DET4) also includes a second input / output (IO2) connected to the slave device associated with the detection circuit. The second input / output (IO2) is configured to send the access request (RQ) from the master device (MM) to the slave device associated with the detection circuit and receive the response (RE) of the slave device to the access request of the master device.

[0057] Each detection circuit (DET1), (DET2), (DET3), and (DET4) also includes an input (I1) connected to a power-on controller (RCC) to receive the status (CLKEN) of the clock associated with the slave device associated with the detection circuit.

[0058] Each detection circuit (DET1), (DET2), (DET3), and (DET4) also includes an input (I2) connected to the clock and power-on controller (RCC) to receive the status (RST) of the slave device associated with the detection circuit.

[0059] Each detection circuit (DET1), (DET2), (DET3), and (DET4) also includes an input (ACLK) and an input (ARST). The input (ACLK) is configured to receive a clock signal that permits clock control of the operation of the detection circuit, and the input (ARST) is configured to receive a reset signal to reset the detection circuit.

[0060] Each detection circuit also includes an output (O1).

[0061] Each detection circuit is configured to detect whether the clock associated with the slave device associated with the detection circuit is deactivated when the master device issues an access request to the slave device. In an embodiment, the deactivation status of the clock stored in the register of the power-on controller (RCC) is sent to the detection circuit so that when the master device issues an access request, the detection circuit can know whether the clock is deactivated.

[0062] Each detection circuit is also configured to detect whether the slave device associated with the detection circuit is powered off when the master device issues an access request to the slave device. In particular, the power-off status of the slave device stored in the register of the power-on controller (RCC) is sent to the detection circuit so that when the master device issues an access request, the detection circuit can know whether the slave device is powered off.

[0063] In addition, each detection circuit (DET1), (DET2), (DET3), and (DET4) is configured to generate an error message, and then when the detection circuit detects that the clock is deactivated and / or the slave device is powered off when the master device issues an access request to the slave device, the error message is sent by the first input / output (IO1) to the master device. When the clock associated with the slave device is deactivated and / or the slave device is powered off, the error message prevents the master device from being blocked while waiting for a response from the slave device.

[0064] In addition, each detection circuit (DET1), (DET2), (DET3), and (DET4) is configured to signal to the collector circuit (CL) of the control system (SC), that is, to issue an access request to the slave device associated with the detection circuit when the clock associated with the slave device is deactivated and / or the slave device is powered off. To this end, each detection circuit is configured to issue a signaling message (MS) using its output (O1) coupled to the collector circuit (CL). In an embodiment, the output (O1) is directly connected to the collector circuit (CL).

[0065] The control system (SC) also includes Figure 3The collector circuit (CL) shown. The collector circuit (CL) includes an input / output (IO3) connected to a computer bus (BS). The collector circuit (CL) also includes an input (BCLK) configured to receive a clock signal that allows clock control of the operation of the collector circuit; and an input (BRST) configured to receive a reset signal to reset the collector circuit.

[0066] The collector circuit (CL) also includes at least one input (I3) connected to an output (O1) of a detection circuit to receive a signaling message (MS). The collector circuit (CL) also includes an output (O2) connected to a master device (MM). The collector circuit (CL) also includes a number of registers. The collector circuit (CL) is configured to store, in its registers, the slave devices for which the master device has issued access requests when the clocks used by the slave devices are deactivated and / or when the slave devices are powered off.

[0067] In an embodiment, when the collector circuit (CL) receives a signaling message from a detector device, the collector circuit (CL) is configured to store, in its registers, the identifier of the slave device associated with the detector device.

[0068] In addition, the collector circuit (CL) is also configured to generate an interrupt to alert the master device (MM) when it receives a signaling message from the detection circuit. The interrupt is issued by the output (O2). Accordingly, the master device (MM) is configured to receive the interrupt generated by the collector circuit (CL).

[0069] Once the master device (MM) receives the interrupt from the collector circuit (CL), the master device (MM) is configured to read the registers of the collector circuit (CL) to determine the slave device targeted by the access request when the clock for the operation of the slave device is deactivated and / or when the slave device is powered off.

[0070] In an embodiment, the master device (MM) is also configured to change the state of each clock and / or change the power-on state in the registers of a power-on controller (RCC).

[0071] In an embodiment, the master device (MM) is configured to update its access request to the slave device once the clock used by the slave device is activated and the slave device is powered on.

[0072] Figure 4 A method for managing transactions between a master device and slave devices is shown. In step 20, the master device issues an access request to a slave device. In step 21, a detection circuit associated with the slave device receives the access request from the master device. In step 22, the detection circuit detects whether the clock associated with the slave device is active or deactivated, and / or whether the slave device is powered on or off.

[0073] Specifically, the detection circuit retrieves the status of the clock associated with the slave device and the power-on status associated with the slave device from the registers of the power-on controller (RCC).

[0074] If the detection circuit detects that the clock is activated and the slave device is powered on, at step 23, the detection circuit sends an access request to the slave device.

[0075] At step 24, the slave device receives the access request and generates a response that it sends to the detection circuit.

[0076] At step 25, the detection circuit receives the response from the slave device and sends it to the master device.

[0077] At step 26, the master device receives the response from the slave device, and the transaction ends.

[0078] In addition, if the detection circuit detects clock deactivation and / or slave device power-off at step 22, the transaction management method includes step 27. In this step 27, the detection circuit generates an error message that is sent to the master device (MM). The detection circuit also generates a signaling message that is sent to the collector circuit.

[0079] Then, at step 28, the collector circuit receives the signaling message from the detection circuit and stores the identifier of the slave device. In addition, the collector circuit generates an interrupt and sends it to the master device.

[0080] When the master device receives the interrupt at step 29, the master device then accesses the registers of the collector circuit to identify the slave device that issued an access request when the clock associated with the slave device was deactivated and / or when the slave device was powered off.

[0081] Once the slave device is identified, at step 30, the master device activates the clock associated with the slave device and / or activates the power-on of the slave device in the clock and power-on controller.

[0082] When the clock associated with the slave device is subsequently activated and when the slave device is powered on, the master device can request access to the slave device again while ensuring that a correct response is received from the slave device.

[0083] Therefore, the transaction management method can then start again at step 20, where the master device issues a new access request to the slave device.

[0084] Figures 5 to 9 illustrated by Figure 1 An example of implementing the transaction management method by the on-chip system shown.

[0085] In one or more embodiments, the clocks are initially activated and the slave devices are powered on. Thus, for each clock, the value of the register associated with the state of each clock of the power-on controller (RCC) is 1 to indicate that these clocks are activated. Thus, for each slave device, the value of the register associated with the power-on state of the slave device of the power-on controller (RCC) is 1 to indicate that these slave devices are powered on.

[0086] In Figure 5 , the master device deactivates the clocks (CLK3) and (CLK4) associated with the devices (ME3) and (ME4) in the clock controller register to reduce the power consumption of the system-on-chip. Thus, the value of the register of the power-on controller (RCC) associated with the clocks (CLK3) and (CLK4) related to the devices (ME3) and (ME4) switches to 0 to indicate that these clocks are deactivated.

[0087] In addition, the master device (MM) issues an access request to the slave device (ME1) to retrieve data from the slave device (ME1). When the clock (CLK1) associated with the slave device (ME1) is activated and the slave device (ME1) is powered on, the master device (MM) receives data from the slave device (ME1). For example, the data can be useful data or instructions.

[0088] Then, the master device (MM) performs calculations using the data and then issues another access request to the slave device (ME2) to write the result to the slave device (ME2). When the clock (CLK2) associated with the slave device (ME2) is activated and the slave device (ME2) is powered on, the data can be written to the slave device (ME2).

[0089] Then, the master device (MM) wishes to perform calculations based on the data recorded in the slave devices (ME1) and (ME3). Thus, as Figure 6 shown, the master device (MM) issues an access request to the slave device (ME1) to retrieve data from the slave device (ME1). When the clock (CLK1) associated with the slave device (ME1) is activated and the slave device (ME1) is powered on, the master device (MM) receives data from the slave device (ME1).

[0090] In addition, the master device (MM) issues an access request to the slave device (ME3) to retrieve data from the slave device (ME3). However, before issuing the access request to the slave device (ME3), a programming error occurs and the clock (CLK3) associated with the slave device (ME3) is not reactivated. Thus, the slave device (ME3) cannot send data to the master device in response to the access request. The master device (MM) is blocked waiting for a response to its access request.

[0091] Then, the detection circuit (DET3) detects that an access request to the slave device (ME3) is issued when the clock (CLK3) associated with the slave device (ME3) is disabled. In an embodiment, the detection circuit (DET3) knows the status (CLKEN) of the clock (CLK3) by retrieving the status (CLKEN) of the clock (CLK3) from the clock controller register associated with the clock.

[0092] Then, in response to the access request, the detection circuit (DET3) sends an error message to the master device (MM) to unblock the master device (MM).

[0093] The collector circuit (CL) records the identifier of the slave device (ME3) in a register.

[0094] Then, as Figure 7 shown, the collector circuit (CL) issues an interrupt to the master device. Then, the master device (MM) reads the register of the collector circuit (CL) to identify the slave device that issued an access request to it when the clock associated with the slave device was disabled. Thus, the master device retrieves the identifier of the slave device (ME3) from the collector circuit.

[0095] Then, as Figure 8 shown, the master device (MM) activates the clock (CLK3) associated with the slave device (ME3) in the power-on controller (RCC). The value of the register associated with the clock then switches to 1 to indicate that the clock is active.

[0096] Then, when the clock (CLK3) associated with the slave device (ME3) and the clock (CLK1) associated with the slave device (ME1) are activated, and the slave devices (ME1) and (ME3) are powered on, the master device can again request access to the two slave devices (ME1) and (ME3) to perform the required calculations while ensuring correct responses are received from the two slave devices.

[0097] Thus, as Figure 9 shown, the master device issues an access request to the slave device (ME1) to retrieve data from the slave device (ME1). When the clock (CLK1) associated with the slave device (ME1) is activated and the slave device (ME1) is powered on, the master device (MM) receives data from the slave device (ME1).

[0098] In addition, the master device issues an access request to the slave device (ME3) to retrieve data from the slave device (ME3). When the clock (CLK3) associated with the slave device (ME3) is activated and the slave device (ME3) is powered on, the master device (MM) receives data from the slave device (ME3).

[0099] Then, the master device can perform the required calculations based on the data retrieved from the slave device (ME1) and the slave device (ME3).

[0100] Of course, the present disclosure is susceptible to many variations and modifications, which will be apparent to those skilled in the art. For example, it is possible to have one detection circuit for several slave devices, especially when these slave devices are clocked with the same clock and can be switched off together, e.g., by resetting them with the same reset signal.

[0101] Although the description has been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In the different figures, the same elements are designated with the same reference numerals. Additionally, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, as those of ordinary skill in the art will readily understand from the present disclosure that processes, machines, manufactures, compositions of matter, devices, methods, or steps that exist currently or will be developed later can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, devices, methods, or steps within their scope.

[0102] Therefore, the specification and the drawings are simply regarded as illustrations of the present disclosure as defined by the appended claims, and are expected to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.

Claims

1. A system on a chip, comprising: a slave device; a master device, coupled to the slave device, the master device being configured to issue a first access request to the slave device; a clock circuit, coupled to the slave device, the clock circuit being configured to clock the operation of the slave device; a clock controller, coupled to the slave device, the clock controller being configured to activate or deactivate the clock circuit; a power-on controller, coupled to the slave device, the power-on controller being configured to power on or power off the slave device; and a control system, configured to generate an interruption based on determining that the clock circuit is deactivated or the slave device is powered off, and wherein the master device is further configured to: in response to receiving the interruption, activate the clock circuit based on the control system determining that the clock circuit is deactivated, in response to receiving the interruption, power on the slave device based on the control system determining that the slave device is powered off, and after the clock circuit is activated or the slave device is powered on, issue a second access request to the slave device.

2. The system on a chip according to claim 1, wherein the control system comprises: a detection circuit, configured to, in response to the master device issuing the first access request: determine whether the clock circuit is deactivated, or determine whether the slave device is powered off; and a collector circuit, configured to, in response to the master device issuing the first access request, store in a register of the collector circuit the slave device to which the master device has issued the first access request, the storing being based on the clock signal for operating the slave device being in a deactivated state, the slave device being powered off, or a combination thereof.

3. The system on a chip according to claim 2, wherein the collector circuit is further configured to: issue the interruption to the master device based on the detection circuit determining that the clock circuit is deactivated.

4. The system on a chip according to claim 3, wherein the master device is further configured to: access the collector circuit after having received the interruption issued by the collector circuit to determine the corresponding slave device to which the master device has issued the first access request, the determination being based on the corresponding clock used by the corresponding slave device being deactivated, the corresponding slave device being powered off, or a combination thereof.

5. The system on a chip according to claim 2, wherein the detection circuit is configured to: receive an access request from the master device; transmit the access request to the slave device; and based on a corresponding clock, transmit a response from the slave device to the master device, the corresponding clock being for the slave device being set to an active state and the slave device being powered on.

6. The system-on-chip according to claim 2, wherein the clock controller includes registers for storing the activation state of each clock, and the power-on controller includes registers for storing the power-on state of the slave device, and the master device is further configured to: change the activation state of the clock circuit in the registers of the clock controller, the power-on state of the slave device in the power-on controller, or a combination thereof.

7. The system-on-chip according to claim 6, wherein the detection circuit is further configured to: receive the activation state of the clock circuit from the clock controller, the power-on state of the slave device from the power-on controller, or a combination thereof.

8. The system-on-chip according to claim 2, wherein the detection circuit is further configured to: generate an error message and transmit the error message to the master device in response to detecting that the clock circuit is deactivated, detecting that the slave device is powered off in response to the master device sending the first access request to the slave device, or a combination thereof.

9. The system-on-chip according to claim 1, further comprising a bus configured to couple the master device to the slave device.

10. A method for operating a system-on-chip, comprising: having the system-on-chip including a master device and a slave device, wherein the operation of the system-on-chip is clocked by a clock circuit; sending, by the master device, a first access request to the slave device, generating, by a control system, an interruption based on determining the deactivation state of the clock circuit stored in a clock controller, the power-off state of the slave device stored in a power-on controller, or a combination thereof; activating, by the master device, the clock circuit stored in the clock controller based on receiving the interruption and determining that the clock circuit is in the deactivation state of the clock circuit; activating, by the master device, the power-on state of the slave device in the power-on controller based on receiving the interruption and determining that the slave device is in the power-off state; and sending, by the master device, a second access request to the slave device after the clock circuit is activated, the slave device is powered on, or a combination thereof.

11. The method according to claim 10, further comprising: determining, in response to the master device sending the first access request, whether the clock circuit is deactivated; determining, in response to the master device sending the first access request, whether the slave device is powered off; and storing, in a register of a collector circuit, the slave device for which the master device has sent the first access request, the storing being based on the clock signal by which the slave device operates being in the deactivation state, the slave device being powered off, or a combination thereof, the storing in response to the master device sending the first access request.

12. The method according to claim 11, further comprising sending the interruption to the master device based on determining that the clock circuit is deactivated.

13. The method according to claim 12 further includes, after receiving the interruption sent by the collector circuit, the master device accessing the collector circuit to determine a corresponding slave device to which the master device has sent the first access request, the determination being based on the corresponding clock used by the corresponding slave device for operation being deactivated, the corresponding slave device being powered off, or a combination thereof.

14. The method according to claim 11 further includes: receiving, by a detection circuit, an access request from the master device; transmitting, by the detection circuit, the access request to the slave device; and transmitting, by the detection circuit, a response from the slave device to the master device based on a corresponding clock, the corresponding clock being for the slave device being set to an active state and the slave device being powered on.

15. An apparatus including a system-on-chip, the system-on-chip including: a slave device; a master device coupled to the slave device, the master device being configured to send a first access request to the slave device; a clock circuit coupled to the slave device, the clock circuit being configured to clock the operation of the slave device; a clock controller coupled to the slave device, the clock controller being configured to activate or deactivate the clock circuit; a power-on controller coupled to the slave device, the power-on controller being configured to power on or power off the slave device; and a control system configured to generate an interruption based on determining that the clock circuit is deactivated or the slave device is powered off, and wherein the master device is further configured to: activate the clock circuit based on the control system determining that the clock circuit is deactivated in response to receiving the interruption; power on the slave device based on the control system determining that the slave device is powered off in response to receiving the interruption; and send a second access request to the slave device after the clock circuit is activated or the slave device is powered on.

16. The apparatus according to claim 15, wherein the control system includes: a detection circuit configured to, in response to the master device sending the first access request: determine whether the clock circuit is deactivated, or determine whether the slave device is powered off; and a collector circuit configured to, in response to the master device sending the first access request, store in a register of the collector circuit the slave device to which the master device has sent the first access request, the storage being based on the clock signal used by the slave device for operation being in a deactivated state, the slave device being powered off, or a combination thereof.

17. The apparatus according to claim 16, wherein the collector circuit is further configured to send the interruption to the master device based on the detection circuit determining that the clock circuit is deactivated.

18. The apparatus according to claim 17, wherein the master device is further configured to: after receiving the interruption issued by the collector circuit, access the collector circuit to determine a corresponding slave device for which the master device has issued the first access request, the determination being based on the corresponding clock used by the corresponding slave device being deactivated, the corresponding slave device being powered off, or a combination thereof.

19. The apparatus according to claim 17, wherein the detection circuit is configured to: receive an access request from the master device; transmit the access request to the slave device; and based on a corresponding clock, transmit a response from the slave device to the master device, the corresponding clock being for the slave device being set to an active state and the slave device being powered on.

20. The apparatus according to claim 17, wherein the clock controller includes a register for storing the activation state of each clock, and the power-on controller includes a register for storing the power-on state of the slave device, and the master device is further configured to change the activation state of the clock circuit in the register of the clock controller, the power-on state of the slave device in the power-on controller, or a combination thereof.

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