Buried power rail contact formation

Abstract

Embodiments of the invention relate to a method of forming a semiconductor product, the method comprising: providing a substrate comprising a buried power rail; forming a sacrificial plug at a contact surface on the buried power rail; applying a front end of line module for forming a device in the semiconductor substrate; providing a via through layers applied by the front end of line module connecting the sacrificial plug on the buried power rail; selectively removing the sacrificial plug thereby obtaining a cavity above the buried power rail; filling the cavity with a metal to electrically connect the device with the buried power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than the area of a cross section of the via parallel to the contact surface.

Description

Invention Field

[0001] This invention relates to embedded power rails. More specifically, this invention relates to the formation of contact with embedded power rails. Background of the Invention

[0002] The power rails used to supply power to the transistors of a chip are typically implemented at the back end of the line.

[0003] To create more wiring possibilities for interconnects, embedded power rails (BPRs) can be applied before the front-end module.

[0004] However, given the resistivity of these contacts, especially with the continuous reduction in critical dimensions, establishing electrical contact with these embedded power rails is extremely challenging.

[0005] For example, the via connection VBPR (via connection to BPR) between the metallization layer M0 and BPR can be scaled to a bottom CD of 10-15 nm and beyond in iN3. This has raised significant concerns about its resistivity and its impact on device performance.

[0006] Figure 1 A schematic vertical cross-sectional view of a semiconductor product stack is shown, illustrating BPR 110 in iN3. In this figure, vias (VBPRs) are connected to the BPRs. It can be seen that a reduced CD will result in a reduced contact surface area between the VBPRs and the BPRs. This could even lead to a reduction in the width of the VBPR to less than 12 nm. Adjacent 5T standard (std) cells with a width of 90 nm are shown in the figure. Metal interconnects are shown at the top of the figure. In this example, the sum of the width of the metal interconnects and the distance between the two metal interconnects is equal to 18 nm. In this example, the BPR is formed in a Si substrate 105. Oxide 107 is present between the BPR and the substrate 105.

[0007] Given that resistivity decreases as the critical size decreases, there is a need to provide a method that can provide good electrical connection between embedded power layers and vias. Summary of the Invention

[0008] One object of the present invention is to provide a good method for electrical contact BPR.

[0009] The above-mentioned objectives are achieved by the method and apparatus described in this invention.

[0010] Embodiments of the present invention relate to a method for forming a semiconductor product, the semiconductor product including embedded contacts with embedded power rails.

[0011] The method includes the following steps:

[0012] -Provides semiconductor substrates including embedded power rails.

[0013] - A sacrificial plug is formed at the contact surface on the embedded power rail.

[0014] - Application front-end modules are used to form devices in semiconductor substrates.

[0015] - Provides through-holes that pass through the layers applied to the front-end module, connecting to sacrificial plugs on the embedded power rails.

[0016] - Selectively remove the sacrificial plug to create a cavity above the embedded power rail.

[0017] - A cavity is filled with metal to electrically connect the device to an embedded power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than the area of ​​the cross section of the through-hole parallel to the contact surface.

[0018] The advantage of embodiments of the present invention is that the resistivity of the connection between the via and the BPR is reduced by providing a sacrificial plug at the contact surface before applying the front-end module and by replacing the sacrificial plug with metal.

[0019] One advantage of embodiments of the present invention is that the contact surface area between the through-hole and the BPR can be increased, and it is not limited by the bottom critical size of the through-hole.

[0020] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claim and other dependent claims, and not merely those expressly stated in the claims.

[0021] These and other aspects of the invention will be disclosed and illustrated with reference to the embodiments described below. Attached Figure Description

[0022] Figure 1 A schematic diagram of a vertical cross-section of a semiconductor product stack is shown, illustrating an embedded power rail.

[0023] Figure 2 A schematic diagram of an intermediate product obtained by forming a sacrificial plug on an embedded power rail is shown according to an embodiment of the present invention.

[0024] Figure 3 A schematic diagram of an intermediate product obtained after through-hole etching landing on an embedded plug, according to an embodiment of the present invention, is shown.

[0025] Figure 4 A schematic diagram of an intermediate product obtained after the removal of an embedded plug, according to an embodiment of the present invention, is shown.

[0026] Figure 5 A schematic diagram of an intermediate product obtained after replacing an embedded sacrificial plug with metal, according to an embodiment of the present invention, is shown.

[0027] Figure 6 A top view of the semiconductor device obtained after conventional through-hole landing is shown.

[0028] Figure 7 A top view of a semiconductor device obtained using a method according to an embodiment of the present invention is shown, wherein the length of the bottom contact of the via extends to the entire width of the embedded power rail.

[0029] Figure 8 A top view of a semiconductor device obtained by a method according to an embodiment of the present invention is shown, and... Figure 6 Compared to the width of the through hole in the figure, the bottom contact of the through hole in this figure has an extended width.

[0030] Figure 9 A top view of a semiconductor device obtained using a method according to an embodiment of the present invention is shown, wherein the bottom contact of a via is shared between two vias.

[0031] Figure 10 A flowchart of an exemplary method according to an embodiment of the present invention is shown.

[0032] Figure 11 A cross-section of an intermediate product obtained using a method according to an embodiment of the present invention is shown.

[0033] Figure 12 A cross-section of an intermediate product obtained using a method according to an embodiment of the invention is shown, wherein the plug liner is deposited prior to the embedded power rail liner.

[0034] Figure 13 A cross-section of an intermediate product obtained using a method according to an embodiment of the invention is shown, wherein an embedded power rail gasket is deposited prior to a plug gasket.

[0035] Any reference numerals in the claims should not be construed as limiting the scope of the invention.

[0036] In different figures, the same reference numerals denote the same or similar elements. Detailed Implementation

[0037] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto, except by the claims. The drawings described are merely illustrative and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions described do not correspond to the actual reductions in practice with respect to the invention.

[0038] Furthermore, in the specification and claims, terms such as "top" and "below" are used for descriptive purposes and not necessarily to describe relative positions. It should be understood that such terms are interchangeable where appropriate, and embodiments of the invention can operate in orientations other than those described or illustrated herein.

[0039] It should be noted that the term "comprising" as used in the claims should not be construed as being limited to the portion listed thereafter, and does not exclude other elements or steps. Therefore, it should be understood as indicating the presence of the stated feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or combinations thereof. Thus, the scope of the expression "device comprising components A and B" should not be limited to devices consisting solely of components A and B. It indicates that, for the present invention, the relevant components of the device are only A and B.

[0040] The phrase "one embodiment" or "one implementation" used in the specification means that a specific feature, structure, or characteristic, together with the description of the embodiment, is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in one implementation" appearing throughout the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art.

[0041] Similarly, it should be understood that in the description of exemplary embodiments of the invention, different features of the invention are sometimes combined into a single embodiment, drawing, or description thereof in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, the methods in this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than expressly referenced in the claims. Furthermore, as reflected in the appended claims, inventive aspects may include fewer features than all the features of a single embodiment of the foregoing disclosure. Therefore, the appended claims are explicitly incorporated into this specific description, and each claim itself represents an independent embodiment of the invention.

[0042] Furthermore, when some embodiments described herein include, but are not included in, other features included in other embodiments, combinations of features from different embodiments are intended to be included within the scope of the invention and to form different embodiments, as will be understood by those skilled in the art. For example, any embodiment claimed in the appended claims may be used in any combination.

[0043] Numerous specific details are set forth in this description. However, it should be understood that embodiments of the invention may be implemented without these specific details. In other instances, well-known methods, structures, and techniques have not been described in detail to avoid obscuring the understanding of this specification.

[0044] Embodiments of the present invention relate to a method for forming a semiconductor product, the semiconductor product including embedded contacts with embedded power rails.

[0045] An exemplary flowchart according to an embodiment of the present invention is shown in Figure 10 The image shown is for illustrative purposes only.

[0046] The method according to embodiments of the present invention includes at least the following steps:

[0047] - Provides a semiconductor substrate 210 including an embedded power rail 110,

[0048] - A sacrificial plug 120 is formed at the contact surface 130 on the embedded power rail 110.

[0049] - An application of a 230-line front-end module for forming device 140 in a semiconductor substrate.

[0050] - Provides a 240 through-hole 150 that passes through the layer applied to the front-end module and connects to the sacrificial plug 120 on the embedded power rail 110.

[0051] - Selectively remove the 250 sacrificial plug 120 to create a cavity above the embedded power rail.

[0052] - The cavity 260 is filled with metal 160 to electrically connect device 140 to embedded power rail 110, wherein sacrificial plug 120 is formed such that the contact surface area is larger than the area of ​​the cross section of the through hole 150 parallel to the contact surface.

[0053] Figure 2 A schematic diagram of an intermediate product according to an embodiment of the invention is shown, obtained by forming a sacrificial plug (also known as an embedded plug) 120 on the liner 130 after BPR metal recess and after deposition of the liner 130. A device 140 that can be formed by FEOL processing is also shown in the figure.

[0054] Figure 3 A schematic diagram of an intermediate product obtained after VBPR etching landing on an embedded plug 120 according to an embodiment of the present invention is shown.

[0055] Figure 4A schematic diagram of an intermediate product obtained after removal of the implanted plug, according to an embodiment of the present invention, is shown. In an embodiment of the invention, only the implanted plug 120 may be removed, or the implanted plug 120 and the gasket 130 on top of the BPR may be removed.

[0056] In embodiments of the present invention, the obtained cavity may be filled with metal. Figure 5 A schematic diagram of an intermediate product obtained after replacing an embedded sacrificial plug with metal 160, according to an embodiment of the present invention, is shown. Two through-holes are shown in the diagram. The left through-hole 150 contacts the BPR through the metal replacing the embedded plug. Therefore, a larger contact area is obtained than the right through-hole, which is a conventional through-hole in direct contact with the BPR. An advantage of this embodiment of the invention is that after replacing the plug with VBPR metal, the contact surface between the VBPR and BPR can be expanded to the entire BPR CD.

[0057] In embodiments of the present invention, the 250 sacrificial plug 120 can be removed by wet or isotropic selective etching.

[0058] In an embodiment of the invention, amorphous silicon is used to form a 220 sacrificial plug 120.

[0059] In an embodiment of the invention, amorphous carbon (APF) is used to form (220) sacrificial plug 120.

[0060] In an embodiment of the invention, a sacrificial plug is formed at the location of the through-hole BPR landing area on top of the BPR.

[0061] The step of forming a 220 sacrificial plug 120 at the contact surface 130 on the embedded power rail 110 may be followed by an oxide filling step and a shallow trench isolation (STI) chemical mechanical polishing step, followed by a conventional FEOL module.

[0062] Next, in an embodiment of the present invention, VBPR landing is achieved on an amorphous plug.

[0063] In an embodiment of the present invention, the contact surface 130 may be the surface of the BPR itself.

[0064] In an embodiment of the present invention, the contact surface 130 may be a pad.

[0065] In an embodiment of the invention, a 220 sacrificial plug 120 is formed after the recess of the embedded power rail metal and after the deposition of the liner 130 on the embedded power rail, and wherein the liner 130 is removed after the removal of the 250 sacrificial plug and before the 260 cavity is filled with metal.

[0066] In an embodiment of the invention, the liner 131 may be deposited after the formation of the 220 sacrificial plug.

[0067] The pads 130 and 131 embedded in the power rails or on the sacrificial plug, also known as BPR pads, can protect the BPR metal surface from oxidation during STI oxide annealing.

[0068] BPR pad 130 can be removed by wet or isotropic selective etching.

[0069] The VBPR is connected to the BPR by filling the cavity. An advantage of this embodiment of the invention is that the contact surface with the BPR can be significantly enlarged compared to conventional through-holes.

[0070] In embodiments of the present invention, the cavity can be filled with metal using atomic layer deposition (ALD) or metal-to-metal selective deposition to completely fill the cavity formed after plug removal. The remaining portion can also be filled using ALD or metal-to-metal selective deposition.

[0071] Alternatively, the remaining portion can be filled using conventional chemical vapor deposition (CVD).

[0072] The metal can be, for example, W, Co, Ru, Mo, or a combination of these metals. However, the invention is not limited thereto.

[0073] Region-selective deposition may be more attractive for cavity filling because it is bottom-up and has fewer barriers. Region-selective deposition allows for selective deposition, metal-to-metal, and bottom-up cavity filling.

[0074] exist Figure 5 In the example, instead, a barrier layer 180 is formed by ALD deposition. In practice, in the ALD case, a thin barrier layer must be deposited before metal deposition. ALD barrier layers such as Ti / TiN / TaN can be used for ALD W / Co / Ru deposition.

[0075] In metal-to-metal selective deposition, such as W or Ru, the deposition of the barrier layer can be skipped, which can significantly reduce the resistivity of metal / metal contact. Figure 5 The diagram illustrates the stack obtained after applying metal lines (MOAs) (e.g., in the middle of a circuit layer) and metal interconnects (MINTs) (e.g., at the rear of a circuit layer). In the example, vias interconnect the metal lines (MOAs) with the BPRs.

[0076] Figure 6 A top view of the semiconductor device obtained after conventional through-hole landing is shown. Figure 6A 5-track standard cell (90nm) with a metal interconnect pitch of 18nm is shown. In this example, the polycrystalline pitch CPP of the contacts is 42nm. The metal interconnect (MINT) corresponds to the first metal layer (horizontal). Hash block 190 shows the available space for VBPR 150 in the standard cell. It can be seen from this figure that the bottom CD of the contact between via 150 and BPR 110 is smaller than the top CD. In this example, the available space for VBPR in the standard cell is 12-18nm, the CPP is 42nm, and the gate length is 14nm.

[0077] Figure 7 and Figure 8 A top view of a semiconductor device obtained using a method according to an embodiment of the present invention is shown.

[0078] exist Figure 7 In the diagram, the bottom contact 160 of the VBPR (i.e., the cavity filled with metal) has a length extending across the entire width of the BPR 110, for example, from 12-18 nm to 24-48 nm. A via 150 lands on the bottom contact 160 of the VBPR. As can be seen from the diagram, a significantly larger bottom contact CD than the top CD can be obtained. Furthermore, it is advantageous for the Y CD (this is the dimension orthogonal to the BPR and parallel to the substrate) to be self-aligned with the BPR. This is because the bottom Y CD of the VBPR is the same as the top metal CD of the BPR.

[0079] Also in Figure 8 In this configuration, the through-hole 150 lands on the VBPR bottom contact 160. Compared to the contact width of a prior art through-hole, the VBPR bottom contact 160 has an extended bottom contact. For example... Figure 8 As shown, the bottom contact width of the VBPR can even extend beyond the polycrystalline spacing CPP of the contact, for example, from 12-18 nm to 30-50 nm. In this example, the nanosheet NS is illustrated.

[0080] The plug area can be defined, for example, by photolithography. For example, the area can be the same as that of a MOA CD.

[0081] In embodiments of the present invention, two adjacent VBPRs may share the same via bottom contact, which allows for further extension of the via bottom contact (e.g., more than 50 nm). Figure 9 A top view of a semiconductor device obtained using a method according to an embodiment of the present invention is shown, wherein a via bottom contact 160 is shared between two vias 150. In an embodiment of the invention, the via bottom contact 160 is buried beneath a gate 165. In an embodiment of the invention, the VBPR can be self-aligned with the gate.

[0082] In embodiments of the invention, the plug height may be limited by the BPR CD. In embodiments of the invention, depending on the BPR CD in the design, the plug may, for example, have a height between 12 and 24 nm or between 12 and 48 nm. It may, for example, have a height of 20 nm.

[0083] In embodiments of the invention, the VBPR metal can be made, for example, of W, Co, Mo, or Ru, or a combination of these metals. The RMG gate can be made, for example, of TiN, TaN, W, or TiAlC. The MOA can be made, for example, of W, Co, Mo, or Ru. The BPR can be made, for example, of W, Co, Mo, or Ru.

[0084] The inventors have discovered a process flow capable of reducing the resistivity of the via-to-BPR contact. This process flow can be integrated into standard process flows, which may include, for example, well implantation, fin formation and STI, formation of buried power rails, fin exposure, gate and spacer formation, source and drain epitaxial growth, activation annealing, ILD0, metal gate replacement, MOA, MOG, and MIV0 as steps in FEOL.

[0085] One advantage of the method according to embodiments of the invention is that a buried plug is formed before the contact hole (i.e., the via). In embodiments of the invention, the sacrificial plug can be formed by photolithography. By using the method according to embodiments of the invention, self-aligned contacts can be obtained. This is crucial for technologies with small CDs (e.g., 3nm nodes). Because self-aligned contacts are obtained by forming the buried plug before the via, the aspect ratio of the via etching can be reduced compared to methods that cannot achieve self-alignment.

[0086] Embedded power rails can be used, for example, to interconnect standard units and / or distribute power to standard units.

[0087] In embodiments of the invention, a plug liner can be deposited first, followed by a BPR liner. This is... Figure 10 and Figure 11 It is displayed in the middle.

[0088] Alternatively, in embodiments of the invention, a BPR liner can be deposited first, followed by a plug liner. This is in Figure 12 As shown in the image.

[0089] Figure 10 The top schematic diagram shows a cross-section of an intermediate product obtained using the method according to an embodiment of the present invention. The top cross-section is orthogonal to BPR 110. The bottom cross-section is taken along BPR (i.e., in the length direction of BPR and orthogonal to substrate 105).

[0090] In this example, substrate 10 is a silicon substrate. The upper left cross-section shows BPR 110 obtained after the BPR metal recess. BPR 110 includes metal in a trench of substrate 105. The walls of the trench are covered with oxide 107. STI oxide 107 is also shown in the figure. Fin 106 is shown between the STI oxide and the trench.

[0091] The second figure from the left shows the intermediate product obtained after depositing the plug liner PL (e.g., oxide) and the plug material 120 (e.g., aSi or APF). In embodiments of the invention, depending on the plug material and the type of BPR metal, the plug liner PL may be skipped.

[0092] In embodiments of the invention, a BPR liner (e.g., SiO2) can be deposited instead of a plug liner at this process stage. The BPR liner deposition step can be followed by a plug material deposition step (e.g., aSi or APF). It should be noted that in the case of using a SiN BPR liner, it may be more difficult to remove the sacrificial plug after removal. No mask is required.

[0093] The third image from the top left shows a schematic diagram of the intermediate stack obtained after chemical mechanical polishing (CMP) of the plug and after etch-back of plug 120. The corresponding image below this figure shows a cross-section of the same intermediate stack cut along BPR.

[0094] Similar to Figure 10 , Figure 11 The upper figure shows a cross-section of the intermediate stack orthogonal to the BPR, and the lower figure shows a corresponding cross-section along the BPR, wherein the intermediate stack is obtained using a method according to an embodiment of the present invention.

[0095] The first image from the left shows the intermediate stack obtained after patterning the sacrificial plug 120. This can be achieved through photolithography / etching patterning and can be self-aligned with the BPR width (e.g., by blockprinting, defining the size of the sacrificial plug and landing it on the BPR).

[0096] The intermediate figure shows an intermediate stack obtained after BPR pad (BPRL) deposition according to an embodiment of the present invention. The BPR pad can be, for example, a SiN pad.

[0097] The right figure shows an intermediate stack obtained after STI oxide filling 108 and CMP according to an embodiment of the present invention. Starting from such a stack, by applying the method steps according to an embodiment of the present invention, a... Figure 5 Stacked bodies in the middle.

[0098] Figure 12The figures illustrate an intermediate stack in the case of depositing a BPR liner BPRL prior to the deposition of the liner PL. The top cross-section is orthogonal to the BPR 110. The bottom cross-section is taken along the BPR (i.e., along the length of the BPR and orthogonal to the substrate). The first figure from the left shows the intermediate stack obtained after patterning the sacrificial plug. This can be achieved via photolithography / etching patterning and can be self-aligned with the width of the BPR (e.g., by engraving, defining the dimensions of the sacrificial plug and landing it on the BPR liner).

[0099] The second figure from the left shows an intermediate stack obtained after PL deposition of a plug liner according to an embodiment of the invention. The plug liner can be, for example, a SiN liner or a SiO liner. However, a plug liner is not strictly required.

[0100] The right figure shows an intermediate stack obtained after STI oxide filling and CMP according to an embodiment of the present invention.

Claims

1. A method (200) for forming a semiconductor product, said semiconductor product including embedded contacts with embedded power rails, said method comprising: - Provides (210) a semiconductor substrate including an embedded power rail (110), - A sacrificial plug (120) is formed (220) at the contact surface (130) on the embedded power rail (110). - Application (230) line front-end module for forming device (140) in semiconductor substrate, - Provides a (240) through-hole (150) that passes through the layer applied to the front-end module and connects to the sacrificial plug (120) on the embedded power rail (110). - Selectively remove (250) the sacrificial plug (120) to create a cavity above the embedded power rail. - The cavity (260) is filled with metal (160) to electrically connect the device (140) to the embedded power rail (110), wherein the sacrificial plug (120) is formed such that the contact surface area is larger than the area of ​​the cross section of the through hole (150) parallel to the contact surface.

2. The method (200) as described in claim 1, wherein, The sacrificial plug (120) (250) was removed by wet etching.

3. The method (200) as described in claim 1, wherein, The sacrificial plug (120) was removed by isotropic selective etching (250).

4. The method (200) according to any one of claims 1 to 3, wherein, Amorphous silicon is used to form (220) sacrificial plugs (120).

5. The method (200) according to any one of claims 1 to 3, wherein, Amorphous carbon is used to form (220) sacrificial plugs (120).

6. The method (200) according to any one of claims 1 to 3, wherein, A (220) sacrificial plug (120) is formed after the recess of the embedded power rail metal and after the pad is deposited on the embedded power rail, and wherein the pad is removed after the (250) sacrificial plug is removed and before the (260) cavity is filled with metal.

7. The method (200) according to any one of claims 1 to 3, wherein, A liner (131) is deposited after the formation of the (220) sacrificial plug (120).

8. The method (200) as described in any one of claims 1 to 3, wherein, The cavity is filled with metal (160) by using regional selective deposition.

9. The method (200) according to any one of claims 1 to 3, wherein, The cavity is filled with metal (160) by metal-to-metal selective deposition.

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