Chip packaging method and chip packaging unit

Abstract

The present invention provides a chip packaging method and a chip packaging unit. The chip packaging method comprises: providing a wafer having a plurality of bumps; dicing the wafer into a plurality of chips, and covering the chips on a substrate, wherein a plurality of vertical heat-conducting structures are provided on the wafer or chips; and providing a packaging material to encapsulate the sides of each chip and the bottom surface of each chip facing the substrate to form each chip packaging unit. In the chip packaging unit, the bumps on the chip abut against the substrate, and the vertical heat-conducting structures are connected to the substrate through a plurality of through-holes in the substrate or directly to the substrate.

Description

Technical Field

[0001] The present invention relates to a chip packaging method, and more particularly to a chip packaging method that generates a plurality of vertical heat-conducting structures by wiring to enhance the heat dissipation capability of the chip. Background Art

[0002] In the prior art, referring to Figure 1 , which shows the chip package structure of U.S. Patent No. 9,984,992. It includes two chips. The lower chip CH is mounted on a substrate 110 and located within a Faraday cage surrounded by multiple bonding wires 100, forming an internal electromagnetic protection structure. The bonding wires 100 are mounted on the substrate 110, connected to the circuits within the substrate 110, and are then encapsulated by a packaging material 120, providing protection against electromagnetic interference.

[0003] Reference Figure 2 , which shows the chip packaging structure of US Patent No. US 9812402. Figure 1 , Figure 2 The wires 100 surround and form a Faraday cage, and the wires 100 are connected to the circuits in the base material 110 to form an electromagnetic interference protection design.

[0004] Also refer to Figure 3 , which shows the chip package structure of U.S. Patent No. 7,355,289. To enhance heat conduction from the chip CH, multiple bonding wires 100 are formed on the chip CH to improve heat dissipation. The bonding wires 100 are exposed outside the packaging material 120 above the chip CH. While this design takes heat dissipation into account, the bonding wires 100 are far from the base plate, resulting in a small exposed area and limited heat dissipation. Furthermore, the chip CH is limited to wire bond lead connections, which restricts its application.

[0005] In view of the existing technology, the present invention provides a chip packaging technology, which has the advantages of good heat dissipation capability, easy manufacturing, and wide application range. Summary of the Invention

[0006] From one perspective, the present invention provides a chip packaging method to address the aforementioned issues. This chip packaging method comprises: providing a wafer having a plurality of bumps; dicing the wafer into a plurality of chips, and covering the chips on a substrate, wherein a plurality of vertical heat-conducting structures are disposed on the wafer or chips; and providing a packaging material to encapsulate the sides of each chip and the bottom surface of each chip facing the substrate to form a plurality of chip packaging units. In the chip packaging units, the bumps on the chip abut against the substrate, and the vertical heat-conducting structures are connected to the substrate through a plurality of through-holes in the substrate or directly to the substrate.

[0007] In some embodiments, the steps of cutting a wafer into multiple chips, setting the chips on a substrate, and setting a vertical heat-conducting structure on the wafer or the multiple chips cut from the wafer can be implemented in different ways as needed: cutting the wafer into multiple chips, then setting multiple vertical heat-conducting structures on each chip, and then covering each chip on the substrate; or setting multiple vertical heat-conducting structures on the wafer, then cutting the wafer into multiple chips, wherein each chip includes multiple vertical heat-conducting structures, and then covering each chip on the substrate; or cutting the wafer into multiple chips, then covering each chip on the substrate, and then setting multiple vertical heat-conducting structures on each chip to connect to the substrate.

[0008] In one embodiment, the vertical heat-conducting structure is a wire produced by wire bonding on a wafer, and the vertical heat-conducting structure is formed by straightening the wire in a vertical direction. In one embodiment, the vertical heat-conducting structure is disposed on a non-connective pad on the wafer.

[0009] In one embodiment, the chip and the substrate are connected by a flip chip wire connection method. In one embodiment, the substrate is a lead frame.

[0010] From one perspective, the present invention provides a chip packaging unit comprising: a lead frame; a chip comprising a plurality of bumps and a plurality of vertical heat-conducting structures, the bumps and the vertical heat-conducting structures being located on the same side of the chip, the chip being disposed on the lead frame, the vertical heat-conducting structures being connected to the lead frame via a plurality of through holes in the lead frame or being directly connected thereto; and a packaging material encapsulating the side edges of the chip and the bottom surface of the chip facing the lead frame.

[0011] The following detailed description is made through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 、 Figure 2 、 Figure 3 A schematic diagram showing a chip packaging structure in the prior art.

[0013] Figures 4A to 4F A schematic diagram showing a chip packaging method according to an embodiment of the present invention is shown.

[0014] Figures 5A to 5F A schematic diagram showing a chip packaging method according to another embodiment of the present invention is shown.

[0015] Figure 6A 、 Figure 6B Schematic diagram showing a chip packaging unit according to an embodiment of the present invention

[0016] Explanation of symbols in the figure

[0017] 10, 20: Chip packaging unit

[0018] 100: Wire

[0019] 110: Base material

[0020] 120: Packaging materials

[0021] 130: Bump

[0022] 140: Vertical heat conduction structure

[0023] CH: Chip

[0024] WF: wafer DETAILED DESCRIPTION

[0025] The drawings in the present invention are schematic diagrams, mainly intended to illustrate the relationship between various circuit components, and the shapes and sizes are not drawn according to scale.

[0026] Figures 4A to 4E An embodiment of the present invention is shown. The chip packaging method according to the present invention includes: providing a wafer WF, the wafer WF includes a plurality of bumps 130 ( Figure 4A ); Then, multiple chips CH cut from the wafer WF ( Figure 4B ), multiple vertical heat conducting structures 140 ( Figure 4C ), and then cover the chip CH on a substrate 110 ( Figure 4D ); and then providing a packaging material 120 to package the side of each chip CH and the bottom surface of each chip CH facing the substrate 110 to form a plurality of chip packaging units 10 ( Figure 4E In the chip package unit 10, the bumps 130 on the chip CH abut against the substrate 110, and the vertical heat-conducting structure 140 passes through a plurality of through holes in the substrate 110 or is directly connected to the substrate 110. Each chip CH includes at least one bump 130.

[0027] Figures 5A to 5E Another embodiment of the present invention is shown. The chip packaging method of the present invention includes: providing a wafer WF, the wafer WF includes a plurality of bumps 130 ( Figure 5A ); Afterwards, a plurality of vertical heat conducting structures 140 are set on the wafer WF and then cut into a plurality of chips CH ( Figure 5B 、 Figure 5C ), and then cover the chip CH on a substrate 110 ( Figure 5D ); and then providing a packaging material 120 to package the side of each chip CH and the bottom surface of each chip CH facing the substrate 110 to form a plurality of chip packaging units 10 ( Figure 5E In the chip package unit 10, the bumps 130 on the chip CH abut against the substrate 110, and the vertical heat-conducting structure 140 passes through a plurality of through holes in the substrate 110 or is directly connected to the substrate 110. Each chip CH includes at least one bump 130.

[0028] In one embodiment, the bump 130 comprises an interconnection structure for connecting signals between the chip CH and the substrate 110 , and may be a solder ball or other structures.

[0029] In some embodiments, the aforementioned steps of dicing the wafer WF into a plurality of chips CH, placing the chips CH on the substrate 110 , and disposing the vertical heat conducting structure 140 on the wafer WF or on the plurality of chips CH diced from the wafer WF may be implemented in different ways as needed:

[0030] (1) Cutting wafer WF into multiple chips CH ( Figure 4A 、 Figure 4B ), then, a plurality of vertical heat conducting structures 140 are provided on each chip CH (on the same side of the chip CH as the bumps 130, Figure 4C ), and then cover each chip CH on the substrate 110 ( Figure 4D ).

[0031] (2) A plurality of vertical heat-conducting structures 140 are provided on the wafer WF (on the same side of the chip CH as the bumps 130, Figure 5A 、 Figure 5B ), then, the wafer WF is cut into multiple chips CH ( Figure 5C ), each chip CH includes a plurality of vertical heat-conducting structures 140, and then covers each chip CH on the substrate 110 ( Figure 5D ).

[0032] (3) Cutting the wafer WF into multiple chips CH, then covering each chip CH on the substrate 110, and then setting multiple vertical heat-conducting structures 140 on each chip CH (which can be on the same side or different side of the chip CH as the bump) to connect the substrate 110 (for example Figure 6A and Figure 6B In the embodiment, the vertical heat conducting structure 140 is connected to the substrate 110 to increase the efficiency of heat transfer to the substrate 110). If necessary, some features of the above three methods can be combined, for example, combining the embodiments (1) and (2), wherein both the wafer WF and the chip CH are provided with a vertical heat conducting structure 140.

[0033] In one embodiment, the vertical heat-conducting structure 140 is a wire bonded on the wafer (WF). The vertical heat-conducting structure 140 is formed by straightening the wire bond in a vertical direction. In one embodiment, the vertical heat-conducting structure 140 is disposed on a non-connective pad on the wafer (WF). This non-connective pad has no signal connection to the chip.

[0034] The packaging material 120 is a material suitable for encapsulating the chip. It has good encapsulation and general heat dissipation effect. The heat transfer coefficient of the vertical heat conductive structure 140 is higher than that of the packaging material 120. Through the vertical heat conductive structure 140, a heat transfer path is formed between the chip CH and the outside of the chip packaging unit 10, 20 ( Figure 4F 、 Figure 6B , wherein the dotted arrows indicate the heat transfer path). In one embodiment, the material of the vertical heat conductive structure includes copper, aluminum, silver, nickel, or a composite metal material, such as a copper alloy, a silver alloy, etc.

[0035] Reference Figure 4D 、 Figure 4E , one side of the vertical heat-conducting structure 140 is exposed on the surface of the chip packaging unit 10. This design is to transfer heat to the outside through the vertical heat-conducting structure 140 or the through-hole of the substrate 110 through which the vertical heat-conducting structure 140 passes. The bumps 130 on the chip CH are in contact with the substrate 110 (which can form a signal connection). The height of the vertical heat-conducting structure 140 is higher than the bumps 130 passing through the through-hole. The packaging material 120 fills the gap between the vertical heat-conducting structure 140 and the through-hole. The vertical heat-conducting structure 140 is very close to the substrate 110. The substrate 110 still has a considerable degree of indirect auxiliary heat dissipation effect through the packaging material 120. Alternatively, the vertical heat-conducting structure 140 is connected to the substrate 110 ( Figure 6A and Figure 6B ), forming a heat transfer path between the chip CH and the outside of the chip package unit 20 through the substrate 110. In other words, in the chip package units 10 and 20, one of the main heat transfer directions of the chip CH is toward the substrate 110.

[0036] In one embodiment, a flip chip lead connection is provided between the chip CH and the substrate 110. In one embodiment, the substrate 110 is a lead frame. In some embodiments, the packaging method includes, for example, a Quad Flat No-Lead (QFN), a Dual Flat No-Lead (DFN), a Small Outline Transistor (SOT), or a Small Outline Package (SOP). For example, in an embodiment where the substrate 110 is a lead frame, the vertical heat conductive structure 140 is, for example, a wire, extending from the chip CH outward through the gaps between the multiple leads of the lead frame.

[0037] Reference Figure 4E 、 Figure 6A From one perspective, the present invention provides a chip packaging unit 10, 20, comprising: a lead frame 110; a chip CH, comprising a plurality of bumps 130 and a plurality of vertical heat-conducting structures 140, wherein the bumps 130 and the vertical heat-conducting structures 140 are located on the same side of the chip CH, and the chip CH is disposed on the lead frame 110, wherein the vertical heat-conducting structures 140 pass through a plurality of through holes in the lead frame 110 or are directly connected to the lead frame 110; and an encapsulation material 120, encapsulating the side edges of the chip CH and the bottom surface of the chip CH facing the lead frame 110.

[0038] The present invention has been described above with reference to the embodiments. However, the above description is intended to facilitate understanding of the present invention by those skilled in the art and is not intended to limit the scope of the present invention. Within the same spirit of the present invention, those skilled in the art may conceive of various equivalent variations. For example, the term "coupled" in the present invention includes both direct and indirect connections. The scope of the present invention encompasses the above and all other equivalent variations.

Claims

1. A chip packaging method, characterized in that: Include: Providing a wafer, the wafer comprising a plurality of bumps; Cutting the wafer into a plurality of chips and covering the plurality of chips on a substrate, wherein a plurality of vertical heat-conducting structures are provided on the wafer or the plurality of chips; as well as Providing a packaging material to package the side edges of each chip and the bottom surface of each chip facing the substrate to form each chip packaging unit; Wherein, in each of the chip packaging units, the plurality of bumps on the plurality of chips abut against the substrate, and the plurality of vertical heat-conducting structures pass through a plurality of through holes in the substrate or are directly connected to the substrate. The plurality of vertical heat-conducting structures are leads generated by bonding on the wafer, and the plurality of vertical heat-conducting structures are formed by straightening the leads in a vertical direction.

2. The chip packaging method according to claim 1, wherein: The aforementioned step of cutting the wafer into the multiple chips and covering the multiple chips on the substrate, wherein the step of setting the multiple vertical heat-conducting structures on the wafer or the multiple chips, includes: cutting the wafer into the multiple chips, then setting the multiple vertical heat-conducting structures on each of the chips, and then covering the multiple chips on the substrate; or setting the multiple vertical heat-conducting structures on the wafer, then cutting the wafer into the multiple chips, each of the chips including the multiple vertical heat-conducting structures, and then covering the multiple chips on the substrate; or cutting the wafer into the multiple chips, then covering the multiple chips on the substrate, and then setting the multiple vertical heat-conducting structures on each of the chips to connect to the substrate.

3. The chip packaging method according to claim 1, wherein: The plurality of vertical heat-conducting structures are generated by bonding non-functional pads on the wafer.

4. The chip packaging method according to claim 1, wherein: One side of the plurality of vertical heat-conducting structures is exposed on the surface of the plurality of chip packaging units, or the plurality of vertical heat-conducting structures are connected to the substrate to form a heat transfer path between each chip and the outside of each chip packaging unit.

5. The chip packaging method according to claim 1, wherein: The chip and the substrate are connected by a flip chip type lead wire connection.

6. The chip packaging method according to claim 1, wherein: The heat transfer coefficients of the plurality of vertical heat-conducting structures are higher than that of the packaging material.

7. The chip packaging method according to claim 1, wherein: The materials of the plurality of vertical heat-conducting structures include copper, aluminum, silver, nickel, or composite metal materials.

8. The chip packaging method according to claim 1, wherein: Each chip is abutted on the substrate through the plurality of bumps.

9. The chip packaging method according to claim 1, wherein: The substrate is a lead frame.

10. The chip packaging method according to claim 1, wherein: The chip is available in a quad flat no-lead package, a dual flat no-lead package, a small outline transistor package, or a small outline package.

11. The chip packaging method according to claim 1, wherein: In each of the chip packaging units, the vertical heat-conducting structure is arranged on a side of each of the chips facing the substrate.

12. A chip packaging unit, characterized in that: Include: a lead frame comprising a plurality of through holes; A chip comprising a plurality of bumps and a plurality of vertical heat-conducting structures, the plurality of bumps and the plurality of vertical heat-conducting structures being located on the same side of the chip, the chip being disposed on the lead frame, the plurality of vertical heat-conducting structures being connected to the lead frame through a plurality of through holes in the lead frame or being directly connected to the lead frame; a packaging material, packaging the side edges of each chip and the bottom surface of each chip facing the lead frame, The plurality of vertical heat-conducting structures are leads generated by bonding on the chip, and the plurality of vertical heat-conducting structures are formed by straightening the leads in a vertical direction.

13. The chip packaging unit according to claim 12, wherein: One side of the plurality of vertical heat-conducting structures is exposed on the surface of the chip packaging unit, or is directly connected to the lead frame, forming a plurality of heat transfer paths between the chip and the outside of the chip packaging unit.

14. The chip packaging unit according to claim 12, wherein: The packaging material fills the gaps between the plurality of vertical heat-conducting structures and the plurality of through holes.

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