Level shifting circuit

Abstract

The application discloses a kind of level conversion circuits.The level conversion circuit includes third PMOS tube, fourth PMOS tube, first bidirectional diode unit, second bidirectional diode unit, first inverter, when low voltage input end inputs low logic signal level, it is converted into first voltage output level by first inverter, enters second bidirectional diode unit, first voltage output level passes through fourth PMOS tube, and its high voltage output level is pulled low to first voltage output level, and the first voltage output level of low logic signal is output from high voltage output end, when low voltage input end inputs high logic signal level, high logic signal level enters first bidirectional diode unit, and the drain of third PMOS tube, fourth PMOS tube is pulled high to high voltage output level, and the high voltage output level of high logic signal is output from output end.It can guarantee that the level conversion circuit can work in overvoltage state.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a level conversion circuit. Background Technology

[0002] Level shifting circuits are frequently used in many semiconductor integrated circuits, especially in interface circuits where operation across voltage domains is often required. Level shifting circuits include high-voltage and low-voltage level shifting circuits. High-voltage level shifting circuits convert low-voltage signals to high-voltage signals, enabling low-voltage logic to control high-voltage logic, while low-voltage level shifting circuits convert high-voltage signals to low-voltage signals, enabling high-voltage logic to control low-voltage logic. Generally, the term "level shifting circuit" often refers to high-voltage level shifting circuits. Traditional level shifting circuits consist of four high-voltage transistors: two high-voltage PMOS transistors for pull-up and two high-voltage NMOS transistors for pull-down. The gates of the two high-voltage NMOS transistors serve as the two input terminals of the level shifting circuit, with a low input voltage. The drains of the two high-voltage PMOS transistors serve as the two output terminals of the level shifting circuit, with a high output voltage. Because the two high-voltage NMOS transistors operate at low voltage, their pull-down capability is very weak. When the low voltage value drops to a certain level, the level conversion circuit cannot work, meaning it cannot perform the level conversion function. This is especially true at small-size process nodes, where the circuit's supply voltage far exceeds the range that the device itself can withstand. Therefore, in this situation, the traditional level conversion circuit structure cannot be used to achieve high-voltage, high-speed circuit conversion. Summary of the Invention

[0003] The purpose of this invention is to provide a level conversion circuit to solve the problem that all MOS transistors in the level conversion circuit do not exceed their voltage rating range, thus achieving high-speed signal level conversion.

[0004] To address the aforementioned problems, this invention provides a level conversion circuit, comprising: a low-voltage input terminal, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, and an output terminal, characterized in that it further comprises:

[0005] The system comprises a third PMOS transistor, a fourth PMOS transistor, a first bidirectional diode unit, a second bidirectional diode unit, and a first inverter. The gate of the first PMOS transistor is electrically connected to the low-voltage input terminal. The drain of the first PMOS transistor is electrically connected to one end of the first bidirectional diode unit, and the other end of the first bidirectional diode unit is electrically connected to the drain of the third PMOS transistor. The gate of the second PMOS transistor is electrically connected to the output terminal of the first inverter. The input terminal of the first inverter is electrically connected to the low-voltage input terminal. The drain of the second PMOS transistor is electrically connected to one end of the second bidirectional diode unit, and the other end of the second bidirectional diode unit is electrically connected to the drain of the fourth PMOS transistor. The source of the first PMOS transistor is electrically connected to a third power supply. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The second PMOS transistor is electrically connected to the source of the fourth PMOS transistor. The source of the second PMOS transistor is electrically connected to a third power supply. The drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to a first bias voltage. The gate of the fourth PMOS transistor is connected to a first bias voltage. When a low logic signal (low logic signal level is 0V) is input to the low voltage input terminal, the low logic signal level is converted into a first voltage output level by the first inverter and enters the second NMOS transistor and the second bidirectional diode unit. The first voltage output level is pulled down to the first voltage output level by the fourth PMOS transistor, the first PMOS transistor, and the second PMOS transistor, thus closing its pull-up path and turning the low logic signal (first voltage output level is VBIAS_P+|V) down. TP |) Output from the output terminal. When a high logic signal (high logic signal level is VDD1) is input to the low voltage input terminal, the high logic signal level enters the first bidirectional diode unit through the first NMOS transistor. The drains of the second, third, and fourth PMOS transistors are pulled high to the high voltage output level, and the high logic signal (high voltage output level is VDD3) is output from the output terminal.

[0006] As a further improvement of the present invention, the first bidirectional diode unit includes a seventh NMOS transistor and an eleventh PMOS transistor, and the second bidirectional diode unit includes an eighth NMOS transistor and a twelfth PMOS transistor. The gate of the seventh NMOS transistor is electrically connected to the source of the eleventh PMOS transistor, the source of the seventh NMOS transistor is electrically connected to the drain of the first NMOS transistor, the drain of the seventh NMOS transistor is electrically connected to the drain of the eleventh PMOS transistor, the gate of the eleventh PMOS transistor is electrically connected to the source of the seventh NMOS transistor, the gate of the eighth NMOS transistor is electrically connected to the source of the twelfth PMOS transistor, the source of the eighth NMOS transistor is electrically connected to the drain of the second NMOS transistor, the drain of the eighth NMOS transistor is electrically connected to the drain of the twelfth PMOS transistor, and the gate of the twelfth PMOS transistor is electrically connected to the source of the eighth NMOS transistor.

[0007] As a further improvement of the present invention, the level conversion circuit further includes: a level feedback unit, the level feedback unit including: a ninth PMOS transistor and a tenth PMOS transistor, the source of the ninth PMOS transistor being electrically connected to the gate of the second PMOS transistor, the drain of the ninth PMOS transistor being electrically connected to the drain of the third PMOS transistor and the source of the eleventh PMOS transistor, the source of the tenth PMOS transistor being electrically connected to the gate of the first PMOS transistor, and the drain of the tenth PMOS transistor being electrically connected to the drain of the fourth PMOS transistor and the source of the twelfth PMOS transistor.

[0008] As a further improvement of the present invention, the level conversion circuit further includes a power-on reset unit, which includes a seventh PMOS transistor and a fifth NMOS transistor. The source of the seventh PMOS transistor is electrically connected to a third power supply, and the drain of the seventh PMOS transistor is electrically connected to the output terminal. The source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is electrically connected to one end of the first bidirectional diode unit.

[0009] As a further improvement of the present invention, the level conversion circuit further includes: a voltage drop control unit, the voltage drop control unit including a third NMOS transistor, a fourth NMOS transistor, an eighth PMOS transistor, and a sixth NMOS transistor, wherein the gate of the third NMOS transistor is connected to a third bias voltage, the source of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor, the drain of the third NMOS transistor is electrically connected to the source of the seventh NMOS transistor, the gate of the fourth NMOS transistor is connected to a third bias voltage, and the source of the fourth NMOS transistor is electrically connected to the drain of the second NMOS transistor. The drain of the MOS transistor is electrically connected to the source of the eighth NMOS transistor. The gate of the eighth PMOS transistor is connected to a second bias voltage. The source of the eighth PMOS transistor is electrically connected to the output terminal and the drain of the seventh PMOS transistor. The drain of the eighth PMOS transistor is electrically connected to the drain of the fourth PMOS transistor and the drain of the tenth PMOS transistor. The source of the sixth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor. The drain of the sixth NMOS transistor is electrically connected to the drain of the third NMOS transistor. The gate of the sixth NMOS transistor is connected to a third bias voltage.

[0010] As a further improvement of the present invention, the level conversion circuit further includes: a second inverter, the input terminal of the second inverter is connected to a second reset signal, and the output terminal of the second inverter is electrically connected to the gate of the fifth NMOS transistor.

[0011] As a further improvement of the present invention, the level conversion circuit further includes: a fifth PMOS transistor and a sixth PMOS transistor, wherein the source of the fifth PMOS transistor is electrically connected to a third power supply, the gate of the fifth PMOS transistor is electrically connected to both the third power supply and the gate of the sixth PMOS transistor, the drain of the fifth PMOS transistor is electrically connected to the gate of the first PMOS transistor, the source of the sixth PMOS transistor is electrically connected to the third power supply, the gate of the sixth PMOS transistor is electrically connected to the third power supply, and the drain of the sixth PMOS transistor is electrically connected to the gate of the second PMOS transistor.

[0012] Compared with existing technologies, this level conversion circuit includes a third PMOS transistor, a fourth PMOS transistor, a first bidirectional diode unit, a second bidirectional diode unit, and a first inverter. The gate of the first NMOS transistor is electrically connected to the low-voltage input terminal, the drain of the first NMOS transistor is electrically connected to one end of the first bidirectional diode unit, and the other end of the first bidirectional diode unit is electrically connected to the drain of the third PMOS transistor. The gate of the second NMOS transistor is electrically connected to the output terminal of the first inverter, the input terminal of the first inverter is electrically connected to the low-voltage input terminal, the drain of the second NMOS transistor is electrically connected to one end of the second bidirectional diode unit, and the other end of the second bidirectional diode unit is electrically connected to the drain of the fourth PMOS transistor. The source of the first PMOS transistor is electrically connected to a third power supply, and the drain of the first PMOS transistor is electrically connected to the output terminal of the third PMOS transistor. The sources of the second PMOS transistor are electrically connected, the drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor, the source of the second PMOS transistor is electrically connected to the third power supply, and the drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to the first bias voltage, and the gate of the fourth PMOS transistor is connected to the first bias voltage. When a low logic signal (low logic signal level is 0V) is input to the low voltage input terminal, the low logic signal level is converted into a first voltage output level through the first inverter and enters the second NMOS transistor and the second bidirectional diode unit. The first voltage output level is pulled down to the first voltage output level through the fourth PMOS transistor, the first PMOS transistor, and the second PMOS transistor, thus closing its pull-up path and turning the low logic signal (first voltage output level is VBIAS_P+|V) down to the first voltage output level. TP The output is from the output terminal. When a high logic signal (high logic signal level is VDD1) is input to the low voltage input terminal, the high logic signal level enters the first bidirectional diode unit through the first NMOS transistor. The drains of the second, third, and fourth PMOS transistors are pulled high to the high voltage output level, outputting the high logic signal (high voltage output level is VDD3) from the output terminal. This ensures that all MOS transistors in the level conversion circuit operate within their maximum withstand voltage, thus allowing the level conversion circuit to operate in an overvoltage state. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of one embodiment of the level conversion circuit of the present invention.

[0014] Figure 2 This is a schematic diagram of another derivative circuit of the level conversion circuit of the present invention.

[0015] Figure 3 This is a schematic diagram of another derivative circuit of the level conversion circuit of the present invention.

[0016] Figure 4This is a schematic diagram of another derivative circuit of the level conversion circuit of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] Figure 1 An embodiment of the level conversion circuit of the present invention is shown. In this embodiment, the level conversion circuit includes: a low-voltage input terminal 0, a first NMOS transistor 1, a second NMOS transistor 3, a first PMOS transistor 41, a second PMOS transistor 42, and an output terminal 5, and further includes:

[0019] The third PMOS transistor 43, the fourth PMOS transistor 44, the first bidirectional diode unit 63, and the second bidirectional diode unit 64 are connected. The gate of the first NMOS transistor 1 is electrically connected to the low-voltage input terminal 0. The drain of the first NMOS transistor 1 is electrically connected to one end of the first bidirectional diode unit 63, and the other end of the first bidirectional diode unit 63 is electrically connected to the drain of the third PMOS transistor 43. The gate of the second NMOS transistor 3 is electrically connected to the output terminal of the first inverter 2, and the input terminal of the first inverter 2 is electrically connected to the low-voltage input terminal 0. The drain of the second NMOS transistor 3 is electrically connected to one end of the second bidirectional diode unit 64, and the other end of the second bidirectional diode unit 64 is electrically connected to the drain of the fourth PMOS transistor 44. The source of the first PMOS transistor 41 is electrically connected to the third power supply, and the drain of the first PMOS transistor 41 is electrically connected to the source of the third PMOS transistor 43. The drain of the second PMOS transistor 42 is electrically connected to the source of the fourth PMOS transistor 44. The source of the second PMOS transistor 42 is electrically connected to the third power supply. The gate of the third PMOS transistor 43 and the gate of the fourth PMOS transistor 44 are connected to the first bias voltage. When a low logic signal (0V) is input to the low voltage input terminal 0, the low logic signal level is converted into a first voltage output level by the first inverter 2 and enters the second NMOS transistor 3 and the second bidirectional diode unit 64. The first voltage output level is pulled down to the first voltage output level by the fourth PMOS transistor 44, the first PMOS transistor 41, and the second PMOS transistor 42, thus closing its pull-up path and turning the low logic signal (the first voltage output level is VBIAS_P+|V) down. TP|) Output from output terminal 5. When a high logic signal (high logic signal level is VDD1) is input to low voltage input terminal 0, the high logic signal level enters the first bidirectional diode unit 63 through the first NMOS transistor 1. The drains of the second PMOS transistor 42, the third PMOS transistor 43, and the fourth PMOS transistor 44 are pulled high to the high voltage output level, and the high logic signal (high voltage output level is VDD3) is output from output terminal 5.

[0020] It should be noted that when traditional level conversion circuits are used with different power supplies, the power supply voltage is within the operating range of the PMOS and NMOS transistors in the level conversion circuit. However, if the low-voltage logic is to be converted to a high-voltage logic that exceeds the voltage withstand range of the MOS transistor itself, the traditional level conversion circuit cannot be used.

[0021] Specifically, when a low logic signal (0V) is input to the low voltage input terminal 0, the first NMOS transistor is turned off. The low logic signal level is converted into the first voltage output level (approximately VBIAS_P+|V) by the first inverter 2. TP When the second NMOS transistor 3 and the second bidirectional diode unit 64 are connected, the gate signal of the first PMOS transistor 41 is pulled low (the voltage is approximately VBIAS_P+|V). TP |). Because the gate signal of the first PMOS transistor 41 is logic low (voltage approximately VBIAS_P+|V). TP Because the gate signal of the third PMOS transistor 43 is connected to the first bias voltage VBIAS_P, the third PMOS transistor 43 is in the on state, and its drain is pulled high. Similarly, the gate of the second PMOS transistor 42 is pulled high (approximately VDD3). The first voltage output level passes through the fourth PMOS transistor 44, the first PMOS transistor 41, and the second PMOS transistor 42, and its high voltage output level is pulled low to the first voltage output level. Therefore, its pull-up path is closed, and the low logic signal (the first voltage output level is VBIAS_P + |V) is turned off. TP |) Output from output terminal 5. When a high logic signal (high logic signal level is VDD1) is input to low voltage input terminal 0, the second NMOS transistor 3 is turned off, and the high logic signal level enters the first bidirectional diode unit 63 through the first NMOS transistor 1. Then, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P+|V). TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TPIf the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the conducting state. Therefore, the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3. Similarly, the gate of the first PMOS transistor 41 is pulled high to a high voltage (approximately VDD3), and the drains of the second PMOS transistor 42, the third PMOS transistor 43, and the fourth PMOS transistor 44 are pulled high to a high voltage output level, outputting a high logic signal (high voltage output level is VDD3) from output terminal 5.

[0022] In this embodiment, the level conversion circuit electrically connects the gate of the first NMOS transistor 1 to the low-voltage input terminal 0, the drain of the first NMOS transistor 1 to one end of the first bidirectional diode unit 63, and the other end of the first bidirectional diode unit 63 to the drain of the third PMOS transistor 43. The gate of the second NMOS transistor 3 is electrically connected to the output terminal of the first inverter 2, the input terminal of the first inverter 2 is electrically connected to the low-voltage input terminal 0, and the drain of the second NMOS transistor 3 is electrically connected to one end of the second bidirectional diode unit 64. The other end is electrically connected to the drain of the fourth PMOS transistor 44. The source of the first PMOS transistor 41 is electrically connected to the third power supply. The drain of the first PMOS transistor 41 is electrically connected to the source of the third PMOS transistor 43. The drain of the second PMOS transistor 42 is electrically connected to the source of the fourth PMOS transistor 44. The source of the second PMOS transistor 42 is electrically connected to the third power supply. The drain of the second PMOS transistor 42 is electrically connected to the source of the fourth PMOS transistor 44. The gate of the third PMOS transistor 43 is connected to the first bias voltage, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage. In this invention, when a low logic signal (low logic signal level is 0V) is input to the low voltage input terminal 0, the first NMOS transistor is cut off. The low logic signal level is converted into a first voltage output level (approximately VBIAS_P+|V) by the first inverter 2. TP When the second NMOS transistor 3 and the second bidirectional diode unit 64 are connected, the gate signal of the first PMOS transistor 41 is pulled low (the voltage is approximately VBIAS_P+|V). TP |). Because the gate signal of the first PMOS transistor 41 is logic low (voltage approximately VBIAS_P+|V). TPBecause the gate signal of the third PMOS transistor 43 is connected to the first bias voltage VBIAS_P, the third PMOS transistor 43 is in the on state, and its drain is pulled high. Similarly, the gate of the second PMOS transistor 42 is pulled high (approximately VDD3). The first voltage output level passes through the fourth PMOS transistor 44, the first PMOS transistor 41, and the second PMOS transistor 42, and its high voltage output level is pulled low to the first voltage output level. Therefore, its pull-up path is closed, and the low logic signal (the first voltage output level is VBIAS_P + |V) is turned off. TP |) Output from output terminal 5. When a high logic signal (high logic signal level is VDD1) is input to low voltage input terminal 0, the second NMOS transistor 3 is turned off, and the high logic signal level enters the first bidirectional diode unit 63 through the first NMOS transistor 1. Then, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P+|V). TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TP If the drain of the fourth PMOS transistor 44 is pulled up to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the conducting state. Therefore, the drain of the fourth PMOS transistor 44 is pulled up to a high voltage VDD3. Similarly, the gate of the first PMOS transistor 41 is pulled up to a high voltage (approximately VDD3), and the drains of the second PMOS transistor 42, the third PMOS transistor 43, and the fourth PMOS transistor 44 are pulled up to a high voltage output level. The high logic signal (high voltage output level is VDD3) is output from the output terminal 5. This ensures that all MOS transistors in the level conversion circuit operate within their maximum withstand voltage, thus allowing the level conversion circuit to operate in an overvoltage state.

[0023] Further, the first bidirectional diode unit 63 includes a seventh NMOS transistor 631 and an eleventh PMOS transistor 632, and the second bidirectional diode unit 64 includes an eighth NMOS transistor 641 and a twelfth PMOS transistor 642. The gate of the seventh NMOS transistor 631 is electrically connected to the source of the eleventh PMOS transistor 632, the source of the seventh NMOS transistor 631 is electrically connected to the drain of the first NMOS transistor 632, and the drain of the seventh NMOS transistor 631 is connected to the drain of the eleventh PMOS transistor 632. Electrically connected, the gate of the eleventh PMOS transistor 632 is electrically connected to the source of the seventh NMOS transistor 631, the gate of the eighth NMOS transistor 641 is electrically connected to the source of the twelfth PMOS transistor 642, the source of the eighth NMOS transistor 641 is electrically connected to the drain of the second NMOS transistor 3, the drain of the eighth NMOS transistor 641 is electrically connected to the drain of the twelfth PMOS transistor 642, and the gate of the twelfth PMOS transistor 642 is electrically connected to the source of the eighth NMOS transistor 641.

[0024] It should be noted that the first bidirectional diode unit 63 and the second bidirectional diode unit 64 serve to reduce voltage, or in simpler terms, "consume voltage," ensuring that the source voltage of the lower NMOS is always one V lower than the source voltage of the upper PMOS. TH (|V TP |or V TN ).

[0025] Specifically, when the input signal at the low-voltage input terminal 0 is low (voltage approximately 0), the first NMOS transistor 1 is turned off, which in turn pulls the drain of the second NMOS transistor 3 low (voltage approximately 0). The voltage passes through the eighth NMOS transistor 641 and the twelfth PMOS transistor 642 to the fourth PMOS transistor 44 and the tenth PMOS transistor 48. The signal of the tenth PMOS transistor 48 is connected to the first bias voltage VBIAS_P, so the tenth PMOS transistor 48 is in the on state, and the gate signal of the first PMOS transistor 41 is pulled low (voltage approximately VBIAS_P + |V TP |). Because the gate signal of the first PMOS transistor 41 is logic low (voltage approximately VBIAS_P+|V). TP If the gate signal of the third PMOS transistor 43 is connected to the first bias voltage VBIAS_P, then its drain is pulled high to a high voltage VDD3. Similarly, the ninth PMOS transistor 47 is also turned on, so the gate of the second PMOS transistor 42 is pulled high (approximately VDD3), closing its pull-up path. This ensures that the drain of the tenth PMOS transistor 48 is logic low (approximately VDD3). TNThe state of the input signal at the low-voltage input terminal 0 is as follows: When the input signal is high (approximately VDD1), the first NMOS transistor 1 is turned on, and its drain is pulled low (approximately 0), thus turning off the second NMOS transistor 3. The voltage passes through the seventh NMOS transistor 631 and the eleventh PMOS transistor 632 to the third PMOS transistor 43 and the ninth PMOS transistor 47. The signal at the drain of the ninth PMOS transistor 47 is also pulled low (approximately VDD1). TN Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS_P, the ninth PMOS transistor 47 is in the on state. Therefore, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P + |V TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TP If the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the on state, and its drain is pulled high to a high voltage VDD3. Similarly, the tenth PMOS transistor 48 is also in the on state, and the gate of the first PMOS transistor 41 is pulled high (voltage approximately VDD3), closing its pull-up path, thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage approximately VDD3). TN ) state.

[0026] Furthermore, the level conversion circuit also includes a level feedback unit 4, which includes a ninth PMOS transistor 47 and a tenth PMOS transistor 48. The source of the ninth PMOS transistor 47 is electrically connected to the gate of the second PMOS transistor 42, the drain of the ninth PMOS transistor 47 is electrically connected to the drain of the third PMOS transistor 43 and the source of the eleventh PMOS transistor 632, the source of the tenth PMOS transistor 48 is electrically connected to the gate of the first PMOS transistor 41, and the drain of the tenth PMOS transistor 48 is electrically connected to the drain of the fourth PMOS transistor 44 and the source of the twelfth PMOS transistor 642.

[0027] Specifically, when the input signal at the low-voltage input terminal 0 is low (voltage approximately 0), the signal of the tenth PMOS transistor 48 in the level feedback unit 4 is connected to the first bias voltage VBIAS_P, so the tenth PMOS transistor 48 is in the on state, and the gate signal of the first PMOS transistor 41 is pulled low (voltage approximately VBIAS_P + |V TP |). Because the gate signal of the first PMOS transistor 41 is logic low (voltage approximately VBIAS_P+|V). TPIf the gate signal of the third PMOS transistor 43 is connected to the first bias voltage VBIAS_P, then its drain is pulled high to a high voltage VDD3. Similarly, the ninth PMOS transistor 47 is also turned on, so the gate of the second PMOS transistor 42 is pulled high (approximately VDD3), closing its pull-up path. This ensures that the drain of the tenth PMOS transistor 48 is logic low (approximately VDD3). TN The state of the low-voltage input terminal 0. When the input signal is high (approximately VDD1), the signal at the drain of the ninth PMOS transistor 47 is also pulled low (approximately V). TN Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS_P, the ninth PMOS transistor 47 is in the on state. Therefore, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P + |V TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TP If the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the on state, and its drain is pulled high to a high voltage VDD3. Similarly, the tenth PMOS transistor 48 is also in the on state, and the gate of the first PMOS transistor 41 is pulled high (voltage approximately VDD3), closing its pull-up path, thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage approximately VDD3). TN ) state.

[0028] Furthermore, the level conversion circuit also includes a power-on reset unit 6, which includes a seventh PMOS transistor 45 and a fifth NMOS transistor 73. The source of the seventh PMOS transistor 45 is electrically connected to the third power supply, and the drain of the seventh PMOS transistor 45 is electrically connected to the output terminal. The source of the fifth NMOS transistor 73 is grounded, and the drain of the fifth NMOS transistor 73 is electrically connected to one end of the first bidirectional diode unit 63.

[0029] It's important to note that the power-on reset circuit operates when the power supply is not in operation. This means there is no power, or the power supply voltage is slowly rising but hasn't reached the normal operating voltage. When the power supply is normal, meaning the power-on process is complete, the power-on reset circuit will stop working, and the overall circuit function (level switching) can proceed. Its purpose is to help ensure that the voltage at each node of the circuit is at a normal level during the power-on process (when the power supply has not yet reached its normal operating state).

[0030] Specifically, during the power supply VDD3 power-on process, a second reset signal S2_PORN is input. Since the second reset signal S2_PORN is logic low (voltage approximately 0), it pulls the drain of the fifth NMOS transistor 73 low (voltage approximately 0). The seventh NMOS transistor 631 and the eleventh PMOS transistor 632 form the first bidirectional diode unit 63, and the signal at the drain of the ninth PMOS transistor 47 is also pulled low (voltage approximately V). TN Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS_P, the ninth PMOS transistor 47 is in the on state. Therefore, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P + |V TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TP If the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the on state, and its drain is pulled high to a high voltage VDD3. Similarly, the tenth PMOS transistor 48 is also in the on state, and the gate of the first PMOS transistor 41 is pulled high (voltage approximately VDD3), closing its pull-up path, thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage approximately VDD3). TN The state of the reset signal S3_PORN is low (approximately VBIAS_P+|V). Also, the reset signal S3_PORN is logic low (approximately VBIAS_P+|V). TP Therefore, the seventh PMOS transistor 45 is in the conducting state, which in turn pulls the output terminal 5 high to the high voltage VDD3. Thus, regardless of whether the input signal logic is high or low, it does not affect the output terminal 5 being logic high (voltage approximately VDD3). When the power supply VDD3 is powered on, the input reset signals S2_PORN and S3_PORN are logic high, the power-on reset circuit does not work, and the circuit can work normally and perform level conversion.

[0031] Furthermore, the level conversion circuit also includes: a voltage drop control unit 7, which includes a third NMOS transistor 61, a fourth NMOS transistor 62, an eighth PMOS transistor 46, and a sixth NMOS transistor 74. The gate of the third NMOS transistor 61 is connected to a third bias voltage, the source of the third NMOS transistor 61 is electrically connected to the drain of the first NMOS transistor 1, and the drain of the third NMOS transistor 61 is electrically connected to the source of the seventh NMOS transistor 631. The gate of the fourth NMOS transistor 62 is connected to a third bias voltage, and the source of the fourth NMOS transistor 62 is electrically connected to the drain of the second NMOS transistor 3. The fourth NMOS transistor 64... The drain of transistor 2 is electrically connected to the source of the eighth NMOS transistor 641. The gate of the eighth PMOS transistor 46 is connected to a second bias voltage. The source of the eighth PMOS transistor 46 is electrically connected to the output terminal 5 and the drain of the seventh PMOS transistor 45. The drain of the eighth PMOS transistor 46 is electrically connected to the drain of the fourth PMOS transistor 44 and the drain of the tenth PMOS transistor 48. The source of the sixth NMOS transistor 74 is electrically connected to the drain of the fifth NMOS transistor 73. The drain of the sixth NMOS transistor 74 is electrically connected to the drain of the third NMOS transistor 61. The gate of the sixth NMOS transistor 74 is connected to a third bias voltage.

[0032] Specifically, when the input signal at the low-voltage input terminal 0 is low (voltage approximately 0), the first NMOS transistor 1 is turned off, which in turn pulls the drain of the second NMOS transistor 3 low (voltage approximately 0). The gate of the fourth NMOS transistor 62 is connected to the third bias voltage VBIAS_N, so the fourth NMOS transistor 62 is in the on state, and its drain is logic low (voltage approximately 0). The voltage passes through the eighth NMOS transistor 641 and the twelfth PMOS transistor 642 to the fourth PMOS transistor 44 and the tenth PMOS transistor 48. The signal of the tenth PMOS transistor 48 is connected to the first bias voltage VBIAS_P, so the tenth PMOS transistor 48 is in the on state, and the gate signal of the first PMOS transistor 41 is pulled low (voltage approximately VBIAS_P + |V TP |). Because the gate signal of the first PMOS transistor 41 is logic low (voltage approximately VBIAS_P+|V). TP If the gate signal of the third PMOS transistor 43 is connected to the first bias voltage VBIAS_P, then its drain is pulled high to a high voltage VDD3. Similarly, the ninth PMOS transistor 47 is also turned on, so the gate of the second PMOS transistor 42 is pulled high (approximately VDD3), closing its pull-up path. This ensures that the drain of the tenth PMOS transistor 48 is logic low (approximately VDD3). TNThe state of the reset signal S3_PORN is low (approximately VBIAS_P+|V). Also, the reset signal S3_PORN is logic low (approximately VBIAS_P+|V). TP Therefore, the seventh PMOS transistor 45 is in the on state, which in turn pulls the output terminal 5 high to the high voltage VDD3. When the input signal at the low voltage input terminal 0 is high (voltage approximately VDD1), the first NMOS transistor 1 is turned on, and its drain is pulled low (voltage approximately 0), thus turning off the second NMOS transistor 3. The gate of the third NMOS transistor 61 receives the third bias voltage VBIAS_N, so the third NMOS transistor 61 is in the on state, and its drain is logic low (voltage approximately 0). The voltage passes through the seventh NMOS transistor 631 and the eleventh PMOS transistor 632 to enter the third PMOS transistor 43 and the ninth PMOS transistor 47. The signal at the drain of the ninth PMOS transistor 47 is also pulled low (voltage approximately V). TN Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS_P, the ninth PMOS transistor 47 is in the on state. Therefore, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P + |V TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TP If the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the on state, and its drain is pulled high to a high voltage VDD3. Similarly, the tenth PMOS transistor 48 is also in the on state, and the gate of the first PMOS transistor 41 is pulled high (voltage approximately VDD3), closing its pull-up path, thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage approximately VDD3). TN The state of ) Similarly, when the eighth PMOS transistor 46 is in the on state, the output terminal 5 is pulled high to the high voltage VDD3 by the drain of the fourth PMOS transistor 44.

[0033] Furthermore, the level conversion circuit also includes a second inverter 72, the input terminal of which is connected to a second reset signal, and the output terminal of which is electrically connected to the gate of the fifth NMOS transistor 73.

[0034] Specifically, when the low-voltage input terminal 0 has a low-level input signal (voltage approximately 0), the first NMOS transistor 1 is turned off, the first inverter 2 outputs a logic high (voltage approximately VDD1), which in turn pulls the drain of the second NMOS transistor 3 low (voltage approximately 0). The gate of the fourth NMOS transistor 62 is connected to the third bias voltage VBIAS_N, so the fourth NMOS transistor 62 is in the on state, and its drain is logic low (voltage approximately 0). The voltage passes through the eighth NMOS transistor 641 and the twelfth PMOS transistor 642 to the fourth PMOS transistor 44 and the tenth PMOS transistor 48. When the low-voltage input terminal 0 has a high-level input signal (voltage approximately VDD1), the first NMOS transistor 1 is turned on, its drain is pulled low (voltage approximately 0), the first inverter 2 outputs a logic low (voltage approximately 0), which in turn turns off the second NMOS transistor 3. The gate of the third NMOS transistor 61 is connected to the third bias voltage VBIAS_N, so the third NMOS transistor 61 is in the on state, and its drain is logic low (voltage approximately 0). The voltage passes through the seventh NMOS transistor 631 and the eleventh PMOS transistor 632 to the third PMOS transistor 43 and the ninth PMOS transistor 47. When the power supply VDD3 is powered on, the second reset signal S2_PORN is input. Since the second reset signal S2_PORN is logic low (voltage approximately 0), the output of the second inverter 72 is logic high (voltage approximately VDD2), pulling the drain of the fifth NMOS transistor 73 low (voltage approximately 0). Because the gate of the sixth NMOS transistor 74 is connected to the third bias voltage VBIAS_N, the drain of the sixth NMOS transistor 74 is also pulled low (voltage approximately 0). The seventh NMOS transistor 631 and the eleventh PMOS transistor 632 form the first bidirectional diode unit 63, and the signal at the drain of the ninth PMOS transistor 47 is also pulled low (voltage approximately V). TN Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS_P, the ninth PMOS transistor 47 is in the on state. Therefore, the gate signal of the second PMOS transistor 42 is pulled low (the voltage is approximately VBIAS_P + |V TP |). Because the gate signal of the second PMOS transistor 42 is logic low (voltage approximately VBIAS_P+|V). TP If the drain of the fourth PMOS transistor 44 is pulled high to a high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS_P, the fourth PMOS transistor 44 is in the on state, and its drain is pulled high to a high voltage VDD3. Similarly, the tenth PMOS transistor 48 is also in the on state, and the gate of the first PMOS transistor 41 is pulled high (voltage approximately VDD3), closing its pull-up path, thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage approximately VDD3). TN The state of the reset signal S3_PORN is low (approximately VBIAS_P+|V). Also, the reset signal S3_PORN is logic low (approximately VBIAS_P+|V).TP Therefore, the seventh PMOS transistor 45 is in the on state, which in turn pulls the output terminal 5 to a high voltage VDD3. So at this time, no matter whether the input signal logic is high or low, it does not affect the output terminal 5 being logic high (voltage approximately VDD3).

[0035] Furthermore, the level conversion circuit also includes: a fifth PMOS transistor 8 and a sixth PMOS transistor 9. The source of the fifth PMOS transistor 8 is electrically connected to the third power supply, the gate of the fifth PMOS transistor 8 is electrically connected to the third power supply and the gate of the sixth PMOS transistor 9, the drain of the fifth PMOS transistor 8 is electrically connected to the gate of the first PMOS transistor 41, the source of the sixth PMOS transistor 9 is electrically connected to the third power supply, the gate of the sixth PMOS transistor 9 is electrically connected to the third power supply, and the drain of the sixth PMOS transistor 9 is electrically connected to the gate of the second PMOS transistor 41.

[0036] Specifically, when the gates of the first PMOS transistor 41 and the second PMOS transistor 42 are higher than VDD3, a discharge path to the power supply VDD3 can be provided, and they can also act as dummy transistors for other PMOS transistors in the circuit.

[0037] like Figure 2 As shown, in Figure 1 Based on this, the ninth PMOS transistor 47 and the tenth PMOS transistor 48 are removed, and the source of the third PMOS transistor 43 is coupled to the gate of the second PMOS transistor 42, and the source of the fourth PMOS transistor 44 is coupled to the gate of the first PMOS transistor 41. This is in contrast to... Figure 1 The effect is the same.

[0038] like Figure 3 As shown, in Figure 1 Based on this, the seventh NMOS transistor 631, the eleventh PMOS transistor 632, the eighth NMOS transistor 641, and the twelfth PMOS transistor 642 are removed. This will reduce one of the voltage drop control measures.

[0039] like Figure 4 As shown, in Figure 1 Based on this, remove the ninth PMOS transistor 47 and the tenth PMOS transistor 48, and couple the source of the third PMOS transistor 43 to the gate of the second PMOS transistor 42, and couple the source of the fourth PMOS transistor 44 to the gate of the first PMOS transistor 41. Also remove the seventh NMOS transistor 631, the eleventh PMOS transistor 632, the eighth NMOS transistor 641, and the twelfth PMOS transistor 642. This will reduce one of the voltage drop control measures.

[0040] The specific embodiments of the invention have been described in detail above, but they are only examples, and the invention is not limited to the specific embodiments described above. For those skilled in the art, any equivalent modifications or substitutions to the invention are also within the scope of the invention. Therefore, all equivalent transformations, modifications, and improvements made without departing from the spirit and principles of the invention should be covered within the scope of the invention.

Claims

1. A level conversion circuit, comprising: The device comprises a low-voltage input terminal, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, and an output terminal, characterized in that it further includes: The system comprises a third PMOS transistor, a fourth PMOS transistor, a first bidirectional diode unit, a second bidirectional diode unit, and a first inverter. The gate of the first PMOS transistor is electrically connected to the low-voltage input terminal. The drain of the first PMOS transistor is electrically connected to one end of the first bidirectional diode unit. The source of the first PMOS transistor is grounded. The other end of the first bidirectional diode unit is electrically connected to the drain of the third PMOS transistor. The gate of the second PMOS transistor is electrically connected to the output terminal of the first inverter. The input terminal of the first inverter is electrically connected to the low-voltage input terminal. The drain of the second PMOS transistor is electrically connected to one end of the second bidirectional diode unit. The source of the second PMOS transistor is grounded. The other end of the second bidirectional diode unit is electrically connected to the drain of the fourth PMOS transistor. The source of the first PMOS transistor is electrically connected to a third power supply. The drain of the first PMOS transistor is connected to the drain of the third PMOS transistor. The source of the second PMOS transistor is electrically connected, the drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor, the source of the second PMOS transistor is electrically connected to the third power supply, the gate of the third PMOS transistor is connected to the first bias voltage, and the gate of the fourth PMOS transistor is connected to the first bias voltage. When a low logic signal level is input to the low voltage input terminal, the low logic signal level is converted into a first voltage output level through the first inverter and enters the second NMOS transistor and the second bidirectional diode unit. The first voltage output level is pulled low through the fourth PMOS transistor, the first PMOS transistor, and the second PMOS transistor, thus closing its pull-up path and outputting the first voltage output level from the output terminal. When a high logic signal level is input to the low voltage input terminal, the high logic signal level enters the first bidirectional diode unit through the first NMOS transistor, and the drains of the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are pulled high, outputting the high voltage output level from the output terminal. The first bidirectional diode unit includes a seventh NMOS transistor and an eleventh PMOS transistor. The second bidirectional diode unit includes an eighth NMOS transistor and a twelfth PMOS transistor. The gate of the seventh NMOS transistor is electrically connected to the source of the eleventh PMOS transistor. The source of the seventh NMOS transistor is electrically connected to the drain of the first NMOS transistor. The drain of the seventh NMOS transistor is electrically connected to the drain of the eleventh PMOS transistor. The gate of the eleventh PMOS transistor is electrically connected to the source of the seventh NMOS transistor. The gate of the eighth NMOS transistor is electrically connected to the source of the twelfth PMOS transistor. The source of the eighth NMOS transistor is electrically connected to the drain of the second NMOS transistor. The drain of the eighth NMOS transistor is electrically connected to the drain of the twelfth PMOS transistor. The gate of the twelfth PMOS transistor is electrically connected to the source of the eighth NMOS transistor. The level conversion circuit further includes a level feedback unit, which includes a ninth PMOS transistor and a tenth PMOS transistor. The gate of the ninth PMOS transistor is connected to the first bias voltage. The source of the ninth PMOS transistor is electrically connected to the gate of the second PMOS transistor. The drain of the ninth PMOS transistor is electrically connected to the drain of the third PMOS transistor and the source of the eleventh PMOS transistor. The gate of the tenth PMOS transistor is connected to the first bias voltage. The source of the tenth PMOS transistor is electrically connected to the gate of the first PMOS transistor. The drain of the tenth PMOS transistor is electrically connected to the drain of the fourth PMOS transistor and the source of the twelfth PMOS transistor. The level conversion circuit further includes a power-on reset unit, which includes a seventh PMOS transistor and a fifth NMOS transistor. The gate of the seventh PMOS transistor is connected to a reset signal S3_PORN, the source of the seventh PMOS transistor is electrically connected to a third power supply, and the drain of the seventh PMOS transistor is electrically connected to the output terminal. The gate of the fifth NMOS transistor is connected to the inverted signal of the second reset signal S2_PORN, the source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is electrically connected to one end of the first bidirectional diode unit.

2. The level conversion circuit according to claim 1, characterized in that, It also includes: a voltage drop control unit, which comprises a third NMOS transistor, a fourth NMOS transistor, an eighth PMOS transistor, and a sixth NMOS transistor. The gate of the third NMOS transistor is connected to a third bias voltage. The source of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor. The drain of the third NMOS transistor is electrically connected to the source of the seventh NMOS transistor. The gate of the fourth NMOS transistor is connected to a third bias voltage. The source of the fourth NMOS transistor is electrically connected to the drain of the second NMOS transistor. The drain of the fourth NMOS transistor is connected to... The source of the eighth NMOS transistor is electrically connected, the gate of the eighth PMOS transistor is connected to a second bias voltage, the source of the eighth PMOS transistor is electrically connected to the output terminal and the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor is electrically connected to the drain of the fourth PMOS transistor and the drain of the tenth PMOS transistor, the source of the sixth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the gate of the sixth NMOS transistor is connected to a third bias voltage.

3. The level conversion circuit according to claim 2, characterized in that, It also includes: a second inverter, the input of which is connected to a second reset signal, and the output of which is electrically connected to the gate of the fifth NMOS transistor.

4. The level conversion circuit according to claim 3, characterized in that, It also includes: a fifth PMOS transistor and a sixth PMOS transistor, wherein the source of the fifth PMOS transistor is electrically connected to a third power supply, the gate of the fifth PMOS transistor is electrically connected to both the third power supply and the gate of the sixth PMOS transistor, the drain of the fifth PMOS transistor is electrically connected to the gate of the first PMOS transistor, the source of the sixth PMOS transistor is electrically connected to the third power supply, the gate of the sixth PMOS transistor is electrically connected to the third power supply, and the drain of the sixth PMOS transistor is electrically connected to the gate of the second PMOS transistor.

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