Signal processing circuit and link initialization method thereof

Abstract

The present application discloses a signal processing circuit that complies with the DisplayPort standard and operates in a display device as a DisplayPort sink device. The signal processing circuit includes a plurality of auxiliary physical circuits and a main physical circuit for receiving a first signal from one of a plurality of DisplayPort connectors of the display device. The display device is connected to a first DisplayPort source device. Only a first auxiliary physical circuit can receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.

Description

Technical Field

[0001] The present application relates to a signal processing circuit and a link initialization method thereof, and in particular to a signal processing circuit and a link initialization method thereof that can improve operating efficiency, reduce costs or achieve error-free communication. Background Art

[0002] DisplayPort is a digital display interface standard for the next generation of personal computer display interfaces, and is currently available in a variety of products (including tablet computers, laptops, desktops, computer monitors, and televisions with 4K (or higher) resolution). A DisplayPort receiver of a DisplayPort receiving device (e.g., a computer monitor with two DisplayPort receiving ports (or DisplayPort RX ports)) includes two sets of receiver circuits (i.e., two main physical circuits, two main link circuits, two auxiliary physical circuits, and two auxiliary link circuits) to operate in display modes such as picture-in-picture (PIP) or picture-by-picture (PBP).

[0003] However, for a DisplayPort sink device that does not need to simultaneously display images from different DisplayPort source devices, having two sets of receiver circuits is more costly and less competitive.

[0004] On the other hand, for a DisplayPort sink device having two DisplayPort receiving ports but only one set of receiver circuits, only one DisplayPort source device can be connected to the DisplayPort sink device through one of the two DisplayPort receiving ports. Another DisplayPort source device plugged into the other DisplayPort receiving port of the two DisplayPort receiving ports cannot recognize the DisplayPort sink device.

[0005] Therefore, there is still room for improvement in the configuration / operation of DisplayPort sink devices. Summary of the invention

[0006] Therefore, the main purpose of the present application is to provide a signal processing circuit and a link initialization method thereof that can improve operating efficiency, reduce costs or achieve error-free communication.

[0007] The present application discloses a signal processing circuit that complies with the DisplayPort standard and operates in a display device as a DisplayPort receiving device, including a main physical circuit for receiving a first signal from one of a plurality of DisplayPort connectors of the display device, the display device being connected to a first DisplayPort source device; and a plurality of auxiliary physical circuits, wherein only a first auxiliary physical circuit among the plurality of auxiliary physical circuits can receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.

[0008] The present application also discloses a link initialization method for use in a signal processing circuit that complies with the DisplayPort standard and operates on a display device as a DisplayPort receiving device, including providing a training completion result to the first DisplayPort source device when a first DisplayPort source device is connected to the display device and a second DisplayPort source device is still connected to the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of an electronic system according to an embodiment of the present application.

[0010] Figure 2 It is a flowchart of the link initialization method of an embodiment of the present application.

[0011] Figures 3 to 6 is a schematic diagram of an electronic system according to an embodiment of the present application.

[0012] The reference numerals are described as follows:

[0013] 10,30~60: Electronic system

[0014] 100: Display device

[0015] 105:Signal processing circuit

[0016] 105AUXLink0, 105AUXLink1, 605AUXLink0~605AUXLinkn: auxiliary link circuit

[0017] 105AUXPhy0, 105AUXPhy1, 605AUXPhy0~605AUXPhyn: auxiliary physical circuit

[0018] 105DPCD0, 105DPCD1, 605DPCD1~605DPCDn: DPCD register

[0019] 105EDID0, 105EDID1, 605EDID1~605EDIDn: EDID register

[0020] 105HPD, 110HPD, 120HPD, 610HPD1~610HPDn: Hot plug detection circuit

[0021] 105LinkPM: Link Strategy Customization Circuit

[0022] 105M1~105M4,405M1~405M2,605M1~605Mn:Multiplexer

[0023] 105MainLink: Main link circuit

[0024] 105MainPhy: Main physical circuit

[0025] 105StreamPM: Streaming strategy customized circuit

[0026] 105StreamS: Stream receiving circuit

[0027] 105SubLink, 605SubLink1~605SubLinkn: Sublink circuit

[0028] 110,120,610SD1~610SDn:DisplayPort source device

[0029] 110AUX, 120AUX, 610AUX1~610AUXn: Auxiliary circuit

[0030] 110Main, 120Main, 610Main1~610Mainn: Main circuit

[0031] 305MCUFW,505MCU:Circuit

[0032] 305sf0,305sf1: Link status field

[0033] 305TB: Link Training Circuit

[0034] det1,det2: detection signal

[0035] S200~S226: Steps

[0036] sel1,sel2: control signal DETAILED DESCRIPTION

[0037] Figure 11 is a schematic diagram of an electronic system 10 according to an embodiment of the present application. The electronic system 10 may include DisplayPort source devices 110 and 120 and a display device 100 (which may serve as a DisplayPort sink device). The display device 100 may include a signal processing circuit 105 and a plurality of DisplayPort connectors (not shown). The signal processing circuit 105 may include a main physical circuit 105MainPhy, two auxiliary physical circuits 105AUXPhy0 and 105AUXPhy1, a main link circuit 105MainLink, two auxiliary link circuits 105AUXLink0 and 105AUXLink1, a sub-link circuit 105SubLink and multiplexers 105M1 to 105M4. For example, the DisplayPort source devices 110 and 120 may be different computers, and the display device 100 may be a computer monitor.

[0038] In short, the signal processing circuit 105 performs a link training process using the main link circuit 105MainLink, so that the DisplayPort source device 110 first inserted into the display device 100 can identify / discover the display device 100, and stream data transmission can be successfully performed between the DisplayPort source device 110 and the display device 100. On the other hand, the signal processing circuit 105 provides the training completion result to the DisplayPort source device 120 without the help of the main link circuit 105MainLink, so that even if there is no data transmission between the DisplayPort source device 120 and the display device 100, the DisplayPort source device 120 inserted into the display device 100 (connected to the DisplayPort source device 110) can recognize / discover the display device 100.

[0039] The ability of the DisplayPort source device 110 / 120 to identify / discover the display device 100 means that the DisplayPort source device 110 / 120 can read the Extended Display Identification Data (EDID) of the display device 100, and the link training process between the signal processing circuit 105 and the DisplayPort source device 110 / 120 can be completed. After reading the EDID of the display device 100, the DisplayPort source device can know the capabilities of the display device 100 (e.g., resolution and data receiving speed). The link training process is used to allow the DisplayPort source device 110 / 120 to communicate physical layer capabilities with the display device 100 (e.g., configure the link between the DisplayPort source device 110 / 120 and the display device 100 with the optimal transmission settings of voltage swing, pre-emphasis, lane speed, and number of lanes (for subsequent data transmission between the DisplayPort source device 110 / 120 and the display device 100)). If a DisplayPort source device cannot identify / discover the display device 100 , subsequent data transmission will not be performed.

[0040] Figure 2 2 is a flow chart of the link initialization method 20 of the embodiment of the present application. The steps of the link initialization method 20 are as follows:

[0041] Step S200: Start.

[0042] Step S202 : The DisplayPort source device 110 is plugged into the (first) DisplayPort connector of the display device 100 .

[0043] Step S204 : The DisplayPort source device 110 may read the EDID stored in the EDID register 105 EDID0 of the signal processing circuit 105 of the display device 100 .

[0044] Step S206 : Initiate a link training process. The link training process may be controlled / initiated by the DisplayPort source device 110 , and the signal processing circuit 105 may respond to a command from the DisplayPort source device 110 .

[0045] Step S208 : During the link training process, the DisplayPort source device 110 may send a training pattern, write a driver setting, and / or send a request to read the DisplayPort configuration data (DPCD) register 105DPCD0 of the signal processing circuit 105 .

[0046] Step S210 : The DisplayPort source device 110 may read the first training completion result provided by the DPCD register 105DPCD0 of the signal processing circuit 105 .

[0047] Step S212: The DisplayPort source device 110 may indicate that the link training process is finished after reading the first training completion result.

[0048] Step S214: The DisplayPort source device 110 may initiate the transmission of stream data.

[0049] Step S216 : The DisplayPort source device 120 is plugged into the (second) DisplayPort connector of the display device 100 .

[0050] Step S218 : The DisplayPort source device 120 may read the EDID stored in the EDID register 105 EDID1 of the signal processing circuit 105 of the display device 100 .

[0051] Step S220 : The DisplayPort source device 110 may attempt to initiate another link training process.

[0052] Step S222 : The DisplayPort source device 110 may read the second training completion result provided by the DPCD register 105DPCD1 of the signal processing circuit 105 .

[0053] Step S224: The DisplayPort source device 110 may indicate that the link training process is finished after reading the second training completion result.

[0054] Step S226: End.

[0055] Specifically, if the DisplayPort source device 110 is first inserted into the DisplayPort connector (hereinafter referred to as the first DisplayPort connector) of the display device 100, the main physical circuit 105MainPhy is used to receive the signal from the first DisplayPort connector (connected to the DisplayPort source device 110). The signal transmitted from the first DisplayPort connector to the main physical circuit 105MainPhy is hereinafter referred to as the first signal. The multiplexer 105M3 electrically connected to all DisplayPort connectors and the main physical circuit 105MainPhy can be switched to receive the first signal from the first DisplayPort connector (connected to the DisplayPort source device 110) to transmit the first signal to the main physical circuit 105MainPhy.

[0056] Corresponding to the operation of the multiplexer 105M3, the multiplexer 105M1 electrically connected to all DisplayPort connectors and the auxiliary physical circuit 105AUXPhy0 can be switched to receive a signal from the first DisplayPort connector (connected to the DisplayPort source device 110) to transmit a signal to the auxiliary physical circuit 105AUXPhy0. The signal transmitted from the first DisplayPort connector to the auxiliary physical circuit 105AUXPhy0 is hereinafter referred to as the second signal. In other words, only the auxiliary physical circuit 105AUXPhy0 is enabled to receive the second signal from the first DisplayPort connector (connected to the DisplayPort source device 110), while the auxiliary physical circuit 105AUXPhy1 is not enabled.

[0057] The auxiliary physical circuit 105AUXPhy0 receiving the second signal may output the processed second signal (e.g., digital signal) to the auxiliary link circuit 105AUXLink0. The auxiliary link circuit 105AUXLink0 receiving the processed second signal may output the further processed second signal (e.g., command) to the main link circuit 105MainLink. In addition, the main physical circuit 105MainPhy receiving the first signal may output the processed first signal to the main link circuit 105MainLink.

[0058] The main link circuit 105MainLink may include an EDID register 105EDID0, a DPCD register 105DPCD0, a link policy maker circuit 105LinkPM, a stream policy maker circuit 105StreamPM, a stream sink circuit 105StreamS, and a hot plug detect circuit 105HPD. The DPCD register 105DPCD0 may store information about the maximum bit rate (i.e., data receiving speed) and / or the number of channels of the display device 100. DPCD is a data format that describes the link and display stream compression capabilities; EDID is a data format that describes the capabilities of the display device 100.

[0059] After the DisplayPort source device 110 is inserted into the display device 100, the DisplayPort source device 110 can read the EDID register 105EDID0 of the display device 100 through the auxiliary physical circuit 105AUXPhy0, the auxiliary link circuit 105AUXLink0 and the link policy customization circuit 105LinkPM to find out the EDID stored in the EDID register 105EDID0 in step S204.

[0060] After the DisplayPort source device 110 is plugged into the display device 100, a link training process may be actually performed in step S206 (e.g., by gradually executing all steps of the DisplayPort standard). The link training process may determine / coordinate the physical link parameters (e.g., number of channels, channel speed, voltage swing, pre-emphasis, equalization) used to transmit video and audio data. The link training process may involve clock and data recovery (CDR) training and / or equalization training.

[0061] For example, in the CDR training of step S208, the DisplayPort source device 110 may send a training pattern to the signal processing circuit 105. The DisplayPort source device 110 may send a request (e.g., a request to read the LANEx_CR_DONE bit) to the display device 100, where x may be 0, 1, 2, or 3 if the DisplayPort interface has 4 lanes, but is not limited thereto. The DisplayPort source device 110 may read the LANEx_CR_DONE bit (value) of the DPCD register 105DPCD0. If the CDR training can be completed (e.g., the clock can be synchronized), the display device 100 may set the LANEx_CR_DONE bit to 1. Otherwise, the LANEx_CR_DONE bit may be maintained without being set additionally (i.e., maintaining the same value as 0). In other words, the first DPCD parameter (e.g., the LANEx_CR_DONE bit) may be set in the DPCD register 105DPCD0 according to the result of the link training process. The DisplayPort source device 110 may iteratively send training patterns and requests until the DisplayPort source device 110 finds that the value of the LANEx_CR_DONE bit is equal to 1, or until the DisplayPort source device 110 ends the link training process without establishing a link between the display device 100 and the DisplayPort source device 110 .

[0062] After CDR training, equalization training is performed. In the equalization training of step S208, the DisplayPort source device 110 may send a training pattern to the signal processing circuit 105. The DisplayPort source device 110 may send a request (e.g., a request to read the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit, and / or the INTERLANE_ALIGN_DONE bit) to the display device 100, wherein the number of transmission channels based on the DisplayPort interface is 4, and x may be 0, 1, 2, or 3, but is not limited thereto. The DisplayPort source device 110 may read (the value of) the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit, and / or the INTERLANE_ALIGN_DONE bit of the DPCD register 105DPCD0. If the equalization training can be completed (for example, the training pattern can be recognized), the display device 100 can set the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and / or the INTERLANE_ALIGN_DONE bit to 1 respectively. Otherwise, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and / or the INTERLANE_ALIGN_DONE bit can be maintained without being set separately (i.e., maintaining the same value of 0). In other words, the first DPCD parameter (for example, the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit or the INTERLANE_ALIGN_DONE bit) can be set in the DPCD register 105DPCD0 according to the result of the link training process. The DisplayPort source device 110 may iteratively send training patterns and requests until the DisplayPort source device 110 finds that the value of the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit, and / or the INTERLANE_ALIGN_DONE bit is equal to 1 (or, until the DisplayPort source device 110 ends the link training process without establishing a link between the display device 100 and the DisplayPort source device 110).

[0063] The display device 100 may indicate success by setting the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and / or the INTERLANE_ALIGN_DONE bit to 1, respectively (which may be the first training completion result). In other words, the DisplayPort source device 110 may read information related to the result of the link training process (e.g., the first training completion result) from the DPCD register 105DPCD0 in step S210.

[0064] After the DisplayPort source device 110 reads the EDID of the display device 100 and the link training process is completed, the DisplayPort source device 110 first plugged into the display device 100 can identify / discover the display device 100. Then, the DisplayPort source device 110 can perform data transmission and image display through the main physical circuit 105MainPhy and / or the main link circuit 105MainLink in step S214.

[0065] Corresponding to the operation of the multiplexer 105M3, the multiplexer 105M2 electrically connected to all DisplayPort connectors and the auxiliary physical circuit 105AUXPhy1 can switch to another DisplayPort connector (referred to as the second DisplayPort connector) of the display device 100. After the DisplayPort source device 120 is inserted into the display device 100 connected to the DisplayPort source device 110, the multiplexer 105M2 transmits the signal from the second DisplayPort connector connected to the DisplayPort source device 120 to the auxiliary physical circuit 105AUXPhy1. The signal transmitted from the second DisplayPort connector to the auxiliary physical circuit 105AUXPhy1 is hereinafter referred to as the third signal. The auxiliary physical circuit 105AUXPhy1 receiving the third signal can output the processed third signal (e.g., a digital signal) to the auxiliary link circuit 105AUXLink1. The auxiliary link circuit 105AUXLink1 receiving the processed third signal can output a further processed third signal (e.g., a command) to the sub-link circuit 105SubLink.

[0066] The sub-link circuit 105SubLink may be hardware, and may include an EDID register 105EDID1 and a DPCD register 105DPCD1. After the DisplayPort source device 120 is inserted into the display device 100 (which has been connected to the DisplayPort source device 110 and can display images from the DisplayPort source device 110), the DisplayPort source device 120 may read the EDID register 105EDID1 of the display device 100 through the auxiliary physical circuit 105AUXPhy1 and the auxiliary link circuit 105AUXLink1 in step S218 to find out the EDID stored in the EDID register 105EDID1.

[0067] The sub-link circuit 105SubLink helps to identify the display device 100. By reading the sub-link circuit 105SubLink, the DisplayPort source device 120 can find out the EDID of the display device 100 even when the main link circuit 105MainLink is not connected to the DisplayPort source device 120.

[0068] EDID register 105EDID1 (or 105EDID0) may be hardware such as a random access memory (RAM). EDID registers 105EDID0 and 105EDID1 may not be physically the same random access memory and may be separate from each other. EDID register 105EDID0 may store information about the capabilities of one DisplayPort connector (e.g., which specifications are supported), while EDID register 105EDID1 may store information about the capabilities of another DisplayPort connector. The data stored in EDID register 105EDID0 (or 105EDID1) may be predetermined (e.g., by a developer) and may be the same as or different from the data in EDID register 105EDID1 (or 105EDID0). In other words, display device 100 may have different EDIDs, each corresponding to one of a plurality of DisplayPort connectors.

[0069] After the DisplayPort source device 120 is inserted into the display device 100 (which is already connected to the DisplayPort source device 110 and can display images from the DisplayPort source device 110), the DisplayPort source device 120 attempts to perform a link training process in accordance with the DisplayPort standard at step S220. Although the DisplayPort source device 120 cannot actually perform a link training process in accordance with the DisplayPort standard with the display device 100, the DisplayPort source device 120 can read information related to the result (e.g., the second training completion result) corresponding to the link training process at step S222, and thus determine / consider that the display device 100 is recognized / discovered. In other words, after the DisplayPort source device 120 reads the EDID of the display device 100 and the second training completion result provided by the DPCD register 105DPCD1, the DisplayPort source device 120 inserted into the display device 100 (which is already connected to the DisplayPort source device 110) can recognize / discover the display device 100 as a DisplayPort sink device.

[0070] The DisplayPort source device 120 can read the DPCD register 105DPCD1 of the sub-link circuit 105SubLink through the auxiliary physical circuit 105AUXPhy1 and the auxiliary link circuit 105AUXLink1. The values ​​of the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and / or the INTERLANE_ALIGN_DONE bit of the DPCD register 105DPCD1 can be set to 1. As long as the DisplayPort source device 120 finds that the values ​​of the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and the INTERLANE_ALIGN_DONE bit are equal to 1 (which can be used as the second training completion result) in step 222, the DisplayPort source device 120 can determine / consider that the expected link training process is successfully performed. In other words, the second training completion result may be provided without recognizing a training pattern from the DisplayPort source device 120 or without receiving any training pattern from the DisplayPort source device 120 (i.e., by setting the values ​​of the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit, and the INTERLANE_ALIGN_DONE bit to 1, respectively).

[0071] Please note that since the multiplexer 105M3 electrically connected to the main physical circuit 105MainPhy can be switched to the first DisplayPort connector (connected to the DisplayPort source device 110) instead of the second DisplayPort connector connected to the DisplayPort source device 120, the signal from the second DisplayPort connector connected to the DisplayPort source device 120 is not transmitted to the main physical circuit 105MainPhy. The DisplayPort source device 120 inserted into the display device 100 (connected to the DisplayPort source device 110) can recognize / discover the display device 100; however, the DisplayPort source device 120 cannot perform data transmission and image display when the data of the DisplayPort source device 110 is transmitted.

[0072] After both DisplayPort source devices 110 and 120 are connected to and can identify / discover display device 100, display device 100 may be disconnected from DisplayPort source device 110 and switched to DisplayPort source device 120. For example, a user of display device 100 may unplug DisplayPort source device 110 to display images transmitted from DisplayPort source device 120. Alternatively, a user of display device 100 may switch display device 100 to DisplayPort source device 110 through a user menu of display device 100 to display images transmitted from DisplayPort source device 120.

[0073] The electronic system 10 of the present application can reduce costs. Figure 1 As shown, the physical layer (of the DisplayPort receiver) of the signal processing circuit 105 includes two auxiliary physical circuits 105AUXPhy0 and 105AUXPhy1, but only one main physical circuit 105MainPhy. The number of auxiliary physical circuits 105AUXPhy0 and 105AUXPhy1 of the signal processing circuit 105 may be equal to the number of DisplayPort connectors of the display device 100. However, the number of main physical circuits 105MainPhy of the signal processing circuit 105 is less than the number of auxiliary physical circuits 105AUXPhy0 and 105AUXPhy1, thereby reducing costs.

[0074] In order to reduce costs, the link layer of the signal processing circuit 105 (of the DisplayPort receiver) may include two auxiliary link circuits 105AUXLink0 and 105AUXLink1, but only one main link circuit 105MainLink. The signal processing circuit 105 may also include a sub-link circuit 105SubLink, but the structure of the sub-link circuit 105SubLink is not as complex as the main link circuit 105MainLink to reduce costs. For example, the sub-link circuit 105SubLink lacks a link strategy customization circuit, a stream strategy customization circuit, a stream receiving circuit, and / or a hot plug detection circuit.

[0075] In summary, the auxiliary physical circuits 105AUXPhy0, 105AUXPhy1 (or auxiliary link circuits 105AUXLink0, 105AUXLink1) of the display device 100 respectively correspond to the DisplayPort connectors of the display device 100. Only one DisplayPort connector (or only one auxiliary physical / link circuit) corresponds to the main physical circuit 105MainPhy and / or the main link circuit 105MainLink; the other DisplayPort connector (or another auxiliary physical / link circuit) does not correspond to the main physical circuit 105MainPhy or the main link circuit 105MainLink.

[0076] Figure 3 is a schematic diagram of an electronic system 30 according to an embodiment of the present application.

[0077] The main physical circuit 105MainPhy of the electronic system 30 may include a link training circuit 305TB for performing a link training process. For example, the link training circuit 305TB may control the CDR circuit (of the DisplayPort receiver) of the signal processing circuit 105 of the electronic system 30 to perform CDR training or control the equalizer (of the DisplayPort receiver) of the signal processing circuit 105 to perform equalization training. The control program of the CDR training or equalization training may be implemented by a digital circuit such as the link training circuit 305TB.

[0078] like Figure 3As shown, the DPCD register 105DPCD0 of the main link circuit 105MainLink of the electronic system 30 may include a link status field 305sf0. The first DPCD parameter (e.g., LANEx_CR_DONE bit, LANEx_CHANNEL_EQ_DONE bit, LANEx_SYMBOL_LOCKED bit, or INTERLANE_ALIGN_DONE bit) may be in the link status field 305sf0 of the DPCD register 105DPCD0 (e.g., in the address range of 00202 to 0020C of the DisplayPort standard). The signal processing circuit 105 of the electronic system 30 may repeatedly set the LANEx_CR_DONE bit in the link status field 305sf0 of the DPCD register 105DPCD0 until the optimization of the driver setting of the DisplayPort source device 110 in the CDR training is completed. The values ​​of the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and / or the INTERLANE_ALIGN_DONE bit are all set to 1 to indicate that a specific bit rate, number of channels, voltage swing and / or pre-emphasis level is determined.

[0079] like Figure 3 As shown, the DPCD register 105DPCD1 of the sub-link circuit 105SubLink of the electronic system 30 may include a link status field 305sf1. The second DPCD parameter (e.g., LANEx_CR_DONE bit, LANEx_CHANNEL_EQ_DONE bit, LANEx_SYMBOL_LOCKED bit, or INTERLANE_ALIGN_DONE bit) may be in the link status field 305sf1 of the DPCD register 105DPCD1 (e.g., in the address range of 00202 to 0020C). The values ​​of the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit, and / or the INTERLANE_ALIGN_DONE bit are all set to 1 to indicate that a specific bit rate, number of channels, voltage swing, and / or pre-emphasis level is determined.

[0080] like Figure 3As shown, the signal processing circuit 105 of the electronic system 30 may include a circuit 305MCUFW. The DPCD register 105DPCD1 may be controlled by the firmware of the circuit 305MCUFW. The circuit 305MCUFW may be a microprocessor.

[0081] In one embodiment, the values ​​of the LANEx_CR_DONE bit, LANEx_CHANNEL_EQ_DONE bit, LANEx_SYMBOL_LOCKED bit and / or INTERLANE_ALIGN_DONE bit of the DPCD register 105DPCD1 (each of which may be used as a second DPCD parameter) may be respectively preset to 1 to indicate that the CDR training or equalization training is successful. In one embodiment, the second DPCD parameter stored in the DPCD register 105DPCD1 may be a fixed value. The fixed value is a value used to make the DisplayPort source device 120 believe / believe that the desired link training process can be completed (without going through the full link training process). For example, the DPCD register 105DPCD1 may provide information about the feasibility of 5.4Gbps. If the DisplayPort source device 120 sets the channel speed to 5.4Gbps, the DisplayPort source device 120 may read the training completion result from the DPCD register 105DPCD1. In another embodiment, the second DPCD parameter stored in the DPCD register 105DPCD1 may be a configurable value that causes the DisplayPort source device 120 to believe / trust that the desired link training process can be completed (without going through the full link training process). The second DPCD parameter may be modified by the circuit 305MCUFW. The firmware of the circuit 305MCUFW may control the DPCD register 105DPCD1 to set the second DPCD parameter or cause the DisplayPort source device 120 to believe / trust that the desired link training process can be completed (without going through the full link training process). In another embodiment, part of the second DPCD parameter stored in the DPCD register 105DPCD1 may be a fixed value, another part may be a configurable value, and the other part may follow the DisplayPort standard.

[0082] Through the sub-link circuit 105SubLink (of the DisplayPort receiver) of the signal processing circuit 105, the display device 100 can enable the DisplayPort source device 120 to read the training completion result when the DisplayPort source device 120 attempts to perform the link training process without the help of, for example, a link policy customization circuit (used to maintain link synchronization between the display device 100 and the DisplayPort source device). Accordingly, the DisplayPort source device 120 can identify / discover the display device 100 connected to the DisplayPort source device 110. The DisplayPort source device 120 can regard the display device 100 including the signal processing circuit 105 as a legitimate / authenticated DisplayPort sink device, and can obtain information about the display device 100.

[0083] Figure 4 4 is a schematic diagram of an electronic system 40 according to an embodiment of the present application. The signal processing circuit 105 of the electronic system 40 may include multiplexers 405M1 and 405M2 instead of the multiplexers 105M1 and 105M2.

[0084] If the DisplayPort source device 110 is first inserted into the DisplayPort connector (hereinafter referred to as the first DisplayPort connector) of the display device 100, the multiplexer 105M3 electrically connected to all DisplayPort connectors and the main physical circuit 105MainPhy can be switched to receive a signal from the first DisplayPort connector (connected to the DisplayPort source device 110) to transmit the signal to the main physical circuit 105MainPhy. The signal transmitted from the first DisplayPort connector to the main physical circuit 105MainPhy is hereinafter referred to as the first signal.

[0085] Corresponding to the operation of the multiplexer 105M3, the multiplexer 405M1 electrically connected to the auxiliary physical circuits 105AUXPhy0, 105AUXPhy1 and the auxiliary link circuit 105AUXLink0 can be switched to the auxiliary physical circuit 105AUXPhy0 (connected to the first DisplayPort connector), so that the auxiliary physical circuit 105AUXPhy0 (receiving the second signal from the first DisplayPort connector) can output the processed second signal to the auxiliary link circuit 105AUXLink0. The auxiliary link circuit 105AUXLink0 that receives the processed second signal can output the further processed second signal to the main link circuit 105MainLink.

[0086] Corresponding to the operation of the multiplexer 105M3, the multiplexer 405M2 electrically connected to the auxiliary physical circuits 105AUXPhy0, 105AUXPhy1 and the auxiliary link circuit 105AUXLink1 may switch to the auxiliary physical circuit 105AUXPhy1 (connected to the second DisplayPort connector). After the DisplayPort source device 120 is inserted into the display device 100 connected to the DisplayPort source device 110, the auxiliary physical circuit 105AUXPhy1 (receiving the third signal from the second DisplayPort connector) may output the processed third signal to the auxiliary link circuit 105AUXLink1. The auxiliary link circuit 105AUXLink1 receiving the processed third signal may output the further processed third signal to the sub-link circuit 105SubLink.

[0087] Figure 5 is a schematic diagram of an electronic system 50 according to an embodiment of the present application. The signal processing circuit 105 of the electronic system 50 may include a circuit 505MCU. The circuit 505MCU may be a microprocessor. The circuit 505MCU may be used to generate a control signal to control any one of the multiplexers 105M1 to 105M4 of the electronic system 50.

[0088] like Figure 1 and Figures 3 to 5 As shown, each DisplayPort connector of the display device 100 can be used as a DisplayPort receiving port and includes a terminal corresponding to the main physical circuit 105MainPhy, a terminal corresponding to the auxiliary physical circuit 105AUXPhy0 or 105AUXPhy1, and a terminal corresponding to the hot plug detection circuit 105HPD. In addition, each DisplayPort connector of the display device 100 may include a detection terminal (or interface (socket)) for detecting whether there is a DisplayPort source device.

[0089] The detection terminal of the DisplayPort connector can be connected to the circuit 505MCU. When a DisplayPort source device is inserted into a DisplayPort connector of the display device 100, the voltage of the detection terminal of the DisplayPort connector (as a detection signal) will change. The circuit 505MCU can determine whether a DisplayPort source device is connected to the display device 100 based on the voltage change of the detection terminal. The circuit 505MCU can generate a control signal based on the voltage of the detection terminal to control at least one of the multiplexers of the display device 100 (for example, 105M1 and 105M2).

[0090] For example, when the DisplayPort source device 110 is first inserted into the first DisplayPort connector of the display device 100 and the second DisplayPort connector is not connected to any DisplayPort source device, the voltage of the detection signal det1 at the detection terminal of the first DisplayPort connector may change (e.g., from a voltage of a logic value 0 to a voltage of a logic value 1). The voltage of the detection signal det2 at the detection terminal of the second DisplayPort connector may remain unchanged (e.g., maintain a logic value of 0). According to the detection signals det1 and det2, the circuit 505MCU may output a control signal sel1 (e.g., equal to a logic value of 0) to switch the multiplexer 105M1 to connect the auxiliary physical circuit 105AUXPhy0 to the first DisplayPort connector (connected to the DisplayPort source device 110).

[0091] When the DisplayPort source device 110 is inserted into the second DisplayPort connector of the display device 100 (which is already connected to the DisplayPort source device 110), the voltage of the detection signal det2 at the detection terminal of the second DisplayPort connector may change (e.g., from a voltage of a logic value 0 to a voltage of a logic value 1). The voltage of the detection signal det1 at the detection terminal of the first DisplayPort connector may remain unchanged (e.g., maintain a logic value of 1). According to the detection signals det1 and det2, the circuit 505MCU may output a control signal sel2 (e.g., equal to a logic value of 1) to switch the multiplexer 105M2 to connect the auxiliary physical circuit 105AUXPhy1 to the second DisplayPort connector (which is connected to the DisplayPort source device 120). The multiplexer 105M1 may not switch again.

[0092] In other words, the DisplayPort source devices 110 and 120 sequentially connected to the display device 100 can respectively establish connections with the auxiliary link circuits 105AUXLink0 and 105AUXLink1 through the auxiliary physical circuits 105AUXPhy0 and 105AUXPhy1.

[0093] Figure 6is a schematic diagram of an electronic system 60 of an embodiment of the present application. The electronic system 60 may include a display device 100 and two or more DisplayPort source devices 610SD1-610SDn, where n is an integer. Accordingly, the signal processing circuit 605 of the display device 100 of the electronic system 60 may include two or more auxiliary physical circuits 605AUXPhy0-605AUXPhyn, two or more auxiliary link circuits 605AUXLink0-605AUXLinkn, one or more sub-link circuits 605SubLink1-605SubLinkn and multiplexers 605M1-605Mn. The structure / function of the DisplayPort source devices 610SD1-610SDn is substantially similar to the structure / function of the DisplayPort source devices 110 / 120. Similarly, the component structure / function of the signal processing circuit 605 is substantially similar to the structure / function of the signal processing circuit 105.

[0094] For example, in the CDR training of step S208, the main circuit 610Main1 of the DisplayPort source device 610SD1 may send a clock recovery pattern (CR pattern) of CR-pattern-at-Voltage-Swing-0 (i.e., minimum voltage swing) to the display device 100. The auxiliary circuit 610AUX1 of the DisplayPort source device 610SD1 may send a request to read the LANEx_CR_DONE bit, which is sequentially transmitted through the auxiliary physical circuit 605AUXPhy0, the auxiliary link circuit 605AUXLink0, and the link policy customization circuit 105LinkPM to the DPCD register 105DPCD0. The DisplayPort source device 610SD1 may read the LANEx_CR_DONE bit of the DPCD register 105DPCD0.

[0095] If the value of the LANEx_CR_DONE bit of the DPCD register 105DPCD0 is equal to 0, the main circuit 610Main1 of the DisplayPort source device 610SD1 may send a CR pattern of CR-pattern-at-Voltage-Swing-1 (i.e., a higher voltage swing) to the display device 100. In addition, the auxiliary circuit 610AUX1 of the DisplayPort source device 610SD1 may send a request to read the LANEx_CR_DONE bit. The DisplayPort source device 610SD1 may read the LANEx_CR_DONE bit of the DPCD register 105DPCD0 again. If the value of LANEx_CR_DONE is still equal to 0, the main circuit 610Main1 of the DisplayPort source device 610SD1 may send a CR pattern of CR-pattern-at-Voltage-Swing-2 to the display device 100. The auxiliary circuit 610AUX1 of the DisplayPort source device 610SD1 may send a request to read the LANEx_CR_DONE bit. The DisplayPort source device 610SD1 may read the LANEx_CR_DONE bit of the DPCD register 105DPCD0 again.

[0096] After the DisplayPort source device 610SD2, ... or 610SDn is inserted into the display device 100 (which has been connected to the DisplayPort source device 610SD1 and can display the image from the DisplayPort source device 610SD1), the DisplayPort source device 610SD2, ... or 610SDn can read information related to the result corresponding to the success of the link training process (e.g., the second training completion result) from the DPCD register 605DPCD1, ... or 605DPCDn of the sub-link circuit 605SubLink1, ... or 605SubLinkn in step S222, and thus determine / consider that the display device 100 is recognized / discovered. The values ​​of the LANEx_CR_DONE bit, the LANEx_CHANNEL_EQ_DONE bit, the LANEx_SYMBOL_LOCKED bit and / or the INTERLANE_ALIGN_DONE bit of the DPCD register 605DPCD1, ... or 605DPCDn can be set to 1.

[0097] In the present application, the signal processing circuit may be implemented as a scaler integrated circuit of a computer screen display (as a display device), but is not limited thereto. The signal processing circuit may be connected to a DisplayPort connector of the display device via a trace of a system circuit board.

[0098] In summary, since a display device that does not need to display images from different DisplayPort source devices simultaneously requires fewer main physical circuits and fewer main link circuits, the cost is lower. The signal processing circuit of the display device of the embodiment of the present application helps prevent a DisplayPort source device (which is inserted into the display device after a DisplayPort source device that was earlier connected and is still connected to the display device) from considering the display device as unrecognizable.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A signal processing circuit, compliant with the DisplayPort standard and operating in a display device as a DisplayPort receiving device, characterized in that: include: a main physical circuit for receiving a first signal from a first DisplayPort connector of a plurality of DisplayPort connectors of the display device, the display device being connected to a first DisplayPort source device, the plurality of DisplayPort connectors including the first DisplayPort connector and a second DisplayPort connector; a plurality of auxiliary physical circuits, wherein only a first auxiliary physical circuit among the plurality of auxiliary physical circuits is capable of receiving a second signal from the first DisplayPort connector connected to the first DisplayPort source device; a main link circuit coupled to the main physical circuit; a first auxiliary link circuit coupled to the main link circuit and configured to receive a processed second signal derived from the second signal from the first DisplayPort connector connected to the first DisplayPort source device; a second auxiliary link circuit coupled to the second DisplayPort connector of the plurality of DisplayPort connectors that is not connected to the first DisplayPort source device; as well as A secondary link circuit is coupled to the second auxiliary link circuit and coupled to the second DisplayPort connector of the plurality of DisplayPort connectors through the second auxiliary link circuit.

2. The signal processing circuit according to claim 1, characterized in that The main physical circuit includes a link training circuit for executing a link training process.

3. The signal processing circuit according to claim 1, characterized in that: Each of the plurality of auxiliary physical circuits is coupled to the plurality of DisplayPort connectors, and the signal processing circuit further comprises: a first multiplexer electrically connected to the plurality of DisplayPort connectors of the display device and the first auxiliary physical circuit, for outputting the second signal from the first DisplayPort connector connected to the first DisplayPort source device; a second multiplexer electrically connected to the plurality of DisplayPort connectors of the display device and another auxiliary physical circuit different from the first auxiliary physical circuit; and A third multiplexer is electrically connected to the plurality of DisplayPort connectors of the display device and the main physical circuit, and is used to output the first signal from the first DisplayPort connector connected to the first DisplayPort source device.

4. The signal processing circuit according to claim 1, characterized in that: The plurality of auxiliary physical circuits are respectively coupled to the plurality of DisplayPort connectors, and the signal processing circuit further comprises: a first multiplexer electrically connected to the plurality of auxiliary physical circuits and the first auxiliary link circuit; a second multiplexer electrically connected to the plurality of auxiliary physical circuits and the second auxiliary link circuit; and A third multiplexer is electrically connected to the plurality of DisplayPort connectors of the display device and the main physical circuit, and is used to output the first signal from the first DisplayPort connector connected to the first DisplayPort source device.

5. The signal processing circuit according to claim 1, wherein: The main link circuit includes a first extended display identification data register and a first DisplayPort configuration data register, a first DisplayPort configuration data parameter is set to the first DisplayPort configuration data register according to the result of a link training process, and the sub-link circuit includes a second extended display identification data register and a second DisplayPort configuration data register, a second DisplayPort configuration data parameter of the second DisplayPort configuration data register is fixed or can be modified by a controller.

6. The signal processing circuit according to claim 5, characterized in that: The signal processing circuit provides a training completion result stored in the second DisplayPort configuration data register to a second DisplayPort source device, where the second DisplayPort source device is connected to the display device later than the first DisplayPort source device, and the first DisplayPort source device is still connected to the display device when the second DisplayPort source device is connected to the display device.

7. The signal processing circuit according to claim 6, characterized in that: The signal processing circuit generates the training completion result without recognizing a link training pattern from the second DisplayPort source device or without receiving any link training pattern from the second DisplayPort source device.

8. A link initialization method for use in a signal processing circuit of a display device that complies with the DisplayPort standard and operates as a DisplayPort receiving device, characterized in that: include: When a first DisplayPort source device is connected to the display device and a second DisplayPort source device is still connected to the display device, providing the first DisplayPort source device with a training completion result; Wherein, the signal processing circuit comprises: a main link circuit coupled to a main physical circuit; a first auxiliary link circuit coupled to the main link circuit and configured to receive a processed first signal, the processed first signal being derived from a first signal from a first DisplayPort connector connected to the second DisplayPort source device, the plurality of DisplayPort connectors including the first DisplayPort connector and a second DisplayPort connector; a second auxiliary link circuit coupled to the second DisplayPort connector that is not connected to the second DisplayPort source device; and A secondary link circuit is coupled to the second auxiliary link circuit and coupled to the second DisplayPort connector through the second auxiliary link circuit.

9. The link initialization method according to claim 8, characterized in that: The training complete result is generated if a link training pattern from the first DisplayPort source device is not recognized or if no link training pattern is received from the first DisplayPort source device.

10. The link initialization method according to claim 8, characterized in that: The signal processing circuit comprises: The main physical circuit is used to receive a second signal from the first DisplayPort connector of the plurality of DisplayPort connectors of the display device, the first DisplayPort connector of the display device being connected to the second DisplayPort source device; and A plurality of auxiliary physical circuits, wherein only a first auxiliary physical circuit among the plurality of auxiliary physical circuits is capable of receiving the first signal from the first DisplayPort connector connected to the second DisplayPort source device.

11. The link initialization method according to claim 10, characterized in that: The main physical circuit includes a link training circuit for executing a link training process.

12. The link initialization method according to claim 10, characterized in that: Each of the plurality of auxiliary physical circuits is coupled to the plurality of DisplayPort connectors, and the signal processing circuit further comprises: a first multiplexer electrically connected to the plurality of DisplayPort connectors of the display device and the first auxiliary physical circuit, for outputting the first signal from the first DisplayPort connector connected to the second DisplayPort source device; a second multiplexer electrically connected to the plurality of DisplayPort connectors of the display device and another auxiliary physical circuit different from the first auxiliary physical circuit; and A third multiplexer is electrically connected to the plurality of DisplayPort connectors of the display device and the main physical circuit, and is used to output the second signal from the first DisplayPort connector connected to the second DisplayPort source device.

13. The link initialization method according to claim 10, characterized in that: The plurality of auxiliary physical circuits are respectively coupled to the plurality of DisplayPort connectors, and the signal processing circuit further comprises: a first multiplexer electrically connected to the plurality of auxiliary physical circuits and the first auxiliary link circuit; a second multiplexer electrically connected to the plurality of auxiliary physical circuits and the second auxiliary link circuit; and A third multiplexer is electrically connected to the plurality of DisplayPort connectors of the display device and the main physical circuit, and is used to output the second signal from the first DisplayPort connector connected to the second DisplayPort source device.

14. The link initialization method according to claim 10, characterized in that: The main link circuit includes a first extended display identification data register and a first DisplayPort configuration data register, a first DisplayPort configuration data parameter is set to the first DisplayPort configuration data register according to the result of a link training process, and the sub-link circuit includes a second extended display identification data register and a second DisplayPort configuration data register, a second DisplayPort configuration data parameter of the second DisplayPort configuration data register is fixed or can be modified by a controller.

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