Missile-borne secondary power supply multi-output timing control circuit

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By using a multi-channel isolated output timing control circuit and a two-stage voltage stabilization and filtering output circuit, the problems of large load characteristics, poor control accuracy and stability in traditional methods are solved, and flexible timing adjustment and controllable power-down timing of the missile-borne secondary power supply are realized.

CN114614660BActive Publication Date: 2026-04-21BEIJING INST OF COMP TECH & APPL

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Patent Information

Authority / Receiving Office: CN · China
Patent Type: Patents(China)
Current Assignee / Owner: BEIJING INST OF COMP TECH & APPL
Filing Date: 2022-03-01
Publication Date: 2026-04-21

AI Technical Summary

Technical Problem

Traditional multi-output timing control methods for missile-borne secondary power supplies are easily affected by load characteristics, resulting in poor control accuracy and stability, inflexible timing adjustment, uncontrollable power-down timing, and inability to achieve advanced power-on and delayed power-down of a certain output.

Method used

The system employs a multi-channel isolated output timing control circuit and a two-stage voltage-regulating and filtering output circuit, combined with input reverse connection protection and EMI filtering, power-down retention and pre-regulation, and a DC push-pull isolated converter rectifier circuit, to achieve power-on timing control and power-off timing control.

Benefits of technology

It improves control precision and stability, allows for flexible timing adjustment, and enables controllable power-down timing, allowing for advanced power-on and delayed power-down of a certain output.

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Abstract

This invention relates to a multi-output timing control circuit for a missile-borne secondary power supply, belonging to the field of missile-borne computers. The output terminal of the input reverse connection protection and EMI filtering circuit is connected to the input terminal of the power-down retention and pre-regulation circuit and the input terminal of the multi-channel isolated output timing control circuit. The output terminal of the power-down retention and pre-regulation circuit is connected to the input terminal of the DC push-pull isolated converter rectifier circuit. The output terminal of the DC push-pull isolated converter rectifier circuit is connected to the input terminal of the multi-channel isolated output timing control circuit and the input terminals of two-stage voltage-regulating filter output circuits a, b, and c. The output terminal of the multi-channel isolated output timing control circuit is connected to the input terminals of two-stage voltage-regulating filter output circuits b and c. This invention features low susceptibility to load characteristics, high control accuracy and stability, flexible timing adjustment, controllable power-down timing, and the ability to achieve advanced power-on and delayed power-off for a specific output.

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Description

Technical Field

[0001] This invention belongs to the field of missile-borne computers, specifically relating to a timing control circuit for multiple outputs of a missile-borne secondary power supply. Background Technology

[0002] The power supply for missile-borne computer equipment is typically provided by multiple isolated secondary power supplies, such as the main unit Vout1, bus Vout2, and switching output Vout3. To ensure reliable operation of logic control and data communication during power-on and power-off, the timing requirements for the multiple isolated secondary power supply outputs are as follows: during power-on, the main unit Vout1 leads the bus Vout2 and switching output Vout3; during power-off, the main unit Vout1 lags the bus Vout2 and switching output Vout3. Therefore, designing a multiple isolated output secondary power supply with controllable power-on and power-off timing is particularly important.

[0003] Traditional multi-channel isolated secondary power supply output timing control methods typically employ a cascaded approach where each output is enabled sequentially. For example, after Vout1 output becomes active, Vout2 output is enabled, and after Vout2 output becomes active, Vout3 output is enabled. This control method is susceptible to interference from the characteristics of each load, resulting in poor control accuracy and stability, inflexible timing adjustment, and uncontrollable power-down timing, or the inability to simultaneously achieve the functions of leading power-up and lagging power-down for a particular output. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] The technical problem to be solved by this invention is how to provide a multi-output timing control circuit for missile-borne secondary power supplies, so as to solve the problems of large load characteristics, poor control accuracy and stability, inflexible timing adjustment, and uncontrollable power-down timing or inability to simultaneously achieve advanced power-on and delayed power-down of a certain output in traditional timing control methods.

[0006] (II) Technical Solution

[0007] To address the aforementioned technical problems, this invention proposes a multi-output timing control circuit for an onboard secondary power supply. This timing control circuit includes an input reverse connection protection and EMI filtering circuit, a power-down retention and pre-regulation circuit, a DC push-pull isolation converter and rectifier circuit, a multi-channel isolated output timing control circuit, and a two-stage voltage-regulating and filtering output circuit. The two-stage voltage-regulating and filtering output circuit includes two-stage voltage-regulating and filtering output circuit a, two-stage voltage-regulating and filtering output circuit b, and three-stage voltage-regulating and filtering output circuit c. The output terminal of the input reverse connection protection and EMI filtering circuit is connected to the input terminal of the power-down retention and pre-regulation circuit and the input terminal of the multi-channel isolated output timing control circuit. The output terminal of the power-down retention and pre-regulation circuit is connected to the input terminal of the DC push-pull isolation converter and rectifier circuit. The output terminal of the DC push-pull isolation converter and rectifier circuit is connected to the input terminal of the multi-channel isolated output timing control circuit and the input terminals of two-stage voltage-regulating and filtering output circuits a, b, and c. The output terminal of the multi-channel isolated output timing control circuit is connected to the input terminals of two-stage voltage-regulating and filtering output circuits b and c.

[0008] (III) Beneficial Effects

[0009] This invention proposes a multi-output timing control circuit for a missile-borne secondary power supply. The invention employs a multi-channel isolated output timing control circuit and a two-stage voltage-regulating and filtering output circuit to achieve the power-on timing control function for the multi-channel isolated outputs of the missile-borne secondary power supply. Furthermore, a power-down retention and pre-regulation circuit is used to achieve the power-down timing control function for the multi-channel isolated outputs. This multi-output timing control method for a missile-borne secondary power supply solves the problems of traditional multi-channel isolated secondary power supply output timing control methods, such as susceptibility to mutual influence of load characteristics, poor control accuracy and stability, inflexible timing adjustment, and uncontrollable power-down timing. It features less susceptibility to load characteristics, high control accuracy and stability, flexible timing adjustment, controllable power-down timing, and the ability to simultaneously achieve both advanced power-on and delayed power-down for a specific output. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the principle of the multi-output timing control method for the missile-borne secondary power supply of the present invention.

[0011] Figure 2 This is a circuit diagram of the input reverse connection protection and EMI filtering circuit of the multi-output timing control method for missile-borne secondary power supply of the present invention.

[0012] Figure 3 This is a circuit diagram of the power-down retention and pre-stabilization circuit of the multi-output timing control method for missile-borne secondary power supply of the present invention;

[0013] Figure 4 This is a DC push-pull isolation converter rectifier circuit diagram for the multi-output timing control method of the missile-borne secondary power supply of the present invention;

[0014] Figure 5 This is a circuit diagram of a multi-channel isolated output timing control method for the multiple-channel output timing control method of the missile-borne secondary power supply of the present invention.

[0015] Figure 6 This is a diagram of a two-stage voltage stabilization and filtering output circuit for the multi-output timing control method of the missile-borne secondary power supply of the present invention. Detailed Implementation

[0016] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0017] This invention discloses a multi-output timing control method for a missile-borne secondary power supply, comprising: an input reverse connection protection and EMI filtering circuit (1), a power-down retention and pre-regulation circuit (2), a DC push-pull isolation converter and rectifier circuit (3), a multi-channel isolated output timing control circuit (4), and a two-stage voltage-regulating and filtering output circuit (5). The output terminal of the input reverse connection protection and EMI filtering circuit (1) is connected to the input terminal of the power-down retention and pre-regulation circuit (2) and the input terminal of the multi-channel isolated output timing control circuit (4). The output terminal of the power-down retention and pre-regulation circuit (2) is connected to the input terminal of the DC push-pull isolation converter and rectifier circuit (3). The output terminal of the DC push-pull isolation converter and rectifier circuit (3) is connected to the input terminal of the multi-channel isolated output timing control circuit (4) and the input terminal of the two-stage voltage-regulating and filtering output circuit (5). The output terminal of the multi-channel isolated output timing control circuit (4) is connected to the input terminal of the two-stage voltage-regulating and filtering output circuit (5).

[0018] This invention employs a multi-channel isolated output timing control circuit and a two-stage voltage-regulating and filtering output circuit to achieve the power-on timing control function of the multi-channel isolated outputs of the missile-borne secondary power supply. Furthermore, it utilizes a power-down retention and pre-regulation circuit to achieve the power-down timing control function of the multi-channel isolated outputs. This missile-borne secondary power supply multi-output timing control method solves the problems of traditional multi-channel isolated secondary power supply output timing control methods, such as susceptibility to mutual influence of load characteristics, poor control accuracy and stability, inflexible timing adjustment, and uncontrollable power-down timing. It features less susceptibility to load characteristics, high control accuracy and stability, flexible timing adjustment, controllable power-down timing, and the ability to simultaneously achieve both advanced power-on and delayed power-down of a specific output.

[0019] The purpose of this invention is to provide a timing control method for multiple isolated outputs of missile-borne secondary power supplies, which solves the problems of traditional timing control methods, such as the large influence of load characteristics, poor control accuracy and stability, inflexible timing adjustment, and uncontrollable power-down timing or the inability to simultaneously achieve advanced power-on and delayed power-down of a certain output.

[0020] A multi-output timing control method for missile-borne secondary power supplies is applied to a circuit including an input reverse connection protection and EMI filter circuit, a power-down retention and pre-stabilization circuit, a DC push-pull isolation converter rectifier circuit, a multi-channel isolation output timing control circuit, and a two-stage voltage stabilization and filtering output circuit. The two-stage voltage stabilization and filtering output circuit includes two-stage voltage stabilization and filtering output circuit a, two-stage voltage stabilization and filtering output circuit b, and two-stage voltage stabilization and filtering output circuit c.

[0021] The input reverse connection protection and EMI filtering circuit includes: transient voltage suppressor diode D1, transient voltage suppressor diode D2, ideal diode controller U1, Zener diode D3, N-channel MOSFET S1, current limiting resistor R1, filter capacitor C1, common-mode inductor L1, differential-mode capacitor C2, differential-mode capacitor C3, differential-mode inductor L2, common-mode capacitor C4, and common-mode capacitor C5. The power-down retention and pre-regulation circuit includes: current limiting resistor R2, current limiting resistor R3, energy storage capacitor C6, energy storage capacitor C7, rectifier diode D4, synchronous switching buck-boost controller U2, N-channel MOSFET S2, N-channel MOSFET S3, N-channel MOSFET S4, N-channel MOSFET S5, energy storage inductor L2, voltage divider resistors R4 and R5, filter capacitor C8, current sampling resistor R6, voltage divider sampling resistor R7, voltage divider sampling resistor R8, and filter capacitor C9. The DC push-pull isolated converter rectifier circuit includes: pulse width modulation push-pull controller U3, N-channel MOSFET S6, N-channel MOSFET S7, high-frequency switching transformer T1, rectifier diodes D5, D6, D7, D8, D9, and D10, filter inductors L3, L4, and L5, and filter capacitors C10, C11, and C12. The multi-channel isolated output timing control circuit includes: a high-precision voltage reference source V1, an optocoupler B1, voltage divider and current-limiting resistors R9, R10, and R11, energy storage delay capacitors C13 and C14, current-limiting resistors R12 and R13, a Zener diode D11, voltage divider and current-limiting resistors R14, R15, R16, and R17, and filter capacitors C15 and C16. The two-stage voltage regulator and filter output circuit includes: low dropout regulator U4, low dropout regulator U5, low dropout regulator U6, voltage divider sampling resistor R18, voltage divider sampling resistor R19, voltage divider sampling resistor R20, voltage divider sampling resistor R21, voltage divider sampling resistor R22, voltage divider sampling resistor R23, output filter capacitor C17, output filter capacitor C18, output filter capacitor C19, load resistor RL1, and load resistor RL2.

[0022] The output of the input reverse connection protection and EMI filter circuit is connected to the input of the power-down retention and pre-regulation circuit and the input of the multi-channel isolated output timing control circuit. The output of the power-down retention and pre-regulation circuit is connected to the input of the DC push-pull isolated converter rectifier circuit. The output of the DC push-pull isolated converter rectifier circuit is connected to the input of the multi-channel isolated output timing control circuit and the inputs of the two-stage voltage-regulating filter output circuits a, b, and c. The output of the multi-channel isolated output timing control circuit is connected to the inputs of the two-stage voltage-regulating filter output circuits b and c.

[0023] In the input reverse connection protection and EMI filtering circuit, the cathode of transient voltage suppressor diode D1 is connected to the high-side input Vin+. The IN terminal of ideal diode controller U1 is connected to the high-side input Vin+, the SOURCE terminal of ideal diode controller U1, the source of N-channel MOSFET S1, and the anode of Zener diode D3. The gate of N-channel MOSFET S1 is connected to the cathode of Zener diode D3 and the GATE terminal of ideal diode controller U1. The drain of N-channel MOSFET S1 is connected to the OUT terminal of ideal diode controller U1, one end of filter capacitor C1, one end of differential-mode capacitor C2, and the positive input terminal of common-mode inductor L1. The anode of transient voltage suppressor diode D1 is connected to the high-side input of transient voltage suppressor diode D2. The anode of diode 2 is connected to the cathode of transient voltage suppression diode D2, which is connected to the VSS terminal of ideal diode controller U1, one end of current limiting resistor R1, and the other end of filter capacitor C1. The negative input terminal of common mode inductor L1 is connected to the other end of differential mode capacitor C2, the other end of current limiting resistor R1, and input ground Vin-. The positive output terminal of common mode inductor L1 is connected to one end of differential mode inductor L2 and one end of differential mode capacitor C3. The other end of differential mode inductor L2 is connected to one end of common mode capacitor C4 and output high-side Va. The other end of common mode capacitor C4 is connected to one end of common mode capacitor C5 and chassis ground. The other end of common mode capacitor C5 is connected to the negative output terminal of common mode inductor L1, the other end of differential mode capacitor C3, and signal ground.

[0024] In the power-down retention and pre-regulation circuit, the high-side input Va is connected to one end of current-limiting resistor R2, one end of current-limiting resistor R3, the cathode of rectifier diode D4, one end of voltage divider resistor R4, one end of filter capacitor C8, and the drain of N-channel MOSFET S2. The other end of current-limiting resistor R2 is connected to the other end of current-limiting resistor R3, the anode of rectifier diode D4, the positive terminal of energy storage capacitor C6, and the positive terminal of energy storage capacitor C7. The other end of voltage divider resistor R4 is connected to the RUN terminal of synchronous switch buck-boost controller U2. One end of the voltage divider resistor R5 is connected, and the other end of the voltage divider resistor R5 is connected to the negative terminals of the energy storage capacitors C6 and C7, the other end of the filter capacitor C8, and the signal ground. The source of the N-channel MOSFET S2 is connected to one end of the energy storage inductor L2 and the drain of the N-channel MOSFET S4. The other end of the energy storage inductor L2 is connected to the source of the N-channel MOSFET S3 and the drain of the N-channel MOSFET S5. The source of the N-channel MOSFET S4 is connected to the source of the N-channel MOSFET S5 and the current sampling circuit. One end of resistor R6 is connected to the ISENSE+ terminal of the synchronous switch buck-boost controller U2. The other end of the current sampling resistor R6 is connected to the ISENSE- terminal, the GND terminal, and the signal ground of the synchronous switch buck-boost controller U2, respectively. The gate of N-channel MOSFET S2 is connected to the TG1 terminal of the synchronous switch buck-boost controller U2. The gate of N-channel MOSFET S4 is connected to the BG1 terminal of the synchronous switch buck-boost controller U2. The gate of N-channel MOSFET S3 is connected to the synchronous switch buck-boost controller U2. The TG2 terminal of the buck controller U2 is connected, the gate of the N-channel MOSFET S5 is connected to the BG2 terminal of the synchronous switch buck-boost controller U2, the drain of the N-channel MOSFET S3 is connected to one end of the voltage divider sampling resistor R7, one end of the filter capacitor C9, and the high-side output Vb, respectively. The other end of the voltage divider sampling resistor R7 is connected to the VSENSE terminal of the synchronous switch buck-boost controller U2 and one end of the voltage divider sampling resistor R8, respectively. The other end of the voltage divider sampling resistor R8 is connected to the other end of the filter capacitor C9 and the signal ground, respectively.

[0025] In the DC push-pull isolated converter rectifier circuit, the high-side input Vb is connected to the VCC terminal of the pulse width modulation push-pull controller U3 and the 2nd terminal of the primary winding Np1 of the high-frequency switching transformer T1, respectively. The 1st terminal of the primary winding Np1 of the high-frequency switching transformer T1 is connected to the drain of the N-channel field-effect transistor S6, and the 3rd terminal of the primary winding Np1 of the high-frequency switching transformer T1 is connected to the drain of the N-channel field-effect transistor S7. The source of the N-channel field-effect transistor S6 is connected to the source of the N-channel field-effect transistor S7, the GND terminal of the pulse width modulation push-pull controller U3, and the signal ground, respectively. The gate of N-channel MOSFET S6 is connected to the PWM1 terminal of pulse width modulation push-pull controller U3. The gate of N-channel MOSFET S7 is connected to the PWM2 terminal of pulse width modulation push-pull controller U3. Terminal 4 of the secondary winding Ns1 of high-frequency switching transformer T1 is connected to the anode of rectifier diode D5. The cathode of rectifier diode D5 is connected to the cathode of rectifier diode D6 and one end of filter inductor L3. The anode of rectifier diode D6 is connected to terminal 6 of the secondary winding Ns1 of high-frequency switching transformer T1. The other end of filter inductor L3 is connected to one end of filter capacitor C10 and the positive output terminal Vc1+. The other end of filter capacitor C10 is connected to terminal 5 of the secondary winding Ns1 of high-frequency switching transformer T1 and the negative output terminal Vc1-. Terminal 7 of the secondary winding Ns2 of high-frequency switching transformer T1 is connected to the anode of rectifier diode D7. The cathode of rectifier diode D7 is connected to the cathode of rectifier diode D8 and the filter inductor L3. One end of L4 is connected to the anode of rectifier diode D8, which is connected to terminal 9 of the secondary winding Ns2 of high-frequency switching transformer T1. The other end of filter inductor L4 is connected to one end of filter capacitor C11 and the positive output terminal Vc2+. The other end of filter capacitor C11 is connected to terminal 8 of the secondary winding Ns2 of high-frequency switching transformer T1 and the negative output terminal Vc2-. Terminal 10 of the secondary winding Ns3 of high-frequency switching transformer T1 is connected to the anode of rectifier diode D9. The cathode of rectifier diode D9 is connected to the cathode of rectifier diode D10 and one end of filter inductor L5. The anode of rectifier diode D10 is connected to terminal 12 of the secondary winding Ns3 of high-frequency switching transformer T1. The other end of filter inductor L5 is connected to one end of filter capacitor C12 and the positive output terminal Vc3+. The other end of filter capacitor C12 is connected to terminal 11 of the secondary winding Ns3 of high-frequency switching transformer T1 and the negative output terminal Vc3-.

[0026] In the multi-channel isolated output timing control circuit, the high-side input Va is connected to one end of the voltage divider and current-limiting resistor R9, one end of the current-limiting resistor R12, and one end of the current-limiting resistor R13. The other end of the voltage divider and current-limiting resistor R9 is connected to one end of the voltage divider and current-limiting resistor R10. The other end of the voltage divider and current-limiting resistor R10 is connected to the Ref terminal of the high-precision voltage reference source V1, one end of the voltage divider and current-limiting resistor R11, one end of the energy storage delay capacitor C13, and one end of the energy storage delay capacitor C14. The other end of the voltage divider and current-limiting resistor R11 is connected to the energy storage delay capacitor C14. The other end of capacitor C13, the other end of energy storage delay capacitor C14, the anode A terminal of high-precision voltage reference source V1, and signal ground are connected. The other end of current limiting resistor R12 is connected to the other end of current limiting resistor R13, the cathode of Zener diode D11, and the cathode C terminal of high-precision voltage reference source V1. The anode of Zener diode D11 is connected to the input terminal 1+ and input terminal 2+ of optocoupler B1. The input terminal 1- of optocoupler B1 is connected to the input terminal 2- of optocoupler B1 and signal ground. The output terminal 1C of optocoupler B1 is connected to one end of voltage divider and current limiting resistor R14, one end of voltage divider and current limiting resistor R15, one end of filter capacitor C15, and the high-side output Vd1. The other end of voltage divider and current limiting resistor R14 is connected to the positive input terminal Vc2+. The output terminal 1E of optocoupler B1 is connected to the other end of voltage divider and current limiting resistor R15, the other end of filter capacitor C15, and the negative input terminal Vc2-. The output terminal 2C of optocoupler B1 is connected to one end of voltage divider and current limiting resistor R16, one end of voltage divider and current limiting resistor R17, one end of filter capacitor C16, and the high-side output Vd2. The other end of voltage divider and current limiting resistor R16 is connected to the positive input terminal Vc3+. The output terminal 2E of optocoupler B1 is connected to the other end of voltage divider and current limiting resistor R17, the other end of filter capacitor C16, and the negative input terminal Vc3-.

[0027] In the two-stage voltage regulator and filter output circuit, the positive input terminal Vc1+ is connected to the IN terminal and the EN terminal of the low-dropout regulator U4, respectively. The OUT terminal of the low-dropout regulator U4 is connected to one end of the voltage divider sampling resistor R18, one end of the output filter capacitor C17, and the high-side output Vout1, respectively. The other end of the voltage divider sampling resistor R18 is connected to the ADJ terminal and one end of the voltage divider sampling resistor R19 of the low-dropout regulator U4, respectively. The GND terminal of the low-dropout regulator U4... The input negative terminal Vc1-, the other end of the voltage divider sampling resistor R19, and the other end of the output filter capacitor C17 are connected respectively. The input positive terminal Vc2+ is connected to the IN terminal of the low-dropout regulator U5. The input high-side terminal Vd1 is connected to the EN terminal of the low-dropout regulator U5. The OUT terminal of the low-dropout regulator U5 is connected to one end of the voltage divider sampling resistor R20, one end of the output filter capacitor C18, one end of the load resistor RL1, and the output high-side terminal Vout2. The voltage divider sampling resistor R20... The other end is connected to the ADJ terminal of the low-dropout regulator U5 and one end of the voltage divider sampling resistor R21, respectively. The GND terminal of the low-dropout regulator U5 is connected to the negative input terminal Vc2-, the other end of the voltage divider sampling resistor R21, the other end of the output filter capacitor C18, and the other end of the load resistor RL1, respectively. The positive input terminal Vc3+ is connected to the IN terminal of the low-dropout regulator U6, the high-side input Vd2 is connected to the EN terminal of the low-dropout regulator U6, and the OUT terminal of the low-dropout regulator U6 is connected to the OUT terminal. The other end of the voltage divider sampling resistor R22 is connected to one end of the voltage divider sampling resistor R22, one end of the output filter capacitor C19, one end of the load resistor RL2, and the high-side output Vout3, respectively. The other end of the voltage divider sampling resistor R22 is connected to the ADJ terminal of the low-dropout regulator U6 and one end of the voltage divider sampling resistor R23, respectively. The GND terminal of the low-dropout regulator U6 is connected to the negative input terminal Vc3-, the other end of the voltage divider sampling resistor R23, the other end of the output filter capacitor C19, and the other end of the load resistor RL2, respectively.

[0028] In a multi-output timing control method for an onboard secondary power supply, the input Vin enters the input reverse connection protection and EMI filtering circuit, which filters both common-mode and differential-mode signals while implementing reverse connection protection. The EMI filtering circuit filters out external electromagnetic interference introduced on the input line and suppresses electromagnetic interference emitted by high-frequency signal circuits to the outside, thus preventing interference to other electronic equipment operating normally in the same electromagnetic environment. The input Vin first enters the input reverse connection protection and EMI filtering circuit. Transient voltage suppression diodes D1 and D2 suppress both forward and reverse input transient interference voltages. When the input Vin is connected in reverse, the transient voltage suppression diode D2 is reverse-biased and cut off, and the N-channel MOSFET S1 is cut off. When the input Vin is connected in forward direction, the ideal diode controller U1 drives the N-channel MOSFET S1 to conduct, thus achieving the input reverse connection protection function. The input Vin enters the EMI filter circuit for common-mode and differential-mode signal filtering. The first-stage common-mode and differential-mode signal filtering circuit consists of common-mode inductor L1, differential-mode capacitors C2 and C3, while the second-stage common-mode and differential-mode signal filtering circuit consists of differential-mode inductor L2, common-mode capacitors C4 and C5. The EMI filter circuit filters out external electromagnetic interference introduced from the input line and suppresses electromagnetic interference emitted by high-frequency signal circuits to prevent interference with the normal operation of other electronic devices in the same electromagnetic environment. After reverse connection protection and the EMI filter circuit, the input Vin outputs Va, which is then fed into the power-down retention and pre-regulation circuit and the multi-channel isolated output timing control circuit.

[0029] The input reverse connection protection and EMI filtering circuit outputs Va, which then enters the power-down retention and pre-regulation circuit. The input voltage Va first charges the energy storage capacitors C6 and C7 via current-limiting resistors R2 and R3 in the power-down retention circuit. Due to the front-end reverse connection protection circuit, energy storage capacitors C6 and C7 can supply power to the downstream circuit via rectifier diode D4 when the input Va is powered down, achieving power-down retention. Simultaneously, the input voltage Va enters the pre-regulation circuit. The synchronous switching buck-boost controller U2 controls the conduction or cutoff of N-channel MOSFETs S2, S3, S4, and S5 to achieve synchronous switching buck-boost conversion, realizing a wide-range input pre-regulation function. The synchronous switching buck-boost controller U2 implements undervoltage protection through voltage divider resistors R4 and R5, and achieves closed-loop feedback of current and voltage through current sampling resistor R6, voltage dividing sampling resistors R7 and R8, enabling rapid and accurate switching regulation of the output Vb.

[0030] The output Vb from the power-down retention and pre-regulation circuit enters the DC push-pull isolation converter and rectifier circuit. The pulse width modulation push-pull controller U3 controls the alternating conduction or cutoff of N-channel MOSFETs S6 and S7 to convert the input voltage Vb through the high-frequency switching transformer T1 for isolation conversion, followed by rectification and filtering to output multiple isolated secondary voltages. The output of the secondary winding Ns1 of the high-frequency switching transformer T1 is rectified by rectifier diodes D5 and D6, and then filtered by filter inductor L3 and filter capacitor C10 to complete LC filtering. Output Vc1 is produced by the secondary winding Ns2 of the high-frequency switching transformer T1, which is rectified by rectifier diodes D7 and D8, then filtered by filter inductor L4 and filter capacitor C11 to produce output Vc2. Similarly, output Vc3 is produced by the secondary winding Ns3 of the high-frequency switching transformer T1, which is rectified by rectifier diodes D9 and D10, then filtered by filter inductor L5 and filter capacitor C12 to produce output Vc3. The secondary voltages Vc1, Vc2, and Vc3 are isolated from each other. Output voltage Vc1 is fed into the two-stage voltage regulator and filter output circuit, while output voltages Vc2 and Vc3 are simultaneously fed into the multi-channel isolated output timing control circuit and the two-stage voltage regulator and filter output circuit, respectively.

[0031] In the multi-channel isolated output timing control circuit, the reference terminal Ref of the high-precision voltage reference source V1 samples the input voltage Va through voltage divider and current limiting resistors R9, R10, and R11, and charges it after a delay through energy storage delay capacitors C13 and C14. When the voltage at the reference terminal Ref of the high-precision voltage reference source V1 is less than the set value, the output cathode C terminal of the high-precision voltage reference source V1 is at a high level. At this time, the input terminal of the optocoupler B1 is turned on, and the outputs Vd1 and Vd2 are connected through the output terminal of the optocoupler. When the saturation conduction is pulled low, and the reference terminal Ref voltage of the high-precision voltage reference source V1 reaches the set value, the output cathode C terminal of the high-precision voltage reference source V1 outputs a low level. At this time, the input terminals of the Zener diode D11 and the optocoupler B1 are cut off, and consequently the output terminal of the optocoupler B1 is cut off. The output Vd1 is pulled up to the input voltage Vc2 after being divided by the voltage divider and current limiting resistors R14 and R15. The output Vd2 is pulled up to the input voltage Vc3 after being divided by the voltage divider and current limiting resistors R16 and R17.

[0032] In the two-stage voltage regulator and filter output circuit, the input voltage Vc1 is regulated and filtered by the low-dropout regulator U4, resulting in output Vout1; the input voltage Vc2 is regulated and filtered by the low-dropout regulator U5, resulting in output Vout2; and the input voltage Vc3 is regulated and filtered by the low-dropout regulator U6, resulting in output Vout3. The EN terminal of the low-dropout regulator U4 is directly pulled up to the IN terminal, meaning that output Vout1 is active when input voltage Vc1 is active. The EN terminal of the low-dropout regulator U5 is controlled by the input voltage Vd1; output Vout2 is active only when both input voltages Vc2 and Vd1 are active. Similarly, the EN terminal of the low-dropout regulator U6 is controlled by the input voltage Vd2; output Vout3 is active only when both input voltages Vc3 and Vd2 are active.

[0033] When the secondary power supply of the missile-borne computer is powered on, the input voltage Vin is output as voltage Va after passing through the input reverse connection protection and EMI filter circuit. When the input voltage Va rises from zero voltage to a value greater than the undervoltage protection voltage setting of the power-down retention and pre-regulation circuit, the output voltage Vb of the pre-regulation circuit becomes effective. The output voltage Vb enters the DC push-pull isolation converter and rectifier circuit, and after push-pull isolation converter and rectifier, it outputs three isolated secondary voltages Vc1, Vc2 and Vc3. The output voltage Vc1 is regulated and adjusted by the low-dropout regulator U4 in the two-stage voltage regulation and filtering output circuit, resulting in output Vout1. Upon power-up of output Vout1, the voltage at the Ref terminal of the high-precision voltage reference source V1 in the multi-channel isolated output timing control circuit is less than the set value. The output cathode C terminal of the high-precision voltage reference source V1 is at a high level, the input terminal of the optocoupler B1 is turned on, and outputs Vd1 and Vd2 are at a low level. The outputs of the low-dropout regulators U5 and U6 in the two-stage voltage regulation and filtering output circuit are disabled. As the input voltage Va continues to rise, when the high-precision voltage in the multi-channel isolated output timing control circuit... When the voltage at the Ref terminal of the reference source V1 reaches the set value after RC delay charging, the output cathode C terminal of the high-precision voltage reference source V1 outputs a low level, the Zener diode D11 is cut off, the input terminal of the optocoupler B1 is cut off, and the output Vd1 is high. The low-dropout regulator U5 of the secondary voltage regulation and filtering output circuit outputs Vout2, which is active. Similarly, when the output Vd2 is high, the low-dropout regulator U6 of the secondary voltage regulation and filtering output circuit outputs Vout3, which is active. At this time, the power-on of outputs Vout2 and Vout3 is completed, thus realizing the function of output Vout1 leading the power-on of outputs Vout2 and Vout3. As the input voltage Va continues to rise to the rated voltage, the voltage on the energy storage capacitors C6 and C7 is also charged from Va to the rated voltage through the current-limiting resistors R2 and R3.

[0034] When the secondary power supply of the missile-borne computer is powered down, the input voltage Va begins to drop from the rated voltage. Due to the reverse connection protection circuit at the front end, the energy of the energy storage capacitors C6 and C7 is discharged from the rated voltage through the rectifier diode D4 branch to the back-end circuit to ensure its normal operation for a certain period of time (tens of milliseconds). As the input voltage Va continues to drop, when the voltage at the Ref terminal of the high-precision voltage reference source V1 in the multi-channel isolated output timing control circuit is less than its set value, the output cathode C terminal of the high-precision voltage reference source V1 outputs a high level, the input terminal of the optocoupler B1 is turned on, and the outputs Vd1 and Vd2 are at a low level. The outputs of the low-dropout regulators U5 and U6 in the secondary voltage regulation and filtering output circuit are disabled. At this time, the power-down of outputs Vout2 and Vout3 is completed. When the load of outputs Vout2 and Vout3 is a capacitive light load, adding load resistors RL1 and RL2 can accelerate their power-down. At this time, since the output of the power-down retention and wide-range pre-regulation circuit is normal, the output Vout1 is still effective. When the voltage of the energy storage capacitors C6 and C7 discharges to a value lower than the undervoltage protection voltage setting of the power-down retention and pre-regulation circuit, the output voltage Vb of the pre-regulation circuit is disabled. Consequently, the output Vc1 of the DC push-pull isolation converter rectifier circuit is disabled, and the output of the low-dropout regulator U4 in the secondary voltage regulation and filter output circuit is disabled. At this time, the power-down of output Vout1 is completed, thus realizing the function of output Vout1 lagging behind the power-down of outputs Vout2 and Vout3. Detailed implementation method:

[0036] A multi-output timing control method for an onboard secondary power supply is applied to a circuit including an input reverse connection protection and EMI filtering circuit, a power-down retention and pre-regulation circuit, a DC push-pull isolation converter rectifier circuit, a multi-channel isolated output timing control circuit, and a two-stage voltage regulation and filtering output circuit. The input reverse connection protection and EMI filtering circuit includes: transient voltage suppression diode D1, transient voltage suppression diode D2, an ideal diode controller U1, a Zener diode D3, an N-channel MOSFET S1, a current-limiting resistor R1, a filter capacitor C1, a common-mode inductor L1, a differential-mode capacitor C2, a differential-mode capacitor C3, a differential-mode inductor L2, a common-mode capacitor C4, and a common-mode capacitor C5. The power-down retention and pre-regulation circuit includes: current-limiting resistor R2, current-limiting resistor R3, energy storage capacitor C6, energy storage capacitor C7, rectifier diode D4, synchronous switching buck-boost controller U2, N-channel MOSFET S2, N-channel MOSFET S3, N-channel MOSFET S4, N-channel MOSFET S5, energy storage inductor L2, voltage divider resistor R4, voltage divider resistor R5, filter capacitor C8, current sampling resistor R6, voltage divider sampling resistor R7, voltage divider sampling resistor R8, and filter capacitor C9. The DC push-pull isolated converter rectifier circuit includes: pulse width modulation push-pull controller U3, N-channel MOSFET S6, N-channel MOSFET S7, high-frequency switching transformer T1, rectifier diodes D5, D6, D7, D8, D9, and D10, filter inductors L3, L4, and L5, and filter capacitors C10, C11, and C12. The multi-channel isolated output timing control circuit includes: a high-precision voltage reference source V1, an optocoupler B1, voltage divider and current-limiting resistors R9, R10, and R11, energy storage delay capacitors C13 and C14, current-limiting resistors R12 and R13, a Zener diode D11, voltage divider and current-limiting resistors R14, R15, R16, and R17, and filter capacitors C15 and C16. The two-stage voltage regulator and filter output circuit includes: low dropout regulator U4, low dropout regulator U5, low dropout regulator U6, voltage divider sampling resistor R18, voltage divider sampling resistor R19, voltage divider sampling resistor R20, voltage divider sampling resistor R21, voltage divider sampling resistor R22, voltage divider sampling resistor R23, output filter capacitor C17, output filter capacitor C18, output filter capacitor C19, load resistor RL1, and load resistor RL2.

[0037] The output of the input reverse connection protection and EMI filter circuit is connected to the input of the power-down retention and pre-regulation circuit and the input of the multi-channel isolated output timing control circuit. The output of the power-down retention and pre-regulation circuit is connected to...

[0038] The input terminal of the DC push-pull isolation converter rectifier circuit is connected to the input terminal of the multi-channel isolation output timing control circuit and the input terminal of the secondary voltage regulator filter output circuit. The output terminal of the multi-channel isolation output timing control circuit is connected to the input terminal of the secondary voltage regulator filter output circuit.

[0039] In the input reverse connection protection and EMI filtering circuit, the cathode of transient voltage suppressor diode D1 is connected to the high-side input Vin+. The IN terminal of ideal diode controller U1 is connected to the high-side input Vin+, the SOURCE terminal of ideal diode controller U1, the source of N-channel MOSFET S1, and the anode of Zener diode D3. The gate of N-channel MOSFET S1 is connected to the cathode of Zener diode D3 and the GATE terminal of ideal diode controller U1. The drain of N-channel MOSFET S1 is connected to the OUT terminal of ideal diode controller U1, one end of filter capacitor C1, one end of differential-mode capacitor C2, and the positive input terminal of common-mode inductor L1. The anode of transient voltage suppressor diode D1 is connected to the high-side input of transient voltage suppressor diode D2. The anode of diode 2 is connected to the cathode of transient voltage suppression diode D2, which is connected to the VSS terminal of ideal diode controller U1, one end of current limiting resistor R1, and the other end of filter capacitor C1. The negative input terminal of common mode inductor L1 is connected to the other end of differential mode capacitor C2, the other end of current limiting resistor R1, and input ground Vin-. The positive output terminal of common mode inductor L1 is connected to one end of differential mode inductor L2 and one end of differential mode capacitor C3. The other end of differential mode inductor L2 is connected to one end of common mode capacitor C4 and output high-side Va. The other end of common mode capacitor C4 is connected to one end of common mode capacitor C5 and chassis ground. The other end of common mode capacitor C5 is connected to the negative output terminal of common mode inductor L1, the other end of differential mode capacitor C3, and signal ground.

[0040] In the power-down retention and pre-regulation circuit, the high-side input Va is connected to one end of current-limiting resistor R2, one end of current-limiting resistor R3, the cathode of rectifier diode D4, one end of voltage divider resistor R4, one end of filter capacitor C8, and the drain of N-channel MOSFET S2. The other end of current-limiting resistor R2 is connected to the other end of current-limiting resistor R3, the anode of rectifier diode D4, the positive terminal of energy storage capacitor C6, and the positive terminal of energy storage capacitor C7. The other end of voltage divider resistor R4 is connected to the RUN terminal of synchronous switch buck-boost controller U2, one end of voltage divider resistor R5, and the other end of voltage divider resistor R5 is connected to the negative terminals of energy storage capacitor C6 and C7, the other end of filter capacitor C8, and signal ground. The source of N-channel MOSFET S2 is connected to one end of energy storage inductor L2 and the drain of N-channel MOSFET S4. The other end of energy storage inductor L2... The source of N-channel MOSFET S3 and the drain of N-channel MOSFET S5 are connected to each other respectively. The source of N-channel MOSFET S4 is connected to the source of N-channel MOSFET S5, one end of current sampling resistor R6, and the ISENSE+ terminal of synchronous switch buck-boost controller U2. The other end of current sampling resistor R6 is connected to the ISENSE- terminal, GND terminal, and signal ground of synchronous switch buck-boost controller U2 respectively. The gate of N-channel MOSFET S2 is connected to the TG1 terminal of synchronous switch buck-boost controller U2. The gate of N-channel MOSFET S4 is connected to the BG1 terminal of synchronous switch buck-boost controller U2. The gate of N-channel MOSFET S3 is connected to the TG2 terminal of synchronous switch buck-boost controller U2. The gate of N-channel MOSFET S5 is connected to the BG2 terminal of synchronous switch buck-boost controller U2.

[0041] The drain of the N-channel MOSFET S3 is connected to one end of the voltage divider sampling resistor R7, one end of the filter capacitor C9, and the high-side output Vb, respectively. The other end of the voltage divider sampling resistor R7 is connected to the VSENSE terminal of the synchronous switch buck-boost controller U2 and one end of the voltage divider sampling resistor R8, respectively. The other end of the voltage divider sampling resistor R8 is connected to the other end of the filter capacitor C9 and the signal ground, respectively.

[0042] In the DC push-pull isolated converter rectifier circuit, the high-side input Vb is connected to the VCC terminal of the pulse width modulation push-pull controller U3 and the 2nd terminal of the primary winding Np1 of the high-frequency switching transformer T1, respectively. The 1st terminal of the primary winding Np1 of the high-frequency switching transformer T1 is connected to the drain of the N-channel field-effect transistor S6, and the 3rd terminal of the primary winding Np1 of the high-frequency switching transformer T1 is connected to the drain of the N-channel field-effect transistor S7. The source of the N-channel field-effect transistor S6 is connected to the source of the N-channel field-effect transistor S7, the GND terminal of the pulse width modulation push-pull controller U3, and the signal ground, respectively. The gate of N-channel MOSFET S6 is connected to the PWM1 terminal of pulse width modulation push-pull controller U3, and the gate of N-channel MOSFET S7 is connected to the PWM2 terminal of pulse width modulation push-pull controller U3. Terminal 4 of the secondary winding Ns1 of high-frequency switching transformer T1 is connected to the anode of rectifier diode D5. The cathode of rectifier diode D5 is connected to the cathode of rectifier diode D6 and one end of filter inductor L3. The anode of rectifier diode D6 is connected to terminal 6 of the secondary winding Ns1 of high-frequency switching transformer T1. The other end of filter inductor L3 is connected to one end of filter capacitor C10 and the positive output terminal Vc1+. The other end of filter capacitor C10 is connected to terminal 5 of the secondary winding Ns1 of high-frequency switching transformer T1 and the negative output terminal Vc1-.

[0043] Terminal 7 of the secondary winding Ns2 of the high-frequency switching transformer T1 is connected to the anode of rectifier diode D7. The cathode of rectifier diode D7 is connected to the cathode of rectifier diode D8 and one end of filter inductor L4. The anode of rectifier diode D8 is connected to terminal 9 of the secondary winding Ns2 of the high-frequency switching transformer T1. The other end of filter inductor L4 is connected to one end of filter capacitor C11 and the positive output terminal Vc2+. The other end of filter capacitor C11 is connected to terminal 8 of the secondary winding Ns2 of the high-frequency switching transformer T1 and the negative output terminal Vc2-.

[0044] Terminal 10 of the secondary winding Ns3 of the high-frequency switching transformer T1 is connected to the anode of rectifier diode D9. The cathode of rectifier diode D9 is connected to the cathode of rectifier diode D10 and one end of filter inductor L5. The anode of rectifier diode D10 is connected to terminal 12 of the secondary winding Ns3 of the high-frequency switching transformer T1. The other end of filter inductor L5 is connected to one end of filter capacitor C12 and the positive output terminal Vc3+. The other end of filter capacitor C12 is connected to terminal 11 of the secondary winding Ns3 of the high-frequency switching transformer T1 and the negative output terminal Vc3-.

[0045] In the multi-channel isolated output timing control circuit, the high-side input Va is connected to one end of the voltage divider and current-limiting resistor R9, one end of the current-limiting resistor R12, and one end of the current-limiting resistor R13. The other end of the voltage divider and current-limiting resistor R9 is connected to one end of the voltage divider and current-limiting resistor R10. The other end of the voltage divider and current-limiting resistor R10 is connected to the Ref terminal of the high-precision voltage reference source V1, one end of the voltage divider and current-limiting resistor R11, one end of the energy storage delay capacitor C13, and one end of the energy storage delay capacitor C14. The other end of the voltage divider and current-limiting resistor R11 is connected to the energy storage delay capacitor C14. The other end of capacitor C13, the other end of energy storage delay capacitor C14, the anode A terminal of high-precision voltage reference source V1, and signal ground are connected. The other end of current limiting resistor R12 is connected to the other end of current limiting resistor R13, the cathode of Zener diode D11, and the cathode C terminal of high-precision voltage reference source V1. The anode of Zener diode D11 is connected to the input terminal 1+ and input terminal 2+ of optocoupler B1. The input terminal 1- of optocoupler B1 is connected to the input terminal 2- of optocoupler B1 and signal ground. The output terminal 1C of optocoupler B1 is connected to one end of voltage divider and current limiting resistor R14, one end of voltage divider and current limiting resistor R15, one end of filter capacitor C15, and the high-side output Vd1. The other end of voltage divider and current limiting resistor R14 is connected to the positive input terminal Vc2+. The output terminal 1E of optocoupler B1 is connected to the other end of voltage divider and current limiting resistor R15, the other end of filter capacitor C15, and the negative input terminal Vc2-. The output terminal 2C of optocoupler B1 is connected to one end of voltage divider and current limiting resistor R16, one end of voltage divider and current limiting resistor R17, one end of filter capacitor C16, and the high-side output Vd2. The other end of voltage divider and current limiting resistor R16 is connected to the positive input terminal Vc3+. The output terminal 2E of optocoupler B1 is connected to the other end of voltage divider and current limiting resistor R17, the other end of filter capacitor C16, and the negative input terminal Vc3-.

[0046] In the two-stage voltage regulator and filter output circuit, the positive input terminal Vc1+ is connected to the IN terminal and the EN terminal of the low-dropout regulator U4, respectively. The OUT terminal of the low-dropout regulator U4 is connected to one end of the voltage divider sampling resistor R18, one end of the output filter capacitor C17, and the high-side output Vout1, respectively. The other end of the voltage divider sampling resistor R18 is connected to the ADJ terminal and one end of the voltage divider sampling resistor R19 of the low-dropout regulator U4, respectively. The GND terminal of the low-dropout regulator U4... The input negative terminal Vc1-, the other end of the voltage divider sampling resistor R19, and the other end of the output filter capacitor C17 are connected respectively. The input positive terminal Vc2+ is connected to the IN terminal of the low-dropout regulator U5. The input high-side terminal Vd1 is connected to the EN terminal of the low-dropout regulator U5. The OUT terminal of the low-dropout regulator U5 is connected to one end of the voltage divider sampling resistor R20, one end of the output filter capacitor C18, one end of the load resistor RL1, and the output high-side terminal Vout2. The voltage divider sampling resistor R20... The other end is connected to the ADJ terminal of the low-dropout regulator U5 and one end of the voltage divider sampling resistor R21, respectively. The GND terminal of the low-dropout regulator U5 is connected to the negative input terminal Vc2-, the other end of the voltage divider sampling resistor R21, the other end of the output filter capacitor C18, and the other end of the load resistor RL1, respectively. The positive input terminal Vc3+ is connected to the IN terminal of the low-dropout regulator U6, the high-side input Vd2 is connected to the EN terminal of the low-dropout regulator U6, and the OUT terminal of the low-dropout regulator U6 is connected to the OUT terminal. The other end of the voltage divider sampling resistor R22 is connected to one end of the voltage divider sampling resistor R22, one end of the output filter capacitor C19, one end of the load resistor RL2, and the high-side output Vout3, respectively. The other end of the voltage divider sampling resistor R22 is connected to the ADJ terminal of the low-dropout regulator U6 and one end of the voltage divider sampling resistor R23, respectively. The GND terminal of the low-dropout regulator U6 is connected to the negative input terminal Vc3-, the other end of the voltage divider sampling resistor R23, the other end of the output filter capacitor C19, and the other end of the load resistor RL2, respectively.

[0047] In a multi-output timing control method for an onboard secondary power supply, the input Vin first enters the input reverse connection protection and EMI filtering circuit. Transient voltage suppression diodes D1 and D2 suppress both forward and reverse input transient interference voltages. When the input Vin is connected in reverse, the transient voltage suppression diode D2 is reverse-biased and cut off, and the N-channel MOSFET S1 is cut off. When the input Vin is connected in forward, the ideal diode controller U1 drives the N-channel MOSFET S1 to conduct, realizing the input reverse connection protection function. The input Vin then enters the EMI filtering circuit for common-mode and differential-mode signal filtering. The common-mode inductor L1, differential-mode capacitor C2, and differential-mode capacitor C3 form the first-stage common-mode and differential-mode signal filtering circuit, while the differential-mode inductor L2, common-mode capacitor C4, and common-mode capacitor C5 form the second-stage common-mode and differential-mode signal filtering circuit. The EMI filtering circuit filters out external electromagnetic interference introduced from the input line and suppresses electromagnetic interference emitted by high-frequency signal circuits to the outside, so as not to affect the normal operation of other electronic equipment in the same electromagnetic environment. The input Vin is processed by the input reverse connection protection and EMI filter circuit, and the output Va is sent to the power-down retention and pre-regulation circuit and the multi-channel isolated output timing control circuit, respectively.

[0048] In the power-down retention and pre-regulation circuit, the input voltage Va first charges the energy storage capacitors C6 and C7 through the current-limiting resistors R2 and R3 in the power-down retention circuit. Due to the reverse connection protection circuit at the front end, the energy storage capacitors C6 and C7 can supply power to the downstream circuit through the rectifier diode D4 when the input Va is powered down, thus achieving the power-down retention function. Simultaneously, the input voltage Va enters the pre-regulation circuit. The synchronous switching buck-boost controller U2 controls the conduction or cutoff of N-channel MOSFETs S2, S3, S4, and S5 to achieve synchronous switching buck-boost conversion, realizing a wide-range input pre-regulation function. The synchronous switching buck-boost controller U2 implements undervoltage protection through voltage divider resistors R4 and R5, and achieves closed-loop feedback of current and voltage through current sampling resistor R6, voltage dividing sampling resistors R7 and R8, enabling rapid and accurate switching regulation of the output Vb.

[0049] In the DC push-pull isolation converter rectifier circuit, the pulse width modulation push-pull controller U3 controls the alternating conduction or cutoff of N-channel MOSFETs S6 and S7 through PWM1 and PWM2 signals respectively. The input voltage Vb is isolated and converted by the high-frequency switching transformer T1, and then rectified and filtered to output multiple isolated secondary voltages. The windings of the high-frequency switching transformer T1 include one primary winding Np1 and three secondary windings Ns1, Ns2 and Ns3. Terminals 1 and 2 of the primary winding Np1, terminal 4 and terminal 5 of the secondary winding Ns1, terminal 7 and terminal 8 of the secondary winding Ns2, terminal 10 and terminal 11 of the secondary winding Ns3 are terminals with the same name. The secondary winding Ns1 of the high-frequency switching transformer T1 is rectified by rectifier diodes D5 and D6, then filtered by filter inductor L3 and filter capacitor C10 to output Vc1. The secondary winding Ns2 of the high-frequency switching transformer T1 is rectified by rectifier diodes D7 and D8, then filtered by filter inductor L4 and filter capacitor C11 to output Vc2. The secondary winding Ns3 of the high-frequency switching transformer T1 is rectified by rectifier diodes D9 and D10, then filtered by filter inductor L5 and filter capacitor C12 to output Vc3. The secondary output voltages Vc1, Vc2, and Vc3 are isolated from each other. Output voltage Vc1 is fed into the two-stage voltage regulator and filter output circuit, while output voltages Vc2 and Vc3 are simultaneously fed into the multi-channel isolated output timing control circuit and the two-stage voltage regulator and filter output circuit, respectively.

[0050] In the multi-channel isolated output timing control circuit, the reference terminal Ref of the high-precision voltage reference source V1 samples the input voltage Va through voltage divider and current limiting resistors R9, R10, and R11, and then...

[0051] Energy storage delay capacitors C13 and C14 are charged with a delay. When the reference terminal Ref voltage of the high-precision voltage reference source V1 is less than the set value, the output cathode C terminal of the high-precision voltage reference source V1 is at a high level. At this time, the input terminal of optocoupler B1 is turned on, and the outputs Vd1 and Vd2 are pulled to a low level through the saturation conduction of the output terminal of the optocoupler. When the reference terminal Ref voltage of the high-precision voltage reference source V1 reaches the set value, the output cathode C terminal of the high-precision voltage reference source V1 outputs a low level. At this time, the input terminal of optocoupler B1 is turned off, and the outputs Vd1 are pulled to a high level through the voltage divider and current limiting resistors R14 and R15, and the outputs Vd2 are pulled to a high level through the voltage divider and current limiting resistors R16 and R17.

[0052] In the two-stage voltage regulator and filter output circuit, the input voltage Vc1 is regulated and filtered by the low-dropout regulator U4, resulting in output Vout1; the input voltage Vc2 is regulated and filtered by the low-dropout regulator U5, resulting in output Vout2; and the input voltage Vc3 is regulated and filtered by the low-dropout regulator U6, resulting in output Vout3. The EN terminal of the low-dropout regulator U4 is directly pulled up to the IN terminal, meaning that output Vout1 is active when input voltage Vc1 is active. The EN terminal of the low-dropout regulator U5 is controlled by the input voltage Vd1; output Vout2 is active only when both input voltages Vc2 and Vd1 are active. Similarly, the EN terminal of the low-dropout regulator U6 is controlled by the input voltage Vd2; output Vout3 is active only when both input voltages Vc3 and Vd2 are active.

[0053] When the secondary power supply of the missile-borne computer is powered on, the input voltage Vin is output as voltage Va after passing through the input reverse connection protection and EMI filter circuit. When the input voltage Va rises from zero voltage to a value greater than the undervoltage protection voltage setting (e.g., 12V) of the power-down retention and pre-regulation circuit, the output voltage Vb of the power-down retention and pre-regulation circuit becomes effective. The output voltage Vb enters the DC push-pull isolation converter and rectifier circuit, and after push-pull isolation converter and rectifier, it outputs three isolated secondary voltages Vc1, Vc2 and Vc3. The output voltage Vc1 is regulated and adjusted by the low-dropout regulator U4 in the two-stage voltage regulation and filtering output circuit, resulting in output Vout1. Upon power-up of output Vout1, the voltage at the Ref terminal of the high-precision voltage reference source V1 in the multi-channel isolated output timing control circuit is less than the set value (e.g., 2.5V). The output cathode C terminal of the high-precision voltage reference source V1 is at a high level, the input terminal of optocoupler B1 is turned on, and outputs Vd1 and Vd2 are at a low level. The outputs of the low-dropout regulators U5 and U6 in the two-stage voltage regulation and filtering output circuit are disabled. As the input voltage Va continues to rise, when the voltage at the Ref terminal of the high-precision voltage reference source V1 in the multi-channel isolated output timing control circuit... When the voltage at terminal ef reaches the set value (e.g., 2.5V) after RC delay charging, the output cathode C of the high-precision voltage reference source V1 outputs a low level (less than 2V), the Zener diode D11 (e.g., 3.5V) is cut off, the input of optocoupler B1 is cut off, and the output Vd1 is high. The low-dropout regulator U5 of the secondary voltage regulator and filter output circuit outputs Vout2, which is active. Similarly, when output Vd2 is high, the low-dropout regulator U6 of the secondary voltage regulator and filter output circuit outputs Vout3, which is active. At this time, the power-on of outputs Vout2 and Vout3 is completed, thus realizing the function of output Vout1 leading the power-on of outputs Vout2 and Vout3. As the input voltage Va continues to rise to the rated voltage (e.g., 28V), the voltage on energy storage capacitors C6 and C7 is also charged from Va to the rated voltage through current-limiting resistors R2 and R3.

[0054] When the secondary power supply of the missile-borne computer is powered down, the input voltage Va begins to drop from the rated voltage (e.g., 28V). Due to the reverse connection protection circuit at the front end, the energy of the energy storage capacitors C6 and C7 is discharged from the rated voltage (28V) to the back-end circuit through the rectifier diode D4 branch to ensure its normal operation for a certain period of time (tens of ms). As the input voltage Va continues to drop, when the voltage at the Ref terminal of the high-precision voltage reference source V1 in the multi-channel isolated output timing control circuit is less than its set value (e.g., 2.5V), the output cathode C terminal of the high-precision voltage reference source V1 outputs a high level, the input terminal of the optocoupler B1 is turned on, and the outputs Vd1 and Vd2 are at a low level. The outputs of the low-dropout regulators U5 and U6 in the secondary voltage regulation and filtering output circuit are disabled. At this time, the power-down of outputs Vout2 and Vout3 is completed. When the load of outputs Vout2 and Vout3 is a capacitive light load, adding load resistors RL1 and RL2 can accelerate their power-down. At this time, since the output Vb of the power-down retention and wide-range pre-regulation circuit is normal, the output Vc1 of the DC push-pull isolation converter rectifier circuit is also normal. Therefore, the output Vout1 is still effective. When the voltage of the energy storage capacitors C6 and C7 discharges to a value lower than the undervoltage protection voltage setting of the power-down retention and pre-regulation circuit (e.g., 12V), the output voltage Vb of the power-down retention and wide-range pre-regulation circuit is disabled. Consequently, the output Vc1 of the DC push-pull isolation converter rectifier circuit is disabled, and the output of the low-dropout regulator U4 in the secondary voltage regulation and filter output circuit is disabled. At this time, the power-down of output Vout1 is completed, thus realizing the function of output Vout1 lagging behind the power-down of outputs Vout2 and Vout3.

[0055] This invention employs a multi-channel isolated output timing control circuit and a two-stage voltage-regulating and filtering output circuit to realize the power-on timing control function of the multi-channel isolated output of the missile-borne secondary power supply. Furthermore, it realizes the power-off timing control function of the multi-channel isolated output through a power-down retention and pre-regulation circuit. It features minimal impact from load characteristics, high control accuracy and stability, flexible timing adjustment, controllable power-off timing, and the ability to simultaneously achieve advanced power-on and delayed power-off of a certain output.

[0056] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A timing control circuit for a multi-output missile-borne secondary power supply, characterized in that, The timing control circuit includes an input reverse connection protection and EMI filter circuit, a power-down retention and pre-regulation circuit, a DC push-pull isolation converter and rectifier circuit, a multi-channel isolated output timing control circuit, and a two-stage voltage regulator and filter output circuit. The two-stage voltage regulator and filter output circuit includes two-stage voltage regulator and filter output circuit a, two-stage voltage regulator and filter output circuit b, and two-stage voltage regulator and filter output circuit c. The output terminal of the input reverse connection protection and EMI filter circuit is connected to the input terminal of the power-down retention and pre-regulation circuit and the input terminal of the multi-channel isolated output timing control circuit. The output terminal of the power-down retention and pre-regulation circuit is connected to the input terminal of the DC push-pull isolation converter and rectifier circuit. The output terminal of the DC push-pull isolation converter and rectifier circuit is connected to the input terminal of the multi-channel isolated output timing control circuit and the input terminals of two-stage voltage regulator and filter output circuits a, b, and c. The output terminal of the multi-channel isolated output timing control circuit is connected to the input terminals of two-stage voltage regulator and filter output circuits b and c. in, The multi-channel isolated output timing control circuit includes: a high-precision voltage reference source V1, an optocoupler B1, voltage divider and current limiting resistors R9, R10, and R11, energy storage delay capacitors C13 and C14, current limiting resistors R12 and R13, a Zener diode D11, voltage divider and current limiting resistors R14, R15, R16, and R17, and filter capacitors C15 and C16. In the multi-channel isolated output timing control circuit, the output terminal Va of the input reverse connection protection and EMI filter circuit is connected to one end of the voltage divider and current limiting resistor R9, one end of the current limiting resistor R12, and one end of the current limiting resistor R13, respectively. The other end of the voltage divider and current limiting resistor R9 is connected to one end of the voltage divider and current limiting resistor R10. The other end of the voltage divider and current limiting resistor R10 is connected to the Ref terminal of the high-precision voltage reference source V1, one end of the voltage divider and current limiting resistor R11, one end of the energy storage delay capacitor C13, and one end of the energy storage delay capacitor. One end of C14 is connected to the voltage divider and current limiting resistor R11, which is connected to the other end of the energy storage delay capacitor C13, the other end of the energy storage delay capacitor C14, the anode A of the high-precision voltage reference source V1, and signal ground, respectively. The other end of the current limiting resistor R12 is connected to the other end of the current limiting resistor R13, the cathode of the Zener diode D11, and the cathode C of the high-precision voltage reference source V1, respectively. The anode of the Zener diode D11 is connected to the input terminal 1+ of the optocoupler B1 and the input terminal 1+ of the optocoupler B1. The input terminal 2+ of optocoupler B1 is connected to the input terminal 2+ of optocoupler B1, and the input terminal 1- of optocoupler B1 is connected to the signal ground. The output terminal 1C of optocoupler B1 is connected to one end of voltage divider and current limiting resistor R14, one end of voltage divider and current limiting resistor R15, one end of filter capacitor C15, and the high-side output Vd1. The other end of voltage divider and current limiting resistor R14 is connected to the positive input terminal Vc2+. The output terminal 1E of optocoupler B1 is connected to the other end of voltage divider and current limiting resistor R15, and the signal ground. The other end of the filter capacitor C15 is connected to the negative input terminal Vc2-. The output terminal 2C of the optocoupler B1 is connected to one end of the voltage divider and current limiting resistor R16, one end of the voltage divider and current limiting resistor R17, one end of the filter capacitor C16, and the high-side output terminal Vd2. The other end of the voltage divider and current limiting resistor R16 is connected to the positive input terminal Vc3+. The output terminal 2E of the optocoupler B1 is connected to the other end of the voltage divider and current limiting resistor R17, the other end of the filter capacitor C16, and the negative input terminal Vc3-. Specifically, the output terminal Va of the input reverse connection protection and EMI filter circuit is the output terminal of the input reverse connection protection and EMI filter circuit; the positive input terminal Vc2+ and the negative input terminal Vc2- are the connection terminals of the DC push-pull isolation converter rectifier circuit and the secondary voltage regulator and filter output circuit b; the positive input terminal Vc3+ and the negative input terminal Vc3- are the connection terminals of the DC push-pull isolation converter rectifier circuit and the secondary voltage regulator and filter output circuit c; the high-end output Vd1 is the connection terminal of the multi-channel isolated output timing control circuit and the secondary voltage regulator and filter output circuit b; and the high-end output Vd2 is the connection terminal of the multi-channel isolated output timing control circuit and the secondary voltage regulator and filter output circuit c.

2. The missile-borne secondary power supply multi-output timing control circuit as described in claim 1, characterized in that, The input reverse connection protection and EMI filtering circuit includes: transient voltage suppression diode D1, transient voltage suppression diode D2, ideal diode controller U1, Zener diode D3, N-channel MOSFET S1, current limiting resistor R1, filter capacitor C1, common mode inductor L1, differential mode capacitor C2, differential mode capacitor C3, differential mode inductor L2, common mode capacitor C4, and common mode capacitor C5.

3. The multi-output timing control circuit for the missile-borne secondary power supply as described in claim 2, characterized in that, In the input reverse connection protection and EMI filtering circuit, the cathode of transient voltage suppressor diode D1 is connected to the high-side input Vin+. The IN terminal of ideal diode controller U1 is connected to the high-side input Vin+, the SOURCE terminal of ideal diode controller U1, the source of N-channel MOSFET S1, and the anode of Zener diode D3. The gate of N-channel MOSFET S1 is connected to the cathode of Zener diode D3 and the GATE terminal of ideal diode controller U1. The drain of N-channel MOSFET S1 is connected to the OUT terminal of ideal diode controller U1, one end of filter capacitor C1, one end of differential-mode capacitor C2, and the positive input terminal of common-mode inductor L1. The anode of transient voltage suppressor diode D1 is connected to the anode of transient voltage suppressor diode D2. The cathode of transient voltage suppression diode D2 is connected to the VSS terminal of ideal diode controller U1, one end of current limiting resistor R1, and the other end of filter capacitor C1, respectively. The negative input terminal of common mode inductor L1 is connected to the other end of differential mode capacitor C2, the other end of current limiting resistor R1, and input ground Vin-, respectively. The positive output terminal of common mode inductor L1 is connected to one end of differential mode inductor L2 and one end of differential mode capacitor C3, respectively. The other end of differential mode inductor L2 is connected to one end of common mode capacitor C4 and the output terminal Va of input reverse connection protection and EMI filter circuit, respectively. The other end of common mode capacitor C4 is connected to one end of common mode capacitor C5 and chassis ground, respectively. The other end of common mode capacitor C5 is connected to the negative output terminal of common mode inductor L1, the other end of differential mode capacitor C3, and signal ground, respectively.

4. The missile-borne secondary power supply multi-output timing control circuit as described in claim 1, characterized in that, The power-down retention and pre-regulation circuit includes: current-limiting resistor R2, current-limiting resistor R3, energy storage capacitor C6, energy storage capacitor C7, rectifier diode D4, synchronous switching buck-boost controller U2, N-channel MOSFET S2, N-channel MOSFET S3, N-channel MOSFET S4, N-channel MOSFET S5, energy storage inductor L2, voltage divider resistor R4, voltage divider resistor R5, filter capacitor C8, current sampling resistor R6, voltage divider sampling resistor R7, voltage divider sampling resistor R8, and filter capacitor C9.

5. The multi-output timing control circuit for the missile-borne secondary power supply as described in claim 4, characterized in that, In the power-down retention and pre-regulation circuit, the output terminal Va of the input reverse connection protection and EMI filter circuit is connected to one end of current-limiting resistor R2, one end of current-limiting resistor R3, the cathode of rectifier diode D4, one end of voltage divider resistor R4, one end of filter capacitor C8, and the drain of N-channel MOSFET S2, respectively. The other end of current-limiting resistor R2 is connected to the other end of current-limiting resistor R3, the anode of rectifier diode D4, the positive terminal of energy storage capacitor C6, and the positive terminal of energy storage capacitor C7, respectively. The other end of voltage divider resistor R4 is connected to the synchronous switch buck-boost controller, respectively. The RUN terminal of U2 is connected to one end of the voltage divider resistor R5. The other end of the voltage divider resistor R5 is connected to the negative terminals of the energy storage capacitors C6 and C7, the other end of the filter capacitor C8, and signal ground. The source of the N-channel MOSFET S2 is connected to one end of the energy storage inductor L2 and the drain of the N-channel MOSFET S4. The other end of the energy storage inductor L2 is connected to the source of the N-channel MOSFET S3 and the drain of the N-channel MOSFET S5. The source of the N-channel MOSFET S4 is connected to the source of the N-channel MOSFET S5 and the current sampling terminal. One end of the current sampling resistor R6 is connected to the ISENSE+ terminal of the synchronous switch buck-boost controller U2. The other end of the current sampling resistor R6 is connected to the ISENSE- terminal, the GND terminal, and the signal ground of the synchronous switch buck-boost controller U2, respectively. The gate of the N-channel MOSFET S2 is connected to the TG1 terminal of the synchronous switch buck-boost controller U2. The gate of the N-channel MOSFET S4 is connected to the BG1 terminal of the synchronous switch buck-boost controller U2. The gate of the N-channel MOSFET S3 is connected to the synchronous switch buck-boost controller U2. The TG2 terminal of the circuit U2 is connected, the gate of the N-channel MOSFET S5 is connected to the BG2 terminal of the synchronous switch buck-boost controller U2, the drain of the N-channel MOSFET S3 is connected to one end of the voltage divider sampling resistor R7, one end of the filter capacitor C9, and the output terminal Vb of the power-down retention and pre-regulation circuit, respectively. The other end of the voltage divider sampling resistor R7 is connected to the VSENSE terminal of the synchronous switch buck-boost controller U2 and one end of the voltage divider sampling resistor R8, respectively. The other end of the voltage divider sampling resistor R8 is connected to the other end of the filter capacitor C9 and the signal ground, respectively.

6. The multi-output timing control circuit for the missile-borne secondary power supply as described in claim 1, characterized in that, The DC push-pull isolated converter rectifier circuit includes: pulse width modulation push-pull controller U3, N-channel MOSFET S6, N-channel MOSFET S7, high-frequency switching transformer T1, rectifier diodes D5, D6, D7, D8, D9, and D10, filter inductors L3, L4, and L5, and filter capacitors C10, C11, and C12.

7. The missile-borne secondary power supply multi-output timing control circuit as described in claim 1, characterized in that, In the DC push-pull isolated converter rectifier circuit, the output terminal Vb of the power-down retention and pre-regulation circuit is connected to the VCC terminal of the pulse width modulation push-pull controller U3 and terminal 2 of the primary winding Np1 of the high-frequency switching transformer T1, respectively. Terminal 1 of the primary winding Np1 of the high-frequency switching transformer T1 is connected to the drain of the N-channel MOSFET S6, and terminal 3 of the primary winding Np1 of the high-frequency switching transformer T1 is connected to the drain of the N-channel MOSFET S7. The source of the N-channel MOSFET S6 is connected to the source of the N-channel MOSFET S7, the GND terminal of the pulse width modulation push-pull controller U3, and the signal ground, respectively. The gate of the N-channel MOSFET S7 is connected to the PWM1 terminal of the pulse width modulation push-pull controller U3. The gate of the N-channel MOSFET S7 is connected to the PWM2 terminal of the pulse width modulation push-pull controller U3. Terminal 4 of the secondary winding Ns1 of the high-frequency switching transformer T1 is connected to the anode of the rectifier diode D5. The cathode of the rectifier diode D5 is connected to the cathode of the rectifier diode D6 and one end of the filter inductor L3. The anode of the rectifier diode D6 is connected to terminal 6 of the secondary winding Ns1 of the high-frequency switching transformer T1. The other end of the filter inductor L3 is connected to one end of the filter capacitor C10 and the positive output terminal Vc1+. The other end of the filter capacitor C10... The terminals are respectively connected to terminal 5 of the secondary winding Ns1 of the high-frequency switching transformer T1 and the negative output terminal Vc1-. Terminal 7 of the secondary winding Ns2 of the high-frequency switching transformer T1 is connected to the anode of rectifier diode D7. The cathode of rectifier diode D7 is connected to the cathode of rectifier diode D8 and one end of filter inductor L4. The anode of rectifier diode D8 is connected to terminal 9 of the secondary winding Ns2 of the high-frequency switching transformer T1. The other end of filter inductor L4 is connected to one end of filter capacitor C11 and the positive output terminal Vc2+. The other end of filter capacitor C11 is connected to the secondary winding Ns1 of the high-frequency switching transformer T1. Terminal 8 of rectifier D1 is connected to the negative output terminal Vc2-. Terminal 10 of the secondary winding Ns3 of high-frequency switching transformer T1 is connected to the anode of rectifier diode D9. The cathode of rectifier diode D9 is connected to the cathode of rectifier diode D10 and one end of filter inductor L5. The anode of rectifier diode D10 is connected to terminal 12 of the secondary winding Ns3 of high-frequency switching transformer T1. The other end of filter inductor L5 is connected to one end of filter capacitor C12 and the positive output terminal Vc3+. The other end of filter capacitor C12 is connected to terminal 11 of the secondary winding Ns3 of high-frequency switching transformer T1 and the negative output terminal Vc3-.

8. The missile-borne secondary power supply multi-output timing control circuit as described in claim 1, characterized in that, The two-stage voltage regulator and filter output circuit includes: low-dropout regulator U4, low-dropout regulator U5, low-dropout regulator U6, voltage divider sampling resistors R18, R19, R20, R21, R22, and R23, output filter capacitors C17, C18, and C19, load resistors RL1 and RL2. In the two-stage voltage regulator and filter output circuit, the positive input terminal Vc1+ is connected to the IN terminal and the EN terminal of the low-dropout regulator U4, respectively. The OUT terminal of the low-dropout regulator U4 is connected to one end of the voltage divider sampling resistor R18, one end of the output filter capacitor C17, and the high-side output Vout1. The other end of the voltage divider sampling resistor R18 is connected to the ADJ terminal of the low-dropout regulator U4 and one end of the voltage divider sampling resistor R19. The GND terminal of the low-dropout regulator U4 is connected to the negative input terminal Vc1-, the other end of the voltage divider sampling resistor R19, and the other end of the output filter capacitor C17. The positive input terminal Vc2+ is connected to the IN terminal of the low-dropout regulator U5. The high-side input Vd1 is connected to the EN terminal of the low-dropout regulator U5. The OUT terminal of the differential voltage regulator U5 is connected to one end of the voltage divider sampling resistor R20, one end of the output filter capacitor C18, one end of the load resistor RL1, and the high-side output Vout2. The other end of the voltage divider sampling resistor R20 is connected to the ADJ terminal of the low-dropout regulator U5 and one end of the voltage divider sampling resistor R21. The GND terminal of the low-dropout regulator U5 is connected to the negative input terminal Vc2-, the other end of the voltage divider sampling resistor R21, the other end of the output filter capacitor C18, and the other end of the load resistor RL1. The positive input terminal Vc3+ is connected to the IN terminal of the low-dropout regulator U6. The high-side input Vd2 is connected to the EN terminal of the low-dropout regulator U6. The OUT terminal of the low-dropout regulator U6 is connected to one end of the voltage divider sampling resistor R22, one end of the output filter capacitor C19, one end of the load resistor RL2, and the high-side output Vout3. The other end of the voltage divider sampling resistor R22 is connected to the ADJ terminal of the low-dropout regulator U6 and one end of the voltage divider sampling resistor R23. The GND terminal of the low-dropout regulator U6 is connected to the negative input terminal Vc3-, the other end of the voltage divider sampling resistor R23, the other end of the output filter capacitor C19, and the other end of the load resistor RL2.

Citation Information

Patent Citations

Buck-boost DC-DC power supply for double-channel redundant parallel synchronization switch
CN107769550A
Power supply with turn-on and turn-off sequential control
CN112953200A

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Description

Patent Citations

Buck-boost DC-DC power supply for double-channel redundant parallel synchronization switch

Power supply with turn-on and turn-off sequential control