A high voltage integrated circuit

Abstract

The application discloses a high-voltage integrated circuit, comprising a Schmitt circuit, a filter, a level conversion circuit, a double-pulse generator, a single DMOS drive circuit and an output circuit; an input end of the Schmitt circuit is electrically connected with an input signal, an output end of the Schmitt circuit is electrically connected with an input end of the filter, an output end of the filter is electrically connected with an input end of the level conversion circuit, an output end of the level conversion circuit is electrically connected with an input end of the double-pulse generator, an output end of the double-pulse generator is electrically connected with an input end of the single DMOS drive circuit, and an output end of the single DMOS drive circuit is electrically connected with the output circuit; the single DMOS drive circuit is used for merging and frequency dividing two pulse signals from the double-pulse generator; the application aims to provide a high-voltage integrated circuit, which reduces mutual interference between DMOS tubes in the circuit by adopting the single DMOS drive circuit, and simultaneously reduces design space.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and more particularly to a high-voltage integrated circuit. Background Technology

[0002] High-voltage integrated circuits, or HVICs, are integrated circuit products that convert MCU signals into signals to drive IGBTs. HVICs integrate PMOS transistors, NMOS transistors, bipolar transistors, diodes, Zener diodes, resistors, and capacitors to form a combined circuit. On one hand, HVICs receive control signals from the MCU to drive subsequent IGBTs or MOS transistors; on the other hand, they send system status detection signals back to the MCU, making them a key chip within the IPM (Integrated Circuit Manager).

[0003] Currently, the mainstream high-voltage driver HVIC uses two DMOS transistors for the conversion of low and high voltage drive signals in each high-side drive. The drive circuit composed of two DMOS transistors is prone to mutual interference during operation. At the same time, multiple DMOS transistors increase the area occupied by the module design, which is not conducive to the miniaturization of the module. Summary of the Invention

[0004] The purpose of this invention is to propose a high-voltage integrated circuit that reduces mutual interference between DMOS transistors in the circuit by using a single DMOS driving circuit, while also reducing design space.

[0005] To achieve this objective, the present invention adopts the following technical solution: a high-voltage integrated circuit, comprising a Schmitt trigger circuit, a filter, a level conversion circuit, a dual-pulse generator, a single DMOS drive circuit, and an output circuit; the input terminal of the Schmitt trigger circuit is electrically connected to the input signal, the output terminal of the Schmitt trigger circuit is electrically connected to the input terminal of the filter, the output terminal of the filter is electrically connected to the input terminal of the level conversion circuit, the output terminal of the level conversion circuit is electrically connected to the input terminal of the dual-pulse generator, the output terminal of the dual-pulse generator is electrically connected to the input terminal of the single DMOS drive circuit, and the output terminal of the single DMOS drive circuit is electrically connected to the output circuit; the single DMOS drive circuit is used to combine and divide the two pulse signals from the dual-pulse generator.

[0006] Preferably, the single DMOS driving circuit includes an OR gate, a first DMOS transistor Q1, a NOT gate, a frequency divider circuit, and a resistor R1; the input terminal of the OR gate is electrically connected to the output terminal of the dual pulse generator, the output terminal of the OR gate is electrically connected to the gate of the first DMOS transistor Q1, the source of the first DMOS transistor Q1 is grounded, the drain of the first DMOS transistor Q1 is electrically connected to the input terminal of the NOT gate and one end of the resistor R1, the other end of the resistor R1 is electrically connected to the output circuit, the output terminal of the NOT gate is electrically connected to the input terminal of the frequency divider circuit, and the output terminal of the frequency divider circuit is electrically connected to the input terminal of the output circuit.

[0007] Preferably, it further includes an electrostatic discharge circuit, one end of which is electrically connected to the input terminal of the NOT gate, and the other end of which is grounded.

[0008] Preferably, the electrostatic discharge circuit includes a Zener diode D1, the negative terminal of which is electrically connected to the input terminal of the NOT gate, and the positive terminal of which is grounded.

[0009] Preferably, the electrostatic discharge circuit includes a MOS transistor Q4, the drain of the MOS transistor Q4 is electrically connected to the input terminal of the NOT gate, and the source and gate of the MOS transistor Q4 are grounded.

[0010] Preferably, the output circuit includes MOSFETs Q2 and Q3, resistors R2 and R3; the gates of MOSFETs Q2 and Q3 are both electrically connected to the output terminal of the frequency divider circuit; the drain of MOSFET Q2 is electrically connected to the other end of resistor R1 and serves as the module output terminal VB; the source of MOSFET Q2 is electrically connected to one end of resistor R2, and the other end of resistor R2 is electrically connected to one end of resistor R3 and serves as the module output terminal HO; the drain of MOSFET Q3 is electrically connected to the other end of resistor R3, and the source of MOSFET Q3 serves as the output terminal VS.

[0011] One beneficial effect of the technical solution of this invention is that the single DMOS drive circuit uses a single DMOS transistor to complete the conversion of the drive signal, replacing the original two DMOS transistors for high- and low-voltage drive signal conversion. This eliminates the mutual interference between the two DMOS transistors. Using a single DMOS transistor reduces the circuit design area of ​​the high- and low-voltage transition region and reduces interference problems caused by the high-voltage DMOS transistor operating at high frequencies. Compared to existing two-DMOS transistor circuits, a single DMOS transistor reduces the electrostatic discharge capability in the high-voltage region when subjected to high-voltage pulses, resulting in higher reliability. Attached Figure Description

[0012] Figure 1This is a circuit connection diagram of one embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of the electrostatic discharge circuit in Embodiment 1 of the present invention;

[0014] Figure 3 This is a schematic diagram of the electrostatic discharge circuit in Embodiment 2 of the present invention.

[0015] The circuit consists of: 1. Schmitt trigger circuit; 2. Filter; 3. Level conversion circuit; 4. Dual pulse generator; 5. Single DMOS drive circuit; 5. OR gate; 51. NOT gate; 52. Frequency divider circuit; 53. Electrostatic discharge circuit; 54. Output circuit. Detailed Implementation

[0016] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] Example 1

[0021] See Figure 1 and Figure 2As shown, a high-voltage integrated circuit includes a Schmitt trigger circuit 1, a filter 2, a level conversion circuit 3, a dual-pulse generator 4, a single DMOS driver circuit 5, and an output circuit 6. The input terminal of the Schmitt trigger circuit 1 is electrically connected to the input signal, the output terminal of the Schmitt trigger circuit 1 is electrically connected to the input terminal of the filter 2, the output terminal of the filter 2 is electrically connected to the input terminal of the level conversion circuit 3, the output terminal of the level conversion circuit 3 is electrically connected to the input terminal of the dual-pulse generator 4, the output terminal of the dual-pulse generator 4 is electrically connected to the input terminal of the single DMOS driver circuit 5, and the output terminal of the single DMOS driver circuit 5 is electrically connected to the output circuit 6. The single DMOS driver circuit 5 is used to combine and divide the two pulse signals from the dual-pulse generator 4.

[0022] The single-DMOS driver circuit 5 uses a single DMOS transistor to complete the drive signal conversion, replacing the original two DMOS transistors for high- and low-voltage drive signal conversion. This eliminates the mutual interference between the two DMOS transistors. Using a single DMOS transistor reduces the circuit design area in the high- and low-voltage transition region and reduces interference problems caused by the high-voltage DMOS transistor operating at high frequencies. Compared to the existing two-DMOS transistor circuit, the single DMOS transistor reduces the impact of high-voltage pulses, thus reducing the electrostatic discharge capability in the high-voltage region and resulting in higher reliability.

[0023] Preferably, the single DMOS driving circuit 5 includes an OR gate 51, a first DMOS transistor Q1, an NOT gate 52, a frequency divider circuit 53, and a resistor R1; the input terminal of the OR gate 51 is electrically connected to the output terminal of the dual pulse generator 4, the output terminal of the OR gate 51 is electrically connected to the gate of the first DMOS transistor Q1, the source of the first DMOS transistor Q1 is grounded, the drain of the first DMOS transistor Q1 is electrically connected to the input terminal of the NOT gate 52 and one end of the resistor R1, the other end of the resistor R1 is electrically connected to the output circuit 6, the output terminal of the NOT gate 52 is electrically connected to the input terminal of the frequency divider circuit 53, and the output terminal of the frequency divider circuit 53 is electrically connected to the input terminal of the output circuit 6.

[0024] With this structure, after receiving a high-level signal at the input of the dual-pulse generator 4, the dual-pulse generator 4 detects the rising and falling edges of the signal. The dual-pulse generator 4 outputs two high-pulse signals a1 and b1, which are several nanoseconds high, from its two outputs. When either of the two high-pulse signals a1 and b1 is high, the OR gate 51 outputs a high-level signal G1. The high-level signal G1 output by the OR gate 51 drives the first DMOS transistor Q1 to turn on and off. The input of the NOT gate 52 is used to detect the drain voltage of the first DMOS transistor Q1. The output of the NOT gate 52 outputs a pulse signal with the same pulse width and polarity as the high-level signal G1. The input of the frequency divider circuit 53 detects the pulse signal output by the NOT gate 52. The output of the frequency divider circuit 53 outputs a pulse signal with a frequency that is half the frequency of the pulse signal output by the NOT gate 52, thereby completing the function of transmitting the pulse signal from the low-voltage area to the high-voltage area. Using the above circuit, a single DMOS transistor is used as the driving circuit. The switching frequency is twice that of the traditional dual DMOS transistor driving circuit. The frequency is divided by the frequency divider circuit 53 to obtain the same output signal as the traditional dual DMOS.

[0025] Specifically, it also includes an electrostatic discharge circuit 54, one end of which is electrically connected to the input terminal of the NOT gate 52, and the other end of which is grounded.

[0026] Meanwhile, the electrostatic discharge circuit 54 includes a Zener diode D1, the negative terminal of which is electrically connected to the input terminal of the NOT gate 52, and the positive terminal of which is grounded.

[0027] In this embodiment, a Zener diode D1 is connected in parallel with the first DMOS transistor Q1 as an electrostatic discharge circuit 54, which provides electrostatic discharge protection and has better reliability than the traditional drive circuit.

[0028] Preferably, the output circuit 6 includes MOSFETs Q2 and Q3, resistors R2 and R3; the gates of MOSFETs Q2 and Q3 are both electrically connected to the output terminal of the frequency divider circuit 53, the drain of MOSFET Q2 is electrically connected to the other end of resistor R1, and serves as the module output terminal VB; the source of MOSFET Q2 is electrically connected to one end of resistor R2, the other end of resistor R2 is electrically connected to one end of resistor R3, and serves as the module output terminal HO; the drain of MOSFET Q3 is electrically connected to the other end of resistor R3, and the source of MOSFET Q3 serves as the output terminal VS.

[0029] Example 2

[0030] See Figure 3As shown, the structure of this embodiment is basically the same as that of Embodiment 1, except that: the electrostatic discharge circuit 54 includes a MOS transistor Q4, the drain of the MOS transistor Q4 is electrically connected to the input terminal of the NOT gate 52, and the source and gate of the MOS transistor Q4 are grounded.

[0031] In this embodiment, a MOS transistor Q4 is connected in parallel at the first DMOS transistor Q1 as an electrostatic discharge circuit 54, which plays a role in electrostatic discharge protection and has better reliability than the traditional drive circuit.

[0032] In the description of this specification, references to terms such as "embodiment," "example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0033] The technical principles of the present invention have been described above with reference to specific embodiments. These descriptions are merely for explaining the principles of the invention and should not be construed as limiting the scope of protection of the invention in any way. Based on this explanation, those skilled in the art can readily conceive of other specific embodiments of the invention without inventive effort, and these embodiments will all fall within the scope of protection of the present invention.

Claims

1. A high-voltage integrated circuit, characterized in that, The system includes a Schmitt trigger circuit, a filter, a level shifting circuit, a dual-pulse generator, a single DMOS driver circuit, and an output circuit. The input terminal of the Schmitt trigger circuit is electrically connected to the input signal; the output terminal of the Schmitt trigger circuit is electrically connected to the input terminal of the filter; the output terminal of the filter is electrically connected to the input terminal of the level shifting circuit; the output terminal of the level shifting circuit is electrically connected to the input terminal of the dual-pulse generator; the output terminal of the dual-pulse generator is electrically connected to the input terminal of the single DMOS driver circuit; and the output terminal of the single DMOS driver circuit is electrically connected to the output circuit. The single DMOS driver circuit is used to combine and divide the two pulse signals from the dual-pulse generator. The single DMOS driving circuit includes an OR gate, a first DMOS transistor Q1, a NOT gate, a frequency divider circuit, and a resistor R1. The input of the OR gate is electrically connected to the output of the dual-pulse generator, the output of the OR gate is electrically connected to the gate of the first DMOS transistor Q1, the source of the first DMOS transistor Q1 is grounded, the drain of the first DMOS transistor Q1 is electrically connected to the input of the NOT gate and one end of the resistor R1, the other end of the resistor R1 is electrically connected to the output circuit, the output of the NOT gate is electrically connected to the input of the frequency divider circuit, and the output of the frequency divider circuit is electrically connected to the input of the output circuit.

2. A high-voltage integrated circuit according to claim 1, characterized in that, It also includes an electrostatic discharge circuit, one end of which is electrically connected to the input terminal of the NOT gate, and the other end of which is grounded.

3. A high-voltage integrated circuit according to claim 2, characterized in that, The electrostatic discharge circuit includes a Zener diode D1, the negative terminal of which is electrically connected to the input terminal of the NOT gate, and the positive terminal of which is grounded.

4. A high-voltage integrated circuit according to claim 2, characterized in that, The electrostatic discharge circuit includes a MOSFET Q4, the drain of which is electrically connected to the input of the NOT gate, and the source and gate of which are grounded.

5. A high-voltage integrated circuit according to claim 1, characterized in that, The output circuit includes MOSFETs Q2 and Q3, resistors R2 and R3; the gates of MOSFETs Q2 and Q3 are both electrically connected to the output terminal of the frequency divider circuit, the drain of MOSFET Q2 is electrically connected to the other end of resistor R1, and serves as the module output terminal VB; the source of MOSFET Q2 is electrically connected to one end of resistor R2, the other end of resistor R2 is electrically connected to one end of resistor R3, and serves as the module output terminal HO; the drain of MOSFET Q3 is electrically connected to the other end of resistor R3, and the source of MOSFET Q3 serves as the output terminal VS.

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