Four-gate split-gate flash memory array with byte-erase operation

Abstract

A memory cell array, the memory cell array having: memory cells arranged in rows and columns; first sub-source lines, each of which connects source regions located in a row and in a first plurality of columns together; second sub-source lines, each of which connects source regions located in a row and in a second plurality of columns together; first erase gate lines and second erase gate lines, each of which connects all erase gates located in the first plurality of columns and the second plurality of columns together; first selection transistors, each of which is connected between a first sub-source line in the first sub-source lines and a source line in a plurality of source lines, and second selection transistors, each of which is connected between a second sub-source line in the second sub-source lines and a source line in the source lines; a first selection transistor line, which is connected to the gate of the first selection transistor, and a second selection transistor line, which is connected to the gate of the second selection transistor.

Description

[0001] Related patent applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 914,799, filed October 14, 2019, and U.S. Patent Application No. 16 / 784,183, filed February 6, 2020. Technical Field

[0003] This invention relates to non-volatile memory arrays. Background Technology

[0004] Parcel-gate nonvolatile memory cells with four gates per memory cell, and arrays of such cells, are also known. For example, U.S. Patent 7,868,375 discloses an array of parcel-gate nonvolatile memory cells with four gates per memory cell, and is incorporated herein by reference for all purposes. Quad-gate memory cells in… Figure 1 As shown in the figure. Each memory cell 10 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed vertically over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A select gate 28 is vertically disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18. A control gate 22 is vertically disposed over and insulated from the floating gate 20. An erase gate 30 is vertically disposed over the source region 14, and preferably includes a notch facing the edge of the floating gate 20.

[0005] The memory cell is erased by applying a high positive voltage to the erase gate 30 (where electrons are removed from the floating gate 20), which causes electrons on the floating gate 20 to tunnel from the edge of the floating gate 20 through the intermediate insulating material to the erase gate 22 via the Fowler-Nordheim tunneling effect (as shown). Figure 1 (As shown).

[0006] Memory cells are programmed by applying a positive programming voltage to the control gate 22, select gate 28, erase gate 30, and source region 14 (where electrons are applied to the floating gate 20). Electron flow occurs from the drain region 16 to the source region 14. When electrons reach the gap between the select gate 28 and the floating gate 20, they accelerate and become heated. Due to electrostatic attraction from the floating gate 20, some of the heated electrons are injected into the floating gate 20 through an intermediate insulating material (e.g., ...). Figure 1 (As shown).

[0007] A memory cell is read by applying a positive read voltage to the drain 16, control gate 22, and select gate 28 (which turns on the channel region 18 below the select gate 28). If the floating gate 20 is positively charged (i.e., electrons are erased and a positive voltage is coupled to the control gate 22), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), although a positive voltage is coupled to the control gate 22, the portion of the channel region 18 below the floating gate 20 is also mostly or completely turned off, and no current (or very little current) flows through the channel region 18, which is sensed as a programmed state or a "0" state.

[0008] Figure 1 The diagram also illustrates how pairs 11 of memory cells 10 can be formed, sharing a single source region 14 and an erase gate 30. Two adjacent pairs 11 of memory cells 10 can be arranged end-to-end and share a single drain region 16.

[0009] Figure 2 A conventional array configuration of memory cells 10 is shown. The memory cells 10 are arranged in rows and columns. Each column includes a pair 11 of memory cells 10 arranged end-to-end. Each column is generally referred to as an active region, and adjacent active regions are insulated from each other by an insulating material formed in an insulating region, generally referred to as an isolation region. Each row of memory cells includes a word line WL that electrically connects all the select gates 28 of that row of memory cells together. Preferably, the select gates are formed continuously across the entire row and constitute the word line WL (i.e., the portion of the word line WL above the channel region 18 of the memory cell for each select gate 28 of the memory cell). Each row of memory cells 10 also includes a control gate line CG that electrically connects all the control gates 22 of that row of memory cells 10 together. Preferably, the control gates 22 are formed continuously across the entire row and constitute the control gate line CG (i.e., the portion of the control gate line CG above the floating gate 20 of the memory cell for each control gate 22 of the memory cell).

[0010] Each row of memory cell pairs 11 includes a source line SL that electrically connects all source regions 14 of that row of memory cell pairs 11 together. The source line SL may be a continuous diffusion region extending across the active / isolation region, or it may include individual conductive lines that include periodic contacts with the source regions 14. Each row of memory cell pairs 11 includes an erase gate line EG that electrically connects all erase gates 30 of that row of memory cell pairs 11 together. Preferably, the erase gates 30 are formed continuously across the entire row of memory cell pairs 11 and constitute the erase gate line EG (i.e., the erase gate 30 of each memory cell pair 11 is the portion of the erase gate line EG disposed above the source regions 14 of that memory cell pair). Each column of memory cells includes a bit line BL that electrically connects all drain regions 16 of that column of memory cells together.

[0011] Figure 2 The diagram shows only two rows of memory cells for 11 and four columns of memory cells. However, it should be understood that memory arrays with this architecture can include hundreds or even thousands of rows and columns.

[0012] As detailed above, memory cells 10 are erased by applying a high voltage to erase gate 30. Therefore, an entire row of memory cells 11 (i.e., two rows of memory cells 10) is erased at once by applying a high voltage to a row of erase gate lines EG. One limitation of this architecture is that if it is necessary to change the information stored in only a portion of a row of memory cells 11, such as a single byte of information, the entire row of memory cells 11 must be erased and reprogrammed. There is no capability to erase only a portion of a row of memory cells 11.

[0013] A memory array architecture is needed that allows selective erasure of only a portion of a row of memory cell pairs. Summary of the Invention

[0014] The aforementioned problems and needs are addressed by a memory device comprising multiple memory cells arranged in rows and columns on a semiconductor substrate. Each memory cell includes: a source region and a drain region formed in the substrate and defining a channel region extending therebetween; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; a control gate disposed above and insulated from the floating gate; and an erase gate disposed above and insulated from the source region. Multiple word lines electrically connect all select gates together in a row of memory cells. Multiple control gate lines electrically connect all control gates together in a row of memory cells. Multiple bit lines electrically connect all drain regions together in a column. Multiple first sub-source lines electrically connect the source regions of memory cells located in a row of memory cells and in a first plurality of columns. Multiple second sub-source lines electrically connect the source regions of memory cells located in a row of memory cells and in a second plurality of columns, wherein the first plurality of columns are different from the second plurality of columns. A first erase gate line electrically connects all erase gates of memory cells located in the first plurality of columns. A second erase gate line electrically connects all erase gates of memory cells located in the second plurality of columns. Multiple first select transistors are each connected between one of the first sub-source lines and one of the plurality of source lines. Multiple second select transistors are each connected between one of the second sub-source lines and one of the source lines. A first select transistor line is connected to the gate of a first select transistor. A second select transistor line is connected to the gate of a second select transistor.

[0015] The memory device includes a plurality of memory cells arranged in alternating odd and even rows and columns on a semiconductor substrate. Each memory cell includes: a source region and a drain region formed in the substrate and defining a channel region extending therebetween; a floating gate disposed over and insulated from a first portion of the channel region; a select gate disposed over and insulated from a second portion of the channel region; a control gate disposed over and insulated from the floating gate; and an erase gate disposed over and insulated from the source region. A plurality of word lines electrically connect all select gates together in a row of memory cells. A plurality of control gate lines electrically connect all control gates together in a row of memory cells. A plurality of bit lines electrically connect all drain regions together in a column. A plurality of first sub-source lines electrically connect the source regions of memory cells located in a row of memory cells and in a plurality of first columns. Multiple second sub-source lines electrically connect the source regions of memory cells located in a row of memory cells and in a second plurality of columns, wherein the first plurality of columns are different from the second plurality of columns. A first erase gate line electrically connects all erase gates of memory cells located in even-numbered rows of memory cells and in the first plurality of columns. A second erase gate line connects all erase gates of memory cells located in odd-numbered rows of memory cells and in the first plurality of columns. A third erase gate line connects all erase gates of memory cells located in even-numbered rows of memory cells and in the second plurality of columns. A fourth erase gate line connects all erase gates of memory cells located in odd-numbered rows of memory cells and in the second plurality of columns. Multiple first select transistors are each connected between one of the first sub-source lines and one of the plurality of source lines. Multiple second select transistors are each connected between one of the second sub-source lines and one of the source lines. A first select transistor line is connected to the gate of a first select transistor. The second selection transistor line is connected to the gate of the second selection transistor.

[0016] Other objects and features of the invention will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of a conventional memory cell.

[0018] Figure 2 This is a schematic diagram illustrating a conventional memory array architecture.

[0019] Figure 3 This is a schematic diagram illustrating a first embodiment of a memory array architecture.

[0020] Figure 4 This is a schematic diagram illustrating an exemplary erase operation voltage for a first embodiment of a memory array architecture.

[0021] Figures 5 to 6 This is a schematic diagram illustrating an exemplary programming operation voltage for a first embodiment of a memory array architecture.

[0022] Figure 7 This is a schematic diagram illustrating an exemplary read operation voltage for a first embodiment of a memory array architecture.

[0023] Figure 8 This is a cross-sectional view of a second embodiment of the memory cell.

[0024] Figure 9 This is a schematic diagram illustrating a second embodiment of the memory array architecture.

[0025] Figure 10 This is a schematic diagram illustrating an exemplary erase operation voltage for a second embodiment of a memory array architecture.

[0026] Figures 11 to 12 This is a schematic diagram illustrating an exemplary programming operation voltage for a second embodiment of a memory array architecture.

[0027] Figure 13 This is a schematic diagram illustrating an exemplary read operation voltage for a second embodiment of a memory array architecture.

[0028] Figure 14 This is a cross-sectional view of a third embodiment of the memory cell.

[0029] Figure 15 This is a schematic diagram illustrating a third embodiment of the memory array architecture.

[0030] Figure 16 This is a schematic diagram illustrating an exemplary erase operation voltage for a third embodiment of a memory array architecture.

[0031] Figures 17 to 18 This is a schematic diagram illustrating an exemplary programming operation voltage for a third embodiment of a memory array architecture.

[0032] Figure 19 This is a schematic diagram illustrating an exemplary read operation voltage for a third embodiment of a memory array architecture.

[0033] Figure 20 This is a cross-sectional view of the fourth embodiment of the memory cell.

[0034] Figure 21 This is a schematic diagram illustrating a fourth embodiment of the memory array architecture.

[0035] Figure 22 This is a schematic diagram illustrating an exemplary erase operation voltage for a fourth embodiment of a memory array architecture.

[0036] Figures 23 to 24 This is a schematic diagram illustrating an exemplary programming operation voltage for a fourth embodiment of a memory array architecture.

[0037] Figure 25 This is a schematic diagram illustrating an exemplary read operation voltage for a fourth embodiment of a memory array architecture.

[0038] Figure 26 This is a schematic diagram illustrating the architecture of an exemplary memory device. Detailed Implementation

[0039] The present invention is an array architecture that provides the ability to erase not only a segment of a row of memory cells 11, but also a single row of memory cells 10 within that segment. Figure 3 It shows Figure 1 The memory cell of memory cell 10 is a first embodiment of memory cell 11. Figure 3 The architecture is similar to Figure 2 The architecture is as follows. However, instead of a single source line SL that extends along the entire length of a row of memory cell pairs 11 and electrically connects all source regions 14 together, each row of memory cell pairs 11 includes multiple sub-source lines SSL, wherein each sub-source line SSL extends only across a subset of the source regions of each row of memory cell pairs 11 (i.e., a sub-row of memory cell pair 11) and electrically connects them together. Specifically, the rows of memory cell pairs 11 are divided into regions R (i.e., different columns of memory cells), wherein each sub-source line SSL extends only across the portion of the source regions of a row of memory cell pairs 11 within a region R and electrically connects those source regions together. Figure 3 Two regions R1 and R2 are shown, each region R being two memory cells 10 wide (i.e., two columns wide, where each sub-row of memory cells includes two memory cells 10, so each sub-row of memory cell pair 11 includes four memory cells 10). However, the number of regions R and their width (i.e., the number of columns of memory cells 10 in region R) can vary. For example, each sub-row of memory cells 10 within region R may include enough memory cells to store one byte (8 bits) of data. Alternatively, a sub-row of memory cells 10 within region R may include enough memory cells to store one word of data (16 or 32 bits). The number of rows of memory cell pair 11 in the memory array can be varied as needed.

[0040] Each sub-row of memory cell pair 11 within any given region R has its own sub-source line SSL. Therefore, each region R has its own set of sub-source lines SSL. Each row of memory cell pair 11 also has its own source line SL, which extends in the row direction and across all regions R. Each sub-source line SSL in any given row of memory cell pair 11 is connected to its source line SL via a corresponding select transistor 34 (i.e., the source / drain channel path of the select transistor 34 is connected between the sub-source line SSL and the source line SL). Each column select transistor 34 is operated by a select transistor line STL connected to it for activation (i.e., turning on the source / drain channel path to electrically connect the SSL to the SL) or deactivation (i.e., de-conducting the source / drain channel path to disconnect the SSL from the SL) (i.e., the select transistor line STL is connected to the gate of the corresponding select transistor 34). The select transistor 34 is activated by applying a voltage exceeding a threshold voltage of the transistor 34 to the select transistor line STL. Transistor 34 is deactivated by applying no voltage, zero voltage, or a low voltage below the threshold voltage of transistor 34. Therefore, for any given row of memory cell pair 11, when all selection transistors 34 in that row are deactivated, the sub-source line SSL in that row is electrically isolated from its source line SL and from the other sub-source lines SSL in that row.

[0041] Figure 3 The array architecture also includes erase gate lines (EG), which are primarily in the column direction rather than as... Figure 2 The erase gate line EG extends in the row direction as shown, but also extends in the row direction in which each erase gate line EG electrically connects all erase gates 30 of one and only one region in region R. Thus, for example, the erase gate line EG of region R1 electrically connects all erase gates 30 of region R1 together (i.e., erase gates 30 in all sub-rows of memory cell pair 11 in region R1), but is electrically isolated from the erase gates 30 of memory cells in other regions R.

[0042] The array configuration described above allows a single sub-row of memory cell 10 to be erased without interfering with the programming state of any other memory cell 10 in the memory array (including other memory cells 10 in the same row and other memory cells 10 in different rows but in the same sub-row of memory cell pair 11). Figure 4 It shows that it can be applied to Figure 3The memory array is erased using an exemplary voltage for only one sub-row of sub-rows of memory cell 10. Specifically, to erase memory cell 10 on word line WL1 and control gate line CG1 in region R1 (i.e., target memory cell TMC), 0V is applied to all bit lines BL, all word lines WL, and all source lines SL. A high positive voltage HV (e.g., greater than about 7V) is applied to EG0, and 0V or a low positive voltage LV (e.g., less than 3V) is applied to all other erase gate lines EG. 0V is applied to CG1, and a positive suppression voltage VCGinh (e.g., greater than about 5V) is applied to all other control gate lines CG. 0V or a low positive voltage LV (e.g., less than 3V) is applied to STL0, and 0V is applied to all other select transistor lines STL. These voltages cause the target memory cell TMC in the row corresponding to WL1 in region R1 to be erased (by the high positive voltage on EG0). Other memory cells 10 in the same row as the target memory cell TMC were not erased because no high voltage was applied to their erase gates. Other memory cells in the same column as the target memory cell TMC were not erased because the suppression voltage VCGinh applied to their control gates was high enough to suppress any tunneling to the erase gates, but not high enough to cause any tunneling to the control gates (because the floating gate would see positive voltages on multiple sides, so only one side edge or corner edge would be erased). To enhance erasure, a negative voltage (e.g., -HV) instead of 0V could be applied to CG1.

[0043] Figure 5 An exemplary voltage is shown for programming one of the TMCs (right-side memory cell 10 in the TMC). A voltage MV applied to STL0 is greater than the threshold voltage of select transistor 34, thus applying MV to SL0 to turn on select transistor 34 in region R1 (causing all sub-source lines SSL in region 1 to couple to their respective source lines SL). Zero voltage is applied to STL1, so select transistor 34 in region R2 remains off. Only the target memory cell receives the correct combination of voltages and currents required for programming via hot electron injection as described above on its word line WL (e.g., LV), control gate line CG (e.g., HV), erase gate line EG (e.g., MV), sub-source lines SSL (e.g., MV), and / or bit line BL (e.g., Idp).

[0044] Figure 6 An alternative combination of exemplary voltages for programming one of the TMCs (right-side memory cell 10 in the TMC) is shown, which, together with Figure 5 The same as shown, except that a high voltage (HV) is applied to EG0 and a suppressor positive voltage VCGinh is applied to the control gate line CG of the non-target memory cell.

[0045] Figure 7 Exemplary voltages for reading one of the TMCs (right-side memory cell 10 in the TMC) are shown. Only the target memory cell receives the necessary combination of read voltages as described above on its word line WL (e.g., LV), control gate line CG (e.g., LV), erase gate line EG (e.g., 0V or LV), sub-source line SSL (e.g., 0V), and / or bit line BL (e.g., LV). Table 1 below summarizes the exemplary non-limiting voltages shown in the figures of all the various embodiments herein:

[0046] Table 1

[0047] LV <3V HV >7V VCGinh >5V MV 3V <MV<7V Idp 1uA-3uA

[0048] Figures 8 to 13 A second implementation scheme is shown, which is similar to Figures 3 to 7 In this implementation scheme, in addition to forming a separate erase gate 30 for each memory cell 10 in a pair of memory cells 11 (i.e., each memory cell 10 sharing a common source region 14 has its own erase gate 30), such as Figure 8 As shown. Figure 9 It shows the use of Figure 8 The memory cell array architecture configured with memory cells, which is related to... Figure 3 The illustrated memory cell array architecture is identical, except that each region R of the memory cell 10 includes two erase gate lines EG instead of one. Specifically, for each region R, one erase gate line EG electrically connects all erase gates 30 of the odd-numbered rows of memory cells 10 together, and another erase gate line EG electrically connects all erase gates 30 of the even-numbered rows of memory cells 10 together for that region R. This means that for any given pair of memory cells 11, the two erase gates 30 are connected to different erase gate lines EG. By using two erase gate lines instead of one in each region R, interference stress on adjacent non-target cells can be reduced.

[0049] Figure 10 An exemplary voltage (i.e., TMC) is shown for all memory cells 10 on word line WL1 in erasure region R1, since only those cells experience a high erase gate voltage without a corresponding positive control gate suppression voltage. To enhance erasure, a negative voltage (e.g., -HV) instead of 0V can be applied to CG1. Figure 11 and Figure 12 Two different exemplary voltage combinations are shown for programming one of the memory cells 10 (the right cell of the TMC). Figure 13 An exemplary voltage is shown for reading one of the memory cells 10 (the right cell of the TMC).

[0050] Figures 14 to 19 A third implementation scheme is shown, which is similar to Figures 3 to 7 In this implementation scheme, in addition to forming a separate source region 14 for each memory cell in the two memory cells 10 for each memory cell pair 11 (i.e., each memory cell 10 sharing the common erase gate 30 isolates its own source region 14 from the other source region 14 of the other memory cell 10), as... Figure 14 As shown. Preferably, source region 14 is separated by STI 36 (shallow trench isolation, such as oxide). Figure 15 It shows the use of Figure 14 The memory cell array architecture configured with memory cells, which is consistent with... Figure 3 The memory cell array architecture shown is the same, except that each individual sub-row of memory cells 10 in each region R includes its own sub-source line SSL and select transistor 34, and each row of memory cells 10 extending across all regions R includes its own source line SL (compared to sharing the sub-source line SSL, select transistor 34, and source line SL between two adjacent rows of memory cells 10 in a single row of memory cells 10). By using two different sub-source lines SSL and source lines SL for two different adjacent rows of memory cells 10 in a single row of memory cells 11, interference stress on adjacent non-target cells can be reduced.

[0051] Figure 16 An exemplary voltage (i.e., TMC) is shown for all memory cells on word line WL1 in erasing region R1, since only those memory cells experience a high erase gate voltage without a corresponding positive control gate suppression voltage. To enhance erasure, a negative voltage (e.g., -HV) instead of 0V can be applied to CG1. Figure 17 and Figure 18 Two different exemplary voltage combinations are shown for programming one of the memory cells 10 (the right cell of the TMC). Figure 19 An exemplary voltage is shown for reading one of the memory cells 10 (the right cell of the TMC).

[0052] Figures 20 to 25 A fourth implementation scheme is shown, which is similar to Figures 3 to 7 In this implementation scheme, in addition to forming a separate source region 14 for each memory cell in the two memory cells 10 for each memory cell pair 11 (i.e., each memory cell in memory cell 10 isolates its own source region 14 from the other source region 14 of the other memory cell 10), a separate erase gate 30 is formed for each memory cell 10 in the pair of memory cells 11 (i.e., each memory cell in memory cell 10 isolates its own erase gate 30 from the other erase gate 30 of the other memory cell), as... Figure 20 As shown. Preferably, source region 14 is separated by STI 36 (shallow trench isolation, such as oxide). Figure 21 It shows the use of Figure 20 The memory cell array architecture configured with memory cells, which is consistent with... Figure 3 The memory cell array architecture shown is the same, except that (1) each individual sub-row of memory cells 10 in each region R includes its own sub-source line SSL and select transistor 34, and each row of memory cells 10 extending across all regions R includes its own source line SL (compared to sharing the sub-source line SSL, select transistor 34, and source line SL between two adjacent rows of memory cells 10 in a row of memory cell pairs 11), and (2) each region R of memory cells 10 includes two, instead of one, erase gate lines EG (i.e., for each region R, one erase gate line EG electrically connects all erase gates 30 of odd-numbered rows of memory cells 10 together, and another erase gate line EG electrically connects all erase gates 30 of even-numbered rows of memory cells 10 together for that region R). By using two different sub-source lines SSL and source lines SL for two different adjacent rows of memory cells 10 in a single row of memory cell pairs 11, and by using two, instead of one, erase gate lines EG in each region R, interference stress on adjacent non-target cells can be reduced.

[0053] Figure 22 An exemplary voltage (i.e., TMC) is shown for all memory cells on word line WL1 in erasing region R1, since only those memory cells experience a high erase gate voltage without a corresponding positive control gate suppression voltage. To enhance erasure, a negative voltage (e.g., -HV) instead of 0V can be applied to CG1. Figure 23 and Figure 24 Two different exemplary voltage combinations are shown for programming one of the memory cells 10 (the right cell of the TMC). Figure 25 An exemplary voltage is shown for reading one of the memory cells 10 (the right cell of the TMC).

[0054] Figure 26 An architecture of an exemplary memory device is illustrated. The memory device includes an array 50 of non-volatile memory cells 10, which can be divided into two separate planes (plane A 52a and plane B 52b). Memory cells 10 may be... Figure 1 , Figure 8 , Figure 14 and Figure 20 The memory cells shown are formed on a single chip and arranged in multiple rows and columns in a semiconductor substrate 12, such as... Figures 3 to 7 , Figures 9 to 13 , Figures 15 to 19 and Figures 21 to 25 As shown. Adjacent to the non-volatile memory cell array are address decoders, such as low-voltage LV row decoders (e.g., XDEC 54), source line drivers (e.g., SLDRV 56), column decoders (e.g., YMUX 58), high-voltage row decoders (e.g., HVDEC 60), and bit line controllers (BLINHCTL 62), which decode addresses and supply various voltages to the gates and regions of the various memory cells during read, program, and erase operations of the selected memory cells. Column decoder 58 includes a sense amplifier containing circuitry for measuring current on the bit lines during read operations. Controller 66 (containing control circuitry) controls various device elements to perform each operation (programming, erasing, read) on the target memory cell, including the aforementioned peripheral circuitry and the select transistor 34 within the memory array, to provide signals on various lines including the select transistor line STL. Charge pump CHRGPMP 64 provides various voltages for reading, programming, and erasing memory cells under the control of controller 66. The controller 66 is configured to operate the memory device to program, erase, and read the memory cell 10.

[0055] For all the above embodiments, the only modest increase in the overall size of the array (to make room for the selection transistors and their lines) is worth the trade-off, because it is possible to erase only a sub-row of memory cells 10 at any given time, and to selectively apply voltage only to certain sub-source lines SSL during operation to improve performance. Furthermore, selection transistors can be added to the memory array without otherwise substantially altering the remainder of the memory array and the process flow that forms it.

[0056] It should be understood that the invention is not limited to the embodiments described above and shown herein, but is covered by any and all variations within the scope of any claim. For example, references to the invention herein are not intended to limit the scope of any claim or claim terminology, but only to one or more features that may be covered by one or more of these claims. Furthermore, it will be apparent from the claims and description that not all method steps need to be performed in the exact order shown or claimed, but rather in any order that allows for the proper formation of the memory device of the invention. A single layer of material may be formed as multiple layers of such or similar material, and vice versa. The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting the claims. For example, applying 0V is equivalent to not applying a voltage or grounding a line, where not applying a voltage or grounding a line results in zero volts on a particular line. Additionally, while many of the applied voltages indicate 0V, applying a low positive or negative voltage to one or more of the indicated lines can produce the same desired result for programming, reading, and erasing memory cells. Finally, the values ​​disclosed above and in the accompanying figures may vary depending on the performance of the manufactured memory cell array.

[0057] It should be noted that, as used herein, the terms “above” and “on” inclusively include “directly on” (without intermediate material, elements, or spaces) and “indirectly on” (with intermediate material, elements, or spaces). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, elements, or spaces) and “indirectly adjacent” (with intermediate material, elements, or spaces), “mounted to” includes “directly mounted to” (without intermediate material, elements, or spaces) and “indirectly mounted to” (with intermediate material, elements, or spaces), and “electrically coupled to” includes “directly electrically coupled to” (without intermediate material or elements electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or elements electrically connecting the elements together). For example, forming an element “above a substrate” can include forming the element directly on the substrate without intermediate material / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A memory device, the memory device include: A plurality of memory cells, the plurality of memory cells being arranged in rows and columns on a semiconductor substrate, wherein each of the memory cells comprises: a source region and a drain region formed in the substrate and defining a channel region of the substrate extending between the source region and the drain region; a floating gate vertically disposed above a first portion of the channel region and insulated from the first portion, a select gate disposed vertically above and insulated from a second portion of the channel region, a control gate disposed vertically above the floating gate and insulated from the floating gate, and an erase gate, the erase gate being vertically disposed above the source region and insulated from the source region; a plurality of word lines, each of the plurality of word lines electrically connecting together all of the select gates in one of the rows of the memory cells; a plurality of control gate lines, each of the plurality of control gate lines electrically connecting together all of the control gates in one of the rows of the memory cells; a plurality of bit lines, each of the plurality of bit lines electrically connecting together all of the drain regions in each of the columns; a plurality of first sub-source lines, each of the plurality of first sub-source lines electrically connecting together the source regions of the memory cells located in one of the rows of the memory cells and located in a first plurality of columns; a plurality of second sub-source lines, each of the plurality of second sub-source lines electrically connecting together the source regions of the memory cells in one of the rows of the memory cells and in a second plurality of columns, wherein the first plurality of columns is different from the second plurality of columns; a first erase gate line, wherein the first erase gate line electrically connects together all the erase gates of the memory cells in the first plurality of columns; a second erase gate line, the second erase gate line electrically connecting all the erase gates of the memory cells in the second plurality of columns; multiple source lines; a plurality of first selection transistors, each of the first selection transistors being connected between one of the first sub-source lines and one of the source lines; a plurality of second selection transistors, each of the second selection transistors being connected between one of the second sub-source lines and one of the source lines; a first select transistor line connected to a gate of the first select transistor; and A second select transistor line is connected to a gate of the second select transistor.

2. The memory device of claim 1 , wherein for each of the source lines, one of the first selection transistors connected to the source line is connected to a first sub-source line of the first sub-source lines of the first row of the memory cells, and one of the second selection transistors connected to the source line is connected to a second sub-source line of the second sub-source lines of the first row of the memory cells.

3. The memory device according to claim 1, further comprising: include: A controller configured to perform an erase operation on a target group of the memory cells in the first plurality of columns and connected to a first one of the control gate lines by: applying a positive voltage to the first erase gate line; applying a zero voltage or a negative voltage to the first control gate line; and A positive voltage is applied to all of the control gate lines except the first control gate line. 4 . The memory device of claim 3 , wherein the controller is configured to further perform the erase operation by applying a zero voltage or a voltage lower than a threshold voltage of the first selection transistor to the first selection transistor line. 5 . The memory device of claim 4 , wherein the controller is configured to further perform the erase operation by applying a zero voltage to the second selection transistor line.

6. The memory device of claim 1, further comprising: include: a controller configured to perform a programming operation on one of the memory cells in the first plurality of columns, wherein the one memory cell is connected to a first word line of the word lines and a first control gate line of the control gate lines, by: applying a positive voltage to the first word line; applying a positive voltage to the first control gate line; applying a positive voltage to the first erase gate line; and A positive voltage is applied to the first select transistor line. 7 . The memory device of claim 6 , wherein the controller is configured to further perform the program operation by applying a zero voltage to the second selection transistor line.

8. The memory device according to claim 1, in: Each of the first sub-source lines electrically connects together the source regions of the memory cells located in a second one of the rows of the memory cells and located in the first plurality of columns; and Each of the second sub-source lines electrically connects together the source regions of the memory cells located in a second one of the rows of the memory cells and located in the second plurality of columns.

9. The memory device according to claim 1, in: For each of the first sub-source lines, all of the source regions electrically connected together by one of the first sub-source lines are used for memory cells in only one of the rows of memory cells; and For each of the second sub-source lines, all of the source regions electrically connected together by one of the second sub-source lines are used for memory cells in only one of the rows of memory cells.

10. A memory device, the memory device include: A plurality of memory cells, the plurality of memory cells being arranged in alternating even and odd rows and in columns on a semiconductor substrate, wherein each of the memory cells comprises: a source region and a drain region formed in the substrate and defining a channel region of the substrate extending between the source region and the drain region; a floating gate vertically disposed above a first portion of the channel region and insulated from the first portion, a select gate disposed vertically above and insulated from a second portion of the channel region, a control gate disposed vertically above the floating gate and insulated from the floating gate, and an erase gate, the erase gate being vertically disposed above the source region and insulated from the source region; a plurality of word lines, each of the plurality of word lines electrically connecting together all of the select gates in one of the rows of the memory cells; a plurality of control gate lines, each of the plurality of control gate lines electrically connecting together all of the control gates in one of the rows of the memory cells; a plurality of bit lines, each of the plurality of bit lines electrically connecting together all of the drain regions in each of the columns; a plurality of first sub-source lines, each of the plurality of first sub-source lines electrically connecting together the source regions of the memory cells located in one of the rows of the memory cells and located in a first plurality of columns; a plurality of second sub-source lines, each of the plurality of second sub-source lines electrically connecting together the source regions of the memory cells in one of the rows of the memory cells and in a second plurality of columns, wherein the first plurality of columns is different from the second plurality of columns; a first erase gate line electrically connecting together all the erase gates of the memory cells in the even-numbered rows of the memory cells and in the first plurality of columns; a second erase gate line electrically connecting together all the erase gates of the memory cells in the odd-numbered rows of the memory cells and in the first plurality of columns; a third erase gate line, the third erase gate line electrically connecting together all the erase gates of the memory cells in the even-numbered rows of the memory cells and in the second plurality of columns; a fourth erase gate line, the fourth erase gate line electrically connecting together all the erase gates of the memory cells located in the odd-numbered rows of the memory cells and located in the second plurality of columns; multiple source lines; a plurality of first selection transistors, each of the first selection transistors being connected between one of the first sub-source lines and one of the source lines; a plurality of second selection transistors, each of the second selection transistors being connected between one of the second sub-source lines and one of the source lines; a first select transistor line connected to a gate of the first select transistor; and A second select transistor line is connected to a gate of the second select transistor.

11. The memory device of claim 10 , wherein for each of the source lines, one of the first selection transistors connected to the source line is connected to a first sub-source line of the first sub-source lines of the first row of the memory cells, and one of the second selection transistors connected to the source line is connected to a second sub-source line of the second sub-source lines of the first row of the memory cells.

12. The memory device of claim 10, further comprising: include: A controller configured to perform an erase operation on a target group of memory cells located in the first plurality of columns, connected to a first control gate line among the control gate lines, and connected to the second erase gate line by: applying a positive voltage to the second erase gate line; applying a zero voltage or a negative voltage to the first control gate line; A positive voltage is applied to all of the control gate lines connected to the memory cells, which are also connected to the second erase gate line except the first control gate line.

13. The memory device of claim 12, wherein the controller is configured to further perform the erase operation by applying a zero voltage to all of the control gate lines connected to the memory cells, the memory cells also being connected to the first erase gate line.

14. The memory device of claim 12 , wherein the controller is configured to further perform the erase operation by applying a low positive voltage to all of the control gate lines connected to the memory cells, the memory cells also being connected to the first erase gate line, wherein the low positive voltage is less than a positive voltage applied to all of the control gate lines connected to the memory cells, the memory cells also being connected to the second erase gate line other than the first control gate line. 15 . The memory device of claim 12 , wherein the controller is configured to further perform the erase operation by applying a zero voltage or a voltage lower than a threshold voltage of the first selection transistor to the first selection transistor line. 16 . The memory device of claim 15 , wherein the controller is configured to further perform the erase operation by applying a zero voltage to the second select transistor line.

17. The memory device of claim 10, further comprising: include: a controller configured to perform a programming operation on one of the memory cells in the first plurality of columns, wherein the one memory cell is connected to a first word line of the word lines, the second erase gate line, and a first control gate line of the control gate lines, by: applying a positive voltage to the first word line; applying a positive voltage to the first control gate line; applying a positive voltage to the second erase gate line; and A positive voltage is applied to the first select transistor line. 18 . The memory device of claim 17 , wherein the controller is configured to further perform the programming operation by applying a zero voltage to the second selection transistor line.

19. The memory device according to claim 10, in: Each of the first sub-source lines electrically connects together the source regions of the memory cells located in a second one of the rows of the memory cells and located in the first plurality of columns; and Each of the second sub-source lines electrically connects together the source regions of the memory cells located in a second one of the rows of the memory cells and located in the second plurality of columns.

20. The memory device according to claim 10, in: For each of the first sub-source lines, all of the source regions electrically connected together by one of the first sub-source lines are used for memory cells in only one of the rows of memory cells; and For each of the second sub-source lines, all of the source regions electrically connected together by one of the second sub-source lines are used for memory cells in only one of the rows of memory cells.

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