Pmos high-k metal gate

Abstract

Disclosed are metal gate stack structures and integrated methods of forming metal gate stack structures. Some embodiments include MoN as a PMOS work function material. Some embodiments include TiSiN as a high-k capping layer. Some embodiments provide improved PMOS band-edge performance. Some embodiments provide improved PMOS band-edge performance with reduced EOT penalty.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to high-κ metal gate (HKMG) stack structures. BACKGROUND

[0002] Integrated circuits have evolved from simple logic gates to incredibly complex devices that can include millions of transistors, capacitors and resistors on a single chip. During the evolution of integrated circuits, the functionality density (i.e., the number of interconnected devices per chip area) has generally increased while the geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] As device sizes shrink, the geometry and materials of the devices encounter difficulties in maintaining switching speed without causing malfunctions. Several new technologies have emerged that allow chip designers to continue to shrink device sizes. Control of device structure size is a key challenge for current and future technology generations.

[0004] Since 1970, the number of components per chip has doubled every two years. Because of this trend, miniaturization of circuits by shrinking transistors has been the main driving force of the semiconductor technology roadmap. The shrinking of materials currently used as N-MOS and P-MOS has become a challenge because of changes in the basic properties.

[0005] Current PMOS high-κ metal gate stack structures include TiN as a high-κ capping layer, followed by TiN as a PMOS work function material. Some new PMOS work function materials advantageously exhibit higher PMOS band edge V fb performance, but also exhibit an equivalent oxide thickness (EOT) penalty.

[0006] Therefore, there is a need for materials that have higher band edge V fb performance than TiN. Further, there is a need for these devices to have minimal EOT penalty. SUMMARY

[0007] One or more embodiments of the present disclosure relate to metal gate stack structures that include a PMOS work function material on a high-κ capping layer. The PMOS work function material includes MoN. The metal gate stack structure has improved V fb performance relative to metal gate stack structures that include a PMOS work function material that includes TiN.

[0008] Further embodiments of the disclosure relate to a metal gate stack structure including a high-k capping layer on a high-k metal oxide layer. The high-k capping layer includes TiSiN. A PMOS work function material is on the high-k capping layer. The PMOS work function material includes MoN. The metal gate stack structure has a reduced EOT increase relative to a metal gate stack structure including a high-k capping layer including TiN and a PMOS work function material including MoN.

[0009] Further embodiments of the disclosure relate to a method of manufacturing a metal gate stack structure. The method includes positioning a substrate including a high-k metal oxide layer in a first processing chamber. A high-k capping layer including TiSiN is deposited on the high-k metal oxide layer by atomic layer deposition. The substrate is transferred to a second processing chamber. A PMOS work function material including MoN is deposited on the high-k capping layer by atomic layer deposition. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments.

[0011] Figure 1 is a cross-sectional view of a metal gate stack structure according to one or more embodiments of the present disclosure;

[0012] Figure 2 is a flow chart of a method for forming a metal gate stack structure according to one or more embodiments of the present disclosure; and

[0013] Figure 3 is a cluster tool according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] Before several exemplary embodiments of the disclosure are described, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0015] As used in this specification and the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can only mean reference to a portion of a substrate unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0016] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a manufacturing process. For example, depending on the application, a substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material that is or can be used in processing. Substrates include, without limitation, semiconductor wafers. A substrate can be pre- processed in preparation for processing. Pre-processing can include cleaning the substrate surface, priming the substrate surface, oxidizing the substrate surface, hydroxylating the substrate surface, annealing the substrate surface, UV curing the substrate surface, e-beam curing the substrate surface, and / or baking the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017] Embodiments of the present disclosure relate to metal gate stack structures having improved V fb ) performance and / or reduced EOT. Some embodiments of the present disclosure provide metal gate stack structures having improved V fb In some embodiments, the PMOS work function material comprises MoN.

[0018] Some embodiments of the present disclosure advantageously provide metal gate stack structures having reduced EOT relative to metal gate stack structures using TiN as a high-k capping layer. In some embodiments, the high-k capping layer comprises TiSiN and the PMOS work function material comprises MoN.

[0019] One or more embodiments of the present disclosure provide devices and methods of formation particularly useful in forming positive metal oxide semiconductor (PMOS) integrated circuit devices, which will be described below. Other devices and applications are within the scope of the present disclosure.

[0020] Figure 1 A cross-sectional view of a PMOS metal gate stack structure device 100 is illustrated. Device 100 includes a substrate 110. In some embodiments, substrate 110 includes silicon. In some embodiments, the surface of substrate 110 is oxidized to form an oxide layer 115 on substrate 110. In some embodiments, the substrate includes additional electronic elements and materials, including but not limited to: source regions, drain regions, conductive channels, and other electrical connectors.

[0021] According to one or more embodiments, PMOS metal gate stack structure device 100 includes a gate dielectric 120, a high-k capping layer 130, and a metal gate work function layer 140. As used herein, metal gate work function layer 140 can also be referred to as a "PMOS work function material."

[0022] Gate dielectric 120 electrically insulates high-k capping layer 130 and metal gate work function layer 140 from substrate 110. In this context, gate dielectric 120, high-k dielectric capping layer 130, and metal gate work function layer 140 together can be referred to as a metal gate stack structure. In some embodiments, the metal gate stack structure further includes a gate electrode 150 on metal gate work function layer 140.

[0023] In some embodiments, gate dielectric 120 includes a metal oxide. In some embodiments, gate dielectric 120 is referred to as a high-k metal oxide layer. In some embodiments, gate dielectric 120 includes Hf02.

[0024] In some embodiments, high-k capping layer 130 includes or consists essentially of TiN. In some embodiments, high-k capping layer includes or consists essentially of TiSiN. As used in this regard, "consists essentially of" means that the named element comprises greater than 95%, greater than 98%, greater than 99%, or greater than 99.5% of the material by atoms. For the avoidance of doubt, the identification of a material disclosed herein does not imply a chemical dosage ratio. For example, a TiN material contains titanium and nitrogen. These elements can or can not be present in a 1 : 1 ratio.

[0025] The high-k cap layer 130 can have any suitable thickness. In some embodiments, the high-k cap layer 130 has a thickness in a range from about 0 A to about 10 A. In some embodiments, the high-k cap layer has a thickness of about 1 A, about 2 A, about 3 A, about 4 A, about 5 A, about 6 A, about 7 A, about 8 A, about 9 A, or about 10 A. to about 10 A. In some embodiments, the high-k cap layer has a thickness of about 1 A, about 2 A, about 3 A, about 4 A, about 5 A, about 6 A, about 7 A, about 8 A, about 9 A, or about 10 A.

[0026] The PMOS work function material 140 includes MoN. The inventors have surprisingly found that using MoN as the PMOS work function material provides higher PMOS band edge performance than TiN.

[0027] The PMOS work function material 140 can have any suitable thickness. In some embodiments, the PMOS work function material 140 has a thickness in a range from about 0 A to about 10 A. In some embodiments, the high-k cap layer has a thickness of about 1 A, about 2 A, about 3 A, about 4 A, about 5 A, about 6 A, about 7 A, about 8 A, about 9 A, or about 10 A. to about 10 A. In some embodiments, the high-k cap layer has a thickness of about 1 A, about 2 A, about 3 A, about 4 A, about 5 A, about 6 A, about 7 A, about 8 A, about 9 A, or about 10 A.

[0028] Flat band voltage (V fb ) provides a measure of the PMOS work function for a given material with a metal gate stack structure. The inventors have found that replacing the PMOS work function material 140 including TiN with MoN provides an increased V fb .

[0029] In some embodiments, the high-k cap layer 130 includes TiN. When the high-k cap layer 130 includes TiN, the V fb increases by greater than or equal to about +100 mV, greater than or equal to about +125 mV, greater than or equal to about +150 mV, greater than or equal to about +200 mV, greater than or equal to about +225 mV, greater than or equal to about +250 mV, greater than or equal to about +275 mV, greater than or equal to about +300 mV, or greater than or equal to about +325 mV. In some embodiments, the V fb increases by about +125 mV, about +175 mV, about +275 mV, or about +300 mV.

[0030] The inventors have also found that using MoN as the PMOS work function material 140 provides additional EOT degradation relative to a metal gate stack structure including TiN as the PMOS work function material. However, the inventors have also surprisingly found that replacing the high-k cap layer 130 including TiN with TiSiN provides reduced EOT degradation.

[0031] For example, a metal gate stack structure including a high-k cap layer 130 including TiN and a PMOS work function layer 140 including TiN has an approximate EOT. In some embodiments, the PMOS work function layer 140 comprising TiN is replaced with a PMOS work function layer 140 comprising MoN. This replacement results in an increase in EOT. In some embodiments, the increase in EOT is greater than or equal to about greater than or equal to about or greater than or equal to about

[0032] In some embodiments, the high-k capping layer 130 comprising TiN is replaced with a high-k capping layer 130 comprising TiSiN. This replacement results in a decrease in the increase in EOT. In some embodiments, the decrease in the increase in EOT is greater than or equal to about greater than or equal to about greater than or equal to about greater than or equal to about greater than or equal to about or greater than or equal to about In other words, in some embodiments, the increase in EOT is less than or equal to about less than or equal to about less than or equal to about less than or equal to about less than or equal to about or less than or equal to about

[0033] In some embodiments, the metal gate stack structure device 100 further comprises a gate electrode 150. The gate electrode 150 can comprise multiple layers. In some embodiments, the gate electrode 150 comprises a first layer and a second layer, the first layer comprising TiAl and the second layer comprising TiN. In some embodiments, the thickness of the first layer is about In some embodiments, the thickness of the second layer is about The first layer and the second layer can be deposited by any suitable method.

[0034] Referring to Figure 2 Another embodiment of the disclosure relates to a method 200 of forming a metal gate stack structure device 100. The method 200 begins at 210 by providing a substrate comprising a high-k metal oxide layer in a first processing chamber. At 220, a high-k capping layer comprising TiSiN is deposited on the high-k metal oxide layer by atomic layer deposition.

[0035] For the atomic layer deposition process referenced at 220, an example process for depositing TiSiN is provided below. The substrate is exposed to a first precursor comprising Ti, a second precursor comprising a nitrogen source, and a third precursor comprising a Si source to provide a TiSiN film. In some embodiments, the substrate is repeatedly exposed to the precursors to achieve a predetermined film thickness. In some embodiments, the substrate is maintained at a temperature of about 200 °C to about 700 °C during deposition.

[0036] Many precursors are within the scope of the present disclosure. The precursors can be plasma, gas, liquid, or solid at ambient temperature and pressure. However, within the ALD chamber, the precursors are volatilized. Organometallic compounds or complexes include any chemical species containing a metal and at least one organic group such as alkyl, alkoxy, alkylamido, and anilide. The precursors can be composed of organometallic compounds and inorganic / halide compounds.

[0037] Generally, any suitable titanium precursor can be used. Thus, the titanium precursor can include, but is not limited to, TiCl4, TiBr4, TiI4, TiF4, tetrakis(dimethylamido) titanium. Additionally, any suitable nitrogen source precursor can be used. Examples include, but are not limited to, nitrogen gas, ammonia, N2H2, or N2H4.

[0038] Various silicon precursors can be used. Examples of silicon precursors can include, but are not limited to, silane, disilane, trimethylsilane, dichlorosilane, and neopentasilane.

[0039] The order of substrate exposure to the precursors can be varied. For example, the substrate can be sequentially exposed to Ti / Si / N or Ti / N / Si. The exposure can be repeated in a deposition cycle. Further, the exposure to the precursors can be repeated within a single deposition cycle. For example, the substrate can be sequentially exposed to Ti / N / Si / N.

[0040] After depositing the high-k capping layer, the substrate is transferred to a second processing chamber at 230. In some embodiments, the first processing chamber and the second processing chamber are integrated into one. In some embodiments, the method 200 is performed without breaking vacuum or without exposure to ambient air. At 240, a PMOS work function material comprising MoN is deposited on the high-k capping layer by atomic layer deposition.

[0041] The methods disclosed herein can be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is moved from a first chamber to a separate second chamber for further processing. The substrate can be moved directly from the first chamber to the separate processing chamber, or the substrate can be moved from the first chamber to one or more transfer chambers and then to the separate processing chamber. Accordingly, suitable processing equipment may include multiple chambers communicating with transfer stations. This type of equipment may be referred to as a "cluster tool" or "clustered system" and the like.

[0042] Generally, clustering tools are modular systems comprising multiple chambers that perform various functions, including substrate center-finding and orientation, annealing, deposition, and / or etching. According to one or more embodiments, a clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot that can transport substrates between a processing chamber and a loading-locking chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transporting substrates from one chamber to another, and / or to a loading-locking chamber located at the front end of the clustering tool. Two well-known clustering tools adaptable to this disclosure are... Both are available from Applied Materials, Inc., Santa Clara, California, USA. However, the actual arrangement and combination of chambers can be modified to perform specific steps of the process described herein. Other processing chambers that can be used include, but are not limited to, circulating layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal treatment (such as RTP), plasma nitriding, annealing, orientation, hydroxylation, and other substrate processes. By performing the process in chambers on clustered tools, surface contamination of the substrate by atmospheric impurities can be avoided without oxidation prior to the deposition of subsequent films.

[0043] In some embodiments, the first processing chamber and the second processing chamber are components of the same clustered processing tool. Accordingly, in some embodiments, the method is an in-situ integration method.

[0044] In some embodiments, the first processing chamber and the second processing chamber are different processing tools. Accordingly, in some embodiments, the method is an ex-situ integration method.

[0045] According to one or more embodiments, the substrate remains under vacuum or "load lock" conditions and is not exposed to ambient air when moving from one chamber to the next. The transfer chamber is thus under vacuum and is "pumped down" under vacuum pressure. Inert gas can be present in the processing chamber or the transfer chamber. In some embodiments, inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, purge gas is injected at the exit of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, a curtain of inert gas flow is formed at the chamber exit.

[0046] The substrate can be processed in a single substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before another substrate is processed. The substrate can also be processed in a continuous manner similar to a conveyor belt system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and associated conveyor belt system can form a straight path or a curved path. Additionally, the processing chamber can be a carousel, where multiple substrates are moved around a central axis and exposed to deposition, etching, annealing, and / or cleaning processes throughout the carousel path.

[0047] The substrate can also be stationary or rotated during processing. A rotating substrate can be continuously rotated or rotated in discreet steps. For example, the substrate can be rotated throughout the entire process, or the substrate can be rotated a small amount between exposures to different reactive or purge gases. Rotating the substrate during processing, whether continuously or in discreet steps, can help produce more uniform deposition or etching by minimizing the effects of local variability in, for example, gas flow geometry.

[0048] In an atomic layer deposition type chamber, the substrate can be exposed to a first precursor and a second precursor in a spatially or temporally separated process. Temporal ALD is a conventional process where a first precursor is flowed into the chamber to react with the surface. The first precursor is purged from the chamber before a second precursor is flowed. In spatial ALD, the first precursor and the second precursor are flowed into the chamber at the same time, but are spatially separated, such that there is a region between the flows that prevents the precursors from mixing. In spatial ALD, the substrate is moved relative to the gas distribution plate, or the gas distribution plate is moved relative to the substrate.

[0049] In embodiments where one or more portions of the method occur within a chamber, the process can be a spatial ALD process. Although one or more of the aforementioned chemical properties may be incompatible (i.e., leading to reactions other than on the substrate surface and / or deposition on the chamber), spatial separation ensures that the reactants are not exposed to every type in the gas phase. For example, time-based ALD involves purging the deposition chamber. However, in practice, it is sometimes impossible to purge excess reactant from the chamber before allowing additional reactant to flow into it. Therefore, any remaining reactant in the chamber may react. With spatial separation, there is no need to purge excess reactant, and cross-contamination is limited. Furthermore, a significant amount of time may be used to purge the chamber, and thus the yield can be increased by eliminating the purge step.

[0050] Please refer to Figure 3 Further embodiments of this disclosure relate to a processing system 900 for performing the methods described herein. Figure 3 The illustration shows a system 900 for processing substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a swarm tool. The system 900 includes a central transfer station 910 having a robot 912 within it. The robot 912 is illustrated as a single-blade robot; however, those skilled in the art will recognize that other robots 912 are configured within the scope of this disclosure. The robots 912 are configured to move one or more substrates between chambers connected to the central transfer station 910.

[0051] At least one pre-cleaning / buffer chamber 920 is connected to the central transfer station 910. The pre-cleaning / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-cleaning / buffer chamber 920 may serve as a holding area for a single semiconductor substrate or as a holding area for a cassette of wafers to be processed. The pre-cleaning / buffer chamber 920 may perform a pre-cleaning process, or may preheat a substrate for processing, or may simply serve as a staging area for a process sequence. In some embodiments, two pre-cleaning / buffer chambers 920 are connected to the central transfer station 910.

[0052] exist Figure 3 In the illustrated embodiment, the pre-cleaning chamber 920 can be used as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 to move substrates from the cassette to the pre-cleaning / buffering chamber 920. Robot 912 may then move the substrates from the pre-cleaning / buffering chamber 920 to other chambers within the system 900.

[0053] The first processing chamber 930 can be connected to the central transfer station 910. The first processing chamber 930 can be configured as an atomic layer deposition chamber for depositing a high-k capping layer, and can be in fluid communication with one or more reactive gas sources to provide a flow of one or more reactive gases to the first processing chamber 930. The substrate can be moved to and from the processing chamber 930 by the robot 912 through an isolation valve 914.

[0054] The processing chamber 940 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 comprises an atomic layer deposition chamber for depositing a PMOS work function material, and is in fluid communication with one or more reactive gas sources to provide a flow of reactive gases to the processing chamber 940. The substrate can be moved to and from the processing chamber 940 by the robot 912 through an isolation valve 914.

[0055] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and is configured as a gate electrode deposition chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0056] In some embodiments, each of the processing chambers 930, 940, and 960 is configured to perform a different portion of a processing method. For example, the processing chamber 930 can be configured to perform a high-k capping layer deposition process, the processing chamber 940 can be configured to perform a PMOS work function material deposition process, and the processing chamber 960 can be configured to perform a gate electrode deposition process. The skilled artisan will recognize that the number and arrangement of individual processing chambers on a tool can be varied, and that Figure 3 The embodiments shown in FIG. 9 merely represent one possible configuration.

[0057] In some embodiments, the processing system 900 includes one or more metrology stations. For example, a metrology station can be located within the pre-clean / buffer chamber 920, within the central transfer station 910, or within any of the individual processing chambers. The metrology station can be located anywhere within the system 900 that allows for measurement of the distance of the recess without exposing the substrate to an oxidizing environment.

[0058] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, or 960. In some embodiments, there is more than one controller 950 connected to the individual chambers or stations, and a master control processor is coupled to each of the individual processors to control the system 900. The controller 950 can be one of any form of general- purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial setting to control various chambers and sub-processors.

[0059] The at least one controller 950 can have a processor 952, a memory 954 coupled to the processor 952, input / output devices 956 coupled to the processor 952, and support circuits 958 for communicating with the various electronic components. The memory 954 can include one or more of a temporary memory (e.g., random access memory), and a non- transitory memory (e.g., a hard disk).

[0060] The memory 954 or computer readable medium of the processor can be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage. The memory 954 can retain an instruction set that is operative by the processor 952 to control the parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. These circuits can include cache, power supplies, clock circuits, input / output circuitry, subsystems, and the like.

[0061] The processes can generally be stored in the memory as software routines, which, when executed by a processor, cause the process chamber to perform processes of the present disclosure. The software routines can also be stored and / or executed by a second processor (not shown) that is remotely located to the hardware being controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. As such, the processes can be implemented as software, executed on a computer system, as hardware, or as a combination of software and hardware. When executed on a computer system, the software routines will transform the general computer into a specific computer (controller) that controls the operation of the chamber to perform processes.

[0062] In some embodiments, the controller 950 has one or more configurations to perform individual processes or sub-processes to perform the methods. The controller 950 can be connected to and configured to operate intermediate components to perform the functions of the methods. For example, the controller 950 can be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controls, etc.

[0063] The controller 950 of some embodiments has one or more configurations selected from the group consisting of: a configuration to move a substrate on a robot between a plurality of processing chambers and a metrology station; a configuration to load and / or unload a substrate from the system; a configuration to deposit a high-k capping layer comprising TiN or TiSiN; a configuration to deposit a PMOS work function material comprising MoN; and / or a configuration to deposit a gate electrode.

[0064] References in the specification to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic being referred to is included in at least one embodiment of the disclosure. Thus, the appearances of such phrases in various places in the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments.

[0065] While the disclosure herein has been described with reference to particular embodiments, it will be understood by those skilled in the art that various modifications in form and details can be made therein without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is not limited to the specific embodiments described in this disclosure.

Claims

1. A metal gate stack structure, comprising: A high-κ capping layer, wherein the high-κ capping layer is on a high-κ metal oxide layer, the high-κ capping layer comprising titanium silicon nitride (TiSiN) and having approximately to approximately Thickness within the range; and PMOS work function material, the PMOS work function material on the high-κ capping layer, the PMOS work function material comprising molybdenum nitride (MoN) and having approximately to approximately Thickness within the range, The metal gate stack structure described therein has a Vo that is greater than or equal to about +125 mV compared to a metal gate stack structure containing a PMOS work function material containing titanium nitride (TiN). fb ,and The metal gate stack structure described therein has a reduced increase in equivalent oxide thickness (EOT) compared to a metal gate stack structure containing a high-κ capping layer of titanium nitride (TiN) and a PMOS work function material containing molybdenum nitride (MoN).

2. The metal gate stack structure as described in claim 1, wherein V fb It increased by more than or equal to approximately +300mV.

3. The metal gate stack structure as described in claim 1, wherein V fb It increased by more than or equal to approximately +175mV.

4. The metal gate stack structure as described in claim 3, wherein V fb It increased by more than or equal to approximately +275mV.

5. A metal gate stack structure, comprising: A high-κ capping layer, wherein the high-κ capping layer is on a high-κ metal oxide layer, the high-κ metal oxide layer comprising hafnium oxide (HfO2), and the high-κ capping layer comprising titanium silicon nitride (TiSiN) and having approximately to approximately Thickness within the range; and PMOS work function material, the PMOS work function material on the high-κ capping layer, the PMOS work function material comprising molybdenum nitride (MoN) and having approximately to approximately Thickness within the range, The metal gate stack structure described therein has a Vo that is greater than or equal to about +125 mV compared to a metal gate stack structure containing a PMOS work function material containing titanium nitride (TiN). fb ,and The metal gate stack structure described therein has a reduced EOT increase compared to a metal gate stack structure containing a high-κ capping layer of titanium nitride (TiN) and a PMOS work function material containing molybdenum nitride (MoN).

6. The metal gate stack structure of claim 5, wherein the increase in EOT is less than or equal to approximately [missing information] relative to a metal gate stack structure comprising a high-κ capping layer containing titanium nitride (TiN) and a work function material containing titanium nitride (TiN).

7. The metal gate stack structure of claim 6, wherein the increase in EOT is less than or equal to approximately 8. The metal gate stack structure as described in claim 5, further comprising: A substrate material having an oxidized surface, wherein the high-k metal oxide layer is on the oxidized surface; and Gate electrode, the gate electrode being located on the PMOS work function material.

9. The metal gate stack structure of claim 8, wherein the gate electrode comprises a first layer and a second layer, the first layer comprising titanium aluminum (TiAl) and the second layer comprising titanium nitride (TiN).

10. A method for manufacturing a metal gate stack structure, the method comprising the following steps: Within the first processing chamber, a high-κ capping layer is deposited on a high-κ metal oxide layer deposited on a substrate via atomic layer deposition. This high-κ capping layer comprises titanium silicon nitride (TiSiN) and has a density of approximately [missing information]. to approximately Thickness within the range; The substrate is transferred to the second processing chamber; and PMOS work function material, comprising molybdenum nitride (MoN) and having a work function of approximately [value missing], is deposited on the high-κ capping layer by atomic layer deposition. to approximately Thickness within the range, The metal gate stack structure described therein has a Vo that is greater than or equal to about +125 mV compared to a metal gate stack structure containing a PMOS work function material containing titanium nitride (TiN). fb ,and The metal gate stack structure described therein has a reduced increase in equivalent oxide thickness (EOT) compared to a metal gate stack structure containing a high-κ capping layer of titanium nitride (TiN) and a PMOS work function material containing molybdenum nitride (MoN).

11. The method of claim 10, wherein the first processing chamber and the second processing chamber are integrated into one unit, and the method is performed without disrupting the vacuum.

12. The method of claim 11, wherein the first processing chamber and the second processing chamber are components of the same processing tool.

13. The method of claim 11, wherein the first processing chamber and the second processing chamber are different processing tools.

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