A leap year judgment circuit and electronic equipment

Abstract

The present application relates to a leap year judgment circuit and electronic equipment, the circuit comprising: a BIN mode leap year judgment circuit, a BCD mode leap year judgment circuit and a multiplexer; the first input end of the multiplexer is connected to the BIN mode leap year judgment circuit, and the second input end of the multiplexer is connected to the BCD mode leap year judgment circuit; the multiplexer controls the on and off of the first input end and / or the second input end according to the received configuration instruction; when the first input end is turned on, the BIN mode leap year judgment circuit judges the input first year information, obtains the first leap year judgment result, and outputs the first leap year judgment result to the multiplexer; when the BCD mode leap year judgment circuit judges the input second year information, the second leap year judgment result is obtained, and the second leap year judgment result is output to the multiplexer. Through the circuit in this embodiment, leap year judgment in BIN mode and BCD mode can be supported at the same time, and can be adapted to a variety of application scenarios.

Description

Technical Field

[0001] The present application relates to the technical field of circuit design, and in particular to a leap year determination circuit and electronic equipment. Background Art

[0002] Clock circuits are widely used in various electronic devices. In related technologies, a real-time clock (RTC) module is generally required in SOC chips. It has timing functions and perpetual calendar functions, and can also automatically determine whether the current year is a leap year by hardware. The perpetual calendar function of current RTC modules can generally work in BIN (binary code corresponding to decimal number) mode or BCD (decimal number corresponding to the code of a decimal number represented by four binary digits) mode.

[0003] However, the leap year determination circuit in the related art can only perform leap year determination in one mode.

[0004] Currently, no effective solution has been provided for the technical problems existing in the relevant technologies. Summary of the invention

[0005] In order to solve the technical problem that a leap year determination circuit can only perform leap year determination in one mode, the present application provides a leap year determination circuit and an electronic device.

[0006] In a first aspect, an embodiment of the present application provides a leap year determination circuit, including: a BIN mode leap year determination circuit, a BCD mode leap year determination circuit, and a multiplexer;

[0007] The first input end of the multiplexer is connected to the BIN mode leap year judgment circuit, and the second input end of the multiplexer is connected to the BCD mode leap year judgment circuit; the multiplexer controls the on and off of the first input end and / or the second input end according to the received configuration instruction; when the first input end is turned on, the BIN mode leap year judgment circuit judges the input first year information to obtain a first leap year judgment result, and outputs the first leap year judgment result to the multiplexer; when the second input end is turned on, the BCD mode leap year judgment circuit judges the input second year information to obtain a second leap year judgment result, and outputs the second leap year judgment result to the multiplexer.

[0008] Optionally, as in the aforementioned leap year judgment circuit, the BIN mode leap year judgment circuit includes: a first judgment circuit for judging whether the decimal number corresponding to the BIN code input as the first year information is divisible by 4, a second judgment circuit for judging whether the decimal number corresponding to the BIN code is divisible by 100, a third judgment circuit for judging whether the decimal number corresponding to the BIN code is divisible by 400, a first AND gate unit, and a first OR gate unit;

[0009] The output ends of the first judgment circuit and the second judgment circuit are connected to a first AND gate unit; when the first judgment circuit judges that the decimal number corresponding to the BIN code is divisible by 4, the first judgment circuit outputs a first high-level signal, and when the second judgment circuit judges that the decimal number corresponding to the BIN code is not divisible by 100, the second judgment circuit outputs a second high-level signal, and the first AND gate unit generates a third high-level signal according to the first high-level signal and the second high-level signal;

[0010] The third judgment circuit and the first AND gate unit are connected to the first OR gate unit; when the third judgment circuit judges that the decimal number corresponding to the BIN code is divisible by 400, the third judgment circuit outputs a fourth high level signal; the first OR gate unit outputs the first leap year judgment result used to characterize that the first year information is a leap year based on the third high level signal or the fourth high level signal.

[0011] Optionally, as in the aforementioned leap year judgment circuit, the first judgment circuit comprises: a first NOT gate unit, a second NOT gate unit and a second AND gate unit;

[0012] Two input ends of the second AND gate unit are respectively connected to the output end of the first NOT gate unit and the output end of the second NOT gate unit;

[0013] When the first NOT gate unit determines that the first bit of the BIN code is 0, the first NOT gate unit outputs a first determination high level signal to the second AND gate unit;

[0014] When the second NOT gate unit determines that the second bit of the BIN code is 0, the second NOT gate unit outputs a second determination high level signal to the second AND gate unit;

[0015] When the second AND gate unit determines that both received two signals are high-level signals, the second AND gate unit outputs the first high-level signal.

[0016] Optionally, as in the aforementioned leap year judgment circuit, the second judgment circuit comprises: at least one first numerical comparator, a third NOT gate unit and a second OR gate unit;

[0017] Each input end of the second OR gate unit is respectively connected to an output end of the first numerical comparator, and the output end of the second OR gate unit is connected to the input end of the third NOT gate unit; when the first numerical comparator determines that the BIN code is consistent with the first preset code, the first numerical comparator outputs a first consistency high-level signal to the second OR gate unit; the decimal number corresponding to the first preset code is divisible by 100.

[0018] Optionally, as in the aforementioned leap year determination circuit, the third determination unit comprises: at least one second numerical comparator and a third OR gate unit;

[0019] Each input end of the third OR gate unit is respectively connected to an output end of the second numerical comparator; when the second numerical comparator determines that the BIN code is consistent with the second preset code, it outputs a second consistency high-level signal to the third OR gate unit; the decimal number corresponding to the second preset code is divisible by 400.

[0020] Optionally, as in the aforementioned leap year judgment circuit, the BCD mode leap year judgment circuit includes: a fourth judgment circuit for judging whether the decimal number corresponding to the BCD code input as the second year information is divisible by 4, a fifth judgment circuit for judging whether the decimal number corresponding to the BCD code is divisible by 100, a sixth judgment circuit for judging whether the decimal number corresponding to the BCD code is divisible by 400, a third AND gate unit, a fourth AND gate unit and a fourth OR gate unit;

[0021] The output ends of the fourth judgment circuit and the fifth judgment circuit are connected to the third AND gate unit; when the fourth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 4, the fourth judgment circuit outputs a fifth high-level signal, and when the fifth judgment circuit judges that the decimal number corresponding to the BCD code is not divisible by 100, the fifth judgment circuit outputs a fifth high-level signal, and the third AND gate unit generates a seventh high-level signal according to the fifth high-level signal and the sixth high-level signal;

[0022] The sixth judgment circuit and the fourth judgment circuit are connected to a fourth AND gate unit; when the sixth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 400, the sixth judgment circuit outputs an eighth high-level signal; the fourth OR gate unit outputs a ninth high-level signal according to the fifth high-level signal or the eighth high-level signal;

[0023] The third AND gate unit and the fourth AND gate unit are connected to a fourth OR gate unit; the fourth OR gate unit generates the second leap year determination result for characterizing that the second year information is a leap year according to the seventh high level signal and the eighth high level signal.

[0024] Optionally, as in the aforementioned leap year judgment circuit, the sixth judgment circuit comprises: a fifth OR gate unit, a sixth OR gate unit, a seventh OR gate unit, a fifth AND gate unit, a sixth AND gate unit, a seventh AND gate unit, an eighth AND gate unit and a fourth NOT gate unit;

[0025] One input end of the fifth AND gate unit is connected to the output end of the fifth OR gate unit, and the other input end is used to receive the signal corresponding to the 13th bit of the BCD code; when the fifth OR gate unit determines that the hundreds digit of the decimal number corresponding to the BCD code is 2 or 6, the third judgment high level signal is output to the fifth AND gate unit; when the 13th bit of the BCD code is 1, the level of the signal corresponding to the 13th bit of the BCD code is high level;

[0026] One input end of the sixth AND gate unit is connected to the output end of the sixth OR gate unit, and the other input end is connected to the fourth NOT gate unit, and the fourth NOT gate unit is used to receive the signal corresponding to the 13th bit of the BCD code; when the sixth OR gate unit determines that the hundreds digit of the decimal number corresponding to the BCD code is 0, 4 or 8, the fifth judgment high level signal is output to the sixth AND gate unit, and when the 13th bit of the BCD code is 0, the level of the signal corresponding to the 13th bit of the BCD code is low level;

[0027] The two input ends of the eighth AND gate unit are respectively connected to the output end of the seventh OR gate unit and the output end of the seventh AND gate unit; when the units digit and the tens digit of the decimal number corresponding to the BCD code are 0, the seventh AND gate unit outputs a sixth judgment high level signal to the eighth AND gate unit.

[0028] Optionally, as in the aforementioned leap year judgment circuit, the fourth judgment circuit comprises: an eighth OR gate unit, a ninth OR gate unit, a tenth OR gate unit, a ninth AND gate unit, a tenth AND gate unit and a fifth NOT gate unit;

[0029] One input end of the ninth AND gate unit is connected to the output end of the eighth OR gate unit, and the other input end is used to receive the signal corresponding to the 5th bit of the BCD code; when the eighth OR gate unit determines that the unit digit of the decimal number corresponding to the BCD code is 2 or 6, the seventh judgment high level signal is output to the ninth AND gate unit; when the 5th bit of the BCD code is 1, the level of the signal corresponding to the 5th bit of the BCD code is high level;

[0030] One input end of the tenth AND gate unit is connected to the output end of the ninth OR gate unit, and the other input end is connected to the output end of the fifth NOT gate unit, and the fifth NOT gate unit is used to receive the signal corresponding to the 5th bit of the BCD code; when the ninth OR gate unit determines that the unit digit of the decimal number corresponding to the BCD code is 0, 4 or 8, it outputs an eighth judgment high-level signal to the tenth AND gate unit; when the 5th bit of the BCD code is 0, the level of the signal corresponding to the 5th bit of the BCD code is a low level;

[0031] Two input ends of the tenth OR gate unit are respectively connected to the output end of the ninth AND gate unit and the output end of the tenth AND gate unit.

[0032] Optionally, as in the aforementioned leap year judgment circuit, the sixth judgment circuit includes an eleventh OR gate unit;

[0033] The eleventh OR gate unit outputs the sixth high level signal to the third AND gate unit when the ones digit or the tens digit of the decimal number corresponding to the BCD code is not 0.

[0034] In a second aspect, an embodiment of the present application provides an electronic device, including: a leap year determination circuit as described in any of the preceding items.

[0035] The embodiment of the present application provides a leap year judgment circuit and an electronic device, wherein the circuit includes: a BIN mode leap year judgment circuit, a BCD mode leap year judgment circuit and a multiplexer; the first input end of the multiplexer is connected to the BIN mode leap year judgment circuit, and the second input end of the multiplexer is connected to the BCD mode leap year judgment circuit; the multiplexer controls the on and off of the first input end and / or the second input end according to the received configuration instruction; when the first input end is turned on, the BIN mode leap year judgment circuit judges the input first year information, obtains the first leap year judgment result, and outputs the first leap year judgment result to the multiplexer; when the second input end is turned on, the BCD mode leap year judgment circuit judges the input second year information, obtains the second leap year judgment result, and outputs the second leap year judgment result to the multiplexer. Through the circuit in this embodiment, leap year judgment in BIN mode and BCD mode can be supported at the same time, and can be adapted to different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] Figure 1 A schematic diagram of a leap year determination circuit provided in an embodiment of the present application;

[0039] Figure 2 A circuit diagram of a BIN mode leap year determination circuit provided in an embodiment of the present application;

[0040] Figure 3 A circuit diagram of a second judgment circuit provided in an embodiment of the present application;

[0041] Figure 4 A circuit diagram of a first numerical comparator provided in an embodiment of the present application;

[0042] Figure 5 A circuit diagram of a third judgment circuit provided in an embodiment of the present application;

[0043] Figure 6 A circuit diagram of a second judgment circuit and a third judgment circuit provided in an embodiment of the present application;

[0044] Figure 7 A circuit diagram of a BCD mode leap year determination circuit provided in an embodiment of the present application;

[0045] Figure 8 A circuit diagram of a sixth judgment circuit provided in an embodiment of the present application;

[0046] Fig. 9 A circuit diagram of a fourth judgment circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0048] In the present application, the leap year determination is performed within the range of 0 to 3999 as an example.

[0049] Figure 1A leap year judgment circuit provided in an embodiment of the present application includes: a BIN mode leap year judgment circuit 1, a BCD mode leap year judgment circuit 2 and a multiplexer 3;

[0050] The first input end of the multiplexer 3 is connected to the BIN mode leap year judgment circuit 1, and the second input end of the multiplexer is connected to the BCD mode leap year judgment circuit 2; the multiplexer 3 controls the on and off of the first input end and / or the second input end according to the received configuration instruction; when the first input end is turned on, the BIN mode leap year judgment circuit 1 judges the input first year information, obtains the first leap year judgment result, and outputs the first leap year judgment result to the multiplexer; when the second input end is turned on, the BCD mode leap year judgment circuit 3 judges the input second year information, obtains the second leap year judgment result, and outputs the second leap year judgment result to the multiplexer.

[0051] Specifically, the multiplexer 3 is a device that can be used to switch between the BIN mode leap year judgment circuit and the BCD mode leap year judgment circuit.

[0052] The configuration instruction may be an instruction for selecting the BIN mode leap year judgment circuit 1 and the BCD mode leap year judgment circuit 2. Therefore, when the configuration instruction is used only for using the BIN mode leap year judgment circuit 1, the first input terminal is connected; when the configuration instruction is used only for using the BCD mode leap year judgment circuit 2, the second input terminal is connected; when the configuration instruction is used only for using the BIN mode leap year judgment circuit 1 and the BCD mode leap year judgment circuit 2 at the same time, the first input terminal and the second input terminal are connected at the same time.

[0053] The first leap year determination result is a result used to characterize whether the first year information is a leap year, and when it is a leap year, it can be characterized by a high level. The second leap year determination result is a result used to characterize whether the second year information is a leap year, and when it is a leap year, it can be characterized by a high level.

[0054] When the first input terminal is turned on and the BIN mode leap year judgment circuit 1 judges that the input first year information is a leap year, the output level 1 (used to indicate that the first year information is a leap year) is sent to the multiplexer; when the second input terminal is turned on and the BCD mode leap year judgment circuit 2 judges that the input second year information is a leap year, the output level 1 (used to indicate that the second year information is a leap year) is sent to the multiplexer 3.

[0055] like Figure 1 The leap year determination results shown include the first leap year determination result and the second leap year determination result described in this embodiment.

[0056] The circuit in this embodiment can support leap year determination in both BIN mode and BCD mode, and can be adapted to different application scenarios.

[0057] like Figure 2 As shown, in some embodiments, such as the aforementioned leap year judgment circuit, the BIN mode leap year judgment circuit includes: a first judgment circuit for judging whether the decimal number corresponding to the BIN code input as the first year information is divisible by 4, a second judgment circuit for judging whether the decimal number corresponding to the BIN code is divisible by 100, a third judgment circuit for judging whether the decimal number corresponding to the BIN code is divisible by 400, a first AND gate unit A2 and a first OR gate unit A3.

[0058] Specifically, the output ends of the first judgment circuit and the second judgment circuit are connected to the first AND gate unit A2; when the first judgment circuit judges that the decimal number corresponding to the BIN code is divisible by 4, the first judgment circuit outputs a first high-level signal, and when the second judgment circuit judges that the decimal number corresponding to the BIN code is not divisible by 100, the second judgment circuit outputs a second high-level signal, and the first AND gate unit A2 generates a third high-level signal according to the first high-level signal and the second high-level signal;

[0059] The third judgment circuit and the first AND gate unit A2 are connected to the first OR gate unit A3; when the third judgment circuit judges that the decimal number corresponding to the BIN code is divisible by 400, the third judgment circuit outputs a fourth high level signal; the first OR gate unit A3 outputs the first leap year judgment result used to characterize that the first year information is a leap year based on the third high level signal or the fourth high level signal.

[0060] In one optional implementation, assuming that the first leap year determination result y is a 16-bit binary number, it can be expressed as follows:

[0061] b15 b14 … … … … b3 b2 b1 b0

[0062] y is represented by a 16-bit (b15, b14, ..., b1, b0) binary number, where bx = 0 or 1 (x = 0, 1, 2, 3, ..., 15), that is:

[0063] y=(b15, b14,...b3, b2, b1, b0)2=b15×2 15 +b14×2 14 +…+b1

[0064] ×2 1 +b0×2 0 .

[0065] like Figure 2 As shown, the implementation method of the circuit for determining whether y is divisible by 4 can be:

[0066] The first judgment circuit includes: a first NOT gate unit B1, a second NOT gate unit B2 and a second AND gate unit A1;

[0067] Two input ends of the second AND gate unit A1 are respectively connected to the output end of the first NOT gate unit and the output end of the second NOT gate unit;

[0068] When the first NOT gate unit B1 determines that the first bit of the BIN code is 0, it outputs a first determination high level signal to the second AND gate unit A1;

[0069] When the second NOT gate unit B2 determines that the second bit of the BIN code is 0, it outputs a second determination high level signal to the second AND gate unit A1;

[0070] The second AND gate unit A1 outputs a first high-level signal when determining that both received two signals are high-level signals.

[0071] Specifically, in BIN (binary) mode, for a binary number, if its lowest two bits are both 0, then this number (including 0) must be divisible by 4. Therefore, as long as b1 (the second bit) and b0 (the first bit) are both 0, y must be divisible by 4. When the signals output by the first NOT gate unit B1 and the second NOT gate unit B2 are both high-level signals, the second AND gate unit A1 must output a high-level signal. Therefore, as long as the output of the second AND gate unit A1 is 1, it means that y is divisible by 4. Further, the device of this embodiment can be used to determine whether it is divisible by 4.

[0072] like Figure 2 and Figure 3 As shown, in some embodiments, like the aforementioned leap year judgment circuit, the second judgment circuit includes: at least one first value comparator B4, a third NOT gate unit B3 and a second OR gate unit U0;

[0073] Each input end of the second OR gate unit U0 is respectively connected to an output end of a first numerical comparator B4, and the output end of the second OR gate unit U0 is connected to the input end of the third NOT gate unit B3; when the first numerical comparator B4 determines that the BIN code is consistent with the first preset code, it outputs a high-level signal to the second OR gate unit U0; when the second OR gate unit U0 determines that there is a high-level signal in the received signal, it outputs a low-level signal to the third NOT gate unit B3, and the third NOT gate unit B3 outputs a second high-level signal based on the received low-level signal; the decimal number corresponding to the first preset code is divisible by 100.

[0074] Specifically, based on the above embodiment, only leap year judgment is implemented for years between 0 and 3999. Within this range, the years that are divisible by 100 are listed in the following table:

[0075] 0 100 200 300 400 … … … 3600 3700 3800 3900

[0076] The above data can form a logical lookup table. As long as y exists in the above data, it can be concluded that y is divisible by 100.

[0077] Each first value comparator B4 is structured as follows Figure 4 As shown in the figure, when the year ranges from 0 to 3999, the corresponding binary number has 14 bits. For two 14-bit binary numbers a (a13, ..., a2, a1, a0) and b (b13, ..., b2, b1, b0), if a and b are equal, the results of the XOR operation on their corresponding binary bits are both 0. The 14 XOR results are then ORed, and the result is 0. After that, they are input to the NOT gate, and the output result is 1 (i.e., a high-level signal). That is to say, when a and b are equal, as Figure 4 The output of the circuit shown will output 1.

[0078] A schematic diagram of connecting a plurality of first value comparators B4 to each other is shown in FIG. Figure 3 As shown, when one of the first value comparators B4 among the plurality of first value comparators B4 outputs 1 to the input end of the second OR gate unit U0, when the out output of the second OR gate unit U0 is 1, it indicates that it is divisible by 100. This means that when the third NOT gate unit B3 outputs 1 (i.e., a low level signal), it indicates that it is not divisible by 100.

[0079] like Figure 5 As shown, in some embodiments, as in the aforementioned leap year determination circuit, the third determination unit includes: at least one second value comparator B5 and a third OR gate unit U1;

[0080] Each input end of the third OR gate unit U1 is respectively connected to an output end of a second numerical comparator B5; when the second numerical comparator B5 determines that the BIN code is consistent with the second preset code, it outputs a high-level signal to the third OR gate unit U1; when the third OR gate unit U1 determines that there is a high-level signal in the received signal, it outputs a fourth high-level signal; the decimal number corresponding to the second preset code is divisible by 400.

[0081] Specifically, the second numerical comparator may also include a plurality of numerical comparison units. Based on the foregoing embodiment, taking leap year determination in a year range between 0 and 3999 as an example, within this range, the years that are divisible by 400 are listed as shown in the following table:

[0082] 0 400 800 1200 1600 2000 2400 2800 3200 3600

[0083] The second value comparator B5 for comparing the data of each year in the above table is connected to the circuit as shown in the following figure. Figure 5The input end of the OR gate U1 in the figure can be used as the input end of the OR gate U1, and then when the out output of U1 is 1, it indicates that the value corresponding to the first leap year determination result can be divided by 400. Optionally, the structure of each second value comparator B5 can refer to the following: Figure 4 The structure of the first numerical comparator B4 is shown.

[0084] In some optional implementations, since a number that is divisible by 400 must be divisible by 100, the following may also be used: Figure 6 The schematic diagram shown in Figure 3 and Figure 5 The circuits shown are combined with each other, and the numerical comparator for judging whether it is divisible by 100 is connected to the second OR gate unit U0, and the numerical comparator for judging whether it is divisible by 400 is connected to the third OR gate unit U1.

[0085] In BCD mode, assuming that the value y corresponding to the second year information is 4 digits, and only considering the case where y is in the range of 0 to 3999, its BCD mode can be expressed as follows:

[0086]

[0087] Let a represent the value of the unit digit, then its range is between 0 and 9, so it only needs to be represented by a 4-bit (a3, a2, a1, a0) binary number, where ax = 0 or 1 (x = 0, 1, 2, 3), that is

[0088] a=(a3, a2, a1, a0)2=a3×2 3 +a2×2 2 +a1×2 1 +a0×2 0 ;

[0089] Similarly, let b represent the value of the tens place, then:

[0090] b=(b3, b2, b1, b0)2=b3×2 3 +b2×2 2 +b1×2 1 +b0×2 0 ;

[0091] Similarly, let c represent the value of the hundreds place, then:

[0092] c=(c3, c2, c1, c0)2=c3×2 3 +c2×2 2 +c1×2 1 +c0×2 0 ;

[0093] Similarly, let d represent the value of thousands, then:

[0094] d=(d3,d2,d1,d0)2=d3×2 3 +d2×2 2 +d1×2 1 +d0×2 0 .

[0095] Based on the numerical representation method in BCD mode, such as Figure 7 As shown, in some embodiments, as the aforementioned leap year judgment circuit, the BCD mode leap year judgment circuit includes: a fourth judgment circuit for judging whether the decimal number corresponding to the BCD code input as the second year information is divisible by 4, a fifth judgment circuit for judging whether the decimal number corresponding to the BCD code is divisible by 100, a sixth judgment circuit for judging whether the decimal number corresponding to the BCD code is divisible by 400, a third AND gate unit, a fourth AND gate unit and a fourth OR gate unit;

[0096] Specifically, the output ends of the fourth judgment circuit and the fifth judgment circuit are connected to the third AND gate unit; when the fourth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 4, the fourth judgment circuit outputs a fifth high-level signal, and when the fifth judgment circuit judges that the decimal number corresponding to the BCD code is not divisible by 100, the fifth judgment circuit outputs a fifth high-level signal, and the third AND gate unit generates a seventh high-level signal according to the fifth high-level signal and the sixth high-level signal;

[0097] The sixth judgment circuit and the fourth judgment circuit are connected to the fourth AND gate unit; when the sixth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 400, the sixth judgment circuit outputs an eighth high-level signal; the fourth OR gate unit outputs a ninth high-level signal according to the fifth high-level signal or the eighth high-level signal;

[0098] The third AND gate unit and the fourth AND gate unit are connected to the fourth OR gate unit; the fourth OR gate unit generates a second leap year determination result for characterizing that the second year information is a leap year according to the seventh high level signal and the eighth high level signal.

[0099] Specifically, according to the device in this embodiment, when the fourth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 4, the fourth judgment circuit outputs a fifth high-level signal; otherwise, when the fourth judgment circuit judges that the decimal number corresponding to the BCD code is not divisible by 4, the fourth judgment circuit outputs a low-high-level signal; when the fifth judgment circuit judges that the decimal number corresponding to the BCD code is not divisible by 100, the fifth judgment circuit outputs a fifth high-level signal; otherwise, when the fifth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 100, the fifth judgment circuit outputs a low-level signal; the third AND gate unit A20 can generate the seventh high-level signal only after receiving two high-level signals (i.e., the fifth high-level signal and the sixth high-level signal).

[0100] When the sixth judgment circuit determines that the decimal number corresponding to the BCD code is divisible by 400, the sixth judgment circuit outputs an eighth high-level signal. Conversely, when the sixth judgment circuit determines that the decimal number corresponding to the BCD code is not divisible by 400, the sixth judgment circuit outputs a low-level signal. As long as there is a high-level signal in the input of the fourth OR gate unit A21, the ninth high-level signal can be output, that is, the ninth high-level signal can be output according to the fifth high-level signal or the eighth high-level signal.

[0101] The fourth OR gate unit A21 generates a high level signal according to the seventh high level signal and the eighth high level signal, that is, a second leap year determination result for indicating that the second year information is a leap year.

[0102] like Fig. 9 As shown, as the aforementioned leap year judgment circuit, the fourth judgment circuit includes: an eighth OR gate unit A5, a ninth OR gate unit A7, a tenth OR gate unit A9, a ninth AND gate unit A4, a tenth AND gate unit A8 and a fifth NOT gate unit A6;

[0103] One input end of the ninth AND gate unit A4 is connected to the output end of the eighth OR gate unit A5, and the other input end is used to receive the signal corresponding to the 5th bit of the BCD code; when the eighth OR gate unit A5 determines that the unit digit of the decimal number corresponding to the BCD code is 2 or 6, it outputs a seventh judgment high-level signal to the ninth AND gate unit; when the 5th bit of the BCD code is 1, the level of the signal corresponding to the 5th bit of the BCD code pair is high;

[0104] One input end of the tenth AND gate unit A8 is connected to the output end of the ninth OR gate unit A7, and the other input end is connected to the output end of the fifth NOT gate unit A6. The fifth NOT gate unit A6 is used to receive a signal corresponding to the 5th bit of the BCD code; when the ninth OR gate unit determines that the unit digit of the decimal number corresponding to the BCD code is 0, 4 or 8, an eighth judgment high-level signal is output to the tenth AND gate unit; when the 5th bit of the BCD code is 0, the level of the signal corresponding to the 5th bit of the BCD code is a low level;

[0105] Two input terminals of the tenth OR gate unit A9 are respectively connected to the output terminal of the ninth AND gate unit A8 and the output terminal of the tenth AND gate unit A5.

[0106] Specifically, the principles underlying this embodiment are:

[0107] If the last two digits of an integer are divisible by 4, then the number is divisible by 4.

[0108] Therefore, we only need to consider whether the number ba composed of the tens and ones digits of y is divisible by 4.

[0109] And the following conclusions were drawn:

[0110] 1-1. If b is an odd number, then when a is 2 or 6, the number is divisible by 4

[0111] 1-2. If b is an even number, then when a is 0, 4, or 8, the number is divisible by 4.

[0112] To determine whether b is an odd number, we only need to determine whether b0 in its binary bit is 1 or 0:

[0113] 2-1. When b0 is 1, b is an odd number

[0114] 2-2. When b0 is 0, then b is an even number

[0115] Corresponds to Fig. 9 As shown, when the output out of the tenth OR gate unit A9 is 1, it means that it is divisible by 4:

[0116] When the signal corresponding to the 5th bit of the BCD code is 1, a high-level signal is input to the ninth AND gate unit; when the eighth OR gate unit A5 determines that the unit digit of the decimal number corresponding to the BCD code is 2 or 6, the seventh judgment high-level signal is output to the ninth AND gate unit A6. Therefore, the ninth AND gate unit A6 can generate a high-level signal based on the two input high-level signals and input it to the tenth OR gate unit A9.

[0117] When the signal corresponding to the 5th bit of the received BCD code is 0, a low-level signal is input to the fifth NOT gate unit A6; when the ninth OR gate unit A7 determines that the unit digit of the decimal number corresponding to the BCD code is 0, 4 or 8, a high-level signal is output to the tenth AND gate unit A8. When the fifth NOT gate unit A6 processes the received low-level signal and inputs the high-level signal to the tenth AND gate unit A8, the tenth AND gate unit A8 outputs a high-level signal to the tenth OR gate unit A9 according to the two input high-level signals;

[0118] The output terminal of the tenth OR gate unit A9 outputs a fifth high level signal when receiving at least one high level signal.

[0119] like Figure 8 As shown, in some embodiments, like the aforementioned leap year judgment circuit, the sixth judgment circuit includes: a fifth OR gate unit A11, a sixth OR gate unit A14, a seventh OR gate unit A16, a fifth AND gate unit A12, a sixth AND gate unit A15, a seventh AND gate unit A17, an eighth AND gate unit A18 and a fourth NOT gate unit A13;

[0120] One input end of the fifth AND gate unit is connected to the output end of the fifth OR gate unit, and the other input end is used to receive the signal corresponding to the 13th bit of the BCD code; when the fifth OR gate unit determines that the hundreds digit of the decimal number corresponding to the BCD code is 2 or 6, the third judgment high level signal is output to the fifth AND gate unit; when the 13th bit of the BCD code is 1, the level of the signal corresponding to the 13th bit of the BCD code is high level;

[0121] One input end of the sixth AND gate unit is connected to the output end of the sixth OR gate unit, and the other input end is connected to the fourth NOT gate unit, and the fourth NOT gate unit is used to receive the signal corresponding to the 13th bit of the BCD code; when the sixth OR gate unit determines that the hundreds digit of the decimal number corresponding to the BCD code is 0, 4 or 8, the fifth judgment high level signal is output to the sixth AND gate unit, and when the 13th bit of the BCD code is 0, the level of the signal corresponding to the 13th bit of the BCD code is a low level;

[0122] The two input ends of the eighth AND gate unit are respectively connected to the output end of the seventh OR gate unit and the output end of the seventh AND gate unit; when the ones digit and the tens digit of the decimal number corresponding to the BCD code are 0, the seventh AND gate unit outputs a sixth judgment high level signal to the eighth AND gate unit.

[0123] Specifically, the principle on which the device of this embodiment is based is:

[0124] If the last two digits of an integer are both 0, and the two-digit number formed by its thousands and hundreds digits is divisible by 4, then the number is divisible by 400.

[0125] Combined with the circuit in BCD mode, determine whether y is divisible by 4 (such as Fig. 9 The circuit structure diagram of the circuit function to determine whether y is divisible by 400 can be obtained as shown in the circuit diagram Figure 8 As shown, when the out output of A18 is 1, it means that y is divisible by 400.

[0126] Based on the device in this embodiment, when the signal corresponding to the 13th bit of the BCD code is 1, a high level signal is input to the fifth AND gate unit A12; and when the fifth OR gate unit A11 determines that the hundreds digit of the decimal number corresponding to the BCD code is 2 or 6, a high level signal is output to the fifth AND gate unit A12. Therefore, the fifth AND gate unit A12 will output a high level signal to the seventh OR gate unit A16 according to the two input high level signals. It can be determined that the two-digit DC number composed of the hundreds digit and the thousands digit of y is divisible by 4.

[0127] When the signal corresponding to the 13th bit of the BCD code is a low-level signal, the fourth NOT gate unit processes the low-level signal to be a high-level signal; when the sixth OR gate unit A14 determines that the hundreds digit of the decimal number corresponding to the BCD code is 0, 4 or 8, it outputs a fifth judgment high-level signal to the sixth AND gate unit A15, and the sixth AND gate unit A15 outputs a high-level signal to the seventh OR gate unit A16 according to the two input high-level signals. It can be determined that the two-digit DC number composed of the hundreds digit and the thousands digit of y can be divided by 4.

[0128] When the output end of the seventh OR gate unit A16 receives at least one high-level signal, it outputs a high-level signal to the eighth AND gate unit A18; after receiving the high-level signal input when the ones digit of the decimal number corresponding to the BCD code is 0 and the high-level signal input when the tens digit is 0, the seventh AND gate unit A17 generates a sixth judgment high-level signal and outputs it to the eighth AND gate unit A18. The eighth AND gate unit A18 outputs a ninth high-level signal based on the two received high-level signals.

[0129] In some embodiments, as in the aforementioned leap year determination circuit, the sixth determination circuit includes an eleventh OR gate unit A10;

[0130] The eleventh OR gate unit A10 outputs a sixth high level signal to the third AND gate unit A20 according to the high level signal when the ones digit of the decimal number corresponding to the BCD code is not 0 or the high level signal when the tens digit is not 0.

[0131] The principle on which this embodiment is based is:

[0132] If the last two digits of an integer are both 0, then the number is divisible by 100, otherwise the number is not divisible by 100.

[0133] The circuit structure diagram is shown in Figure 7, where when the output out of A10 is 1, it means that y cannot be divided by 100.

[0134] As can be seen from the above, the leap year determination circuit in the present application has a simple structure and thus consumes little area, which can ensure that as few clocks as possible are consumed in the leap year determination process.

[0135] According to another embodiment of the present application, an electronic device is provided, including: a leap year determination circuit as described in any of the previous embodiments.

[0136] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0137] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A leap year determination circuit, characterized in that: include: BIN mode leap year judgment circuit, BCD mode leap year judgment circuit and multiplexer; The first input end of the multiplexer is connected to the BIN mode leap year judgment circuit, and the second input end of the multiplexer is connected to the BCD mode leap year judgment circuit; the multiplexer controls the on and off of the first input end and / or the second input end according to the received configuration instruction; when the first input end is turned on, the BIN mode leap year judgment circuit judges the input first year information to obtain a first leap year judgment result, and outputs the first leap year judgment result to the multiplexer; When the second input terminal is turned on, the BCD mode leap year judgment circuit judges the input second year information to obtain a second leap year judgment result, and outputs the second leap year judgment result to the multiplexer; The BIN mode leap year judgment circuit comprises: a first judgment circuit for judging whether the decimal number corresponding to the BIN code input as the first year information is divisible by 4, a second judgment circuit for judging whether the decimal number corresponding to the BIN code is divisible by 100, a third judgment circuit for judging whether the decimal number corresponding to the BIN code is divisible by 400, a first AND gate unit and a first OR gate unit; The output ends of the first judgment circuit and the second judgment circuit are connected to a first AND gate unit; when the first judgment circuit judges that the decimal number corresponding to the BIN code is divisible by 4, the first judgment circuit outputs a first high-level signal, and when the second judgment circuit judges that the decimal number corresponding to the BIN code is not divisible by 100, the second judgment circuit outputs a second high-level signal, and the first AND gate unit generates a third high-level signal according to the first high-level signal and the second high-level signal; The third judgment circuit and the first AND gate unit are connected to the first OR gate unit; when the third judgment circuit judges that the decimal number corresponding to the BIN code is divisible by 400, the third judgment circuit outputs a fourth high level signal; the first OR gate unit outputs the first leap year judgment result used to characterize that the first year information is a leap year based on the third high level signal or the fourth high level signal.

2. The leap year determination circuit according to claim 1, characterized in that: The first judgment circuit includes: a first NOT gate unit, a second NOT gate unit and a second AND gate unit; Two input ends of the second AND gate unit are respectively connected to the output end of the first NOT gate unit and the output end of the second NOT gate unit; When the first NOT gate unit determines that the first bit of the BIN code is 0, the first NOT gate unit outputs a first determination high level signal to the second AND gate unit; When the second NOT gate unit determines that the second bit of the BIN code is 0, the second NOT gate unit outputs a second determination high level signal to the second AND gate unit; When the second AND gate unit determines that both received two signals are high-level signals, the second AND gate unit outputs the first high-level signal.

3. The leap year determination circuit according to claim 1, characterized in that: The second judgment circuit includes: at least one first value comparator, a third NOT gate unit and a second OR gate unit; Each input end of the second OR gate unit is respectively connected to an output end of the first numerical comparator, and the output end of the second OR gate unit is connected to the input end of the third NOT gate unit; when the first numerical comparator determines that the BIN code is consistent with the first preset code, the first numerical comparator outputs a first consistency high-level signal to the second OR gate unit; the decimal number corresponding to the first preset code is divisible by 100.

4. The leap year determination circuit according to claim 1, characterized in that: The third judgment circuit comprises: at least one second value comparator and a third OR gate unit; Each input end of the third OR gate unit is respectively connected to an output end of the second numerical comparator; when the second numerical comparator determines that the BIN code is consistent with the second preset code, it outputs a second consistency high-level signal to the third OR gate unit; the decimal number corresponding to the second preset code is divisible by 400.

5. The leap year determination circuit according to claim 1, characterized in that: The BCD mode leap year judgment circuit includes: a fourth judgment circuit for judging whether the decimal number corresponding to the BCD code input as the second year information is divisible by 4, a fifth judgment circuit for judging whether the decimal number corresponding to the BCD code is divisible by 100, a sixth judgment circuit for judging whether the decimal number corresponding to the BCD code is divisible by 400, a third AND gate unit, a fourth AND gate unit and a fourth OR gate unit; The output ends of the fourth judgment circuit and the fifth judgment circuit are connected to the third AND gate unit; when the fourth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 4, the fourth judgment circuit outputs a fifth high-level signal, and when the fifth judgment circuit judges that the decimal number corresponding to the BCD code is not divisible by 100, the fifth judgment circuit outputs a fifth high-level signal, and the third AND gate unit generates a seventh high-level signal according to the fifth high-level signal and the sixth high-level signal; The sixth judgment circuit and the fourth judgment circuit are connected to a fourth AND gate unit; when the sixth judgment circuit judges that the decimal number corresponding to the BCD code is divisible by 400, the sixth judgment circuit outputs an eighth high-level signal; the fourth OR gate unit outputs a ninth high-level signal according to the fifth high-level signal or the eighth high-level signal; The third AND gate unit and the fourth AND gate unit are connected to a fourth OR gate unit; the fourth OR gate unit generates the second leap year determination result for characterizing that the second year information is a leap year according to the seventh high level signal and the eighth high level signal.

6. The leap year determination circuit according to claim 5, characterized in that: The sixth judgment circuit includes: a fifth OR gate unit, a sixth OR gate unit, a seventh OR gate unit, a fifth AND gate unit, a sixth AND gate unit, a seventh AND gate unit, an eighth AND gate unit and a fourth NOT gate unit; One input end of the fifth AND gate unit is connected to the output end of the fifth OR gate unit, and the other input end is used to receive the signal corresponding to the 13th bit of the BCD code; when the fifth OR gate unit determines that the hundreds digit of the decimal number corresponding to the BCD code is 2 or 6, the third judgment high level signal is output to the fifth AND gate unit; when the 13th bit of the BCD code is 1, the level of the signal corresponding to the 13th bit of the BCD code is high level; One input end of the sixth AND gate unit is connected to the output end of the sixth OR gate unit, and the other input end is connected to the fourth NOT gate unit, and the fourth NOT gate unit is used to receive the signal corresponding to the 13th bit of the BCD code; when the sixth OR gate unit determines that the hundreds digit of the decimal number corresponding to the BCD code is 0, 4 or 8, the fifth judgment high level signal is output to the sixth AND gate unit, and when the 13th bit of the BCD code is 0, the level of the signal corresponding to the 13th bit of the BCD code is low level; The two input ends of the eighth AND gate unit are respectively connected to the output end of the seventh OR gate unit and the output end of the seventh AND gate unit; when the units digit and the tens digit of the decimal number corresponding to the BCD code are 0, the seventh AND gate unit outputs a sixth judgment high level signal to the eighth AND gate unit.

7. The leap year determination circuit according to claim 5, characterized in that: The fourth judgment circuit includes: an eighth OR gate unit, a ninth OR gate unit, a tenth OR gate unit, a ninth AND gate unit, a tenth AND gate unit and a fifth NOT gate unit; One input end of the ninth AND gate unit is connected to the output end of the eighth OR gate unit, and the other input end is used to receive the signal corresponding to the 5th bit of the BCD code; when the eighth OR gate unit determines that the unit digit of the decimal number corresponding to the BCD code is 2 or 6, the seventh judgment high level signal is output to the ninth AND gate unit; when the 5th bit of the BCD code is 1, the level of the signal corresponding to the 5th bit of the BCD code is high level; One input end of the tenth AND gate unit is connected to the output end of the ninth OR gate unit, and the other input end is connected to the output end of the fifth NOT gate unit, and the fifth NOT gate unit is used to receive the signal corresponding to the 5th bit of the BCD code; when the ninth OR gate unit determines that the unit digit of the decimal number corresponding to the BCD code is 0, 4 or 8, it outputs an eighth judgment high-level signal to the tenth AND gate unit; when the 5th bit of the BCD code is 0, the level of the signal corresponding to the 5th bit of the BCD code is a low level; Two input ends of the tenth OR gate unit are respectively connected to the output end of the ninth AND gate unit and the output end of the tenth AND gate unit.

8. The leap year determination circuit according to claim 5, characterized in that: The sixth judgment circuit includes an eleventh OR gate unit; The eleventh OR gate unit outputs the sixth high level signal to the third AND gate unit when the ones digit or the tens digit of the decimal number corresponding to the BCD code is not 0.

9. An electronic device, characterized in that: include: A leap year determination circuit as claimed in any one of claims 1 to 8.

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