Circuit Optimization, Chip Verification Method, Device, Electronic Device and Storage Medium

Abstract

The present disclosure provides a circuit optimization, chip verification method, apparatus, electronic device, storage medium, and chip. The circuit optimization method includes: obtaining connection relationship information between a plurality of modules to be detected in a circuit to be optimized, and physical location information of each port in the module to be detected; after determining a plurality of target ports with the same input signal on a target module to be detected among the plurality of modules to be detected, determining other ports of other modules to be detected connected to the plurality of target ports based on the connection relationship information; determining a wire crossing result between the plurality of target ports and the other ports based on the physical location information of the plurality of target ports and the physical location information of the other ports; and adjusting the circuit to be optimized based on the wire crossing result to obtain a target circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and more particularly, to a circuit optimization, chip verification method, apparatus, electronic device, storage medium, and chip. Background Art

[0002] With the development of artificial intelligence technology, the development of artificial intelligence (AI) chips has become increasingly mature. Among them, an AI chip refers to a chip that has been specially accelerated for artificial intelligence algorithms, such as a deep learning algorithm for artificial intelligence algorithms.

[0003] Since more and more AI application scenarios have high requirements for the performance of the AI chips used, it is becoming increasingly important to improve the performance of AI chips. Generally, software algorithm optimization, hardware performance optimization, etc. can be used to improve the performance of AI chips. Among them, the wiring connection quality and blockage degree in the implementation stage of the AI chip can determine the level of the chip hardware performance. Therefore, it is particularly important to propose a method for optimizing the wiring connection of the chip circuit. Summary of the Invention

[0004] In view of this, the present disclosure provides at least a circuit optimization, chip verification method, apparatus, electronic device, storage medium, and chip.

[0005] In a first aspect, the present disclosure provides a circuit optimization method, including:

[0006] Obtaining connection relationship information between multiple to-be-detected modules in a to-be-optimized circuit, and physical location information of each port in the to-be-detected modules;

[0007] After determining multiple target ports with the same input signal on a target to-be-detected module among the multiple to-be-detected modules, based on the connection relationship information, determining other ports of other to-be-detected modules connected to the multiple target ports;

[0008] Based on the physical location information of the multiple target ports and the physical location information of the other ports, determining a wire crossing result between the multiple target ports and the other ports;

[0009] Based on the wire crossing result, adjusting the to-be-optimized circuit to obtain a target circuit.

[0010] In the above method, based on the obtained connection relationship information, other ports of other modules to be detected connected to multiple target ports are determined; based on the physical location information of the multiple target ports and the physical location information of the other ports, the wire crossing result between the multiple target ports and the other ports is determined. Since the physical location information can accurately represent the positions of the target ports and the other ports, the physical location information can be used to simply and accurately determine the wire crossing result between the multiple target ports and the other ports. Then, based on the wire crossing result, the circuit to be optimized can be adjusted more efficiently and accurately to obtain the target circuit, reducing the wire winding blockage of the interconnection wires in the target circuit and improving the hardware performance of the target circuit.

[0011] In a possible implementation manner, the determining the wire crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports includes:

[0012] For each target port, based on the physical location information of the target port and the physical location information of the other ports connected to the target port, the connection line information corresponding to the target port is determined;

[0013] Based on the connection line information respectively corresponding to the multiple target ports, the wire crossing result between the multiple target ports and the other ports is determined.

[0014] In the implementation manner of the present disclosure, the wire crossing result between the multiple target ports and the other ports can be accurately determined by determining the connection line information corresponding to each target port and then based on the connection line information respectively corresponding to the multiple target ports.

[0015] In a possible implementation manner, the determining the wire crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports includes:

[0016] Select two target ports from the multiple target ports as two current ports, and based on the physical location information of the two current ports, determine the first relative position information of the two current ports; and

[0017] Based on the physical location information of the two other ports connected to the two current ports, determine the second relative position information of the two other ports;

[0018] Based on the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports indicated by the connection relationship information, determine the local wire crossing result corresponding to the two current ports;

[0019] Re-select two target ports from the multiple target ports as the two updated current ports, and return to the step of determining the first relative position information of the two current ports based on the physical position information of the two current ports, until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined;

[0020] Based on at least one of the local wire crossing results, determine the wire crossing results between the multiple target ports and the other ports.

[0021] In the embodiments of the present disclosure, any two target ports among the multiple target ports can be used as the current ports to determine the first relative position information of the two current ports and the second relative position information of the other ports connected to the two current ports. Then, based on the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports, the local wire crossing results corresponding to the two current ports can be determined more accurately. Furthermore, based on at least one local wire crossing result, the wire crossing results between the multiple target ports and the other ports can be determined. By traversing the target ports multiple times to determine the wire crossing results, the wire crossing results can be made more precise and accurate.

[0022] In a possible implementation manner, the determining the wire crossing results between the multiple target ports and the other ports based on the physical position information of the multiple target ports and the physical position information of the other ports includes:

[0023] Select two target ports from the multiple target ports as the two current ports, and determine the dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports;

[0024] Based on the physical position information of the two other ports connected to the two current ports and the dividing line coordinate information, determine the local wire crossing results corresponding to the two current ports;

[0025] Re-select two target ports from the multiple target ports as the two updated current ports, and return to the step of determining the dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports, until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined;

[0026] Based on at least one of the local wire crossing results, determine the wire crossing results between the multiple target ports and the other ports.

[0027] In the embodiments of the present disclosure, any two of the multiple target ports can be used as the current ports. By determining the coordinate information of the dividing line corresponding to the two current ports, and using the physical location information of the two other ports connected to the two current ports and the coordinate information of the dividing line, the local wire crossing result corresponding to the two current ports can be determined more comprehensively and simply. Furthermore, based on at least one local wire crossing result, the wire crossing result between the multiple target ports and other ports can be determined. By traversing the target ports multiple times to determine the wire crossing result, the wire crossing result can be made more precise and accurate.

[0028] In a possible implementation manner, the determining the local wire crossing result corresponding to the two current ports based on the physical location information of the two other ports connected to the two current ports and the coordinate information of the dividing line includes:

[0029] Determining the relative position information between the physical location information of the other port connected to the first current port among the two current ports and the coordinate information of the dividing line; and / or, determining the relative position information between the physical location information of the other port connected to the second current port among the two current ports and the coordinate information of the dividing line; wherein, the physical location of the first current port is above the second current port;

[0030] Based on the relative position information, determining the local wire crossing result corresponding to the two current ports.

[0031] Here, determine the relative position information between the physical location information of the other port connected to the first current port and the coordinate information of the dividing line; and / or, determine the relative position information between the physical location information of the other port connected to the second current port and the coordinate information of the dividing line; then based on the relative position information, determine the local wire crossing result corresponding to the two current ports. For example, if the physical location of the other port connected to the first current port is below the dividing line, and / or the physical location of the other port connected to the second current port is above the dividing line, it is determined that there is a crossing in the local wire crossing result corresponding to the two current ports. By the above method, after obtaining the target circuit, the other ports connected to the first current port in the target circuit are located above the dividing line, and / or the other ports connected to the second current port are located below the dividing line, the interconnection wires of the target circuit are clearer, the wire winding blockage of the target circuit is reduced, and the hardware performance of the target circuit is improved.

[0032] In a possible implementation manner, the adjusting the circuit to be optimized based on the wire crossing result to obtain a target circuit includes:

[0033] Based on the wire crossing result, determine the ports to be adjusted with crossings from the multiple target ports;

[0034] Adjust the physical positions and / or connection relationships corresponding to the other ports connected to the ports to be adjusted to obtain a target circuit.

[0035] In the above embodiments, based on the wire crossing result, determine the ports to be adjusted with crossings from the multiple target ports; adjust the physical positions and / or connection relationships corresponding to the other ports connected to the ports to be adjusted, and accurately obtain the target circuit. The adjustment method is relatively flexible and diverse.

[0036] In a second aspect, the present disclosure provides a chip verification method, including:

[0037] Obtain a circuit to be verified corresponding to the chip to be verified;

[0038] Perform register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result;

[0039] After the first verification result indicates that the verification is passed, use the circuit optimization method described in the first aspect or any of the embodiments to optimize the circuit to be verified to obtain the target circuit corresponding to the circuit to be verified;

[0040] When it is detected that there is no crossing in the connection between the target port and other ports in the target circuit, perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit to obtain a second verification result;

[0041] After the second verification result indicates that the verification is passed, determine that the detection result corresponding to the chip to be verified is passed for sign-off.

[0042] In the embodiments of the present disclosure, after performing RTL implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result, if the first verification result indicates that the verification is passed, use the circuit optimization method described in the above embodiments to optimize the circuit to be verified to obtain the target circuit corresponding to the circuit to be verified, so that the wire crossing degree of the target circuit is lower than that of the circuit to be verified, and the modification of the connection lines is relatively simple and efficient. And when it is detected that there is no crossing in the connection between the target port and other ports in the target circuit, perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit to obtain a second verification result. After the second verification result indicates that the verification is passed, determine that the detection result corresponding to the chip to be verified is passed for sign-off, improving the verification efficiency of the chip.

[0043] In a possible implementation manner, the method further includes:

[0044] In the case where a connection line between a target port and other ports in the target circuit is detected to be crossed, the target circuit is used as the updated circuit to be verified and returned to the step of performing register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified until there is no crossing in the connection line between the target port and other ports in the target circuit.

[0045] For the effect descriptions of the following devices, electronic devices, etc., refer to the descriptions of the above methods and will not be elaborated here.

[0046] In a third aspect, the present disclosure provides a circuit optimization device, including:

[0047] A first acquisition module, configured to acquire connection relationship information between a plurality of modules to be detected in a circuit to be optimized, and physical location information of each port in the modules to be detected;

[0048] A first determination module, configured to, after determining a plurality of target ports having the same input signal on a target module to be detected among the plurality of modules to be detected, determine other ports of other modules to be detected connected to the plurality of target ports based on the connection relationship information;

[0049] A second determination module, configured to determine a connection line crossing result between the plurality of target ports and the other ports based on the physical location information of the plurality of target ports and the physical location information of the other ports;

[0050] An adjustment module, configured to adjust the circuit to be optimized based on the connection line crossing result to obtain a target circuit.

[0051] In a possible implementation manner, when determining the connection line crossing result between the plurality of target ports and the other ports based on the physical location information of the plurality of target ports and the physical location information of the other ports, the second determination module is configured to:

[0052] For each target port, determine connection line information corresponding to the target port based on the physical location information of the target port and the physical location information of other ports connected to the target port;

[0053] Determine the connection line crossing result between the plurality of target ports and the other ports based on the connection line information respectively corresponding to the plurality of target ports.

[0054] In a possible implementation manner, when determining the connection line crossing result between the plurality of target ports and the other ports based on the physical location information of the plurality of target ports and the physical location information of the other ports, the second determination module is configured to:

[0055] Select two target ports from the multiple target ports as two current ports, and determine first relative position information of the two current ports based on physical position information of the two current ports; and

[0056] Determine second relative position information of the two other ports based on physical position information of the two other ports connected to the two current ports;

[0057] Determine a local wire crossing result corresponding to the two current ports based on the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports indicated by the connection relationship information;

[0058] Re-select two target ports from the multiple target ports as the updated two current ports, and return to the step of determining the first relative position information of the two current ports based on the physical position information of the two current ports, until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined;

[0059] Determine a wire crossing result between the multiple target ports and the other ports based on at least one of the local wire crossing results.

[0060] In a possible implementation manner, when determining the wire crossing result between the multiple target ports and the other ports based on the physical position information of the multiple target ports and the physical position information of the other ports, the second determination module is configured to:

[0061] Select two target ports from the multiple target ports as two current ports, and determine dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports;

[0062] Determine a local wire crossing result corresponding to the two current ports based on the physical position information of the two other ports connected to the two current ports and the dividing line coordinate information;

[0063] Re-select two target ports from the multiple target ports as the updated two current ports, and return to the step of determining the dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports, until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined;

[0064] Determine a wire crossing result between the multiple target ports and the other ports based on at least one of the local wire crossing results.

[0065] In a possible implementation manner, when determining the local wire crossing result corresponding to the two current ports based on the physical location information of the two other ports connected to the two current ports and the dividing line coordinate information, the second determination module is configured to:

[0066] Determine the relative position information between the physical location information of the other port connected to the first current port among the two current ports and the dividing line coordinate information; and / or determine the relative position information between the physical location information of the other port connected to the second current port among the two current ports and the dividing line coordinate information; wherein, the physical location of the first current port is above the physical location of the second current port;

[0067] Based on the relative position information, determine the local wire crossing result corresponding to the two current ports.

[0068] In a possible implementation manner, when adjusting the circuit to be optimized based on the wire crossing result to obtain a target circuit, the adjustment module is configured to:

[0069] Based on the wire crossing result, determine the ports to be adjusted with crossings among the multiple target ports;

[0070] Adjust the physical location and / or connection relationship corresponding to the other ports connected to the ports to be adjusted to obtain a target circuit.

[0071] In a fourth aspect, the present disclosure provides a chip verification device, including:

[0072] A second acquisition module, configured to acquire a circuit to be verified corresponding to a chip to be verified;

[0073] A first verification module, configured to perform register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result;

[0074] An optimization module, configured to, after the first verification result indicates verification passed, use the circuit optimization method according to the first aspect or any implementation manner to optimize the circuit to be verified to obtain a target circuit corresponding to the circuit to be verified;

[0075] A second verification module, configured to perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit when it is detected that there is no crossing between the target port and other ports in the target circuit to obtain a second verification result;

[0076] A third determination module, configured to determine that the detection result corresponding to the chip to be verified is sign-off passed after the second verification result indicates verification passed.

[0077] In a possible implementation, the second verification module is further configured to:

[0078] When it is detected that there is a crossover in the connection between the target port and other ports in the target circuit, the target circuit is used as the updated circuit to be verified and returned to the step of performing register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified until there is no crossover in the connection between the target port and other ports in the target circuit.

[0079] In a fifth aspect, the present disclosure provides a chip, including: the circuit included in the chip is obtained by adjusting according to the steps of the circuit optimization method described in the first aspect or any implementation; or the chip is verified according to the steps of the method described in the second aspect or any implementation.

[0080] In a sixth aspect, the present disclosure provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory through the bus. When the machine-readable instructions are executed by the processor, the steps of the circuit optimization method described in the first aspect or any implementation are executed, or the steps of the chip verification method described in the second aspect or any implementation are executed, or the circuit described in the fifth aspect is included.

[0081] In a seventh aspect, the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the steps of the circuit optimization method described in the first aspect or any implementation are executed, or the steps of the chip verification method described in the second aspect or any implementation are executed.

[0082] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specific embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required to be used in the embodiments will be briefly introduced below. The drawings here are incorporated into the specification and constitute a part of this specification. These drawings show the embodiments that conform to the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0084] Figure 1The flowchart of a circuit optimization method provided by an embodiment of the present disclosure is shown;

[0085] Figure 2 In a circuit optimization method provided by an embodiment of the present disclosure, a schematic diagram of the connection relationship between different modules is shown;

[0086] Figure 3 In a circuit optimization method provided by an embodiment of the present disclosure, schematic diagrams of a circuit to be optimized and a target circuit are shown;

[0087] Figure 4 The flowchart of a chip verification method provided by an embodiment of the present disclosure is shown;

[0088] Figure 5 The architecture schematic diagram of a circuit optimization device provided by an embodiment of the present disclosure is shown;

[0089] Figure 6 The architecture schematic diagram of a chip verification device provided by an embodiment of the present disclosure is shown;

[0090] Figure 7 The structural schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. Detailed implementation manners

[0091] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only some, rather than all, of the embodiments of the present disclosure. Usually, the components of the embodiments of the present disclosure described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure to be protected, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0092] Since more and more AI application scenarios have put forward higher requirements for the performance of the used AI chips, it has become increasingly important to improve the performance of AI chips. Generally, software algorithm optimization, hardware performance optimization, etc. can be used to improve the performance of AI chips. Among them, the wire connection quality and blockage degree in the implementation stage of the AI chip can determine the level of the chip hardware performance.

[0093] Based on this, the embodiments of the present disclosure provide a circuit optimization, chip verification method, device, electronic device, and storage medium.

[0094] It should be noted that like reference numerals and letters refer to like items in the following figures; thus, once an item is defined in one figure, further definition and explanation thereof is not required in subsequent figures.

[0095] To facilitate understanding of the embodiments of the present disclosure, a circuit optimization method disclosed in the embodiments of the present disclosure will be introduced in detail first. The execution subject of the circuit optimization method provided by the embodiments of the present disclosure is generally a computer device with certain computing capabilities, and the computer device includes, for example: a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a computing device, etc. In some possible implementation manners, the circuit optimization method may be implemented by a processor invoking computer-readable instructions stored in a memory.

[0096] See Figure 1 As shown, it is a schematic flowchart of the circuit optimization method provided by the embodiments of the present disclosure, S101-S104, wherein:

[0097] S101, obtain connection relationship information between multiple to-be-detected modules in the to-be-optimized circuit, and physical location information of each port in the to-be-detected modules;

[0098] S102, after determining multiple target ports with the same input signal on a target to-be-detected module among the multiple to-be-detected modules, based on the connection relationship information, determine other ports of other to-be-detected modules connected to the multiple target ports;

[0099] S103, based on the physical location information of the multiple target ports and the physical location information of the other ports, determine a wire crossing result between the multiple target ports and the other ports;

[0100] S104, based on the wire crossing result, adjust the to-be-optimized circuit to obtain a target circuit.

[0101] In the above method, by determining other ports of other to-be-detected modules connected to multiple target ports based on the obtained connection relationship information, and determining a wire crossing result between the multiple target ports and the other ports based on the obtained physical location information of the multiple target ports and the physical location information of the other ports. Since the physical location information can accurately represent the positions of the target ports and the other ports, the physical location information can be used to simply and accurately determine the wire crossing result between the multiple target ports and the other ports. Then, based on the wire crossing result, the to-be-optimized circuit can be adjusted more efficiently and accurately to obtain a target circuit, reducing the wire winding blockage of the interconnection lines in the target circuit and improving the hardware performance of the target circuit.

[0102] The following specifically describes S101 - S104.

[0103] Regarding S101:

[0104] The circuit to be optimized can be any designed circuit. For example, the circuit to be optimized can be the designed circuit corresponding to an AI chip, or a partial circuit on the designed circuit corresponding to an AI chip, etc. Among them, the circuit to be optimized is the circuit before chip tape - out.

[0105] The circuit to be optimized can include multiple modules to be detected, and there is corresponding connection relationship information between each module to be detected. Among them, the module to be detected can be a module with a specific function on the circuit to be optimized. For example, the module to be detected can be a cache module, a processing module, an Intellectual Property (IP) core, etc.

[0106] Among them, the connection relationship information between each module to be detected can be determined according to the circuit to be optimized. Exemplarily, the connection relationship information can include the connection relationship between the module to be detected and the module to be detected. For example, the connection relationship information can include: the IP core is connected to module 1, the IP core is connected to module 2, etc.; or, after instantiating the module to obtain multiple modules with the same function, the connection relationship information can include the IP core is connected to the multiple identical modules after instantiation, etc.

[0107] The connection relationship information can also include the connection relationship between ports on different modules to be detected. For example, the connection relationship information can include: port 1 of the IP core is connected to module M1, port 2 of the IP core is connected to module M2, etc. For another example, the connection relationship information can also include: port 1 of the IP core is connected to port P1 on module M1, port 2 of the IP core is connected to port P2 on module M1, etc. Among them, the port can be used to realize the transmission of data between different modules. For example, port 1 of the IP core is connected to port P1 on module M1, and the data output by module M1 can be transmitted to the IP core through port P1 and port 1, so that the IP core can process the received data.

[0108] During implementation, it is also possible to obtain the physical location information of each port on each module to be detected in the circuit to be optimized. This physical location information can be coordinate information in a preset coordinate system. For example, when the circuit to be optimized is a design circuit on an AI chip, a two-dimensional coordinate system can be established with the lower left vertex of the AI chip as the origin to determine the physical location information of each port on the module to be detected in this coordinate system. For example, the physical location information of output port 1 of module 1 to be detected can be (x1, y1), and the physical location information of output port 2 can be (x1, y2). Since ports of the same type (output ports or input ports) are located on the same side of the module to be detected, the abscissa values of the ports of the same type on the module to be detected are the same, and the ordinate values are different.

[0109] Regarding S102:

[0110] During implementation, the target module to be detected among multiple modules to be detected can be determined. The target module to be detected can be a module with multiple ports connected to multiple instantiated modules. For example, the target detection module can be an IP core on an AI chip.

[0111] Determine multiple target ports on the target module to be detected that have the same input signal. For example, if the input signals corresponding to port 1, port 2, and port 3 on target module to be detected 1 are the same, then port 1, port 2, and port 3 can be used as target ports. Generally, the function information of each port of the target module to be detected can be determined; and based on the function information of each port, multiple target ports with the same input signal can be determined. For example, if the function information corresponding to port 1, port 2, and port 3 is the same, it is determined that the input signals corresponding to port 1, port 2, and port 3 are the same.

[0112] Or, if the input signals corresponding to port M1, port M2, and port M3 on target module to be detected 1 are the same, and the input signals corresponding to port N1, port N2, and port N3 are the same, then port M1, port M2, and port M3 can be used as a group of target ports, and port N1, port N2, and port N3 can be used as another group of target ports.

[0113] When the target ports include multiple groups, the connection crossing results corresponding to each group of target ports can be determined respectively in the subsequent process; and based on the connection crossing results corresponding to each group of target ports, the circuit to be optimized is adjusted to obtain the target circuit.

[0114] After obtaining multiple target ports with the same input signal, based on the obtained connection relationship information, other ports of other to-be-detected modules connected to the multiple target ports can be determined. For example, when the target ports include target port 1, target port 2, and target port 3, other port 1 connected to target port 1, other port 2 connected to target port 2, and other port 3 connected to target port 3 can be determined. Here, other port 1, other port 2, and other port 3 can be output ports on the same to-be-detected module or output ports on different to-be-detected modules.

[0115] Regarding S103:

[0116] After determining multiple target ports with the same input signal and other ports connected to the multiple target ports, the physical location information of the multiple target ports and the physical location information of the other ports can be determined. And based on the physical location information of the multiple target ports and the physical location information of the other ports, the wire crossing result between the multiple target ports and the other ports can be determined.

[0117] Optionally, the following process provides three ways to determine the wire crossing result based on the physical location information of multiple target ports and the physical location information of other ports.

[0118] In one way, based on the physical location information of multiple target ports and the physical location information of other ports, determining the wire crossing result between the multiple target ports and the other ports may include:

[0119] Step A1, for each target port, based on the physical location information of the target port and the physical location information of the other port connected to the target port, determine the connection line information corresponding to the target port.

[0120] Step A2, based on the connection line information respectively corresponding to the multiple target ports, determine the wire crossing result between the multiple target ports and the other ports.

[0121] In step A1, for each of the multiple target ports, based on the physical location information of the target port and the physical location information of the other port connected to the target port, the connection line information corresponding to the target port can be determined. Furthermore, the connection line information respectively corresponding to each target port can be obtained. For example, the connection line information can be an expression corresponding to the connection line.

[0122] For example, when the target ports include target port 1, target port 2, and target port 3, based on the physical location information of target port 1 and the physical location information of other port 1, the connection line information corresponding to target port 1 can be obtained. Similarly, the connection line information corresponding to target port 2 and the connection line information corresponding to target port 3 can be obtained.

[0123] In step A2, after obtaining the connection line information corresponding to multiple target ports, the connection line crossing results between the multiple target ports and other ports can be determined based on the connection line information corresponding to each of the multiple target ports.

[0124] Continuing with the example in step A1, the connection line crossing results between the multiple target ports and other ports can be determined according to the connection line information corresponding to target port 1, the connection line information corresponding to target port 2, and the connection line information corresponding to target port 3.

[0125] Alternatively, the local connection line crossing result 1 between target port 1 and target port 2 can be determined according to the connection line information corresponding to target port 1 and the connection line information corresponding to target port 2; the local connection line crossing result 2 between target port 1 and target port 3 can be determined according to the connection line information corresponding to target port 1 and the connection line information corresponding to target port 3; the local connection line crossing result 3 between target port 2 and target port 3 can be determined according to the connection line information corresponding to target port 2 and the connection line information corresponding to target port 3. Finally, the local connection line crossing result 1, the local connection line crossing result 2, and the local connection line crossing result 3 are determined as the connection line crossing results between the multiple target ports and other ports.

[0126] See Figure 2 As shown, the figure includes the target module to be detected 21, and other modules to be detected M1 and other modules to be detected M2 connected to the target module to be detected 21. The target module to be detected 21 includes target port Y1 and target port Y2, and target port Y1 is connected to other ports on other module to be detected M2, and target port Y2 is connected to other ports on other module to be detected M1. Among them, when the function information of port Y1 and port Y2 is detected to be the same, port Y1 and port Y2 are determined to be multiple target ports with the same input signal.

[0127] Furthermore, the connection line information of the first connection line 22 can be obtained according to the physical location information of target port Y1 and the physical location information of other ports on other module to be detected M2; and the connection line information of the first connection line 23 can be obtained according to the physical location information of target port Y2 and the physical location information of other ports on other module to be detected M1.

[0128] Then, the connection line crossing result between target port Y1 and target port Y2 can be determined according to the connection line information of the first connection line 22 and the connection line information of the second connection line 23. For example, according to the connection line information of the first connection line 22 and the connection line information of the second connection line 23, it can be determined whether there is an intersection point between the first connection line 22 and the second connection line 23. If there is, the connection line crossing result is determined to be a crossing; if not, the connection line crossing result is determined to be no crossing.

[0129] In the embodiments of the present disclosure, the connection line information corresponding to each target port can be determined, and then based on the connection line information respectively corresponding to multiple target ports, the connection line crossing result between multiple target ports and other ports can be determined more accurately.

[0130] In another way, based on the physical location information of multiple target ports and the physical location information of other ports, determining the connection line crossing result between multiple target ports and other ports includes:

[0131] Step B1, select two target ports from multiple target ports as two current ports, and based on the physical location information of the two current ports, determine the first relative position information of the two current ports. And based on the physical location information of two other ports connected to the two current ports, determine the second relative position information of the two other ports.

[0132] Step B2, based on the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports indicated by the connection relationship information, determine the local connection line crossing result corresponding to the two current ports.

[0133] Step B3, reselect two target ports from multiple target ports as the updated two current ports, and return to the step of determining the first relative position information of the two current ports based on the physical location information of the two current ports until the local connection line crossing results corresponding to any two target ports among multiple target ports are determined.

[0134] Step B4, based on at least one of the local connection line crossing results, determine the connection line crossing result between multiple target ports and the other ports.

[0135] In step B1, two target ports can be selected from multiple target ports as two current ports, and according to the physical location information of the two current ports, the first relative position information of the two current ports can be determined. For example, if the physical location information of current port 1 is (x1, y1) and the physical location information of current port 2 is (x1, y2), if y1 is greater than y2, it is determined that the position of current port 1 is above current port 2, that is, the first relative position information is: the position of current port 1 is higher than that of current port 2.

[0136] Meanwhile, in step B1, based on the physical location information of two other ports connected to the two current ports, the second relative position information of the two other ports can be determined. For example, the second relative position information can be: the position of other port 1 is higher than that of other port 2.

[0137] Combine Figure 2As shown, it can be known that when the target ports Y1 and Y2 are two current ports, the first relative position information of the two current ports can be: the position of the target port Y1 is higher than the position of the target port Y2. The second relative position information of the two other ports can be: the position of the other ports of the other module to be detected M1 is higher than the position of the other ports of the other module to be detected M2.

[0138] In step B2, based on the connection relationship information, the connection relationship between the two current ports and the two other ports can be determined. And according to the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports, the local wire crossing result corresponding to the two current ports can be determined.

[0139] Combined with Figure 2 As shown, the connection relationship information indicates that the target port Y1 is connected to the other ports on the other module to be detected M2, and the target port Y2 is connected to the other ports on the other module to be detected M1, that is, M2 <-> PHY / Y1, M1 <-> PHY / Y2. Therefore, according to the first relative position information: the position of the target port Y1 is higher than the position of the target port Y2, the second relative position information: the position of the other ports of the other module to be detected M1 is higher than the position of the other ports of the other module to be detected M2, and the connection relationship between the two current ports and the two other ports, the local wire crossing result corresponding to the two current ports is determined. For example, the local wire crossing result can be that there is a crossing between the target port Y1 and the target port Y2.

[0140] In step B3, after obtaining the local wire crossing result corresponding to the two current ports, two target ports can be reselected from the multiple target ports as the updated two current ports. Among them, the port pair formed by the updated two current ports is a port pair that has not been selected before. And return to step B1 until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined. For example, when the number of multiple target ports is 3, the process ends after obtaining the local wire crossing results of 3 port pairs; when the number of multiple target ports is 4, the process ends after obtaining the local wire crossing results of 6 port pairs.

[0141] In step B4, after obtaining at least one local wire crossing result, based on the at least one local wire crossing result, the wire crossing result between the multiple target ports and the other ports can be determined. For example, the at least one local wire crossing result can be determined as the wire crossing result between the multiple target ports and the other ports. Or, the at least one local wire crossing result can also be screened. For example, the local wire crossing results indicating no crossing are screened out, and the screened local wire crossing results are determined as the wire crossing result between the multiple target ports and the other ports.

[0142] In the embodiments of the present disclosure, any two of the multiple target ports can be used as the current ports, and the first relative position information of the two current ports and the second relative position information of the other ports connected to the two current ports are determined. Then, based on the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports, the local wire crossing result corresponding to the two current ports is determined more precisely. Furthermore, based on at least one local wire crossing result, the wire crossing result between the multiple target ports and the other ports can be determined. By traversing the target ports multiple times to determine the wire crossing result, the wire crossing result can be made more precise and accurate.

[0143] In another way, based on the physical position information of the multiple target ports and the physical position information of the other ports, determining the wire crossing result between the multiple target ports and the other ports may include:

[0144] Step C1, select two target ports from the multiple target ports as the two current ports, and based on the physical position information of the two current ports, determine the dividing line coordinate information corresponding to the two current ports.

[0145] Step C2, based on the physical position information of the two other ports connected to the two current ports and the dividing line coordinate information, determine the local wire crossing result corresponding to the two current ports.

[0146] Step C3, re-select two target ports from the multiple target ports as the updated two current ports, and return to the step of determining the dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined.

[0147] Step C4, based on at least one of the local wire crossing results, determine the wire crossing result between the multiple target ports and the other ports.

[0148] In the embodiments of the present disclosure, any two of the multiple target ports can be used as the current ports. By determining the dividing line coordinate information corresponding to the two current ports and using the physical position information of the two other ports connected to the two current ports and the dividing line coordinate information, the local wire crossing result corresponding to the two current ports can be determined more comprehensively and simply. Furthermore, based on at least one local wire crossing result, the wire crossing result between the multiple target ports and the other ports can be determined. By traversing the target ports multiple times to determine the wire crossing result, the wire crossing result can be made more precise and accurate.

[0149] In step C1, two target ports can be selected from multiple target ports as two current ports, and based on the physical location information of the two current ports, the dividing line coordinate information corresponding to the two current ports can be determined. For example, if the physical location information of current port 1 is (x1, y1) and the physical location information of current port 2 is (x1, y2), the dividing line coordinate information can be: Y = (Y1 + Y2) / 2.

[0150] In step C2, the physical location information of the two other ports connected to the two current ports is compared with the dividing line coordinate information to determine the local connection crossing result corresponding to the two current ports.

[0151] For example, when the position of the first current port among the two current ports is above the second current port (i.e., the ordinate value of the first current port is greater than the ordinate value of the second current port), and the first current port is connected to the first other port and the second current port is connected to the second other port, if the ordinate value in the physical location information of the first other port is greater than or equal to the dividing line coordinate information, and the ordinate value in the physical location information of the second other port is less than the dividing line coordinate information, it is determined that the local connection crossing result corresponding to the two current ports is: the connection is normal or the connection does not cross.

[0152] If the ordinate value in the physical location information of the first other port is less than the dividing line coordinate information, or the ordinate value in the physical location information of the second other port is greater than or equal to the dividing line coordinate information, it is determined that the local connection crossing result corresponding to the two current ports is: the connection is abnormal or the connection crosses.

[0153] In an alternative embodiment, in step C2, based on the physical location information of the two other ports connected to the two current ports and the dividing line coordinate information, determining the local connection crossing result corresponding to the two current ports may include:

[0154] Step C21, determining the relative position information between the physical location information of the other port connected to the first current port among the two current ports and the dividing line coordinate information; and / or determining the relative position information between the physical location information of the other port connected to the second current port among the two current ports and the dividing line coordinate information; wherein, the physical location of the first current port is above the second current port.

[0155] Step C22, based on the relative position information, determining the local connection crossing result corresponding to the two current ports.

[0156] Here, determine the relative position information between the physical position information of other ports connected to the first current port and the dividing line coordinate information; and / or, determine the relative position information between the physical position information of other ports connected to the second current port and the dividing line coordinate information; then, based on the relative position information, determine the local wire crossing result corresponding to the two current ports. For example, if the physical positions of other ports connected to the first current port are below the dividing line, and / or the physical positions of other ports connected to the second current port are above the dividing line, determine that the local wire crossing result corresponding to the two current ports is that there is a crossing. By the above method, after obtaining the target circuit, other ports connected to the first current port in the target circuit can be above the dividing line, and / or other ports connected to the second current port can be below the dividing line, the interconnection wires of the target circuit are clearer, the wire winding blockage of the target circuit is reduced, and the hardware performance of the target circuit is improved.

[0157] In step C21, among them, the position of the first current port among the two current ports is above the second current port. Determine the relative position information between the physical position information of other ports connected to the first current port and the dividing line coordinate information. And / or, determine the relative position information between the physical position information of other ports connected to the second current port and the dividing line coordinate information.

[0158] Combined Figure 2 For illustration, after obtaining the dividing line coordinate information Y corresponding to the target port Y1 and the target port Y2, according to the physical position information of other ports of other to-be-detected modules M2 connected to the first current port (target port Y1) and the dividing line coordinate information Y, the relative position information corresponding to other ports of other to-be-detected modules M2 can be determined as: M2 is lower than Y. And / or, according to the physical position information of other ports of other to-be-detected modules M1 connected to the second current port (target port Y2) and the dividing line coordinate information Y, the relative position information corresponding to other ports of other to-be-detected modules M1 can be determined as: M1 is higher than Y.

[0159] In step C22, according to the determined relative position information, determine the local wire crossing result corresponding to the two current ports. For example, if the relative position information 1 between the physical position information of other ports connected to the first current port and the dividing line coordinate information indicates that: the position of other ports is higher than the dividing line coordinate information, then determine that the local wire crossing result is: the wire connection is normal or there is no wire crossing. Otherwise, determine that the local wire crossing result is: the wire connection is abnormal or there is a wire crossing.

[0160] For another example, if the relative position information 2 between the physical location information of other ports connected to the second current port and the dividing line coordinate information indicates that the positions of the other ports are lower than the dividing line coordinate information, then it is determined that the local wire connection crossing result is: the wire connection is normal or there is no wire connection crossing. Otherwise, it is determined that the local wire connection crossing result is: the wire connection is abnormal or there is a wire connection crossing.

[0161] For another example, if the relative position information 1 between the physical location information of other ports connected to the first current port and the dividing line coordinate information indicates that the positions of the other ports are higher than the dividing line coordinate information, and the relative position information 2 between the physical location information of other ports connected to the second current port and the dividing line coordinate information indicates that the positions of the other ports are lower than the dividing line coordinate information, then it is determined that the local wire connection crossing result is: the wire connection is normal or there is no wire connection crossing. If the relative position information 1 indicates that the positions of the other ports are lower than the dividing line coordinate information, or the relative position information 2 indicates that the positions of the other ports are lower than the dividing line coordinate information, then it is determined that the local wire connection crossing result is: the wire connection is abnormal or there is a wire connection crossing.

[0162] See Figure 2 As shown, it can be seen that the other ports of other to-be-detected modules M2 connected to the target port Y1 are located below the dividing line, and the other ports of other to-be-detected modules M1 connected to the target port Y2 are located above the dividing line. Therefore, the local wire connection crossing results corresponding to the target port Y1 and the target port Y2 are: the wire connection is abnormal or there is a wire connection crossing. Here, by determining the local wire connection crossing result in the above manner, it can be ensured that the positions of the other ports connected to the target port Y1 in the obtained target circuit are located above the dividing line, and the positions of the other ports connected to the target port Y2 are located below the dividing line, reducing the crossing degree of the wire connections in the target circuit and improving the hardware performance of the target circuit.

[0163] In step C3, after obtaining the local wire connection crossing results corresponding to two current ports, two target ports can be reselected from multiple target ports as the updated two current ports. Among them, the port pair formed by the updated two current ports is a port pair that has not been selected before. And return to step C1 until the local wire connection crossing results corresponding to any two target ports among multiple target ports are determined.

[0164] Among them, the process of step C4 can refer to the above specific description of step B4, and will not be elaborated here.

[0165] Regarding S104:

[0166] During implementation, after obtaining the wire crossing result, a crossing signal report can be generated based on the wire crossing result; then, in response to the received crossing signal report, the circuit to be optimized is adjusted to obtain the target circuit. Among them, the wire crossing degree between the target port and other ports in the target circuit is less than that in the circuit to be optimized.

[0167] In an alternative implementation manner, in S104, based on the wire crossing result, adjusting the circuit to be optimized to obtain the target circuit may include:

[0168] S1041, based on the wire crossing result, determining the ports to be adjusted with crossings from multiple target ports.

[0169] S1042, adjusting the physical positions and / or connection relationships corresponding to the other ports connected to the ports to be adjusted to obtain the target circuit.

[0170] During implementation, the ports to be adjusted with corresponding wire crossings can be determined from multiple target ports according to the wire crossing result. And determine the other ports connected to the ports to be adjusted. Adjust the physical positions and / or connection relationships of the other ports connected to the ports to be adjusted to obtain the target circuit.

[0171] For example, for Figure 2 , the physical positions of the other ports of the other detection module M1 and the physical positions of the other ports of the other detection module M2 can be adjusted so that after the position adjustment, the position of the other detection module M2 is above the other detection module M1, and the target circuit is obtained after the adjustment.

[0172] When the other detection module M1 and the other detection module M2 are two instantiated modules, the functions of the other detection module M1 and the other detection module M2 are the same. Therefore, the connection relationships between the other detection module M1, the other detection module M2 and the target ports Y1, Y2 can be adjusted, that is, the other ports of the other detection module M1 are connected to the target port Y1, and the other ports of the other detection module M2 are connected to the target port Y2. The target circuit is obtained after the adjustment.

[0173] In the above implementation manner, based on the wire crossing result, the ports to be adjusted with crossings are determined from multiple target ports; the physical positions and / or connection relationships corresponding to the other ports connected to the ports to be adjusted are adjusted, and the target circuit can be obtained more accurately, and the adjustment methods are relatively flexible and diverse.

[0174] Exemplarily, the circuit optimization method can be applied to an AI chip, which may include IP cores. Generally, in an AI chip, the physical location information of the IP cores is fixed, and the IP cores are connected to multiple identical reusable modules. To avoid crossovers in the connections between the IP cores and the reusable modules, the IP cores and the reusable modules in the circuit to be optimized can be regarded as multiple modules to be detected, and the circuit to be optimized can be adjusted using the above circuit optimization method to obtain a target circuit. Among them, the IP cores can be used as the target modules to be detected, and the multiple reusable modules can be used as other modules to be detected. The specific process includes:

[0175] 1. Obtain the connection relationship information between the IP cores and the reusable modules in the circuit to be optimized, as well as the physical location information of each port in the IP cores and the reusable modules.

[0176] 2. Determine multiple target ports on the IP cores that have the same input signal.

[0177] 3. Based on the obtained connection relationship information, determine the other ports of the reusable modules connected to the multiple target ports.

[0178] 4. Based on the physical location information of the multiple target ports on the IP cores and the physical location information of the other ports on the reusable modules, determine the wiring crossover result between the multiple target ports and the other ports.

[0179] 5. Based on the wiring crossover result, adjust the circuit to be optimized to obtain a target circuit.

[0180] For example, the physical location information of the other ports can be adjusted, or the connection relationship between the target ports and the other ports can be adjusted.

[0181] See Figure 3 the schematic diagrams of a circuit to be optimized and a target circuit shown in Figure 3 wherein, on the leftmost side, the connection relationship of each module to be detected in the circuit to be optimized is exemplarily shown; in the middle, the connection relationship of each module to be detected in the target circuit is exemplarily shown; and on the rightmost side, the connection relationship of each module to be detected in another target circuit is exemplarily shown.

[0182] Figure 3 In

[0183] When implementing, a device installed with an Electronic Design Automation (EDA) tool can be used to complete the process of the above-mentioned circuit optimization method. Taking the application of this method in the chip verification scenario as an example, the circuit optimization method may include:

[0184] Step 1: Obtain the design file corresponding to the chip, and determine the connection relationship information between the various functional modules of the design circuit indicated by the design file.

[0185] Among them, the design circuit can be determined as the circuit to be optimized. The design file indicates the various functional modules included in the design circuit, the uses of each functional module, the ports included on the functional module, the interconnection relationship between the various functional modules, etc.

[0186] Step 2: Obtain the function information and physical location information of each port on each functional module; and establish a mapping check relationship between the ports of different functional modules according to the data flow information on the chip, the connection relationship information between the various modules, the function information and physical location information of each port.

[0187] Exemplarily, the mapping check relationship may include: Port M11, Port M12, Port M13 of Functional Module 1 — Port P21, Port P22, Port P23 of Functional Module 2; Port M14, Port M15, Port M16 of Functional Module 1 — Port P24, Port P25, Port P26 of Functional Module 2, and so on.

[0188] Step 3: Control the synthesis tool (such as logic synthesis DesignCompiler, fusion synthesis FusionCompiler, etc.) to read in the register-transfer level (RTL) design information of each functional module and the physical location information of the functional module.

[0189] Step 4: Determine the target module to be detected among multiple functional modules. For example, the target module to be detected can be an IP core. And based on the mapping check relationship, select two target ports with the same input signals from the target module to be detected, and determine the dividing line coordinate information corresponding to the two target ports based on the physical location information of the selected two target ports.

[0190] Step 5: Determine other modules to be detected (functional modules) connected to the selected two target ports. Use the synthesis tool command to report the connection relationship between the other modules to be detected and the target ports, and determine the connection crossing result corresponding to the two current ports based on the physical location information of the two other ports connected to the two current ports and the dividing line coordinate information.

[0191] Step 6: Traverse each target port in the target module to be detected, and repeat Step 4 and Step 5 until all target ports in the target module to be detected have been traversed.

[0192] Step 7: Generate a cross-signal report based on the wire crossing results obtained in each traversal process. In response to the receipt of the cross-signal report, adjust the design file corresponding to the chip to obtain a modified design file, and return to Step 1 until the cross-signal report indicates that there is no wire crossing between different target ports.

[0193] Based on the same concept, the present disclosure proposes a chip verification method. Refer to Figure 4 As shown, it is a schematic flowchart of the chip verification method provided by the embodiment of the present disclosure. The method includes S401-S405, where:

[0194] S401: Obtain the circuit to be verified corresponding to the chip to be verified;

[0195] S402: Perform register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result;

[0196] S403: After the first verification result indicates that the verification is passed, use the circuit optimization method described in the above embodiment to optimize the circuit to be verified to obtain the target circuit corresponding to the circuit to be verified;

[0197] S404: When it is detected that there is no wire crossing between the target port and other ports in the target circuit, perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit to obtain a second verification result;

[0198] S405: After the second verification result indicates that the verification is passed, determine that the detection result corresponding to the chip to be verified is passed for sign-off.

[0199] Generally, before the chip is taped out, the chip needs to be verified. After the verification is passed, the chip production is carried out. Therefore, the chip to be verified here can be any chip that needs to be verified. For example, the chip to be verified can be an AI chip, etc. Obtain the circuit to be verified corresponding to the chip to be verified. The circuit to be verified can be a designed circuit obtained after designing the chip to be verified according to the requirements of the chip to be verified.

[0200] The to-be-verified circuit can be first verified through RTL implementation verification and / or functional verification to obtain a first verification result. When including RTL implementation verification and functional verification, the to-be-verified circuit can be first verified through RTL implementation verification to obtain a first intermediate verification result; after the first intermediate verification result indicates verification passed, the to-be-verified circuit is verified through functional verification to obtain a first verification result. If the first intermediate verification result indicates verification failed, a first verification report can be generated, and in response to the generation of the first verification report, the to-be-verified circuit corresponding to the to-be-verified chip is modified to obtain a modified to-be-verified circuit, and then return to execute step S402.

[0201] After the first verification result indicates verification passed, the circuit optimization method described in the above embodiments can be used to optimize the to-be-verified circuit to obtain a target circuit corresponding to the to-be-verified circuit. Among them, if there is no cross between the connections of ports in the to-be-verified circuit, the target circuit is the same as the to-be-verified circuit. If the first verification result indicates verification failed, a second verification report can be generated, and in response to the generation of the second verification report, the to-be-verified circuit corresponding to the to-be-verified chip is modified to obtain a modified to-be-verified circuit, and then return to execute step S402.

[0202] Detect whether there is a cross between the target port and other ports in the target circuit. If it is detected that there is a cross between the connections of the target port and other ports in the target circuit, the target circuit is used as the updated to-be-verified circuit, and return to the step of performing register transfer level (RTL) implementation verification and / or functional verification on the to-be-verified circuit until there is no cross between the connections of the target port and other ports in the target circuit.

[0203] If it is detected that there is no cross between the connections of the target port and other ports in the target circuit, at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification is performed on the target circuit to obtain a second verification result.

[0204] If the verification process includes logic implementation verification, physical implementation verification, high-performance verification, and routing verification, the target circuit can be first verified through logic implementation verification and physical implementation verification to obtain a second intermediate verification result.

[0205] After the second intermediate verification result indicates verification passed, high-performance verification and routing verification are performed on the target circuit to obtain a second verification result. And after the second verification result indicates verification passed, it is determined that the detection result corresponding to the to-be-verified chip is passed for sign-off. If the second intermediate verification result indicates verification failed, a third verification report can be generated, and in response to the generation of the third verification report, the to-be-verified circuit corresponding to the to-be-verified chip is modified to obtain a modified to-be-verified circuit, and then return to execute step S402.

[0206] If the second verification result indicates that the verification fails, a fourth verification report can be generated. In response to the generation of the fourth verification report, the circuit to be verified corresponding to the chip to be verified is modified to obtain a modified circuit to be verified, and step S402 is executed again.

[0207] Generally, in the chip implementation process, after obtaining the design file of the chip, chip implementers can perform processing such as logic synthesis and physical synthesis on the design file. After the above processing, the wire congestion result of the chip design can be obtained, and the wire connection of the chip can be modified according to the wire congestion result. However, the above method makes the modification of the wire connection of the chip relatively complex and cumbersome, and the efficiency is low.

[0208] In the embodiments of the present disclosure, after performing RTL implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result, if the first verification result indicates that the verification is passed, the circuit optimization method described in the above embodiments is used to optimize the circuit to be verified to obtain a target circuit corresponding to the circuit to be verified, so that the wire crossing degree of the target circuit is lower than that of the circuit to be verified, and the connection line modification is relatively simple and the efficiency is high. And when it is detected that there is no crossing in the connection line between the target port and other ports in the target circuit, at least one of logic implementation verification, physical implementation verification, high-performance verification, and wire verification is performed on the target circuit to obtain a second verification result. After the second verification result indicates that the verification is passed, it is determined that the detection result corresponding to the chip to be verified is passed for signature, which improves the verification efficiency of the chip.

[0209] Here, the interconnection lines of the functional modules in the chip design are combined with the module physical location information, and this method is used to guide the connection and implementation of the interconnection lines in the chip design, reducing the iteration cycle and wire congestion degree of the chip design implementation, and improving the high-performance area (power performance area, PPA) and turn-around time (TAT) of the chip design.

[0210] Those skilled in the art can understand that in the above method of the specific embodiment, the writing order of each step does not mean a strict execution order and does not constitute any limitation to the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0211] Based on the same concept, the embodiments of the present disclosure also provide a circuit optimization device. Refer to Figure 5 As shown, it is a schematic architecture diagram of the circuit optimization device provided by the embodiments of the present disclosure, including a first acquisition module 501, a first determination module 502, a second determination module 503, and an adjustment module 504. Specifically:

[0212] The first acquisition module 501 is configured to acquire the connection relationship information between multiple modules to be detected in the circuit to be optimized, and the physical location information of each port in the module to be detected;

[0213] The first determination module 502 is configured to, after determining multiple target ports with the same input signal on a target module to be detected among the multiple modules to be detected, determine other ports of other modules to be detected connected to the multiple target ports based on the connection relationship information;

[0214] The second determination module 503 is configured to determine the wire crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports;

[0215] The adjustment module 504 is configured to adjust the circuit to be optimized based on the wire crossing result to obtain a target circuit.

[0216] In a possible implementation manner, when the second determination module 503 determines the wire crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports, it is configured to:

[0217] For each target port, determine the connection line information corresponding to the target port based on the physical location information of the target port and the physical location information of the other port connected to the target port;

[0218] Based on the connection line information respectively corresponding to the multiple target ports, determine the wire crossing result between the multiple target ports and the other ports.

[0219] In a possible implementation manner, when the second determination module 503 determines the wire crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports, it is configured to:

[0220] Select two target ports from the multiple target ports as two current ports, and determine the first relative position information of the two current ports based on the physical location information of the two current ports; and

[0221] Based on the physical location information of two other ports connected to the two current ports, determine the second relative position information of the two other ports;

[0222] Determine the local wire crossing result corresponding to the two current ports based on the connection relationship between the two current ports and the two other ports indicated by the first relative position information, the second relative position information, and the connection relationship information;

[0223] Re-select two target ports from the multiple target ports as the updated two current ports, and return to the step of determining the first relative position information of the two current ports based on the physical position information of the two current ports, until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined;

[0224] Determine the wire crossing result between the multiple target ports and the other ports based on at least one of the local wire crossing results.

[0225] In a possible implementation manner, when determining the wire crossing result between the multiple target ports and the other ports based on the physical position information of the multiple target ports and the physical position information of the other ports, the second determination module 503 is configured to:

[0226] Select two target ports from the multiple target ports as two current ports, and determine the dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports;

[0227] Determine the local wire crossing result corresponding to the two current ports based on the physical position information of the two other ports connected to the two current ports and the dividing line coordinate information;

[0228] Re-select two target ports from the multiple target ports as the updated two current ports, and return to the step of determining the dividing line coordinate information corresponding to the two current ports based on the physical position information of the two current ports, until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined;

[0229] Determine the wire crossing result between the multiple target ports and the other ports based on at least one of the local wire crossing results.

[0230] In a possible implementation manner, when determining the local wire crossing result corresponding to the two current ports based on the physical position information of the two other ports connected to the two current ports and the dividing line coordinate information, the second determination module 503 is configured to:

[0231] Determine the physical location information of other ports connected to the first current port among the two current ports, and the relative position information between the physical location information and the dividing line coordinate information; and / or, determine the physical location information of other ports connected to the second current port among the two current ports, and the relative position information between the physical location information and the dividing line coordinate information; wherein, the physical location of the first current port is above the physical location of the second current port.

[0232] Based on the relative position information, determine the local wire crossing result corresponding to the two current ports.

[0233] In a possible implementation manner, when the adjustment module 504 adjusts the circuit to be optimized based on the wire crossing result to obtain a target circuit, it is configured to:

[0234] Based on the wire crossing result, determine the ports to be adjusted with crossings among the multiple target ports.

[0235] Adjust the physical location and / or connection relationship corresponding to other ports connected to the ports to be adjusted to obtain a target circuit.

[0236] Based on the same concept, an embodiment of the present disclosure further provides a chip verification device. Refer to Figure 6 As shown, it is a schematic architecture diagram of the chip verification device provided by the embodiment of the present disclosure, including a second acquisition module 601, a first verification module 602, an optimization module 603, a second verification module 604, and a third determination module 605. Specifically:

[0237] The second acquisition module 601 is configured to acquire a circuit to be verified corresponding to the chip to be verified.

[0238] The first verification module 602 is configured to perform register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result.

[0239] The optimization module 603 is configured to, after the first verification result indicates that the verification is passed, use the circuit optimization method described in the above implementation manner to optimize the circuit to be verified to obtain a target circuit corresponding to the circuit to be verified.

[0240] The second verification module 604 is configured to perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit when it is detected that there is no crossing between the target port and other ports in the target circuit, to obtain a second verification result.

[0241] The third determination module 605 is configured to determine that the detection result corresponding to the chip to be verified is passed for sign-off after the second verification result indicates that the verification is passed.

[0242] In a possible implementation manner, the second verification module 604 is further configured to:

[0243] When it is detected that there is a cross in the connection line between the target port and other ports in the target circuit, the target circuit is used as the updated circuit to be verified, and returned to the step of performing register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified until there is no cross in the connection line between the target port and other ports in the target circuit.

[0244] In some embodiments, the functions or templates included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0245] The embodiments of the present disclosure further provide a chip, and the circuit included in the chip is adjusted by using any of the circuit optimization methods in the embodiments of the present disclosure; or, the chip is verified by using any of the chip verification methods in the embodiments of the present disclosure.

[0246] Based on the same inventive concept, the embodiments of the present disclosure further provide an electronic device. Referring to Figure 7 As shown, it is a schematic structural diagram of the electronic device provided by the embodiments of the present disclosure, including a processor 701, a memory 702, and a bus 703. Among them, the memory 702 is used to store execution instructions, including an internal memory 7021 and an external memory 7022; the internal memory 7021 here is also called the main memory, which is used to temporarily store the operation data in the processor 701 and the data exchanged with the external memory 7022 such as a hard disk. The processor 701 exchanges data with the external memory 7022 through the internal memory 7021. When the electronic device 700 runs, the processor 701 communicates with the memory 702 through the bus 703, so that the processor 701 executes the following instructions:

[0247] Obtain the connection relationship information between multiple modules to be detected in the circuit to be optimized, and the physical location information of each port in the module to be detected;

[0248] After determining multiple target ports with the same input signal on the target module to be detected among the multiple modules to be detected, based on the connection relationship information, determine other ports of other modules to be detected connected to the multiple target ports;

[0249] Based on the physical location information of the multiple target ports and the physical location information of the other ports, determine the connection cross result between the multiple target ports and the other ports;

[0250] Based on the connection cross result, adjust the circuit to be optimized to obtain a target circuit.

[0251] Or the processor 701 executes the following instructions:

[0252] Obtain the circuit to be tested corresponding to the chip to be tested;

[0253] Perform register transfer level (RTL) implementation verification and / or functional verification on the circuit to be tested to obtain a first verification result;

[0254] After the first verification result indicates that the verification is passed, use the circuit optimization method according to any one of claims 1 to 6 to optimize the circuit to be tested to obtain the target circuit corresponding to the circuit to be tested;

[0255] When it is detected that there is no crossing in the connection between the target port and other ports in the target circuit, perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit to obtain a second verification result;

[0256] After the second verification result indicates that the verification is passed, determine that the detection result corresponding to the chip to be tested is passed for signature.

[0257] Wherein, the specific processing flow of the processor 701 may refer to the description in the above method embodiment and will not be elaborated here.

[0258] The electronic device provided by the embodiment of the present disclosure may include the chip provided by the above embodiment of the present disclosure.

[0259] In addition, the embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the circuit optimization method or the chip verification method described in the above method embodiment. Wherein, the storage medium may be a volatile or non-volatile computer-readable storage medium.

[0260] The embodiment of the present disclosure further provides a computer program product, which carries program codes. The instructions included in the program codes can be used to execute the steps of the circuit optimization method or the chip verification method described in the above method embodiment. Specifically, refer to the above method embodiment and will not be elaborated here.

[0261] Wherein, the above computer program product can be specifically implemented by means of hardware, software, or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0262] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein. In several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces. The indirect coupling or communication connection of the devices or units can be in electrical, mechanical, or other forms.

[0263] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0264] In addition, in each embodiment of the present disclosure, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0265] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art or part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present disclosure. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0266] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A circuit optimization method, characterized in that, Including: Obtaining connection relationship information between multiple modules to be detected in the circuit to be optimized, and physical location information of each port in the module to be detected; After determining multiple target ports with the same input signal on the target module to be detected among the multiple modules to be detected, based on the connection relationship information, determining other ports of other modules to be detected connected to the multiple target ports; Based on the physical location information of the multiple target ports and the physical location information of the other ports, determining a connection line crossing result between the multiple target ports and the other ports; Based on the connection line crossing result, adjusting the circuit to be optimized to obtain a target circuit; The adjusting the circuit to be optimized based on the connection line crossing result to obtain a target circuit includes: based on the connection line crossing result, determining ports to be adjusted with crossings among the multiple target ports; Adjusting the physical location and / or connection relationship corresponding to the other ports connected to the ports to be adjusted to obtain a target circuit.

2. The method according to claim 1, wherein The determining the connection line crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports includes: For each target port, based on the physical location information of the target port and the physical location information of the other ports connected to the target port, determining connection line information corresponding to the target port; Based on the connection line information respectively corresponding to the multiple target ports, determining the connection line crossing result between the multiple target ports and the other ports.

3. The method according to claim 1, characterized in that The determining the connection line crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports includes: Selecting two target ports from the multiple target ports as two current ports, and based on the physical location information of the two current ports, determining first relative position information of the two current ports; and Based on the physical location information of two other ports connected to the two current ports, determining second relative position information of the two other ports; Based on the first relative position information, the second relative position information, and the connection relationship between the two current ports and the two other ports indicated by the connection relationship information, determining a local connection line crossing result corresponding to the two current ports; Selecting two target ports from the multiple target ports again as the updated two current ports, and returning to the step of determining the first relative position information of the two current ports based on the physical location information of the two current ports until the local connection line crossing results corresponding to any two target ports among the multiple target ports are determined; Based on at least one of the local connection line crossing results, determining the connection line crossing result between the multiple target ports and the other ports.

4. The method according to claim 1, wherein The determining the connection line crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports includes: Select two target ports from the multiple target ports as two current ports, and determine the dividing line coordinate information corresponding to the two current ports based on the physical location information of the two current ports; Determine the local wire crossing result corresponding to the two current ports based on the physical location information of two other ports connected to the two current ports and the dividing line coordinate information; Re-select two target ports from the multiple target ports as the updated two current ports, and return to the step of determining the dividing line coordinate information corresponding to the two current ports based on the physical location information of the two current ports until the local wire crossing results corresponding to any two target ports among the multiple target ports are determined; Determine the wire crossing result between the multiple target ports and the other ports based on at least one of the local wire crossing results.

5. The method according to claim 4, characterized in that, The determining the local wire crossing result corresponding to the two current ports based on the physical location information of two other ports connected to the two current ports and the dividing line coordinate information includes: Determine the relative position information between the physical location information of the other port connected to the first current port among the two current ports and the dividing line coordinate information; and / or, determine the relative position information between the physical location information of the other port connected to the second current port among the two current ports and the dividing line coordinate information; wherein, the physical location of the first current port is above the second current port; Determine the local wire crossing result corresponding to the two current ports based on the relative position information.

6. A chip verification method, characterized in that including: Obtain the circuit to be verified corresponding to the chip to be verified; Perform register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified to obtain a first verification result; After the first verification result indicates that the verification is passed, use any one of the circuit optimization methods of claims 1 to 5 to optimize the circuit to be verified to obtain the target circuit corresponding to the circuit to be verified; When it is detected that there is no crossing in the wires between the target ports and other ports in the target circuit, perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit to obtain a second verification result; After the second verification result indicates that the verification is passed, determine that the detection result corresponding to the chip to be verified is passed for sign-off.

7. The method according to claim 6, characterized in that The method further includes: When it is detected that there is a crossing in the wires between the target ports and other ports in the target circuit, use the target circuit as the updated circuit to be verified, and return to the step of performing register transfer level (RTL) implementation verification and / or functional verification on the circuit to be verified until there is no crossing in the wires between the target ports and other ports in the target circuit.

8. A circuit optimization device, characterized in that, including: A first acquisition module, configured to acquire the connection relationship information between multiple modules to be detected in the circuit to be optimized, and the physical location information of each port in the module to be detected; A first determination module, configured to, after determining multiple target ports on a target to-be-detected module among the multiple to-be-detected modules that have the same input signal, determine other ports of other to-be-detected modules connected to the multiple target ports based on the connection relationship information; A second determination module, configured to determine a wire crossing result between the multiple target ports and the other ports based on the physical location information of the multiple target ports and the physical location information of the other ports; An adjustment module, configured to adjust the to-be-optimized circuit based on the wire crossing result to obtain a target circuit; When adjusting the to-be-optimized circuit based on the wire crossing result to obtain a target circuit, the adjustment module is configured to: determine to-be-adjusted ports with crossings from the multiple target ports based on the wire crossing result; and adjust the physical location and / or connection relationship corresponding to the other ports connected to the to-be-adjusted ports to obtain a target circuit.

9. A chip verification device, characterized in that, Comprising: A second acquisition module, configured to acquire a to-be-verified circuit corresponding to a to-be-verified chip; A first verification module, configured to perform register transfer level (RTL) implementation verification and / or functional verification on the to-be-verified circuit to obtain a first verification result; An optimization module, configured to, after the first verification result indicates verification passed, optimize the to-be-verified circuit by using the circuit optimization method according to any one of claims 1 to 5 to obtain a target circuit corresponding to the to-be-verified circuit; A second verification module, configured to, when it is detected that there is no crossing between the target ports and other ports in the target circuit, perform at least one of logic implementation verification, physical implementation verification, high-performance verification, and routing verification on the target circuit to obtain a second verification result; A third determination module, configured to, after the second verification result indicates verification passed, determine that the detection result corresponding to the to-be-verified chip is passed for signing.

10. A chip, characterized in that, Comprising: The circuit included in the chip is obtained by adjustment using the method according to any one of claims 1 to 5; or the chip is obtained by verification using the method according to any one of claims 6 to 7.

11. An electronic device, characterized in that, Comprising: A processor, a memory, and a bus, where the memory stores machine-readable instructions executable by the processor. When the electronic device runs, the processor communicates with the memory through the bus. When the machine-readable instructions are executed by the processor, the steps of the circuit optimization method according to any one of claims 1 to 5 are executed; or the steps of the chip verification method according to claim 6 or 7 are executed; or the circuit according to claim 10 is included.

12. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium. When the computer program is run by the processor, the steps of the circuit optimization method according to any one of claims 1 to 5 are executed; or the steps of the chip verification method according to claim 6 or 7 are executed.

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