Display substrate motherboard and preparation method thereof, display substrate and display device

Abstract

The embodiments of the present disclosure provide a display substrate motherboard and a preparation method thereof, a display substrate and a display device, wherein the display substrate motherboard comprises: a base substrate, a display substrate region located on the base substrate and a marking region located around the display substrate region; the display substrate motherboard further comprises: a thin film transistor arranged in the display substrate region, a marking structure arranged in the marking region and a planarization layer arranged on a side of the thin film transistor away from the base substrate; wherein the planarization layer comprises: a groove arranged at a position corresponding to the marking structure and extending in a direction close to the base substrate, the orthographic projection of the groove on the base substrate covers the orthographic projection of the marking structure on the base substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate motherboard and a method for preparing the same, a display substrate, and a display device. Background Art

[0002] Fully reflective display devices and semi-transmissive and semi-reflective display devices are attracting more and more attention. Such products are widely used in outdoor displays such as electronic price tags, billboards, and watches.

[0003] In order to meet the high reflectivity requirements of such products, metals with extremely high reflectivity are added as reflective layers in such products. For example, Ag (silver) metal is used as a reflective layer. However, in the substrate manufacturing process of such products, when the reflective layer Mask process is carried out, the reflective layer has an extremely high reflectivity, which will cause the designed Mark to be unrecognizable. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a display substrate motherboard and a method for preparing the same, a display substrate and a display device, which can effectively solve the problem that a mark cannot be recognized due to the extremely high reflectivity of a reflective layer.

[0006] The embodiments of the present disclosure mainly provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present disclosure provides a display substrate motherboard, which includes: a base substrate, a display substrate region located on the base substrate, and a marking region located around the display substrate region; the display substrate motherboard also includes: a thin film transistor arranged in the display substrate region, a marking structure arranged in the marking region, and a planarization layer arranged on a side of the thin film transistor away from the base substrate; wherein the planarization layer includes: a groove arranged at a position corresponding to the marking structure and extending in a direction close to the base substrate, the orthographic projection of the groove on the base substrate covers the orthographic projection of the marking structure on the base substrate.

[0008] In a second aspect, an embodiment of the present disclosure provides a display substrate, which is formed by cutting the above-mentioned display substrate motherboard along the marking area to obtain the display substrate area.

[0009] In a third aspect, an embodiment of the present disclosure provides a display device, comprising the above-mentioned display substrate.

[0010] In a fourth aspect, an embodiment of the present disclosure provides a method for preparing a display substrate motherboard, wherein the display substrate motherboard comprises: a base substrate, a display substrate region located on the base substrate, and a marking region located around the display substrate region; the preparation method comprises: forming a thin film transistor in the display substrate region, and forming a marking structure in the marking region; forming a planarization layer covering the thin film transistor and the marking region; and forming a groove in the planarization layer, which is arranged at a position corresponding to the marking structure and extends in a direction close to the base substrate.

[0011] The display substrate motherboard and its preparation method, display substrate and display device provided by the embodiment of the present disclosure may include: a substrate substrate, a display substrate area located on the substrate substrate and a marking area located around the display substrate area; the display substrate motherboard may also include: a thin film transistor arranged in the display substrate area, a marking structure arranged in the marking area and a planarization layer arranged on the side of the thin film transistor away from the substrate substrate; wherein the planarization layer includes: a groove arranged at a corresponding position of the marking structure and extending in a direction close to the substrate substrate, and the positive projection of the groove on the substrate substrate covers the positive projection of the marking structure on the substrate substrate. In this way, by arranging the groove extending in a direction close to the substrate substrate in the planarization layer, the light between the marking structure and the lens of the device for identifying the mark is refracted and absorbed less, and the reflectivity difference between the marking area and the surrounding display substrate area can be increased (that is, the difference in reflection or light transmission between the marking area and the surrounding display substrate area is large), thereby improving the clarity of the marking structure, and further improving the recognition success rate of the marking structure.

[0012] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the content of the present invention.

[0014] Figure 1A A schematic diagram of a marking area in a display substrate motherboard in some technologies;

[0015] Figure 1B for Figure 1AThe SEM (Scanning Electron Microscope) image of the marking area in the display substrate motherboard shown;

[0016] Figure 1C for Figure 1A A schematic diagram of a recognition result of a marking structure in a display substrate motherboard is shown;

[0017] Figure 1D for Figure 1A Another schematic diagram of recognition results of the marking structure in the display substrate motherboard is shown;

[0018] Figure 1E for Figure 1A A schematic diagram showing another recognition result of a marking structure in a display substrate motherboard is shown;

[0019] Figure 2 A schematic diagram of a region of a display substrate motherboard in an embodiment of the present disclosure;

[0020] Figure 3A A schematic diagram of a marking area in an embodiment of the present disclosure in a plane parallel to a display substrate motherboard;

[0021] Figure 3B Another schematic diagram of the marking area in the embodiment of the present disclosure in a plane parallel to the display substrate motherboard;

[0022] Figure 3C It is another schematic diagram of the marking area in the embodiment of the present disclosure in a plane parallel to the display substrate motherboard;

[0023] Figure 4A A schematic diagram of a marking area in an embodiment of the present disclosure in a plane perpendicular to a display substrate motherboard;

[0024] Figure 4B Another schematic diagram of the marking area in the embodiment of the present disclosure in a plane perpendicular to the display substrate motherboard;

[0025] Figure 4C is another schematic diagram of the marking area in the embodiment of the present disclosure in a plane perpendicular to the display substrate motherboard;

[0026] Figure 4D It is another schematic diagram of the marking area in the embodiment of the present disclosure in a plane perpendicular to the display substrate motherboard;

[0027] Figure 5A For example, in the embodiment of the present disclosure Figure 3A A SEM image of the marked area shown;

[0028] Figure 5B For example, in the embodiment of the present disclosure Figure 3A Another SEM image of the marked area shown;

[0029] Fig. 6A A schematic diagram of a recognition result of a marking structure in an embodiment of the present disclosure;

[0030] Figure 6B is another schematic diagram of recognition results of the marking structure in the embodiment of the present disclosure;

[0031] Figure 6C It is another schematic diagram of recognition results of the marking structure in the embodiment of the present disclosure.

[0032] Description of reference numerals:

[0033] 10- marking structure; 11- planarization layer; 12- reflection layer;

[0034] 13-photoresist layer; 14-interlayer insulating layer; 15-gate insulating layer;

[0035] 21-substrate substrate; 22-display substrate area; 23-marking area;

[0036] 24-substrate group area; 31-groove; 41-first sub-mark;

[0037] 42-second sub-tag; 43-third sub-tag. DETAILED DESCRIPTION

[0038] Multiple embodiments are described herein, but the description is exemplary rather than restrictive, and there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0039] When describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of steps herein, the method or process should not be limited to the steps of the specific order. As will be appreciated by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0040] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present invention is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present invention is not limited to the shapes or values ​​shown in the drawings.

[0041] The ordinal numbers such as "first", "second", and "third" in this article are set to avoid confusion among constituent elements rather than to limit the quantity.

[0042] In this document, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this document and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present invention. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0043] In this article, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, a drain region, or a drain electrode) and a source electrode (source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this article, the channel region refers to the region where the current mainly flows. In the case of using transistors with opposite polarities or the case where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this article, the "source electrode" and the "drain electrode" can be interchanged.

[0044] In this article, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes the state where the angle is greater than 85° and less than 95°.

[0045] The inventors of the present disclosure have found that in the substrate manufacturing process, in the identification, testing and monitoring of the mark, the equipment used to identify the mark (for example, an exposure machine) usually adopts a multi-directional light supply mode of the front, side and back, and identifies and captures the difference in reflected light between the mark position and the non-mark position through the lens of the equipment. However, for a fully reflective display device and a semi-transmissive and semi-reflective display device, for example, Figure 1A As shown, when the reflective layer Mask process is performed, the film layer covering directly above the mark structure 10 includes at least a planarization layer (PLN) 11, a reflective layer (for example, an Ag layer) 12, and a photoresist (PR) glue layer 13 (for example, taking the mark structure 10 including: a mark A arranged in the same layer as the source and drain metal layer in the thin film transistor, a mark B arranged in the same layer as the gate electrode in the thin film transistor, and a mark C arranged in the same layer as the active layer in the thin film transistor as an example, above the mark A may include a planarization layer 11, a reflective layer 12 and a photoresist layer 13, above the mark B may include: an interlayer insulating layer (ILD, Inter Layer Dielectric) 14, a planarization layer 11, a reflective layer 12 and a photoresist layer 13, and above the mark C may include: a gate insulating layer (GI, Gate Insulator), an ILD layer 14, a planarization layer 11, a reflective layer 12 and a photoresist layer 13). Since PLN has a flat effect on the Mark, and the reflective layer (for example, Ag) is arranged on the PLN film layer, there is basically no step difference between the area of ​​the reflective layer at the corresponding position of the mark structure and the adjacent area (for example, Figure 1B As shown, the thickness h1 of the Mark (i.e., the marking structure 10) can be approximately 0.58 μm (micrometer), the thickness h2 of the portion of the planarization layer 11 located in the non-Mark area can be approximately 2.78 μm, and the thickness h3 of the portion of the planarization layer 11 located in the Mark area covering the Mark can be approximately 2.3 μm, then, the height difference h4 between the Mark area and the adjacent non-Mark area can be approximately 0.01 μm), and the reflectivity of the reflective layer is extremely high, resulting in a small grayscale difference (i.e., low contrast) at the edge of the Mark and the adjacent non-Mark area (i.e., the display substrate area used to form the display substrate). Thus, as Figure 1C to Figure 1E As shown, the reflectivity or transmittance between the Mark region and the adjacent non-Mark region is substantially the same, so that the edge of the mark structure 10 is unclear, resulting in the mark being unable to be effectively identified. In this article, thickness refers to a feature in a direction away from the substrate.

[0046] An embodiment of the present disclosure provides a display substrate motherboard, which may include: a base substrate, a display substrate region located on the base substrate, and a marking region located around the display substrate region; the display substrate motherboard may also include: a thin film transistor arranged in the display substrate region, a marking structure arranged in the marking region, and a planarization layer arranged on a side of the thin film transistor away from the base substrate; wherein the planarization layer includes: a groove arranged at a position corresponding to the marking structure and extending in a direction close to the base substrate, the orthographic projection of the groove on the base substrate covers the orthographic projection of the marking structure on the base substrate. In this way, by setting a groove at the position corresponding to the mark structure in the planarization layer, the area where the groove is located in the planarization layer (i.e., the area at the corresponding position of the mark structure in the planarization layer) can be made lower than the area in the planarization layer adjacent to the area where the groove is located (i.e., the area in the planarization layer adjacent to the area at the corresponding position of the mark structure), so that a larger step difference is formed between the two areas. As a result, the light between the mark structure and the lens of the device for identifying the mark can be refracted and absorbed less, and the reflectivity difference between the corresponding area of ​​the mark structure and the surrounding area can be increased (i.e., the difference in reflection or transmittance between the corresponding area of ​​the mark structure and the surrounding area is large), thereby improving the clarity of the mark structure, improving the recognition success rate of the mark structure, and greatly reducing the defective rate caused by the inability to identify the mark in the substrate manufacturing process.

[0047] In an exemplary embodiment, the specific type of the marking structure is not particularly limited. For example, depending on the function, the marking structure may include but is not limited to: a first alignment mark (Plate alignment mark) for alignment calibration during exposure alignment, a positioning mark (Glass Center Mark) for determining the center position of a substrate (such as a glass substrate) during testing, a second alignment mark (OL Mark) for testing the actual alignment accuracy during Mask process control, and a cutting mark for cutting a display substrate (Single Panel) from a display substrate master. One or more of the above.

[0048] In an exemplary embodiment, the display substrate motherboard may further include: a reflective layer, which is arranged on a side of the planarization layer away from the base substrate; wherein, in the direction away from the base substrate, the first area of ​​the reflective layer covering the groove is lower than the second area of ​​the reflective layer adjacent to the first area, and there is a step difference greater than a preset threshold between the first area and the second area. Here, since part of the film layer in the planarization layer located in the marking area is removed (i.e., a groove is opened in the planarization layer), then, after the entire reflective layer is formed, the first area of ​​the reflective layer covering the groove is lower than the second area of ​​the reflective layer adjacent to the first area, and there is a step difference greater than a preset threshold between the first area and the second area, so that the light between the marking structure and the lens of the device for identifying the mark is refracted and absorbed less, and the reflectivity difference between the groove in the marking area and the marking structure and the surrounding display substrate area is large (i.e., the reflection or light transmission difference between the marking area and the surrounding display substrate area is large), so that the edge of the marking area is clear (for example, the edge of the groove). Thereby, the clarity of the marking structure is improved, and then, the recognition success rate of the marking structure is improved.

[0049] Figure 2 FIG. 1 is a schematic diagram of a region of a display substrate motherboard in an embodiment of the present disclosure. Figure 2 As shown, in a plane direction parallel to the display substrate motherboard, the display substrate motherboard may include: a base substrate 21, a plurality of display substrate regions 22 located on the base substrate 21 for forming a plurality of display substrates, and a marking region 23 located around the display substrate region 22, wherein a plurality of marking structures 10 are arranged in the marking region 23. Here, Figure 2 50 display substrate regions 22 and 52 marking structures 10 are shown in FIG. 1 , but the number of display substrate regions 22 and marking structures 10 included in the display substrate motherboard is not limited thereto. Here, one display substrate region may correspond to forming one display substrate (Single Panel).

[0050] For example, the display substrate motherboard may be an array substrate motherboard or a color filter substrate motherboard.

[0051] For example, still Figure 2 As shown, in order to facilitate the Mask process, according to the size of the Mask used in the Mask process, the display substrate motherboard can be divided into multiple substrate group areas (Q-Panel), where: Figure 2 6 substrate group areas 24 are shown in FIG. 1 , but the number of substrate group areas 24 included in the display substrate motherboard and the number of display substrate areas 22 included in the substrate group area 24 are not limited thereto. For example, the display substrate motherboard can be divided into 4 substrate group areas. For example, the first alignment mark (Plate alignment mark) and the second alignment mark (OL Mark) ( Figure 2 The two Marks (indicated as a cross mark in the figure) are distributed in the gaps between adjacent display substrates (Single Panel) and are set at the left, middle and right positions of each Q-Panel, for a total of 48. Of course, these two Marks can be reasonably increased or decreased according to the distribution of the display substrate on the base substrate (such as a glass substrate). The average distribution of these two Marks on the base substrate (such as a glass substrate) facilitates the exposure correction and alignment accuracy test control of each position on the base substrate (such as a glass substrate) during the exposure alignment process and the test process in the actual process. For example, the positioning mark (Glass Center Mark) ( Figure 2 The four corners of the substrate (such as a glass substrate) can be set only at the four corners of the substrate (such as a glass substrate), with a total of four. The coordinates are completely symmetrical relative to the center of the substrate (such as a glass substrate), so that the center position of the substrate (such as a glass substrate) can be accurately found in actual testing.

[0052] In an exemplary embodiment, the base substrate may be a glass substrate, or a flexible transparent substrate attached to a glass substrate, and this is not limited in the embodiments of the present disclosure.

[0053] In an exemplary embodiment, the material of the reflective layer may be silver (Ag). Of course, the embodiments of the present disclosure include but are not limited to this. For example, the material of the reflective layer may also be other materials with higher reflectivity.

[0054] In an exemplary embodiment, the material of the planarization layer may be a resin material. For example, the material of the planarization layer may be an epoxy resin. Of course, the embodiments of the present disclosure include but are not limited to this. For example, the material of the planarization layer may also be other materials such as silicon nitride (SiNx).

[0055] In addition, in addition to the above-mentioned base substrate, thin film transistor, marking structure, planarization layer and reflective layer, the display substrate motherboard may also include other necessary components and structures. Those skilled in the art can design and supplement them accordingly according to the type of the display substrate motherboard, which will not be repeated here.

[0056] In an exemplary embodiment, the groove in the planarization layer, which is arranged at a position corresponding to the mark structure and extends in a direction close to the substrate, can be: a groove that penetrates the planarization layer or a groove that does not penetrate the planarization layer. When the planarization layer is provided with a groove that penetrates the planarization layer, the mark structure can be arranged in the groove; when the groove does not penetrate the planarization layer, the groove is arranged on a side of the mark structure away from the substrate, and the area where the groove in the planarization layer is located can completely cover the mark structure.

[0057] In an exemplary embodiment, the orthographic projection of the groove on the substrate covers the orthographic projection of the marking structure on the substrate. FIG. 3A to FIG. 3C As shown, the orthographic projection of the marking structure 10 on the substrate 21 can be accommodated within the orthographic projection of the groove 31 on the substrate 21 (that is, the orthographic projection of the marking structure 10 on the substrate 21 is smaller than the orthographic projection of the groove 31 on the substrate, and the edge of the orthographic projection of the marking structure 10 on the substrate 21 does not intersect with the edge of the orthographic projection of the groove 31 on the substrate).

[0058] In an exemplary embodiment, the center of the orthographic projection of the groove on the substrate coincides with the center of the orthographic projection of the marking structure on the substrate (ie, FIG. 3A to FIG. 3C As shown, in a plane parallel to the display substrate motherboard, the groove 31 coincides with the center of the marking structure 10 and is centrally symmetrical).

[0059] In an exemplary embodiment, in a plane parallel to the substrate, the cross-sectional shape of the groove is a rectangle or a square.

[0060] In an exemplary embodiment, FIG. 3A to FIG. 3C As shown, a distance d between an edge of an orthographic projection of the groove on the substrate and an edge of an orthographic projection of the mark structure on the substrate may be 20 μm to 300 μm.

[0061] In an exemplary embodiment, the marking structure may be a rectangular structure, a cross-shaped structure, or one or more of the above. Figure 3A As shown, the marking structure 10 may be a square structure. Figure 3B As shown, the marking structure 10 may be a solid cross-shaped structure. Figure 3C As shown, the marking structure 10 may be a hollow cross-shaped structure.

[0062] In an exemplary embodiment, the marking structure may be disposed in the same layer as at least one of the source-drain metal layer, the gate electrode, and the active layer in the thin film transistor. For example, the marking structure may be disposed in the same layer as the source-drain metal layer in the thin film transistor. For example, the marking structure may be disposed in the same layer as the gate electrode in the thin film transistor. Alternatively, the marking structure may be disposed in the same layer as the active layer in the thin film transistor. Of course, the embodiments of the present disclosure include but are not limited to this.

[0063] In an exemplary embodiment, the marking structure may be a stacked structure, and the stacked structure may include: a first sub-mark that is stacked in the same layer as the active layer of the thin film transistor, a second sub-mark that is stacked in the same layer as the gate electrode of the thin film transistor, and at least two of the third sub-mark that is stacked in the same layer as the source-drain metal layer of the thin film transistor. For example, taking the marking structure as a stacked structure as an example, the stacked structure may include: a first sub-mark that is stacked in the same layer as the active layer of the thin film transistor, a second sub-mark that is stacked in the same layer as the gate electrode of the thin film transistor, and a third sub-mark that is stacked in the same layer as the source-drain metal layer of the thin film transistor. For example, the area of ​​the orthographic projection of the first sub-mark on the substrate substrate is greater than the area of ​​the orthographic projection of the second sub-mark on the substrate substrate, and the area of ​​the orthographic projection of the second sub-mark on the substrate substrate is greater than the area of ​​the orthographic projection of the third sub-mark on the substrate substrate.

[0064] In an exemplary embodiment, the material of the marking structure can be any one of metal materials such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), etc., or an alloy material made of any one or more of the above metal materials, such as molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure, or can be a multi-layer composite structure, such as a composite structure consisting of a Mo layer, a Cu layer and a Mo layer, etc.

[0065] The display substrate motherboard in the embodiment of the present disclosure is described below by taking an example in which a groove penetrating the planarization layer is provided in the planarization layer.

[0066] In an exemplary embodiment, Figure 4A FIG. 1 is a schematic diagram of a marking area in an embodiment of the present disclosure in a plane perpendicular to a display substrate motherboard, such as Figure 4A As shown, in a plane direction perpendicular to the display substrate motherboard, the marking area may include: a gate insulating layer 15 arranged on the base substrate 21, an interlayer insulating layer 14 arranged on the gate insulating layer 15, a planarization layer 11 with grooves arranged on the interlayer insulating layer 14, a marking structure 10 arranged in the groove and arranged on the same layer as the source and drain metal layer in the thin film transistor, and a reflective layer 12 covering the planarization layer 11 and the marking structure 10.

[0067] In an exemplary embodiment, Figure 4B FIG. 1 is another schematic diagram of the marking area in the embodiment of the present disclosure in a plane perpendicular to the display substrate motherboard, such as Figure 4BAs shown, in a plane direction perpendicular to the display substrate motherboard, the marking area may include: a gate insulating layer 15 arranged on the base substrate 21, a marking structure 10 arranged on the gate insulating layer 15 and on the same layer as the gate electrode in the thin film transistor, an interlayer insulating layer 14 arranged on the gate insulating layer 15 and the marking structure 10, a planarization layer 11 with a groove arranged on the interlayer insulating layer 14, and a reflective layer 12 arranged on the planarization layer 11, wherein the setting position of the groove corresponds to the setting position of the marking structure 10.

[0068] In an exemplary embodiment, Figure 4C FIG. 1 is another schematic diagram of the marking area in the embodiment of the present disclosure in a plane perpendicular to the display substrate motherboard, such as Figure 4C As shown, in a plane direction perpendicular to the display substrate motherboard, the marking area may include: a marking structure 10 arranged on the base substrate 21 and arranged in the same layer as the active layer in the thin film transistor, a gate insulating layer 15 arranged on the gate insulating layer 15 and the marking structure 10, an interlayer insulating layer 14 arranged on the gate insulating layer 15, a planarization layer 11 with a groove arranged on the interlayer insulating layer 14, and a reflective layer 12 arranged on the planarization layer 11, wherein the setting position of the groove corresponds to the setting position of the marking structure 10.

[0069] In an exemplary embodiment, the mark structure is a stacked structure, including: a first sub-mark arranged in the same layer as the active layer in the thin film transistor, a second sub-mark arranged in the same layer as the gate electrode in the thin film transistor, and a third sub-mark arranged in the same layer as the source and drain metal layer in the thin film transistor. Figure 4D FIG. 1 is another schematic diagram of the marking area in the embodiment of the present disclosure in a plane perpendicular to the display substrate motherboard, such as Figure 4D As shown, the marking structure 10 may include a first sub-mark 41, a second sub-mark 42 and a third sub-mark 43; in a direction perpendicular to the plane of the display substrate motherboard, the marking area may include: a first sub-mark 41 disposed on the base substrate 21, a gate insulating layer 15 disposed on the gate insulating layer 15 and the first sub-mark 41, a second sub-mark 42 disposed on the gate insulating layer 15, an interlayer insulating layer 14 disposed on the gate insulating layer 15 and the second sub-mark 42, a planarization layer 11 with a groove disposed on the interlayer insulating layer 14, a third sub-mark 43 disposed in the groove, and a reflective layer 12 covering the planarization layer 11 and the third sub-mark 43. The setting position of the groove corresponds to the setting position of the third sub-mark 43.

[0070] In an exemplary embodiment, taking the case where the marking structure is arranged in the same layer as the source and drain metal layer in the thin film transistor, and the marking structure is located in a groove that penetrates the planarization layer, the step difference between the marking area and the display substrate area can be about 1.84μm to 2.76μm, the thickness of the marking structure can be about 0.46μm to 0.69μm, and the thickness of the reflective layer can be about 0.8μm to 1.2μm. For example, the thickness of the marking structure can be about 0.58μm, the thickness of the area at the corresponding position of the marking structure in the planarization layer (that is, the part located in the marking area) can be about 2.3μm, and the thickness of the area adjacent to the area at the corresponding position of the marking structure in the planarization layer (that is, the part of the display substrate area that is located around the marking area) can be about 2.78μm. Here, since the area at the corresponding position of the marking structure in the planarization layer is removed (that is, the part of the planarization layer located in the marking area has a groove that penetrates the planarization layer and exposes the marking structure), as shown in FIG. Figure 5A As shown, after the entire reflective layer 12 is formed, the reflective layer (e.g., Ag metal film) 12 will be in direct contact with the marking structure 10. Thus, a larger step difference is formed between the marking structure and the adjacent area, so that the light between the marking structure and the lens of the device for identifying the mark is refracted and absorbed less. Figure 5A The dotted line frame in the figure shows the cross-sectional SEM image of the marking area perpendicular to the substrate. Figure 5B As shown, the reflectivity difference between the groove 31 and the mark structure 10 set in the mark area and the surrounding display substrate area is relatively large (that is, the difference in light reflection or light transmission between the mark area and the surrounding display substrate area is relatively large), so that the edge of the mark area is clear (for example, the edge of the groove 31). Therefore, the clarity of the mark structure is improved, and then the recognition success rate of the mark structure is improved.

[0071] For example, the marking structure is set to be in the same layer as the source and drain metal layer in the thin film transistor. FIG. 6A to FIG. 6C As shown, the marking structure 10 located in the groove 31 can be effectively identified.

[0072] The structure of the display substrate motherboard in the embodiment of the present disclosure is explained below by the preparation process of the display substrate motherboard. Among them, the "patterning process" mentioned in the embodiment of the present disclosure includes deposition of film layer, coating of photoresist, mask exposure, development, etching and stripping of photoresist and other processes. Deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, coating can be any one or more of spraying and spin coating, and etching can be any one or more of dry etching and wet etching. "Thin film" refers to a layer of thin film made by a deposition or coating process on a substrate of a certain material. When the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". When the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". "A and B are arranged in the same layer" in the embodiment of the present invention means that A and B are formed simultaneously by the same patterning process.

[0073] The embodiment of the present disclosure also provides a method for preparing a display substrate motherboard, wherein the display substrate motherboard comprises: a base substrate, a display substrate area located on the base substrate, and a marking area located around the display substrate area; the preparation method comprises:

[0074] S11, forming a thin film transistor in the display substrate area, and forming a marking structure in the marking area;

[0075] S12, forming a planarization layer covering the thin film transistor and the mark area;

[0076] S13, forming a groove in the planarization layer, which is arranged at a position corresponding to the mark structure and extends in a direction close to the substrate.

[0077] In an exemplary embodiment, taking the case where the marking structure and the source-drain metal layer in the thin film transistor are arranged in the same layer, and the thin film transistor may include: an active layer, a gate electrode and a source-drain metal layer, then S11 may include: forming an active layer on a substrate; forming a gate insulating layer covering the active layer; forming a gate electrode on the gate insulating layer; forming an interlayer insulating layer covering the gate insulating layer and the gate electrode; forming a source-drain metal layer and a marking structure on the interlayer insulating layer through the same patterning process. Among them, the active layer, the gate electrode, and the source-drain metal layer are arranged in the display substrate area, and the marking structure is arranged in the marking area.

[0078] In an exemplary embodiment, taking the case where the marking structure and the gate electrode in the thin film transistor are arranged in the same layer as an example, and the thin film transistor may include: an active layer, a gate electrode and a source-drain metal layer, then S11 may include: forming an active layer on a substrate; forming a gate insulating layer covering the active layer; forming a gate electrode and a marking structure on the gate insulating layer by a same patterning process; forming an interlayer insulating layer covering the gate insulating layer, the gate electrode and the marking structure; forming a source-drain metal layer on the interlayer insulating layer. Among them, the active layer, the gate electrode, and the source-drain metal layer are arranged in the display substrate area, and the marking structure is arranged in the marking area.

[0079] In an exemplary embodiment, taking the case where the marking structure is arranged in the same layer as the active layer in the thin film transistor, and the thin film transistor may include: an active layer, a gate electrode, and a source-drain metal layer, then S11 may include: forming an active layer and a marking structure on a substrate through a same patterning process; forming a gate insulating layer covering the active layer and the marking structure; forming a gate electrode on the gate insulating layer; forming an interlayer insulating layer covering the gate insulating layer and the gate electrode; and forming a source-drain metal layer on the interlayer insulating layer. Among them, the active layer, the gate electrode, and the source-drain metal layer are arranged in the display substrate area, and the marking structure is arranged in the marking area.

[0080] In an exemplary embodiment, the mark structure is a stacked structure, including: a first sub-mark set in the same layer as the active layer in the thin film transistor, a second sub-mark set in the same layer as the gate electrode in the thin film transistor, and a third sub-mark set in the same layer as the source-drain metal layer in the thin film transistor, and the thin film transistor may include: an active layer, a gate electrode, and a source-drain metal layer. Then, S11 may include: forming an active layer and a first sub-mark on a substrate by a same patterning process; forming a gate insulating layer covering the active layer and the first sub-mark; forming a gate electrode and a second sub-mark on the gate insulating layer by a same patterning process; forming an interlayer insulating layer covering the gate insulating layer, the gate electrode, and the second sub-mark; forming a source-drain metal layer and a third sub-mark on the interlayer insulating layer by a same patterning process. Among them, the active layer, the gate electrode, and the source-drain metal layer are set in the display substrate area, and the first sub-mark, the second sub-mark, and the third sub-mark are all set in the mark area.

[0081] In an exemplary embodiment, taking the case where the marking structure is arranged in the same layer as the source and drain metal layer in the thin film transistor, and the groove passes through the planarization layer, S13 may include: removing the film layer portion corresponding to the marking structure in the planarization layer, so as to form a groove passing through the planarization layer at a position corresponding to the marking structure in the planarization layer, and making the marking structure located in the groove.

[0082] In an exemplary embodiment, the material of the active layer can be amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the embodiment of the present disclosure is applicable to thin film transistors manufactured based on oxide technology, silicon technology or organic technology.

[0083] In an exemplary embodiment, the gate insulating layer and the interlayer insulating layer may be made of silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), etc., and may be a single-layer structure or a multi-layer composite structure.

[0084] In an exemplary embodiment, the material of the gate electrode and the source and drain metal layer can be a metal material, such as silver (Ag), copper (Cu), aluminum (Al) or molybdenum (Mo), etc., or an alloy material composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure, or can be a multi-layer composite structure, such as a composite structure composed of a Mo layer, a Cu layer and a Mo layer.

[0085] In an exemplary embodiment, the display substrate motherboard further includes: a reflective layer, which is arranged on a side of the planarization layer away from the base substrate; the preparation method may further include: S14, forming the reflective layer on the planarization layer.

[0086] In an exemplary embodiment, taking the example of a planarization layer being arranged in the same layer as the source / drain metal layer in the thin film transistor and having a groove penetrating the planarization layer and exposing the marking structure, S14 may include: forming a reflective layer covering the planarization layer, the groove and the marking structure.

[0087] The embodiment of the present disclosure further provides a display substrate, which is formed by cutting the display substrate motherboard along the marking area to obtain the display substrate area in one or more of the above embodiments.

[0088] In an exemplary embodiment, the display substrate may include, but is not limited to, any one of a liquid crystal display (LCD) display substrate, an organic light-emitting diode (OLED) display substrate, a quantum dot light-emitting diode (QLED) display substrate, and an inorganic light-emitting diode display substrate. For example, the display substrate may be an LCD array substrate.

[0089] An embodiment of the present disclosure further provides a display device, comprising the display substrate in one or more of the above embodiments.

[0090] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The embodiment of the present disclosure does not limit the type of the display device.

[0091] Although the embodiments disclosed in the present disclosure are as above, the above contents are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate motherboard, characterized in that: The display substrate motherboard comprises: a base substrate, a display substrate region located on the base substrate for forming a reflective display substrate, and a marking region located around the display substrate region; the reflective display substrate comprises: a fully reflective display substrate or a semi-transmissive and semi-reflective display substrate; The display substrate motherboard further includes: a thin film transistor disposed in the display substrate region, a marking structure disposed in the marking region, and a planarization layer disposed on a side of the thin film transistor away from the base substrate; Wherein, the planarization layer comprises: a groove arranged at a position corresponding to the mark structure and extending in a direction close to the base substrate, wherein the orthographic projection of the groove on the base substrate covers the orthographic projection of the mark structure on the base substrate; The display substrate motherboard further includes: a reflective layer, which is arranged on a side of the planarization layer away from the base substrate; wherein, in a direction away from the base substrate, a first area of ​​the reflective layer covering the groove is lower than a second area of ​​the reflective layer adjacent to the first area, and a step difference between the first area and the second area is 1.84 μm to 2.76 μm; the reflective layer is made of silver; The marking structure is a stacked structure, comprising: a first sub-mark arranged in the same layer as the active layer of the thin film transistor, a second sub-mark arranged in the same layer as the gate electrode of the thin film transistor, and a third sub-mark arranged in the same layer as the source / drain metal layer of the thin film transistor, which are stacked in sequence; the orthographic projection of the first sub-mark on the substrate overlaps with the orthographic projection of the second sub-mark on the substrate, and the orthographic projection of the second sub-mark on the substrate overlaps with the orthographic projection of the third sub-mark on the substrate; the area of ​​the orthographic projection of the first sub-mark on the substrate is greater than the area of ​​the orthographic projection of the second sub-mark on the substrate, and the area of ​​the orthographic projection of the second sub-mark on the substrate is greater than the area of ​​the orthographic projection of the third sub-mark on the substrate.

2. The display substrate motherboard according to claim 1, characterized in that: The groove passes through the planarization layer, and the marking structure is located in the groove; Alternatively, the groove does not penetrate the planarization layer, and the area of ​​the planarization layer where the groove is located covers the mark structure.

3. The display substrate motherboard according to claim 1, characterized in that: The center of the orthographic projection of the groove on the substrate coincides with the center of the orthographic projection of the mark structure on the substrate.

4. The display substrate motherboard according to claim 1, characterized in that: In a plane parallel to the base substrate, the cross-sectional shape of the groove is a rectangle or a square.

5. The display substrate motherboard according to claim 4, characterized in that: A distance between an edge of an orthographic projection of the groove on the substrate and an edge of an orthographic projection of the mark structure on the substrate is 20 μm to 300 μm.

6. The display substrate motherboard according to claim 1, characterized in that: The marking structure is arranged in the same layer as at least one of a source / drain metal layer, a gate electrode and an active layer in the thin film transistor.

7. The display substrate motherboard according to claim 1, characterized in that: The thickness of the marking structure is 0.46 μm to 0.69 μm, and the thickness of the reflective layer is 0.8 μm to 1.2 μm.

8. The display substrate motherboard according to claim 1, characterized in that: The marking structure includes: one or more of a rectangular structure and a cross structure.

9. A display substrate, characterized in that: The display substrate region is formed by cutting the display substrate motherboard according to any one of claims 1 to 8 along the marking region.

10. A display device, characterized in that: Comprising the display substrate as claimed in claim 9.

11. A method for preparing a display substrate motherboard, characterized in that: The display substrate motherboard comprises: a base substrate, a display substrate region located on the base substrate for forming a reflective display substrate, and a marking region located around the display substrate region; the reflective display substrate comprises: a fully reflective display substrate or a semi-transmissive and semi-reflective display substrate; The preparation method comprises: forming a thin film transistor in the display substrate region, and forming a marking structure in the marking region; forming a planarization layer covering the thin film transistor and the mark area; A groove is formed in the planarization layer at a position corresponding to the mark structure and extending in a direction close to the substrate, and the orthographic projection of the groove on the substrate covers the orthographic projection of the mark structure on the substrate; wherein the mark structure is a stacked structure, and the stacked structure includes: a first sub-mark arranged in the same layer as the active layer of the thin film transistor, a second sub-mark arranged in the same layer as the gate electrode of the thin film transistor, and a third sub-mark arranged in the same layer as the source-drain metal layer of the thin film transistor, which are stacked in sequence; the orthographic projection of the first sub-mark on the substrate overlaps with the orthographic projection of the second sub-mark on the substrate, and the orthographic projection of the second sub-mark on the substrate overlaps with the orthographic projection of the third sub-mark on the substrate; the area of ​​the orthographic projection of the first sub-mark on the substrate is greater than the area of ​​the orthographic projection of the second sub-mark on the substrate, and the area of ​​the orthographic projection of the second sub-mark on the substrate is greater than the area of ​​the orthographic projection of the third sub-mark on the substrate; The preparation method also includes: forming a reflective layer on a side of the planarization layer away from the base substrate, wherein, in a direction away from the base substrate, a first area of ​​the reflective layer covering the groove is lower than a second area of ​​the reflective layer adjacent to the first area, and a step difference between the first area and the second area is 1.84 μm to 2.76 μm; the material of the reflective layer is silver.

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