Multi-stage signal selection circuit, timing adjustment system and method

Abstract

The present invention provides a multi-stage signal selection circuit, timing adjustment system, and method, comprising: a multi-stage signal selection module that performs multi-stage delay on an input signal and outputs a multi-stage delayed signal; a gating module that selects a corresponding delayed signal for output based on a control signal; and a timing adjustment circuit that samples a superconducting control signal based on a clock signal output by the multi-stage signal selection circuit to obtain a control signal for a CMOS circuit. The multi-stage signal selection circuit, timing adjustment system, and method of the present invention address the timing adjustment issues associated with signal exchange and synchronization between superconducting and CMOS circuits. They perform timing selection and delay adjustment for signals requiring delay, such as clock signals, more effectively meeting the operational requirements of CMOS circuits and SRAMs.

Description

Technical Field

[0001] The present invention relates to the field of superconducting technology, and in particular to a multi-level signal selection circuit, a timing adjustment system and a method. Background Art

[0002] Superconducting circuit technology is a key development direction for future computers, and numerous institutions both domestically and internationally are conducting research and development on superconducting components and computers. Existing superconducting circuit component designs are mostly based on the "traveling wave flow" principle, where all signals arrive and terminate at the same time. This lacks the traditional concept of triggers, making register implementation difficult and preventing effective timing adjustments.

[0003] Therefore, how to solve the signal exchange and synchronization problem between superconducting circuits and CMOS circuits has become one of the problems that need to be solved urgently by those skilled in the art. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a multi-stage signal selection circuit, a timing adjustment system and a method for solving the problem of difficulty in signal exchange and synchronization between superconducting circuits and CMOS circuits in the prior art.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a multi-stage signal selection circuit, which at least includes:

[0006] Multi-level signal selection module and gating module;

[0007] The multi-stage signal selection module receives an input signal, performs multi-stage delay on the input signal, and outputs a multi-stage delayed signal;

[0008] The gating module is connected to the output end of the multi-stage signal selection module and receives a control signal, and selects a corresponding delayed signal for output based on the control signal.

[0009] Optionally, the multi-stage signal selection module includes 2n delay units cascaded in sequence, where n is an odd number greater than or equal to 1.

[0010] Optionally, the odd-stage delay unit includes a first PMOS tube and a first NMOS tube; the source of the first PMOS tube is connected to the power supply voltage; the drain of the first PMOS tube is connected to the drain of the first NMOS tube and outputs a delay signal; the source of the first NMOS tube is grounded; the gates of the first PMOS tube and the first NMOS tube are connected and receive the previous stage output signal.

[0011] More optionally, the substrate of the first PMOS transistor is connected to the power supply voltage, and the substrate of the first NMOS transistor is grounded.

[0012] Optionally, the odd-stage delay unit includes a second PMOS tube, a third PMOS tube, a second NMOS tube and a third NMOS tube; the source of the second PMOS tube is connected to the power supply voltage; the drain of the second PMOS tube is connected to the source of the third PMOS tube, and is connected to the source of the second NMOS tube and the drain of the third NMOS tube; the drain of the third PMOS tube is connected to the drain of the second NMOS tube and outputs a delay signal; the source of the second NMOS tube is connected to the drain of the third NMOS tube; the source of the third NMOS tube is grounded; the gates of the second PMOS tube, the third PMOS tube, the second NMOS tube and the third NMOS tube are connected, and receive the output signal of the previous stage.

[0013] More optionally, substrates of the second PMOS transistor and the third PMOS transistor are connected to the power supply voltage, and substrates of the second NMOS transistor and the third NMOS transistor are grounded.

[0014] More optionally, the even-numbered delay unit adds two stages of inverters connected in series at the output end of the odd-numbered delay unit.

[0015] Optionally, the gating module includes a decoder and multiple gating branches; the decoder decodes the control signal to obtain a gating signal for each gating branch; each gating branch corresponds one-to-one to the multi-stage delay signal, and selects a corresponding delayed signal output based on the corresponding gating signal.

[0016] Optionally, the input signal is a clock signal.

[0017] To achieve the above-mentioned and other related objectives, the present invention further provides a timing adjustment system, which at least includes:

[0018] The above-mentioned multi-stage signal selection circuit and timing adjustment circuit;

[0019] The multi-stage signal selection circuit receives a clock signal, delays the clock signal to obtain a multi-stage delayed signal, and selects a corresponding delayed signal for output based on a control signal;

[0020] The timing adjustment circuit receives the output signal of the multi-stage signal selection circuit and the superconducting control signal, and samples the superconducting control signal based on the clock signal output by the multi-stage signal selection circuit to obtain a control signal for the CMOS circuit.

[0021] To achieve the above-mentioned and other related objectives, the present invention further provides a timing adjustment method, which at least includes:

[0022] Performing multi-stage delay on the clock signal to obtain multi-stage delayed signals, and selecting corresponding delayed signals for output based on the control signal;

[0023] The superconducting control signal is sampled based on the delay signal to obtain a control signal for the CMOS circuit.

[0024] As described above, the multi-stage signal selection circuit, timing adjustment system and method of the present invention have the following beneficial effects:

[0025] The multi-level signal selection circuit, timing adjustment system and method of the present invention solve the timing adjustment problem of signal exchange and synchronization between superconducting circuits and CMOS circuits, and perform timing selection and delay adjustment for signals that need to be delayed, such as clock signals, to more effectively meet the working requirements of CMOS circuits and SRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a structural schematic diagram of the multi-stage signal selection circuit of the present invention.

[0027] Figure 2 Shown is a structural schematic diagram of the multi-stage signal selection module of the present invention.

[0028] Figure 3 It is a schematic structural diagram of the delay unit of the present invention.

[0029] Figure 4 FIG. 2 is another structural diagram of the delay unit of the present invention.

[0030] Figure 5 It is a structural diagram of the last-stage delay unit of the present invention.

[0031] Figure 6 It is a schematic diagram showing the relative relationship of the delay time between the delay signals of the present invention.

[0032] Figure 7 Shown is a structural schematic diagram of the timing adjustment system of the present invention.

[0033] Figure 8 Shown is a schematic diagram of the principle of timing adjustment of the timing adjustment system and method of the present invention.

[0034] Component number description

[0035] 1 Multi-level signal selection circuit

[0036] 11. Multi-level signal selection module

[0037] 111a odd-stage delay unit

[0038] 111b even-stage delay unit

[0039] 12 steps

[0040] 2 Timing Adjustment Circuit DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] See also Figures 1 to 8 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0043] Example 1

[0044] like Figure 1 As shown, the present invention provides a multi-stage signal selection circuit 1, and the multi-stage signal selection circuit 1 includes:

[0045] A multi-stage signal selection module 11 and a gating module 12 .

[0046] like Figure 1 As shown, the multi-stage signal selection module 11 receives an input signal, performs multi-stage delay on the input signal, and outputs a multi-stage delayed signal.

[0047] Specifically, in this embodiment, the input signal is a clock signal CLK, but in actual use, any signal is applicable.

[0048] Specifically, if Figure 2 As shown, the multi-stage signal selection module 11 includes 2n delay units cascaded in sequence, and each stage of the delay unit outputs a corresponding delayed signal, wherein n is an odd number greater than or equal to 1.

[0049] More specifically, the structures of the odd-numbered delay units 111a are the same, and the delay time can be controlled by adjusting the parameters of the devices in each delay unit. This embodiment only takes the first-level delay unit as an example. Figure 3As shown, the first-stage delay unit 111a includes a first PMOS transistor P1 and a first NMOS transistor N1. The source of the first PMOS transistor P1 is connected to the power supply voltage VDD, and the drain is connected to the drain of the first NMOS transistor N1. The source of the first NMOS transistor N1 is grounded to VSS. The gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected and connected to the clock signal CLK (the third and subsequent odd-numbered delay units receive the output signal of the previous delay unit). The drains of the first PMOS transistor P1 and the first NMOS transistor N1 output the corresponding delay signal CLK1. In this embodiment, the substrate of the first PMOS transistor P1 is connected to the power supply voltage VDD, and the substrate of the first NMOS transistor N1 is grounded to VSS. As another example, the first-stage delay unit 111a includes a second PMOS transistor P2, a third PMOS transistor P3, a second NMOS transistor N2, and a third NMOS transistor N3; the source of the second PMOS transistor P2 is connected to the power supply voltage VDD; the drain of the second PMOS transistor P2 is connected to the source of the third PMOS transistor P3, and is also connected to the source N2 of the second NMOS transistor and the drain of the third NMOS transistor N3; the drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2 and outputs a corresponding delay signal CLK1; the source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3; the source of the third NMOS transistor N3 is grounded to VSS; the gates of the second PMOS transistor P2, the third PMOS transistor P3, the second NMOS transistor N2, and the third NMOS transistor N3 are connected, and receive the clock signal CLK (the third-stage and subsequent odd-numbered delay units receive the output signal of the previous-stage delay unit). In this embodiment, substrates of the second PMOS transistor P2 and the third PMOS transistor P3 are connected to the power supply voltage VDD, and substrates of the second NMOS transistor N2 and the third NMOS transistor N3 are grounded to VSS.

[0050] More specifically, the structures of the even-numbered delay units 111b are the same. Based on the structure of the odd-numbered delay units, two stages of inverters connected in series are added to the output of the even-numbered delay units 111b. The delay time can be controlled by adjusting the parameters of the devices in each delay unit so that the delay time of the even-numbered delay units is consistent with the delay time of the odd-numbered delay units. This embodiment only takes the 2n-th stage delay unit as an example. Figure 5As shown, taking an inverter combination consisting of two PMOS transistors and two NMOS transistors as an example, the input of the first inverter not1 is connected to the drains of the third PMOS transistor P3 and the second NMOS transistor N2 in the final delay unit. The input of the second inverter not2 is connected to the output of the first inverter not1, and the second inverter not2 outputs the corresponding delay signal CLK2n. This reduces overshoot without affecting the delay time of even-numbered delay units 111b.

[0051] It should be noted that the structure of the even-numbered delay unit can also be Figure 3 Two stages of inverters connected in series are added to the basis of the odd-numbered delay units shown, which will not be described in detail here.

[0052] Specifically, assuming that the period of the clock signal CLK is t, and the delay time between the output and input of each delay unit is t0, then the delay time between the clock signal CLK2n output by the 2nth delay unit (the last delay unit) and the original clock signal CLK is 2nt0; the delay time between the clock signal CLKn output by the nth delay unit and the original clock signal CLK is t / 2+nt0. Figure 6 As shown, the clock signal CLK passes through the first delay unit to obtain the delayed signal CLK1. Since the delayed signal CLK1 has undergone inversion and delay, the delay time between the delayed signal CLK1 and the original clock signal CLK is t / 2+t0. The delayed signal CLK1 passes through the second delay unit to obtain the delayed signal CLK2. Since the delayed signal CLK2 has undergone inversion and delay, the delay time between the delayed signal CLK2 and the original clock signal CLK is 2t0. The delay times of other delayed signals are similar and are not described in detail here.

[0053] It should be noted that, in this embodiment, the multi-stage delay signal CLK_D[2n:1] includes 2n signals. In actual use, some of the 2n signals can be selected for output as needed.

[0054] like Figure 1 As shown, the gating module 12 is connected to the output end of the multi-stage signal selection module 11 and receives a control signal. Based on the control signal, the corresponding delayed signal is selected for output, thereby playing a role in timing adjustment.

[0055] Specifically, in this embodiment, the control signals include TR1, TR2, TR3, and TR4. In actual use, the number of control signals can be set based on the number of signals output by the multi-stage signal selection module 11, and is not limited to this embodiment. As an example, the gating module 12 includes a decoder and multiple gating branches (not shown). The decoder decodes the control signals to obtain gating signals for each gating branch. Each gating branch corresponds to the multi-stage delay signal and selects a corresponding delayed signal for output based on the corresponding gating signal, which is denoted as CLK_D.

[0056] Example 2

[0057] like Figure 7 As shown, this embodiment provides a timing adjustment system, the timing adjustment system comprising:

[0058] Multi-stage signal selection circuit 1 and timing adjustment circuit 2.

[0059] like Figure 7 As shown, the multi-stage signal selection circuit 1 receives a clock signal CLK, delays the clock signal CLK to obtain a multi-stage delayed signal, and selects a corresponding delayed signal CLK_D for output based on a control signal.

[0060] Specifically, the structure and principle of the multi-stage signal selection circuit 11 refer to the first embodiment, which will not be described in detail here.

[0061] like Figure 7 As shown, the timing adjustment circuit 2 receives the output signal CLK_D and the superconducting control signal CTL_SFQ of the multi-stage signal selection circuit 1, and samples the superconducting control signal CTL_SFQ based on the clock signal CLK_D output by the multi-stage signal selection circuit 1 to obtain the control signal CTL_CMOS for the CMOS circuit.

[0062] Specifically, if Figure 8As shown, a first superconducting control signal CEB_SFQ is obtained, and the first superconducting control signal CEB_SFQ is sampled at the rising edge of the clock signal CLK_D output by the multi-stage signal selection circuit 1. If a high level is sampled, a high level is output, and if a low level is sampled, a low level is output, thereby obtaining a first control signal CEB_SRAM (in this embodiment, used in an SRAM circuit). The timing of the first control signal CEB_SRAM is determined by the rising edge of the clock signal CLK_D, thereby realizing the timing adjustment of signal exchange and synchronization between the superconducting circuit and the CMOS circuit; similarly, a second superconducting control signal READB_SFQ is obtained, and the second superconducting control signal READB_SFQ is sampled at the rising edge of the clock signal CLK_D output by the multi-stage signal selection circuit 1 to obtain the second control signal READB_SRAM; a third superconducting control signal WRITEB_SFQ is obtained, and the third superconducting control signal WRITEB_SFQ is sampled at the rising edge of the clock signal CLK_D output by the multi-stage signal selection circuit 1 to obtain the third control signal WRITEB_SRAM.

[0063] Example 3

[0064] This embodiment provides a timing adjustment method, which includes:

[0065] The clock signal is delayed in multiple stages to obtain a multi-stage delayed signal, and the corresponding delayed signal is selected for output based on the control signal; the superconducting control signal is sampled based on the delayed signal to obtain a control signal for the CMOS circuit.

[0066] Specifically, the timing adjustment method of the present invention may be implemented using the timing adjustment system of the second embodiment, and the specific principles are not described in detail here.

[0067] The multi-level signal selection circuit, timing adjustment system and method of the present invention meet the timing requirements of superconducting circuits accessing SRAM or other CMOS circuits by adding controllable delay, thereby more effectively meeting the working requirements of CMOS circuits and SRAM.

[0068] In summary, the present invention provides a multi-stage signal selection circuit, a timing adjustment system, and a method, comprising: a multi-stage signal selection module that receives an input signal, performs multi-stage delay on the input signal, and outputs a multi-stage delayed signal; a selection module that is connected to the output end of the multi-stage signal selection module and receives a control signal, and selects a corresponding delayed signal for output based on the control signal; a timing adjustment circuit that receives the output signal of the multi-stage signal selection circuit and a superconducting control signal, and samples the superconducting control signal based on a clock signal output by the multi-stage signal selection circuit to obtain a control signal for a CMOS circuit. The multi-stage signal selection circuit, timing adjustment system, and method of the present invention solve the timing adjustment problem of signal exchange and synchronization between superconducting circuits and CMOS circuits, and perform timing selection and delay adjustment for signals that require delay, such as clock signals, to more effectively meet the operating requirements of CMOS circuits and SRAMs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A multi-stage signal selection circuit, characterized in that: The multi-stage signal selection circuit at least includes: Multi-level signal selection module and gating module; The multi-stage signal selection module receives an input signal, performs multi-stage delay on the input signal, and outputs a multi-stage delayed signal; wherein the odd-stage delay unit includes a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor; the source of the second PMOS transistor is connected to a power supply voltage; the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, and is connected to the source of the second NMOS transistor and the drain of the third NMOS transistor; the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor and outputs a delayed signal; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded; the gates of the second PMOS transistor, the third PMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected and receive the output signal of the previous stage; The gating module is connected to the output end of the multi-stage signal selection module and receives a control signal, and selects a corresponding delayed signal for output based on the control signal.

2. The multi-stage signal selection circuit according to claim 1, wherein: The multi-stage signal selection module includes 2n delay units cascaded in sequence, where n is an odd number greater than or equal to 1.

3. The multi-stage signal selection circuit according to claim 1, wherein: The substrates of the second PMOS transistor and the third PMOS transistor are connected to the power supply voltage, and the substrates of the second NMOS transistor and the third NMOS transistor are grounded.

4. The multi-stage signal selection circuit according to any one of claims 2 to 3, wherein: The even-numbered delay unit adds two stages of inverters connected in series at the output end of the odd-numbered delay unit.

5. The multi-stage signal selection circuit according to claim 1, wherein: The gating module includes a decoder and multiple gating branches; the decoder decodes the control signal to obtain a gating signal for each gating branch; each gating branch corresponds one-to-one to the multi-stage delay signal, and selects a corresponding delayed signal output based on the corresponding gating signal.

6. The multi-stage signal selection circuit according to claim 1, wherein: The input signal is a clock signal.

7. A timing adjustment system for superconducting circuits to access CMOS circuits, characterized in that: The timing adjustment system at least includes: The multi-stage signal selection circuit and timing adjustment circuit according to any one of claims 1 to 6; The multi-stage signal selection circuit receives a clock signal, delays the clock signal to obtain a multi-stage delayed signal, and selects a corresponding delayed signal for output based on a control signal; The timing adjustment circuit receives the output signal of the multi-stage signal selection circuit and the superconducting control signal, and samples the superconducting control signal based on the clock signal output by the multi-stage signal selection circuit to obtain a control signal for the CMOS circuit.

8. A timing adjustment method for a superconducting circuit to access a CMOS circuit, implemented based on the timing adjustment system according to claim 7, characterized in that: The timing adjustment method at least includes: Performing multi-stage delay on the clock signal to obtain multi-stage delayed signals, and selecting corresponding delayed signals for output based on the control signal; The superconducting control signal is sampled based on the delay signal to obtain a control signal for the CMOS circuit.

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