Memory subsystem write sequence tracking

Abstract

This application relates to a memory subsystem write sequence tracking. A system includes a memory device and a processing means communicatively coupled to the memory device. The processing means writes data to a plurality of memory cell groups of the memory device in a physically discontinuous manner. The processing means further tracks the sequence of data written to the plurality of memory cell groups. In response to a trigger event, the processing means further identifies at least a portion of the plurality of memory cell groups having data received within a predefined period prior to the trigger event, based at least in part on the tracking sequence.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory systems and more specifically to a memory subsystem write sequence tracing. Background Technology

[0002] A memory system may include one or more memory devices for storing data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, a host system may utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] One aspect of this application relates to a memory subsystem write sequence tracking system, comprising: a memory device; and a processing device communicatively coupled to the memory device, wherein the processing device performs: writing data in a physically discontinuous manner to a plurality of memory cell groups of the memory device; tracking the sequence of data written to the plurality of memory cell groups; and, in response to a trigger event, identifying at least a portion of the plurality of memory cell groups of data received within a predefined period prior to the trigger event, based at least in part on the tracking sequence.

[0004] Another aspect of this application relates to a memory subsystem write sequence tracking system, comprising: a memory device including a plurality of blocks, each comprising a plurality of pages; and a processing device communicatively coupled to the memory device, wherein the processing device performs: writing data to the plurality of blocks in a physically discontinuous manner, wherein the data is sequentially written to the plurality of pages within each of the plurality of blocks; and, in response to a trigger event, generating entries comprising a sequence of data received within a predefined period prior to the trigger event being written to the plurality of blocks in a first portion, wherein the generated entries are stored in the memory device.

[0005] Another aspect of this application relates to a method for tracing a write sequence in a memory subsystem, comprising: sequentially writing a first portion of data to several pages of a first block of a plurality of blocks; sequentially writing a second portion of the data to several pages of a second block of the plurality of blocks after the first portion of the data has been sequentially written to the several pages of the first block, wherein the second block is not contiguous with the first block; determining that a triggering event has occurred when the second portion of the data has been sequentially written to a specific page of the second block; tracing backward from the specific page of the second block the plurality of blocks written with an amount of data having a known size corresponding to a predefined period prior to the triggering event; and generating and storing in a memory device an entry comprising: a sequence of writing the plurality of blocks with the amount of data; and a logical address of the specific page of the second block. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 Examples of memory devices according to some embodiments of the present disclosure are described.

[0009] Figure 3A This illustrates a graph associated with superblocks that use linked lists to identify data corresponding to snapshots, according to some embodiments of this disclosure.

[0010] Figure 3B Another diagram illustrating the association of superblocks with data corresponding to snapshots using linked lists, according to some embodiments of this disclosure.

[0011] Figure 4 This is a flowchart of an instance method for writing sequence tracking according to some embodiments of the present disclosure.

[0012] Figure 5 Examples of systems including a computing system in a vehicle are described according to some embodiments of the present disclosure.

[0013] Figure 6 A diagram illustrating a portion of a memory array having physical blocks coupled to a controller, according to some embodiments of the present disclosure.

[0014] Figure 7 A diagram illustrating a portion of a memory array having a superblock according to some embodiments of the present disclosure.

[0015] Figure 8 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0016] This disclosure relates to a write sequence tracing method for a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more memory devices, such as memory devices for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0017] The storage subsystem can be used to store data by various components of a vehicle, such as applications running on the vehicle's main system. An example of such an application is the vehicle's event recorder. The event recorder can also be called a "black box" or accident data recorder.

[0018] The advent of autonomous vehicles, the Internet of Things (IoT), and monitoring devices has led to a greater gap between the total bytes written (TBW) over the lifetime of a memory subsystem and its user capacity. For example, the TBW to user capacity ratio of some memory systems used in such applications has increased by one to three orders of magnitude. Some autonomous vehicles require real-time buffering of telemetry data, such as data from cameras, radar, lidar, ultrasound, and other sensors required to replay sequences prior to an incident. The total data from various sensors represents a significant throughput requirement per unit time (e.g., 1 gigabyte per second (GB / sec) of sequence write throughput from the host). After an event is triggered, a certain amount of data corresponding to a predetermined replay time immediately preceding the event needs to be captured (e.g., to determine the cause of the incident). The telemetry sensor data recorded corresponding to the predetermined replay time can be referred to as a “snapshot.” ​​An event logger is one such application where user capacity requirements can be as low as 128 (128) GB, but TBW requirements can be as high as hundreds of petabytes. The examples of the values ​​given are not limited, but highlight the relative difference between capacity requirements and TBW. An event logger may need to store at least several recent snapshots.

[0019] Flash memory devices may include a flash translation layer (FTL) that can be used (e.g., during programming operations performed on the flash memory device) to map logical addresses to physical addresses in the flash memory (e.g., via a logic-to-physical (L2P) table). As an example, in some prior methods, entries in the logic-to-physical (L2P) address mapping table may include references to dies, blocks, planes, and pages of memory in which a portion of data is stored. Furthermore, a die may comprise several planes, each of which may each comprise several blocks, and each of which may each comprise several pages.

[0020] Because the event logger's memory subsystem continuously receives input data from sensors and writes the received data sequentially into memory (e.g., a non-volatile NAND flash memory array), it is typically necessary to update the address mapping table each time new data is written to memory, so that the logical sequence entries in the address mapping table indicate the sequence of programming physical addresses. However, this approach can result in a relatively large total memory usage (TBW), require a significant portion of the memory, and / or be difficult to manage. Therefore, it is desirable to minimize the resource footprint of the event logger's memory subsystem while maintaining the address mapping table.

[0021] The present disclosure addresses the aforementioned and other drawbacks by having a memory subsystem that captures snapshots without exhausting the resources of the memory subsystem while maintaining the L2P table. If the L2P table is not repeatedly updated each time new data is written to the memory subsystem, the memory subsystem of this disclosure can track only the sequence of data written to logical addresses. Once a triggering event is determined to have occurred, the memory subsystem can generate only a list indicating the location of the data stored in the memory portion (and / or the corresponding logical address) and the sequence of data written to the memory portion. Therefore, when a snapshot is retrieved, the data corresponding to the snapshot can be retrieved only from the memory portion and reorganized based on the sequence indicated by the list. This method substantially reduces the TBW caused by maintaining the address mapping table according to previous methods.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 104 according to some embodiments of the present disclosure. The memory subsystem 104 may include media, such as one or more volatile memory devices (e.g., memory device 114), one or more non-volatile memory devices (e.g., memory device 116), or a combination thereof.

[0023] The memory subsystem 104 may be a storage device, a memory module, or a combination of both. Examples of storage devices include SSDs, flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), IoT-enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or a similar computing system containing memory and processing devices.

[0025] The computing system 100 includes a host system 102 coupled to one or more memory subsystems 104. In some embodiments, the host system 102 is coupled to different types of memory subsystems 104. Figure 1 This describes an example of a host system 102 coupled to a memory subsystem 104. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like.

[0026] In at least one embodiment, the host system 102 is a computing device for controlling a vehicle (e.g., an autonomous vehicle), and the memory subsystem 104 is an SSD that provides event recorder storage for the vehicle. For example, the memory subsystem 104 may store time-based telemetry sensor data of the vehicle.

[0027] Host system 102 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, etc.). Host system 102 may, for example, use memory subsystem 104 to write data to and read data from memory subsystem 104.

[0028] Host system 102 can be coupled to memory subsystem 104 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, PCIe interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 102 and memory subsystem 104. Host system 102 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 116) when memory subsystem 104 is coupled to host system 102 via a PCIe interface. The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 104 and host system 102. Figure 1 The memory subsystem 104 is illustrated as an example. Generally, the host system 102 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0029] For example, host system 102 may send a request to memory subsystem 104 to write data to or read data from memory subsystem 104. The data to be written or read, specified by the host request, is called "host data". The host request may contain logical address information. The logical address information may be a logical block address (LBA), which may include or be accompanied by a partition number. The logical address information is the location associated with the host data by the host system. The logical address information may be part of the metadata of the host data. The LBA may also correspond to (e.g., dynamically mapped to) a physical address, such as a physical block address (PBA), which indicates the physical location in memory where the host data is stored.

[0030] Memory devices 114 and 116 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 114) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Examples of non-volatile memory devices (such as memory device 116) include NAND flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in volume resistance and stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasure of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of memory devices 114 and 116 may include one or more arrays of memory cells. One method of operating a memory cell includes storing one bit per cell, referred to as a single-level cell (SLC). "Level" refers to the number of states a cell is programmed to, excluding the erase state (level). An SLC is programmable to one level other than the erase level. Other methods of operating memory cells include storing more than one bit per cell, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), etc. As used herein, "multi-level cell (MLC)" refers to a memory cell programmable to two levels other than the erase level. In some embodiments, non-volatile memory device 116 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, TLC portion, QLC portion, or PLC portion of memory cells. The memory cells of the non-volatile memory device 116 can be grouped into pages that refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0033] Although a non-volatile memory component is described as a three-dimensional cross-point array of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND), memory device 116 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 106 (or simply controller 106) can communicate with the memory device 116 to perform operations such as reading data, writing data, erasing data, and other such operations at the non-volatile memory device 116. The memory subsystem controller 106 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 106 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable circuit system.

[0035] The memory subsystem controller 106 may include a processor 108 (e.g., a processing device) configured to execute instructions stored in local memory 110. In the illustrated example, the local memory 110 of the memory subsystem controller 106 includes embedded memory configured to store various processes, operations, logical flows, and routines for performing operations controlling the memory subsystem 104 (including handling communication between the memory subsystem 104 and the host system 102).

[0036] In some embodiments, local memory 110 may include memory registers storing memory pointers, acquired data, etc. For example, local memory 110 may also include ROM for storing microcode. Although Figure 1 The instance memory subsystem 104 has been described as including a memory subsystem controller 106, but in another embodiment of this disclosure, the memory subsystem 104 does not include a memory subsystem controller 106, but may rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem 104).

[0037] Generally, the memory subsystem controller 106 can receive commands or operations from the host system 102 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 116 and / or 114. The memory subsystem controller 106 may handle other operations such as wear leveling, discard item collection, error detection and / or correction, encryption, caching, and address translation between logical addresses (e.g., LBAs, namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 116. The memory subsystem controller 106 may further include a host interface circuitry for communicating with the host system 102 via a physical host interface. The host interface circuitry can translate commands received from the host system 102 into command instructions to access memory devices 116 and / or 114 and translate responses associated with memory devices 116 and / or 114 into information for the host system 102.

[0038] The memory subsystem 104 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 104 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving and decoding addresses from the memory subsystem controller 106 to access the memory device 116 and / or the memory device 114.

[0039] In some embodiments, memory device 116 includes a local media controller 118 that operates in conjunction with memory subsystem controller 106 to perform operations on one or more memory cells of memory device 116. An external controller (e.g., memory subsystem controller 106) may externally manage non-volatile memory device 116 (e.g., perform media management operations on memory device 116). In some embodiments, memory device 116 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 118) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The memory subsystem controller 106 may also include a sequence tracking component 112. Although Figure 1 While not shown in the diagrams to avoid confusion, sequence tracing component 112 may include various circuit systems to facilitate the performance of the operations described herein. For example, sequence tracing component 112 may include dedicated circuit systems in the form of ASICs, FPGAs, state machines, and / or other logic circuit systems, which may allow sequence tracing component 112 to orchestrate and / or perform the operations described herein.

[0041] In some embodiments, the memory subsystem controller 106 includes at least a portion of the sequence tracking component 112. For example, the memory subsystem controller 106 may include a processor (e.g., a processing means) configured to execute instructions stored in local memory 110 for performing the operations described herein. In some embodiments, the sequence tracking component 112 is part of the host system 102, an application, or an operating system.

[0042] The sequence tracking component 112 can track sequences of data written to memory portions of memory devices 114 and 116 with received data. In response to a trigger event, the tracked sequence can be used to identify sequences of data received within a predetermined period immediately preceding the trigger event (alternately referred to as a snapshot) that have programmed the memory portions. For example, the identified sequence can be a certain type of data (e.g., ... Figures 3A to 3B The linked list (331) described herein is stored in memory device 116. The stored data associated with the identified sequence can later be used to retrieve data corresponding to the snapshot. As further described herein, a predefined period prior to the triggering event can be determined / obtained based on the known size of the snapshot.

[0043] Figure 2 Examples of memory devices 216 according to some embodiments of this disclosure are described. Host data may be received by the memory subsystem (e.g., from...). Figure 1 (The host system 102 described herein). Host data may be time-based telemetry sensor data from different sensors of the vehicle. The time-based telemetry sensor data from different sensors may be aggregated by the host and sent to the memory subsystem at a data rate. The host data may be received by the memory subsystem and stored in non-volatile memory device 216. When non-volatile memory device 216 is full of host data, new data received from the host is stored sequentially, but data in non-volatile memory device 216 determined to be earlier than a threshold time may be erased or overwritten. Therefore, non-volatile memory device 216 can operate as a first-in, first-out (FIFO) buffer, in which newly received data replaces the oldest data. Therefore, except that the location of the written data is not inherently known without tracking, the data written before other data is written is inherently known, making the data written during a specific period easily identifiable, provided that the sequence of data written to the memory portion is known.

[0044] Once a trigger event occurs, the memory portion of the non-volatile memory device 216 storing a time-based amount of telemetry sensor data from the circular buffer portion 222 can be identified. The amount of host data corresponding to a defined time period (which may be referred to as the playback time (e.g., 30 seconds)) is called the snapshot size, and the data within the defined time period itself is called a snapshot. The snapshot size may be predefined for a time period immediately preceding the trigger event. The snapshot size and / or playback time may be predefined values ​​programmed into the memory subsystem by the manufacturer, supplier, or user. In some embodiments, determining that a trigger event has occurred may include actuating a trigger signal based at least in part on sensor information received from the host that exceeds a threshold (e.g., a quantitative value). In some embodiments, the trigger event may include the reception of a host trigger signal (independent of sensor information), which includes the scenario where the non-volatile memory device 216 is taken to a service center.

[0045] Under normal circumstances, the non-volatile memory device 216 can be powered by the power supply 228 of the memory subsystem. However, the non-volatile memory device 216 can be powered by a backup power supply (e.g., one or more holding capacitors 230) in response to a loss of system power (e.g., power supply 228), which may be associated with a triggering event (e.g., a traffic accident) that can be a host triggering event. A host triggering event may include a traffic accident that initiates the triggering event, a power loss from the power supply (e.g., power supply 228), and / or a host request (e.g., issued from host system 102, unrelated to the traffic accident or power loss). The size and / or number of holding capacitors 230 are sufficient to provide adequate power, for example, to identify a memory portion of the non-volatile memory device 216 storing a snapshot. As illustrated, the power supply 228 and the holding capacitors 230 are coupled to the memory device 216 to provide it with power. When there is no direct physical connection between the power supply 228 or the holding capacitor 230 and the non-volatile memory device 216, power can be provided through a write circuit system (not specified).

[0046] Once those memory portions storing data corresponding to the snapshot are identified, the snapshot can be retrieved later. This includes scenarios where non-volatile memory device 216 is brought to a service center and reliability is restored. As further described herein in conjunction with Figures 3 and 4, the sequence can be stored as a type of data, such as the linked list 331 illustrated in Figure 3. Furthermore, the memory portions where data is written can be superblocks.

[0047] Figure 3A This illustrates a graph associated with superblocks 334, which are identified using linked list 331 and have data corresponding to snapshots, according to some embodiments of this disclosure. (As in conjunction with...) Figure 7Further description, as used herein, refers to a set of data blocks written in an interleaved manner across multiple dies. In some cases, a superblock may span all dies within a memory subsystem (e.g., an SSD). A superblock may contain multiple data blocks from a single die. A superblock may serve as a management unit within the memory subsystem.

[0048] like Figure 3A The documentation states that data can be sequentially written to superblocks 334-1, 334-2, 334-3, ..., 334-(N-1) and 334-N. Although... Figure 3A Not described in the text, but superblocks 334-1, 334-2, 334-3, ..., 334-(N-1) are physically discontinuous; therefore, data is written to superblock 334 in a physically discontinuous manner. For example, such as Figure 3A The documentation states that once data is written to superblock 334-1, subsequent data can be written to superblock 334-2, which is not contiguous with superblock 334-1. In comparison, Figure 3A The pages within each superblock 334 (e.g., pages 339-1-1, ..., 339-1-Q) are physically contiguous, allowing data to be written to the pages in a physically contiguous manner within each superblock 334. For example, when writing data to superblock 334-1, the data can be written sequentially from page 339-1-1 to page 339-1-Q. Therefore, the sequence of data written to the pages is known and does not need to be traced. As described above, it is desirable to trace the sequence of data written to superblock 334.

[0049] In this way, the sequence of writes to a superblock (e.g., superblock 334) can be continuously monitored and tracked. In response to a triggering event, a linked list (e.g., linked list 331) can be generated based on the tracked sequence. The linked list may contain identifiers of the corresponding superblock 334 and / or page 339 within superblock 334, and may link groups of two or more superblocks, which allows identification of which superblocks (e.g., superblock 334-1) were programmed earlier than another superblock (e.g., superblock 334-2).

[0050] For example, such as Figure 3A The description states that the triggering event is determined to have occurred when data is written to page 339-(NB) of superblock 334-N. Therefore, page 339-(NB) corresponds to the end time of a predefined period prior to the triggering event. In this example, the sequence of programming superblock 334 can be traced backward from page 339-(NB) until the size of the set of traced pages / superblocks reaches the known size of the snapshot, such as the known size 335 of the snapshot. Based on the reverse-traced sequence, a linked list 331 can be generated. Figure 3AThe description states that linked list 331 contains identifiers 332-1, 332-2, ..., 332-N symbolically representing superblocks 334-1, ..., 334-N, where link 333-R indicates that superblock 334-N is programmed after superblock 334-(N-1); link 333-2 indicates that superblock 334-3 is programmed after superblock 334-2; and linked list 331 contains link 333-1 indicating that superblock 334-2 is programmed after superblock 334-1. Linked list 331 further contains an identifier / logical address corresponding to page 339-1-3. Figure 3A (Not shown) to indicate that the known size 335 of the reverse-tracking snapshot has ended at page 339-1-3 and excludes pages 339-1-1 and 339-1-2 from the snapshot portion. In other words, the identifier / logical address corresponding to page 339-1-3 corresponds to the start time of a predefined period. Therefore, list 331 indicates that the data corresponding to the snapshot is stored in a portion 357 of superblocks 334-N (e.g., from page 339-(N-1) to page 339-(NB)), superblocks 334-(N-1), ..., superblocks 334-3, superblocks 334-2, and a portion 359 of superblocks 334-1 (e.g., the remainder starting from page 339-1-3 of superblock 334-1). As used herein, the term "identifier" refers to information that can be used to identify a superblock from other superblocks. For example, an identifier may contain logical addresses (e.g., LBAs), physical addresses, etc.

[0051] In some embodiments, links (e.g., links 333-1, ..., 333-R) may be pointers. For example, link 333-1 may be a pointer from superblock 334-1 (e.g., its logical address) to superblock 334-2 (e.g., its logical address); link 333-2 may be a pointer from superblock 334-2 (e.g., its logical address) to superblock 334-3 (e.g., its logical address); and link 333-R may be a pointer from superblock 334-(N-1) (e.g., its logical address) to superblock 334-N (e.g., its logical address).

[0052] Using a linked list (e.g., linked list 331) to identify the location where data corresponding to a snapshot is stored offers an advantage over previous methods by eliminating the need to substantially maintain an address mapping table. In previous methods, those sequentially received datasets needed to be stored in logical sequence entries (e.g., in an address mapping table) to track the sequence of the programmed memory portion. This method consumes significant resources of the memory subsystem because each time a new dataset is programmed (e.g., to…)… Figure 1When the memory device 116 described in the present disclosure is used, the address mapping table needs to be updated. In contrast, in several embodiments of the present disclosure, it is not necessary to maintain an address mapping table to this extent to identify sequences. Specifically, the data indicating the sequence itself is generated separately from the L2P table in the present disclosure to identify the sequence, and even if the L2P table is used, the logical sequence entries do not indicate the sequence corresponding to the programmed physical address. Therefore, the L2P table in several embodiments of the present disclosure does not need to be updated every time a new dataset is programmed into the memory device.

[0053] Figure 3B Another diagram illustrating the association of superblock 334 with data corresponding to snapshots, based on some embodiments of this disclosure, using linked list 331 to identify superblock 334. Figure 3B Superblocks 334-1, ..., 334-4 (collectively referred to as superblock 334) can be similar to Figure 3A Superblock 334 is described in the text. Furthermore, as... Figure 3B The description states that linked lists 331-1 and 331-2 can be generated in response to a triggering event to indicate the storage location of the data corresponding to the snapshot in the superblock and the sequence of programming the superblock with the data corresponding to the snapshot.

[0054] like Figure 3B The description states that the linked list 331-1 generated in response to the triggering event indicates that data has been sequentially written to superblocks 334-1, ..., 334-4, and the data corresponding to the snapshot is stored in a portion of superblock 334-1 (e.g., sequentially from page 339-1-M to the last page of superblock 334-1), superblock 334-2, a portion of superblock 334-3 (e.g., starting from the first page of superblock 334-3 and sequentially up to page 339-3-X), and a portion of superblock 334-4 (e.g., starting from the first page of superblock 334-4 and sequentially up to page 339-3-C). Although Figure 3B Not described in the text, but at least some of the superblocks 334-1, ..., 334-4 are physically discontinuous. Therefore, data is written to superblock 334 in a physically discontinuous manner.

[0055] Figure 3B This further explains the scenarios where program failures occur during writes to a specific superblock. For example, such as... Figure 3BThe document explains that data has been sequentially written to superblocks 334-1, 334-2, and 334-3, and a program failure occurred while writing data to page 339-3-X of superblock 334-3. When this occurs, writing data to superblock 334-3 can be paused (without erasing previously written data), and subsequent data can continue to be written to superblock 334-4. Therefore, linked list 331-1 may further contain information associated with the program failure. For example, linked list 331-1 may further contain the logical address of page 339-3-X, indicating that superblock 334-3 stores valid data only within the pages starting from the first page and sequentially up to page 339-3-X.

[0056] In some embodiments, a superblock that has experienced a program failure may be flushed to another superblock later. During the flush, the linked list may be modified to reflect the flushing of data (e.g., valid data) already stored in the failed superblock to the new superblock. For example, such as... Figure 3B The description states that valid data already stored in superblock 334-3 can be flushed to superblock 334-5 later. In this example, the previous linked list 331-1, which indicates the sequence in the order of 334-1, 334-2, 334-3, and 334-4, can be modified to a linked list 331-2, which indicates the sequence in the order of 334-1, 334-2, 334-5, and 334-4, whereby superblock 334-5 is instructed to store valid data in pages that continue sequentially up to 339-5-X.

[0057] Figure 4 This is a flowchart of an example method 440 for writing sequence traces according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is performed by or uses... Figure 1 The memory subsystem controller 106, processing device 108, sequence tracking component 112, non-volatile memory device 116 and / or volatile memory device 114 and / or local media controller 118 shown in the diagram are executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0058] In operation 441, the first portion of the data can be sequentially written to multiple blocks (e.g., Figures 3A to 3BSeveral pages of the first block in the superblock 334 described in the text (e.g.) Figures 3A to 3B (See page 339 for details). In operation 442, after the first portion of the data has been sequentially written to several pages of the first block, the second portion of the data can be sequentially written to several pages of the second block. The second block does not need to be contiguous with the first block.

[0059] In operation 443, it can be determined that a triggering event has occurred when the second portion of the data is sequentially written to a specific page of the second block. In operation 445, it is possible to trace back from the specific page of the second block using data with a known size (e.g., ...). Figure 3A The data volume (335) described herein is written to multiple blocks. The known size may correspond to a predefined period prior to the triggering event. Therefore, the data volume may correspond to a snapshot.

[0060] In operation 446, the entry contains a sequence of data written to multiple blocks and the logical address of a specific page in the second block. The entry may be similar to... Figures 3A to 3B The linked list 331 described herein. Entries may further contain the logical address of a superblock identified as containing data corresponding to a snapshot. In some embodiments, the multiple blocks written with the data volume may be traced back based on known information, such as the known size of each of the multiple blocks, the known size of each of the multiple blocks' pages, and the number of pages within each of the multiple blocks.

[0061] In some embodiments, multiple blocks can be tracked without saving logic to a physical table. For example, as described herein, the memory subsystem (e.g., Figure 1 The L2P table of the memory subsystem 104 described herein does not need to be written to the memory device (e.g., every time new data is written) Figure 1 The memory subsystem 116 described herein is updated to indicate the sequence from the logical sequence entries of the L2P table.

[0062] After a portion of the first part of the data is written to the first page of the first block, a program failure can occur when another portion of the first part of the data is written to the second page of the first block. In this example, the logical address of the first page of the first block can be associated with an entry to indicate that only pages of the first block, sequentially leading up to the first page, store valid data. Therefore, when retrieving the data volume later (e.g., a snapshot), data can be read from several pages of the first block, sequentially leading up to the first page.

[0063] Continuing with the example above, a refresh operation can be performed on the first block to copy data (e.g., valid data stored in the pages of the first block that sequentially follow the first page, but excluding the second page of the first block) to a third block among multiple blocks. In response to performing the refresh operation, the sequence of entries can be modified to replace the first block with the third block.

[0064] Figure 5 This section describes an example of a system 548 comprising a computing system 500 in a vehicle 550, according to some embodiments of the present disclosure. The computing system 500 may include a memory subsystem 504, which, for simplicity, is described as including a controller 506 and a non-volatile memory device 516, but is similar to... Figure 1 The memory subsystem 104 is described in the diagram. The controller 506 may be similar to... Figure 1 The memory subsystem controller 106 is described herein. Controller 506 may further include a sequence tracking component 512, which is also located within controller 506. As described herein, in some embodiments, the sequence tracking component 512 may cause controller 506 to perform operations described in conjunction with the sequence tracking component 112.

[0065] The computing system 500 and therefore the host 502 may be directly (as illustrated with respect to sensor 544-4) or via transceiver 552 (as illustrated with respect to sensors 544-1, 544-2, 544-3, 544-5, 544-6, 544-7, 544-8, ..., 544-N) coupled to several sensors 544. The transceiver 552 is capable of wirelessly (e.g., via radio frequency communication) receiving time-based telemetry sensor data from the sensors 544. In at least one embodiment, each of the sensors 544 may wirelessly communicate with the computing system 500 via the transceiver 552. In at least one embodiment, each of the sensors 544 is directly connected to the computing system 500 (e.g., via wires or fiber optic cables). As used herein, telemetry sensor data means data collected by the sensors 544 remotely from the memory subsystem 504 (receiving device) where the data is stored. Telemetry sensor data is time-based because the data is time-dependent. The time corresponding to each data point can be stored along with the telemetry data or derived from it based on some metrics, such as the known start time of the data and the data rate. For example, time can be used in the replay of sequences prior to an incident.

[0066] Vehicle 550 can be an automobile (e.g., a car, van, truck, etc.), a connected vehicle (e.g., a vehicle with computing capabilities to communicate with an external server), an autonomous vehicle (e.g., a vehicle with automation capabilities such as autonomous driving), a drone, an aircraft, a ship, and / or anything used to transport people and / or goods. Sensor 544 in Figure 5The description includes instance attributes. For example, sensors 544-1, 544-2, and 544-3 are camera sensors that collect data from the front of vehicle 550. Sensors 544-4, 544-5, and 544-6 are microphone sensors that collect data from the front, middle, and rear of vehicle 550. Sensors 544-7, 544-8, and 544-N are camera sensors that collect data from the rear of vehicle 550. As another example, sensors 544-5 and 544-6 are tire pressure sensors. As another example, sensor 544-4 is a navigation sensor, such as a Global Positioning System (GPS) receiver. As another example, sensor 544-6 is a speedometer. As another example, sensor 544-4 represents several engine sensors, such as a temperature sensor, pressure sensor, voltmeter, ammeter, tachometer, fuel gauge, etc. As another example, sensor 544-4 represents a camera.

[0067] In some embodiments, system 500 may be associated with a vehicle's braking system and may receive time-based telemetry sensor data from camera sensor 544, temperature sensor 544, and / or acoustic sensor 544. In some embodiments, system 500 may be associated with a vehicle's heating / cooling system and may receive time-based telemetry sensor data from temperature sensor 544 and / or acoustic sensor 544. In some embodiments, system 500 may be associated with an ambient noise system and may receive time-based telemetry sensor data from acoustic sensor 544.

[0068] The host 502 can execute instructions to provide a general control system and / or operating system for the vehicle 550. The host 502 can be a controller designed to assist in the automated operation of the vehicle 550. For example, the host 502 can be an Advanced Driver Assistance System (ADAS) controller. ADAS can monitor data to prevent accidents and provide warnings of potential unsafe situations. For example, ADAS can monitor sensors in the vehicle 550 and control the operation of the vehicle 550 to avoid accidents or injuries (e.g., to avoid accidents when the user of the vehicle is incapacitated). The host 502 is expected to act and make decisions quickly to avoid accidents. The memory subsystem 504 can store reference data in a non-volatile memory device 516, allowing the host 502 to compare time-based telemetry sensor data from sensor 544 with the reference data to make rapid decisions.

[0069] Figure 6 This diagram illustrates a portion of a memory array 665 having a physical block 662 coupled to a controller 606, according to some embodiments of the present disclosure. The controller 606 may be similar to... Figure 1The memory subsystem controller 606 is described herein. Controller 606 may further include a sequence tracking component 612. As described herein, in some embodiments, the sequence tracking component 612 may cause controller 606 to perform the operations described herein with respect to sequence tracking component 112.

[0070] For example, memory array 665 can represent Figure 1 The memory array 665 of the non-volatile memory device 116. The memory array 665 can be, for example, a NAND flash memory array. As an additional example, the memory array 665 can be an SCM array, such as a three-dimensional cross-point (3D cross-point) memory array, a ferroelectric RAM (FRAM) array, or a resistive variable memory array, such as PCRAM, RRAM, or a spin torque transfer (STT) array, etc. Furthermore, although... Figure 6 Not shown, but the memory array 665 can be located on a specific semiconductor die along with various peripheral circuitry systems associated with its operation.

[0071] like Figure 6 As shown, the memory array 665 has several physical blocks 662-1 (block 1), 662-2 (block 2), ..., 662-B (block B) of memory cells. The memory cells can be operated with characteristics tailored to the performance targets of the circular buffers or snapshots described herein. The several physical blocks 662 of the memory cells may be contained within a plane of the memory cells, and the several planes of the memory cells may be contained on a die. For example, in... Figure 6 In the example shown, each physical block 662 can be a portion of a single die. That is, Figure 6 The portion of the memory array 665 described herein may be a bare die of a memory cell.

[0072] like Figure 6 As shown, each physical block 662 contains several physical rows (e.g., rows 658-1, 658-2, ..., 658-R) of memory cells coupled to access lines (e.g., word lines). Furthermore, although... Figure 6 Not shown, but memory cells may be coupled to sensing lines (e.g., data lines and / or digital lines). Those skilled in the art will understand that each row 658 may contain several pages (e.g., physical pages) of memory cells. Physical pages refer to programming and / or sensing units (e.g., several memory cells programmed and / or sensed together as a functional group). Figure 6In the embodiments shown, each row 658 includes a physical page of a memory cell. However, embodiments of this disclosure are not limited thereto. For example, in embodiments, each row may include multiple physical pages of memory cells (e.g., one or more even-numbered pages of memory cells coupled to even-numbered bit lines and one or more odd-numbered pages of memory cells coupled to odd-numbered bit lines). Additionally, for embodiments including multi-level units, the physical pages of memory cells may store multiple logical pages of data (e.g., an upper page and a lower page of data, wherein each cell in a physical page stores one or more bits near the upper page and one or more bits near the lower page).

[0073] like Figure 6 As shown, a row of memory cells 658 may include several physical sectors 660-1, 660-2, ..., 660-S (e.g., subsets of memory cells). Each physical sector 660 of the cell may store several logical sectors of data. Additionally, each logical sector of data may correspond to a portion of a specific page of data. As an example, one logical sector of data stored in a specific physical sector may correspond to a logical sector corresponding to a page of data, and other logical sectors of data stored in a specific physical sector may correspond to other pages of data. Each physical sector 660 may store system data, user data, and / or overhead data, such as error correction code (ECC) data, LBA data, and metadata.

[0074] Figure 7 The diagram illustrates a plurality of memory dies 754 having a superblock 734 according to some embodiments of the present disclosure. Each memory die 754-1, 754-2, and 754-3 may correspond to Figure 7 The memory array / die 754 and the memory device 716 coupled to the controller 706 (similar to) Figure 1 The memory device 116 described herein. The controller 706 may be similar to... Figure 1 The memory subsystem controller 106 is described herein. Controller 706 may further include a sequence tracking component 712. As described herein, in some embodiments, the sequence tracking component 712 may cause controller 706 to perform the operations described herein with respect to sequence tracking component 112.

[0075] Each memory die 754-1, 754-2, and 754-3 may contain multiple planes. For example... Figure 7The description, for example, shows that memory die 754-1 contains two planes 771-1 (plane 0) and 771-2 (plane 1); memory die 754-2 contains two planes 771-3 (plane 0) and 771-4 (plane 1); and memory die 754-3 contains two planes 771-5 (plane 0) and 771-6 (plane 1), but each memory die is not limited to a specific number of planes it may contain.

[0076] As used herein, the term "superblock" may refer to a group of memory cells whose memory cells are distributed across multiple planes on a memory die and / or multiple memory dies. For example, such as Figure 7 The description states that the memory cells of each of superblocks 734-1 (superblock 0), 734-2 (superblock 1), 734-3 (superblock 2), and 734-P (superblock P) are distributed on corresponding portions of planes 771-1 and 771-2 of memory die 754-1, planes 771-3 and 771-4 of memory die 754-2, and planes 771-5 and 771-6 of memory die 754-3, as follows. Figure 7 The explanation is in the text. Although... Figure 7 The text describes three dies, but the superblock is not limited to a specific number of dies on which the superblock's memory cells can be distributed.

[0077] In some embodiments, erase operations can be performed on multiple blocks of a superblock simultaneously. In other words, multiple blocks forming the same superblock can be erased substantially simultaneously. Similarly, write and / or read operations can be performed on pages of a superblock simultaneously. In other words, multiple pages forming the same superblock can be written and / or read substantially simultaneously.

[0078] Figure 8 This describes an example machine of computer system 890, which contains a set of instructions executable to cause the machine to perform one or more of the methods discussed herein. In some embodiments, computer system 890 may correspond to a host system (e.g., Figure 1 The host system 102), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 104) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the sequence tracking component 112). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0079] A machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network device, a server, a network router, a switch, or a bridge, or another machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by the machine. Furthermore, although a single machine has been described, the term "machine" should also be considered to include a collection of machines that individually or collectively execute a set (or more) of instructions to perform one or more of the methods discussed herein.

[0080] The example computer system 890 includes a processing device 892, a main memory 894 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 898 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 899, which communicate with each other via a bus 897.

[0081] Processing device 892 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 892 may also be one or more special-purpose processing devices, such as an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. Processing device 892 is configured to execute instructions 893 for performing the operations and steps discussed herein. Computer system 890 may further include a network interface device 895 communicating via network 896.

[0082] Data storage system 899 may include machine-readable storage medium 891 (also referred to as computer-readable medium) storing one or more sets of instructions 893 or software embodying one or more of the methods or functions described herein. Instructions 893 may also reside wholly or at least partially within main memory 894 and / or processing device 892 during execution by computer system 890, which also constitute machine-readable storage medium. Machine-readable storage medium 891, data storage system 899, and / or main memory 894 may correspond to... Figure 1 The memory subsystem 104.

[0083] In one embodiment, instruction 893 includes implementing a sequence tracking component (e.g. Figure 1The sequence tracking component 112) contains functional instructions. Although the machine-readable storage medium 891 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include media capable of storing or encoding a set of instructions for machine execution and causing the machine to perform one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0084] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is an operation that requires the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily due to common use, it has sometimes proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0085] However, it should be remembered that all such terms and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0086] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially configured for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, optical cards, or other media types suitable for storing electronic instructions, each coupled to a computer system bus.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to execute the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0088] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes mechanisms for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0089] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the embodiments of the present disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than limiting.

Claims

1. A memory subsystem write sequence tracking system, comprising: Memory devices (114, 116); 216；516；716)； and Processing device (108), communicatively coupled to the memory device, wherein the processing device will: Data is written to several memory cell groups (334-1, ..., 334-N; 734-1, ..., 734-P) of the memory device in a physically discontinuous manner; Track the sequence of data written to the plurality of memory cell groups; and In response to a triggering event, at least in part based on the tracking sequence, an entry containing the tracking sequence is generated to identify at least a portion of the plurality of memory cell groups containing data received within a predefined period prior to the triggering event, wherein the processing means further associates the following with the entry: The logical address of a first page corresponding to at least a portion of the plurality of memory cell groups, wherein the first page corresponds to the start time of the predefined period; and The logical address of a second page corresponding to at least a portion of the plurality of memory cell groups, wherein the second page corresponds to the end time of the predefined period.

2. The system of claim 1, wherein the processing means further determines the at least said portion of the plurality of memory cell groups including the data based on: The known size of each of the plurality of memory cell groups; and The known size (335) of the data received within the predefined period prior to the triggering event.

3. The system of claim 1, wherein the processing means identifies at least the portion of the plurality of memory cell groups without storing logic to a physical L2P table.

4. The system of claim 3, wherein the memory cell groups corresponding to logical sequence entries of the L2P table do not correspond to the sequence in which the data is written to the plurality of memory cell groups.

5. The system according to any one of claims 1 to 4, wherein at least a portion of the plurality of memory cell groups corresponds to a superblock (334-1, ..., 334-N; 734-1, ..., 734-P) on a plurality of memory dies (754-1, 754-2, 754-3) of the memory device.

6. A memory subsystem write sequence tracking system, comprising: Memory devices (114, 116); 216; 516; 716), each comprising multiple blocks (334-1, ..., 334-N; 734-1, ..., 734-P) each containing multiple pages (339-1-1, ..., 339-1-Q, 339-(N-1), 339-(N-2), 339-(NB)); and Processing device (108), communicatively coupled to the memory device, wherein the processing device will: Data is written to the plurality of blocks in a physically discontinuous manner, wherein the data is sequentially written to the plurality of pages within each of the plurality of blocks; and In response to a trigger event, an entry (331) is generated comprising a sequence of data received within a predefined period prior to the trigger event being written into a first portion of the plurality of blocks, wherein the generated entry is stored in the memory device, wherein the processing device further: In response to another triggering event, an entry (331) is generated comprising a second portion of a sequence of data received within the predefined period prior to the other triggering event and written into the plurality of blocks; and The entry is stored in the memory device.

7. The system of claim 6, wherein the processing means associates the following with the entry: The logical address of the first page (339-1-3) corresponding to the first portion of the plurality of blocks, wherein the first page corresponds to the start time of the predefined period; and The logical address of the second page (339-(NB)) corresponding to the first portion of the plurality of blocks, wherein the second page corresponds to the end time of the predefined period.

8. The system according to any one of claims 6 to 7, wherein each of the plurality of blocks corresponds to a superblock (334-1, ..., 334-N; 734-1, ..., 734-P) whose memory cells are distributed on a plurality of memory dies (754-1, 754-2, 754-3) of the memory device.

9. The system according to any one of claims 6 to 7, wherein the system includes a solid-state drive to provide event recorder storage for the autonomous vehicle (550).

10. The system according to any one of claims 6 to 7, wherein the processing means identifies the first portion and the sequence of the plurality of blocks based on: The known size of each page of each of the plurality of blocks; and The number of pages within each of the plurality of blocks.

11. The system according to any one of claims 6 to 7, wherein the processing means performs a refresh operation on one of the plurality of blocks in response to a program failure in writing data to one of the plurality of blocks to copy the data from one of the plurality of blocks to another of the plurality of blocks.

12. The system of claim 11, wherein the processing means modifies the sequence in response to the refresh operation to replace one of the plurality of blocks of the sequence with the other of the plurality of blocks.

13. The system according to any one of claims 6 to 7, wherein the processing means associates a logical address corresponding to the specific page in response to a program failure following the writing of data to a specific page (339-3-X) of one of the plurality of blocks (334-3).

14. A method for tracing a write sequence in a memory subsystem, comprising: The first part of the data is sequentially written to at least the first and second pages of several pages, and the first part of the data is sequentially written to the several pages (339-1-1, ..., 334-N; 734-1, ..., 734-P) of the first block (339-1-1, ..., 339-1-Q, 339-(N-1), 339-(N-2), 339-(NB)). After the first portion of the data is sequentially written to the plurality of pages of the first block, the second portion of the data is sequentially written to the plurality of pages of the second block (339-1-1, ..., 339-1-Q, 339-(N-1), 339-(N-2), 339-(NB)), wherein the second block is not contiguous with the first block; It is determined that a triggering event has occurred when the second portion of the data is sequentially written to a specific page (339-(NB)) of the second block; The plurality of blocks are traced backward from the specific page of the second block, with the amount of data written in a known size (335) corresponding to a predefined period prior to the triggering event; The memory devices (114, 116; 216; 516; 716) generate and store entries (331) including the following: Write the amount of said data into the sequence of said plurality of blocks; and The logical address of the specific page in the second block; and In response to determining that writing a portion of the first part of the data to the second page has failed, the logical address of the first page of the first block is associated with the entry.

15. The method of claim 14, further comprising further reverse tracing of the plurality of blocks written with the amount of said data from the specific page of the second block based on the following: The known size of each of the plurality of blocks; and The known size of each of the plurality of pages in each of the plurality of blocks.

16. The method of claim 14, further comprising tracking the plurality of blocks without saving logic to a physical L2P table.

17. The method of claim 14, further comprising reading data from a plurality of pages sequentially proceeding up to the first page while retrieving the amount of data.

18. The method of claim 14, further comprising: Perform a refresh operation on the first block to copy data stored in several pages up to the first page to a third block (334-5) of the plurality of blocks; and Modify the sequence of the entries to replace the first block with the third block.

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