Method for manufacturing a semiconductor structure having an air gap region

Abstract

The present invention discloses a method for manufacturing a semiconductor structure having an air gap region, comprising: forming a sacrificial material layer and a conductive element, the sacrificial material layer laterally adjacent to the conductive element; forming a mask pattern on the conductive element and the sacrificial material layer; removing a portion of the sacrificial material layer according to the mask pattern to expose the side surface of the remaining sacrificial material layer; and performing a plasma etching process on the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer and form an air gap region adjacent to the conductive element. This method, by forming the sacrificial material layer, removing a portion of the sacrificial material layer, and performing a plasma etching process on the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer, forms an air gap region (having a dielectric constant of 1) between two conductive elements, thereby effectively reducing parasitic capacitance between the two conductive elements.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor structure with an air gap region. Background Art

[0002] As semiconductor components continue to miniaturize, the performance and density of semiconductor integrated circuits have increased significantly. When semiconductor integrated circuit manufacturing reaches sub-micron or nanometer levels, resistance-capacitance delay becomes a bottleneck for further improvements in circuit performance.

[0003] To reduce resistance-capacitance delay, one approach is to reduce the parasitic capacitance between conductors, thereby increasing the transmission speed of metal interconnects while reducing power consumption. For example, low-k dielectric materials can be used to reduce parasitic capacitance between conductors. However, with the miniaturization of semiconductor devices, the parasitic capacitance reduction effect of low-k dielectric materials is becoming increasingly insufficient. Therefore, further reducing parasitic capacitance between conductors has become a pressing issue in this field. Summary of the Invention

[0004] To solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor structure having an air gap region. This method forms an air gap region (whose dielectric constant is 1) between two conductive elements by forming a sacrificial material layer, removing a portion of the sacrificial material layer, and performing a plasma etching process on the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer, thereby effectively reducing the parasitic capacitance between the two conductive elements. It is worth noting that, compared to exposing the top surface of the sacrificial material layer and then performing a wet etching process to completely remove the sacrificial material layer, the present invention's "performing a plasma etching process on the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer" is more suitable for removing sacrificial material layers with extremely small sizes (for example, a width less than or equal to 5 nanometers).

[0005] The present invention provides a method for manufacturing a semiconductor structure with an air gap region, comprising: forming a sacrificial material layer and a conductive element, wherein the sacrificial material layer is laterally adjacent to the conductive element; forming a mask pattern on the conductive element and the sacrificial material layer; removing a portion of the sacrificial material layer according to the mask pattern to expose the side surface of the remaining sacrificial material layer; and performing a plasma etching process on the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer to form an air gap region adjacent to the conductive element.

[0006] According to some embodiments of the present invention, forming a sacrificial material layer and a conductive element includes: forming a conductive element; forming a sacrificial material to cover the conductive element; and performing a spacer etching process on the sacrificial material to form a sacrificial material layer laterally adjacent to the conductive element.

[0007] According to some embodiments of the present invention, the method further includes: before forming the mask pattern, forming a covering layer to cover the sacrificial material layer.

[0008] According to some embodiments of the present invention, forming a sacrificial material layer and a conductive element includes: sequentially forming a sacrificial material and a covering material above the sacrificial material, with the covering material being located above the sacrificial material; removing a portion of the covering material and a portion of the sacrificial material thereunder to form a sacrificial material layer and a covering layer covering the sacrificial material layer, the sacrificial material layer having a first opening, the covering layer having a second opening, and the second opening being roughly aligned with the first opening; forming a conductive element material within the first opening and the second opening and on the covering layer; and performing a grinding process on the conductive element material until the covering layer is exposed to form a conductive element laterally adjacent to the sacrificial material layer.

[0009] According to some embodiments of the present invention, removing the portion of the sacrificial material layer according to the mask pattern further comprises removing a portion of the cover layer according to the mask pattern.

[0010] According to some embodiments of the present invention, after the portion of the sacrificial material layer and the portion of the cover layer are removed according to the mask pattern, the top surface of the remaining sacrificial material layer is covered by the remaining cover layer and is not exposed.

[0011] According to some embodiments of the present invention, removing the portion of the sacrificial material layer according to the mask pattern further comprises removing a portion of the conductive element according to the mask pattern.

[0012] According to some embodiments of the present invention, removing the portion of the sacrificial material layer and the portion of the conductive element according to the mask pattern is performed using a halogen-containing plasma.

[0013] According to some embodiments of the present invention, the sacrificial material layer includes hydrocarbons.

[0014] According to some embodiments of the present invention, the plasma etching process performed on the side surface of the sacrificial material layer is performed using oxygen plasma, nitrogen plasma, hydrogen plasma, ammonia plasma, or a combination thereof.

[0015] According to some embodiments of the present invention, the width of the remaining sacrificial material layer is less than or equal to 5 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, please read the following detailed description in conjunction with the corresponding drawings:

[0017] Figures 1 to 5 Schematic cross-sectional views of various process steps of a method for fabricating a semiconductor structure with an air gap region according to an embodiment of the present invention are shown.

[0018] Figures 6 to 12Schematic cross-sectional views of various process steps of a method for fabricating a semiconductor structure with an air gap region according to an embodiment of the present invention are shown.

[0019] Description of main reference numerals:

[0020] 100 - sacrificial material, 102 - sacrificial material layer, 102s - side surface, 102t - top surface, 200 - conductive element material, 202 - conductive element, 300 - covering material, 302 - covering layer, 400, 600 - mask patterns, 500 - air gap region, w1 - width. DETAILED DESCRIPTION

[0021] The following provides a variety of different embodiments or examples of the present invention to achieve the different technical features of the subject matter provided. The elements and designs of the following specific examples are used to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, the specification discloses that a first characteristic structure is formed above a second characteristic structure, which includes an embodiment in which the first characteristic structure and the second characteristic structure are formed and in direct contact, and also includes an embodiment in which there are other characteristic structures between the first characteristic structure and the second characteristic structure, that is, the first characteristic structure and the second characteristic structure are not in direct contact. In addition, the present invention may use repeated reference symbols and / or words in various examples. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and / or the structures.

[0022] Additionally, spatially relative terms, such as "lower" and "upper," are used to conveniently describe the relative relationship of one element or feature to other elements or features in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0023] To address the problems described in the prior art, the present invention provides a method for fabricating a semiconductor structure with an air gap region. This method forms a sacrificial material layer, removes a portion of the sacrificial material layer, and then performs a plasma etching process on the side surfaces of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer. This method thereby forms an air gap region (having a dielectric constant of 1) between two conductive elements, effectively reducing parasitic capacitance between the two conductive elements.

[0024] It is worth noting that, compared to exposing the top surface of the sacrificial material layer and then performing a wet etching process to completely remove the sacrificial material layer, the present invention's "performing a plasma etching process from the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer" is more suitable for removing sacrificial material layers with extremely small sizes (for example, a width less than or equal to 5 nanometers). In detail, for removing sacrificial material layers with extremely small sizes, it may be difficult for the etching solution to penetrate during the wet etching process, resulting in incomplete etching effect. However, the present invention performs a plasma etching process from the side surface of the sacrificial material layer, so it can effectively and completely remove the sacrificial material layer to form an air gap region. Various embodiments of the manufacturing method of a semiconductor structure with an air gap region of the present invention will be described in detail below.

[0025] Figures 1 to 5 Schematic cross-sectional views of various process steps of a method for manufacturing a semiconductor structure with an air gap region according to an embodiment of the present invention are shown. Figures 1 to 5 The diagram illustrates the process steps of the front-end of line (FEOL) of a semiconductor structure.

[0026] like Figure 1 As shown, a conductive element 202 is formed. In some embodiments, a plurality of conductive elements 202 are formed, forming a conductive element array. In some embodiments, the conductive element 202 comprises a conductive material, such as a metal, a metal compound, or polysilicon. The metal may be, for example, titanium, tantalum, tungsten, aluminum, copper, molybdenum, platinum, or other suitable metals. The metal compound may be, for example, titanium nitride, tantalum nitride, tantalum carbide, tantalum silicon nitride, tungsten nitride, molybdenum nitride, molybdenum oxynitride, ruthenium oxide, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, or other suitable metal compounds. In some embodiments, the conductive element material is first deposited on a substrate (not shown), and then the conductive element material is subjected to a lithographic etching process to form the conductive element 202. In some embodiments, the substrate comprises an elemental semiconductor, including crystalline, polycrystalline, or amorphous structures of silicon or germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or gallium indium arsenide phosphide; any other suitable material; or a combination thereof. In some embodiments, the substrate is a doped substrate, such as an n-type doped substrate or a p-type doped substrate.

[0027] Continue to refer to Figure 1 After forming the conductive element 202, a sacrificial material 100 is formed to cover the conductive element 202. In some embodiments, the sacrificial material 100 includes hydrocarbons or other materials that are easily removed by a specific plasma process. In some embodiments, the sacrificial material 100 can be formed by coating.

[0028] Then, if Figure 1 and Figure 2 As shown, the sacrificial material 100 is subjected to a spacer etching process to form a sacrificial material layer 102 that is laterally adjacent to the conductive element 202. In some embodiments, the sacrificial material 100 is subjected to anisotropic plasma etching to obtain a Figure 2 The sacrificial material layer 102 is shown. In some embodiments, the width w1 of the sacrificial material layer 102 is less than or equal to 5 nanometers.

[0029] Continue to refer to Figure 2 After forming the sacrificial material layer 102, a capping layer 302 is formed to cover the sacrificial material layer 102, leaving the top surface of the sacrificial material layer 102 uncovered. In some embodiments, the capping layer 302 also covers the conductive element 202, leaving the top surface of the conductive element 202 uncovered. In some embodiments, a capping material is deposited on the sacrificial material layer 102 and the conductive element 202 to form the capping layer 302. In some embodiments, the capping layer 302 comprises a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric materials.

[0030] Then, if Figure 2 and Figure 3 As shown, a mask pattern 400 is formed on the conductive element 202 and the sacrificial material layer 102. In some embodiments, the mask pattern 400 is also formed on the capping layer 302. In some embodiments, the mask pattern 400 exposes a portion of the capping layer 302. In some embodiments, the mask pattern 400 is a hard mask. In some embodiments, a mask material (not shown) is first formed on the capping layer 302, and then the mask pattern 400 is formed through an exposure and development process.

[0031] Then, if Figure 3 and Figure 4 As shown, a portion of the sacrificial material layer 102 is removed according to the mask pattern 400 to expose the side surface 102s of the remaining sacrificial material layer 102. In some embodiments, removing the portion of the sacrificial material layer 102 according to the mask pattern 400 further includes removing the portion of the capping layer 302 exposed according to the mask pattern 400. In some embodiments, as Figure 4 As shown, the top surface 102 t of the remaining sacrificial material layer 102 is covered by the remaining capping layer 302 and is not exposed.

[0032] In some embodiments, removing the portion of the sacrificial material layer 102 according to the mask pattern 400 also includes removing a portion of the conductive element 202 according to the mask pattern 400. In some embodiments, removing the portion of the sacrificial material layer 102 and the portion of the conductive element 202 according to the mask pattern 400 is performed using a halogen-containing plasma (e.g., a CF4-containing plasma). In some embodiments, the halogen-containing plasma can also be used to remove the exposed portion of the capping layer 302. In other words, the exposed portion of the capping layer 302 and the underlying portion of the sacrificial material layer 102 and the portion of the conductive element 202 can be removed according to the mask pattern 400, thereby exposing the remaining side surfaces 102s of the sacrificial material layer 102.

[0033] Then, if Figure 4 and Figure 5 As shown, a plasma etching process is performed on the side surfaces 102s of the remaining sacrificial material layer 102 to completely remove the remaining sacrificial material layer 102, thereby forming an air gap region 500 adjacent to the conductive element 202. Because a plasma etching process is used to remove the remaining sacrificial material layer 102, rather than a wet etching process, incomplete etching due to poor etching solution penetration is avoided. The method for forming the air gap region 500 described herein can be applied to remove sacrificial material layers of extremely small dimensions (e.g., width less than or equal to 5 nanometers).

[0034] Figures 6 to 12 Schematic cross-sectional views of various process steps of a method for manufacturing a semiconductor structure with an air gap region according to an embodiment of the present invention are shown. Figures 6 to 12 The diagram illustrates the process steps of the backend of line (BEOL) of a semiconductor structure.

[0035] like Figure 6 As shown, in some embodiments, a sacrificial material 100 and a capping material 300 are sequentially formed, with the capping material 300 located above the sacrificial material 100. In some embodiments, the sacrificial material 100 comprises a hydrocarbon or other material that is easily removed by a specific plasma process. In some embodiments, the capping material 300 comprises a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric material. In some embodiments, the sacrificial material 100 can be formed by coating. In some embodiments, the capping material 300 can be formed by deposition. In some embodiments, the sacrificial material 100 and the capping material 300 can be sequentially formed on a substrate (not shown).

[0036] Then, if Figure 6 and Figure 7As shown, a portion of the covering material 300 and a portion of the sacrificial material 100 thereunder are removed to form a sacrificial material layer 102 and a covering layer 302 covering the sacrificial material layer 102. Figure 7 As shown, the sacrificial material layer 102 has a first opening 102a, and the cover layer 302 has a second opening 302a, which is substantially aligned with the first opening 102a. The term "substantially aligned" means that the second opening 302a and the first opening 102a are completely overlapped or nearly completely overlapped in their vertical projections.

[0037] In some embodiments, as Figure 6 and Figure 7 As shown, an etching process is performed based on the mask pattern 600 to remove the portion of the capping material 300 and the portion of the sacrificial material 100 thereunder. In some embodiments, a mask material (not shown) is first formed on the capping material 300, and then the mask material is exposed and developed to form the mask pattern 600. In some embodiments, the mask pattern 600 is a hard mask comprising a metal nitride, such as titanium nitride. In some embodiments, the etching process is, for example, a wet etching process or a dry etching process (e.g., a plasma etching process).

[0038] Then, if Figure 7 and Figure 8 As shown, a conductive element material 200 is formed in the first opening 102a and the second opening 302a and on the capping layer 302. In some embodiments, the conductive element material 200 includes a conductive material, such as a metal, a metal compound, or polysilicon. In some embodiments, the conductive element material 200 can be formed by electroplating, chemical plating, or deposition.

[0039] Then, if Figure 8 and Figure 9 As shown, the conductive element material 200 is subjected to a grinding process until the cover layer 302 is exposed to form the conductive element 202 laterally adjacent to the sacrificial material layer 102. In some embodiments, as shown in FIG. Figure 9 As shown, the capping layer 302 laterally abuts the conductive element 202. In some embodiments, the polishing process is, for example, a chemical mechanical polishing process.

[0040] Then, if Figure 9 and Figure 10As shown, a mask pattern 400 is formed on the conductive element 202 and the sacrificial material layer 102. In some embodiments, the mask pattern 400 is also formed on the capping layer 302. In some embodiments, a mask material (not shown) is first formed on the capping layer 302, and then the mask material is exposed and developed to form the mask pattern 400. In some embodiments, the mask pattern 400 is a hard mask. In some embodiments, the mask pattern 400 exposes a portion of the capping layer 302 and a portion of the conductive element 202.

[0041] Then, if Figure 10 and Figure 11 As shown, a portion of the sacrificial material layer 102 is removed according to the mask pattern 400 to expose the side surface 102s of the remaining sacrificial material layer 102. In some embodiments, the width w1 of the remaining sacrificial material layer 102 is less than or equal to 5 nanometers. In some embodiments, removing the portion of the sacrificial material layer 102 according to the mask pattern 400 also includes removing a portion of the cover layer 302 according to the mask pattern 400. In some embodiments, as Figure 11 As shown, the top surface 102 t of the remaining sacrificial material layer 102 is covered by the remaining capping layer 302 and is not exposed.

[0042] In some embodiments, removing the portion of the sacrificial material layer 102 according to the mask pattern 400 also includes removing a portion of the conductive element 202 according to the mask pattern 400. In some embodiments, removing the portion of the sacrificial material layer 102 and the portion of the conductive element 202 according to the mask pattern 400 utilizes a halogen-containing plasma. In some embodiments, the halogen-containing plasma may also be used to remove the portion of the capping layer 302. In other words, the exposed portion of the capping layer 302, the underlying portion of the sacrificial material layer 102, and the exposed portion of the conductive element 202 may be removed according to the mask pattern 400, thereby exposing the remaining side surfaces 102s of the sacrificial material layer 102.

[0043] Then, if Figure 11 and Figure 12 As shown, a plasma etching process is performed on the side surfaces 102s of the remaining sacrificial material layer 102 to completely remove the remaining sacrificial material layer 102, thereby forming an air gap region 500 adjacent to the conductive element 202. Because a plasma etching process is used to remove the remaining sacrificial material layer 102, rather than a wet etching process, incomplete etching due to poor etching solution penetration is avoided. The method for forming the air gap region 500 described herein can be applied to remove sacrificial material layers of extremely small dimensions (e.g., width less than or equal to 5 nanometers).

[0044] The features of various embodiments have been briefly mentioned above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same objectives and / or obtain the same advantages as the embodiments set forth herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alternatives may be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor structure having an air gap region, characterized in that: include: forming a sacrificial material layer and a conductive element, the sacrificial material layer laterally adjacent to the conductive element; forming a mask pattern on the conductive element and the sacrificial material layer; removing a portion of the sacrificial material layer according to the mask pattern to expose a side surface of the remaining sacrificial material layer; as well as A plasma etching process is performed on the side surface of the remaining sacrificial material layer to completely remove the remaining sacrificial material layer to form the air gap region adjacent to the conductive element, wherein a width of the remaining sacrificial material layer is less than or equal to 5 nanometers.

2. The manufacturing method according to claim 1, wherein Forming the sacrificial material layer and the conductive element includes: forming a conductive element; forming a sacrificial material covering the conductive element; and A spacer etching process is performed on the sacrificial material to form the sacrificial material layer laterally adjacent to the conductive element.

3. The manufacturing method according to claim 1, wherein: Also includes: Before forming the mask pattern, a covering layer is formed to cover the sacrificial material layer.

4. The manufacturing method according to claim 3, wherein: Forming the sacrificial material layer and the conductive element includes: forming a sacrificial material and a covering material in sequence, wherein the covering material is located above the sacrificial material; removing a portion of the covering material and a portion of the sacrificial material thereunder to form the sacrificial material layer and the covering layer covering the sacrificial material layer, wherein the sacrificial material layer has a first opening, and the covering layer has a second opening, and the second opening is aligned with the first opening; forming a conductive element material in the first opening and the second opening and on the cover layer; and The conductive element material is subjected to a grinding process until the cover layer is exposed to form the conductive element laterally adjacent to the sacrificial material layer.

5. The manufacturing method according to claim 3, wherein: Removing the portion of the sacrificial material layer according to the mask pattern further includes removing a portion of the cover layer according to the mask pattern.

6. The manufacturing method according to claim 5, wherein: After the portion of the sacrificial material layer and the portion of the cover layer are removed according to the mask pattern, the top surface of the remaining sacrificial material layer is covered by the remaining cover layer and is not exposed.

7. The manufacturing method according to claim 1, wherein: Removing the portion of the sacrificial material layer according to the mask pattern further includes removing a portion of the conductive element according to the mask pattern.

8. The manufacturing method according to claim 7, wherein: Removing the portion of the sacrificial material layer and the portion of the conductive element according to the mask pattern uses halogen-containing plasma.

9. The manufacturing method according to claim 1, wherein: The sacrificial material layer includes hydrocarbon.

10. The manufacturing method according to claim 1, wherein The plasma etching process is performed from the side surface of the sacrificial material layer using oxygen plasma, nitrogen plasma, hydrogen plasma, ammonia plasma or a combination thereof.

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