Semiconductor package including stacked semiconductor chips and method of manufacturing the same

Abstract

The present application relates to a semiconductor package including stacked semiconductor chips and a method of manufacturing the same. A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number greater than 1), which are sequentially offset and stacked above the base layer such that chip pad portions of one side edge region are exposed, wherein the chip pad portions include chip pads and include redistribution pads that are in partial contact with the chip pads and extend away from the chip pads; and bonding wirings that, when k is a natural number greater than 1, connect the chip pads of the kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pads of the (k - 1)th semiconductor chip or the (k + 1)th semiconductor chip, and that, when k is 1, connect the chip pads of the kth semiconductor chip to the pads of the base layer or the redistribution pads of the (k + 1)th semiconductor chip.

Description

Technical Field

[0001] This patent document relates to semiconductor packages, and more particularly, to semiconductor packages including a plurality of semiconductor chips stacked in a vertical direction. Background Art

[0002] Electronic products require a large amount of data processing while their sizes are getting smaller and smaller. Therefore, the demand for improving the integration of semiconductor devices used in such electronic products is increasing.

[0003] However, due to the limitations of semiconductor integration technology, it is difficult to meet the required functions with only a single semiconductor chip. Therefore, semiconductor packages in which a plurality of semiconductor chips are embedded have been manufactured.

[0004] A plurality of semiconductor chips can be stacked in a vertical direction and can be electrically connected to each other through bonding wirings. Summary of the Invention

[0005] In one embodiment, a semiconductor package may include: a base layer; a first semiconductor chip to an Nth semiconductor chip, the first semiconductor chip to the Nth semiconductor chip being sequentially offset and stacked above the base layer such that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that is in partial contact with the chip pad and extends away from the chip pad, wherein N is a natural number greater than 1; and bonding wirings that, when k is a natural number greater than 1, connect the chip pad of the kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip to the redistribution pad of the (k - 1)th semiconductor chip or the (k + 1)th semiconductor chip, and that, when k is 1, connect the chip pad of the kth semiconductor chip to the pad of the base layer or the redistribution pad of the (k + 1)th semiconductor chip.

[0006] In another embodiment, a method for manufacturing a semiconductor package may include: forming a base layer; forming a first semiconductor chip to an Nth semiconductor chip above the base layer, the first semiconductor chip to the Nth semiconductor chip being sequentially offset and stacked such that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that is in partial contact with the chip pad and extends away from the chip pad, wherein N is a natural number of 2 or greater; and forming bonding wirings that connect the chip pad of the kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip to the redistribution pad of the (k - 1)th semiconductor chip or the (k + 1)th semiconductor chip when k is a natural number greater than 1, and that connect the chip pad of the kth semiconductor chip to the pad of the base layer or the redistribution pad of the (k + 1)th semiconductor chip when k is 1. Brief Description of the Drawings

[0007] Figure 1A is a cross-sectional view of a semiconductor package illustrating a comparative example.

[0008] Figure 1B is a plan view of a part of the semiconductor package Figure 1A viewed from the top.

[0009] Figures 2A to 2C is a cross-sectional view illustrating an example of a method of forming bonding wirings in a semiconductor package according to a comparative example.

[0010] Figures 3A to 3E is a cross-sectional view illustrating another example of a method of forming bonding wirings in a semiconductor package according to a comparative example.

[0011] Figure 4A is a cross-sectional view of a semiconductor package illustrating an embodiment according to the present disclosure.

[0012] Figure 4B is a plan view of the semiconductor package Figure 4A viewed from the top.

[0013] Figure 4C illustrates Figure 4A an enlarged perspective view of a chip pad portion of the semiconductor package.

[0014] Figure 4D illustrates Figure 4A an enlarged cross-sectional view of a chip pad portion of the semiconductor package and bonding wirings connected to the chip pad portion.

[0015] Figure 5A and Figure 5B are cross-sectional views illustrating examples of a method of forming bonding wirings in the semiconductor package Figure 4A and Figure 4B respectively.

[0016] Figure 6 is a cross-sectional view illustrating a semiconductor package and a bonding wiring forming method according to another embodiment of the present disclosure.

[0017] Figure 7 is a cross-sectional view illustrating a semiconductor package and a bonding wiring forming method according to another embodiment of the present disclosure.

[0018] Figure 8 shows a block diagram illustrating an electronic system that employs a memory card including a semiconductor package according to an embodiment.

[0019] Figure 9 shows a block diagram illustrating another electronic system that includes a semiconductor package according to an embodiment. Detailed implementation manners

[0020] Hereinafter, various implementation manners of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the accompanying drawings may have been exaggerated in order to clearly illustrate some features of the described implementation manners. When presenting a specific example in an accompanying drawing or description having two or more layers in a multi-layer structure, the relative positional relationship of the layers shown or the arrangement order of these layers reflects a specific implementation of the described or illustrated example, and different relative positional relationships or arrangement orders of the layers are also possible. Additionally, the example of the multi-layer structure described or illustrated may not reflect all the layers present in the specific multi-layer structure (for example, there may be one or more additional layers between the two layers shown). As a specific example, when the first layer in the described or illustrated multi-layer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0022] Before describing this implementation manner, a semiconductor package of a comparative example, a method of forming bonding wirings in the semiconductor package of the comparative example, and problems thereof will be described.

[0023] Figure 1A is a cross-sectional view illustrating a semiconductor package of a comparative example, and Figure 1B is a plan view of a part of the Figure 1A semiconductor package as viewed from the top.

[0024] Referring to Figure 1A and Figure 1B the semiconductor package of the comparative example may include a base layer 100, a chip stack 110, a molding layer 130, and external connection electrodes 140.

[0025] The base layer 100 may be a layer having a circuit and / or wiring structure (not shown) for electrically connecting the chip stack 110 to external components of the semiconductor package. For example, the base layer 100 may include a substrate such as a printed circuit board (PCB), an intervening layer, a redistribution layer, etc. Alternatively, when the chip stack 110 includes a memory chip, the base layer 100 may be a semiconductor chip having a logic circuit that supports the operation of the memory chip, for example, reading data from the memory chip or writing data to the memory chip.

[0026] The base layer 100 may have one surface (e.g., the upper surface) on which the chip stack 110 is disposed and another surface (e.g., the lower surface) on which the external connection electrodes 140 are disposed. The pads 102 for electrically connecting to the chip stack 110 may be disposed on the upper surface of the base layer 100. The pads 102 may be part of the circuit and / or wiring structure of the base layer 100. In addition, although not shown, various pads for making electrical connections between the base layer 100 and other components (such as the external connection electrodes 140) may be further disposed on the upper surface and / or the lower surface of the base layer 100.

[0027] The chip stack 110 may include a plurality of semiconductor chips 110-1 to 110-8 stacked vertically above one surface of the base layer 100. In this comparative example, the chip stack 110 includes eight semiconductor chips 110-1 to 110-8, but the number of semiconductor chips included in the chip stack 110 may be modified in various ways. For ease of description, based on the distance from the base layer 100, the plurality of semiconductor chips 110-1 to 110-8 will be referred to as the first semiconductor chip 110-1, the second semiconductor chip 110-2, the third semiconductor chip 110-3, the fourth semiconductor chip 110-4, the fifth semiconductor chip 110-5, the sixth semiconductor chip 110-6, the seventh semiconductor chip 110-7, and the eighth semiconductor chip 110-8. The first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 may be the same memory chips, for example, NAND flash memory chips. However, the present disclosure is not limited thereto, and the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 may be semiconductor chips of various types and functions.

[0028] A plurality of chip pads 112 may be disposed on the upper surface of each of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8. The plurality of chip pads 112 may be disposed at one side edge region in the first direction of each of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8. The first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 may be stacked such that the upper surface on which the chip pads 112 are disposed faces upward and the lower surface faces the base layer 100, that is, face-up type. In this case, the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 may be offset and stacked in a direction from one side adjacent to the chip pads 112 in the first direction toward the other side positioned opposite to the one side in the first direction, so that all the chip pads 112 of each of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 can be exposed. In a second direction intersecting the first direction, one side of each of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 may be substantially aligned with each other, and the other side of each of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 may be substantially aligned with each other.

[0029] In each of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8, the plurality of chip pads 112 may be arranged in a row along the second direction. The corresponding chip pads 112 of the first semiconductor chip 110-1 to the eighth semiconductor chip 110-8 (for example, the chip pads 112 substantially aligned with each other in the first direction) may be connected to each other by bonding wirings 120 and may be connected to the pads 102 of the base layer 100. Therefore, the chip pads can be used as terminals for receiving power from the base layer 100 or exchanging signals with the base layer 100.

[0030] The molding layer 130 may cover the chip stack 110 above the upper surface of the base layer 100. The molding layer 130 may include various molding materials such as EMC (epoxy molding compound).

[0031] The external connection electrodes 140 may be formed above the lower surface of the base layer 100 and may function to connect to external components of the semiconductor package. The external connection electrodes 140 may include various interconnectors such as solder balls.

[0032] In the above semiconductor package, the method of forming the bonding wirings 120 will be described in more detail with reference to Figures 2A to 3E more specifically below.

[0033] Figures 2A to 2CIt is a cross-sectional view illustrating an example of a method for forming bonding wirings in a semiconductor package according to a comparative example. For ease of description, only a part of the semiconductor package of the comparative example is illustrated, that is, a part of the base layer 100 and the first semiconductor chip 110-1 to the third semiconductor chip 110-3.

[0034] Referring Figure 2A , the first bonding wiring 120-1 that connects the chip pad 112 of the first semiconductor chip 110-1 to the pad 102 of the base layer 100 can be formed by using a capillary CP that performs a wire bonding process.

[0035] More specifically, first, the capillary CP can move above the chip pad 112 of the first semiconductor chip 110-1 to perform ball bonding, and thereby the first ball bump 121-1 that is bonded to the chip pad 112 of the first semiconductor chip 110-1 can be formed (see ).

[0036] Subsequently, when the capillary CP moves in the direction toward the pad 102 of the base layer 100, the first wiring loop 123-1 that extends from the first ball bump 121-1 can be formed (see ).

[0037] Subsequently, the capillary CP can move above the pad 102 of the base layer 100 to perform stitch bonding, and thereby the first joint portion 125-1 that is bonded to the pad 102 of the base layer 100 can be formed (see ).

[0038] As a result, the first bonding wiring 120-1 having the first ball bump 121-1, the first wiring loop 123-1, and the first joint portion 125-1 can be formed.

[0039] Referring Figure 2B , the second bonding wiring 120-2 that connects the chip pad 112 of the second semiconductor chip 110-2 to the chip pad 112 of the first semiconductor chip 110-1 can be formed. The method for forming the second bonding wiring 120-2 can be substantially the same as the method for forming the first bonding wiring 120-1.

[0040] More specifically, first, the capillary CP can move above the chip pad 112 of the second semiconductor chip 110-2 to perform ball bonding, and thereby the second ball bump 121-2 that is bonded to the chip pad 112 of the second semiconductor chip 110-2 can be formed (see ).

[0041] Subsequently, when the bonding tool CP moves in the direction toward the chip pad 112 of the first semiconductor chip 110-1, a second wiring loop 123-2 extending from the second ball bump 121-2 can be formed (see ).

[0042] Subsequently, the bonding tool CP can move above the chip pad 112 of the first semiconductor chip 110-1 to perform a wire bonding, and thereby a second bonding portion 125-2 can be formed (see ). At this time, since a part of the first bonding wiring 120-1 (specifically, the first ball bump 121-1) exists above the chip pad 112 of the first semiconductor chip 110-1, the second bonding portion 125-2 can be bonded to the first ball bump 121-1.

[0043] As a result, a second bonding wiring 120-2 having the second ball bump 121-2, the second wiring loop 123-2, and the second bonding portion 125-2 can be formed. The method of forming the second bonding wiring 120-2 can be referred to as a forward bonding method.

[0044] Referring to Figure 2C , a third bonding wiring 120-3 connecting the chip pad 112 of the third semiconductor chip 110-3 to the chip pad 112 of the second semiconductor chip 110-2 can be formed by a process substantially the same as the process described in Figure 2B . The third bonding wiring 120-3 can include a third ball bump 121-3, a third wiring loop 123-3, and a third bonding portion 125-3.

[0045] Although not shown, bonding wirings connecting a plurality of semiconductor chips stacked above the third semiconductor chip 110-3 can be formed by repeating a process substantially the same as the process described in Figure 2B . As a reference, the bonding wiring can include a metal such as gold, silver, copper, platinum, or an alloy thereof that can be bonded to the chip pad 112.

[0046] However, when the size and pitch of the chip pad 112 are small, it may be difficult to use the method in Figures 2A to 2CThe bonding wire forming method described in [reference], i.e., the forward bonding method. When the size and pitch of the chip pads 112 are small, it may be necessary to use fine wires, and for this purpose, a wire bonder with a small-diameter end such as a bottleneck bonder can be used. In this case, the contact area between the bonding wires (e.g., the contact area between the second bonding portion 125-2 of the second bonding wire 120-2 and the first ball bump 121-1 of the first bonding wire 120-1) can be relatively small. In other words, when the size and pitch of the chip pads 112 are small and a wire bonder with a corresponding small-diameter end is used, the bonding force at the contact portion between the bonding wires can be reduced, resulting in a poor connection between them.

[0047] Figures 3A to 3E FIG. [reference number] is a cross-sectional view illustrating another example of a method for forming bonding wires in a semiconductor package according to a comparative example.

[0048] Referring to Figure 3A , the first bonding wire 120-1' that connects the chip pad 112 of the first semiconductor chip 110-1 to the pad 102 of the base layer 100 can be formed by performing a process substantially the same as the process of Figure 2A . The first bonding wire 120-1' can include a first ball bump 121-1', a first wire loop 123-1', and a first bonding portion 125-1'.

[0049] Subsequently, the wire bonder CP can move above the chip pad 112 of the second semiconductor chip 110-2 to perform ball bonding, and thereby a second ball bump 121-2' bonded to the chip pad 112 of the second semiconductor chip 110-2 can be formed (see ).

[0050] Subsequently, the wire bonder CP can cut the wire on the second ball bump 121-2' such that only the second ball bump 121-2' exists above the chip pad 112 of the second semiconductor chip 110-2. The cutting of the wire can be performed by moving the wire bonder CP in the upward direction (see ).

[0051] Referring to Figure 3B , the wire bonder CP can move above the chip pad 112 of the first semiconductor chip 110-1 to perform ball bonding, and thereby an additional second ball bump 127-2' can be formed (see ) At this time, since the first ball bump 121-1' exists above the chip pad 112 of the first semiconductor chip 110-1, an additional second ball bump 127-2' can be bonded to the first ball bump 121-1'. Since the additional second ball bump 127-2' has a relatively large volume compared to the joint formed by pin bonding, the contact area with the first ball bump 121-1' can be increased, and thus the bonding can be advantageous. For reference, during this bonding, a part of the first wiring loop 123-1' on the first ball bump 121-1' can be integrated with the additional second ball bump 127-2'. As a result, the first wiring loop 123-1' can extend from the additional second ball bump 127-2'.

[0052] Subsequently, when the bonding tool CP moves in the direction toward the chip pad 112 of the second semiconductor chip 110-2, a second wiring loop 123-2' extending from the additional second ball bump 127-2' can be formed (see ).

[0053] Referring to Figure 3C , the bonding tool CP can move above the chip pad 112 of the second semiconductor chip 110-2 to perform pin bonding, and a second joint 125-2' can be formed (see ). At this time, since the second ball bump 121-2' exists on the chip pad 112 of the second semiconductor chip 110-2, the second joint 125-2' can be bonded to the second ball bump 121-2'.

[0054] As a result, a second bonding wiring 120-2' having a second ball bump 121-2', a second wiring loop 123-2', a second joint 125-2', and an additional second ball bump 127-2' can be formed. The method of forming the second bonding wiring 120-2' can be called a reverse bonding method.

[0055] The third bonding wiring 120-3' can also be formed by a process substantially the same as the processes described in Figure 3B and Figure 3C .

[0056] Referring to Figure 3D , a third ball bump 121-3' bonded to the chip pad 112 of the third semiconductor chip 110-3 can be formed.

[0057] Subsequently, the bonding tool CP can move above the chip pad 112 of the second semiconductor chip 110-2 to perform ball bonding, and thus an additional third ball bump 127-3' bonded to the second ball bump 121-2' can be formed (see ).

[0058] Subsequently, when the bonding head CP moves in the direction toward the chip pad 112 of the third semiconductor chip 110-3, a third wiring loop 123-3′ extending from the additional third ball bump 127-3′ can be formed (see ).

[0059] Referring to Figure 3E , one end of the third wiring loop 123-3′ can be stitch-bonded, and thereby a third bonding portion 125-3′ bonded to the third ball bump 121-3′ can be formed.

[0060] As a result, a third bonding wiring 120-3′ having the third ball bump 121-3′, the third wiring loop 123-3′, the third bonding portion 125-3′, and the additional third ball bump 127-3′ can be formed.

[0061] Although not shown, bonding wirings connecting a plurality of semiconductor chips to be additionally stacked above the third semiconductor chip 110-3 can be formed by repeating a process substantially the same as the process described in Figure 3B and Figure 3C .

[0062] In the case of the bonding wiring forming method (i.e., the reverse bonding method) described in Figures 3A to 3D , the contact area between the bonding wirings (e.g., the contact area between the additional second ball bump 127-2′ of the second bonding wiring 120-2′ and the first ball bump 121-1′ of the first bonding wiring 120-1′) can be increased.

[0063] However, even in this case, a plurality of bonding stresses can be applied to one chip pad 112. For example, ball bonding for forming the second ball bump 121-2′, stitch-bonding for forming the second bonding portion 125-2′, and ball bonding for forming the additional third ball bump 127-3′ can be performed on the chip pad 112 of the second semiconductor chip 110-2. That is, three bonding stresses can be applied to the chip pad 112 of the second semiconductor chip 110-2. Such bonding stresses may cause a poor connection between the chip pad 112 and the bonding wiring.

[0064] In the present disclosure, a semiconductor package including a chip pad portion having a new structure and a method of forming bonding wirings in the semiconductor package can be provided to solve the problems of the above comparative example.

[0065] Figure 4A is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure, and Figure 4B is a plan view of the semiconductor package observed from the top of Figure 4A . Figure 4C IllustratesFigure 4A An enlarged perspective view of a chip pad portion of a semiconductor package, and Figure 4D is an enlarged cross-sectional view that illustrates Figure 4A a chip pad portion of a semiconductor package and bonding wirings connected to the chip pad portion. In Figure 4A and Figure 4B , for ease of description, only a base layer and three semiconductor chips stacked above one surface of the base layer are illustrated. However, similar to the cases shown in Figure 1A and Figure 1B , the semiconductor package of the present embodiment may include a plurality (e.g., eight) of semiconductor chips stacked above one surface of the base layer, a molding layer covering the plurality of semiconductor chips, and external connection electrodes formed above the other surface of the base layer.

[0066] First, referring to Figure 4A and Figure 4B , the semiconductor package of the present embodiment may include: a base layer 200; first semiconductor chips 210-1 to third semiconductor chips 210-3, which are stacked above one surface of the base layer 200; a first bonding wiring 220-1, which connects the base layer 200 and the first semiconductor chip 210-1 to each other; a second bonding wiring 220-2, which connects the first semiconductor chip 210-1 and the second semiconductor chip 210-2 to each other; and a third bonding wiring 220-3, which connects the second semiconductor chip 210-2 and the third semiconductor chip 210-3 to each other.

[0067] The base layer 200 may be a layer having a circuit and / or wiring structure (not shown) for electrically connecting the first semiconductor chips 210-1 to third semiconductor chips 210-3 to external components of the semiconductor package. The base layer 200 may have one surface (e.g., an upper surface) on which the first semiconductor chips 210-1 to third semiconductor chips 210-3 are disposed and another surface (e.g., a lower surface) on which external connection electrodes (not shown) are disposed. Pads 202 for electrically connecting to the first semiconductor chips 210-1 to third semiconductor chips 210-3 may be disposed on the upper surface of the base layer 200. The pads 202 may be a part of the circuit and / or wiring structure of the base layer 200.

[0068] The first semiconductor chips 210-1 to third semiconductor chips 210-3 may be stacked above one surface of the base layer 200 in a vertical direction. As described above, the number of semiconductor chips stacked above one surface of the base layer 200 in the vertical direction may be modified in various ways.

[0069] A plurality of chip pads 212 may be disposed above the upper surface of each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3. The plurality of chip pads 212 may be disposed at one side edge region of each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3 in a first direction. The first semiconductor chip 210-1 to the third semiconductor chip 210-3 may be stacked in a face-up type in which the upper surface provided with the chip pads 212 faces upward and the lower surface faces the base layer 200. At this time, the first semiconductor chip 210-1 to the third semiconductor chip 210-3 may be stacked with an offset in a direction from one side adjacent to the chip pads 212 in the first direction toward the other side positioned opposite to the one side in the first direction, so as to expose all the chip pads 212 of each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3. Hereinafter, this direction will be referred to as the offset direction. In a second direction intersecting the first direction, one side of each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3 may be substantially aligned with each other, and the other side of each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3 may be substantially aligned with each other.

[0070] In each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3, the plurality of chip pads 212 may be arranged in a row along the second direction. The corresponding chip pads 212 of the first semiconductor chip 210-1 to the third semiconductor chip 210-3 (for example, the chip pads 212 substantially aligned with each other in the first direction) may be connected to each other through bonding wirings 220-1, 220-2, and 220-3, and may be connected to the pads 202 of the base layer 200. Therefore, the chip pads may be used as terminals for receiving power from the base layer 200 or exchanging signals with the base layer 200.

[0071] In addition, on the upper surface of each of the first semiconductor chip 210-1 to the third semiconductor chip 210-3, redistribution pads 216 that partially contact each of the plurality of chip pads 212 and extend outside the chip pads 212 may be provided. Hereinafter, with reference to Figure 4C and Figure 4D the chip pad portion having the chip pads 212 and the redistribution pads 216 in contact with the chip pads 212 will be described in detail (see A1).

[0072] With reference to Figure 4C and Figure 4D the chip pad portion A1 may include a stacked structure of the chip pads 212 defined by a passivation layer PL, and the insulating patterns 214 and the redistribution pads 216 that contact the chip pads 212 and extend from the chip pads 212.

[0073] As a reference, although not shown in detail in the cross-sectional view of Figure 4A , each semiconductor chip may include a main body portion BP having various wiring structures and a passivation layer PL covering the upper surface of the main body portion BP. For ease of description, in Figure 4D , only the wiring layer WL1 of the wiring structure of the main body portion BP is shown. The wiring layer WL1 is located at the top of the main body portion BP and its upper surface is at the same height as the upper surface of the main body portion BP. The passivation layer PL may have an opening exposing a part of the wiring layer WL1, and this part of the wiring layer WL1 exposed through the opening of the passivation layer PL may correspond to the chip pad 212.

[0074] The passivation layer PL may include an insulating material. The passivation layer PL may include various polymer-based insulating materials such as polyimide-isoisoindolinquinone (PIQ). The upper surface of the passivation layer PL may be located above the upper surface of the main body portion BP and the upper surface of the chip pad 212, and the side surface of the passivation layer PL adjacent to the opening may have an inclined shape. The opening of the passivation layer PL and the chip pad 212 defined by the opening of the passivation layer PL may have a rectangular shape having two sides in a first direction and two sides in a second direction. One side of the chip pad 212 in the first direction may be set to face the offset direction, while the other side may be set on the opposite side.

[0075] The stacked structure of the insulating pattern 214 and the redistribution pad 216 may contact a part of the chip pad 212 and may extend onto the passivation layer PL outside the chip pad 212 along the inclined side surface and the upper surface of the passivation layer PL. In the present embodiment, the stacked structure of the insulating pattern 214 and the redistribution pad 216 may contact a part of the chip pad 212 adjacent to the side facing the offset direction among the two sides of the chip pad 212 in the first direction, while extending on the passivation layer PL in the offset direction. Specifically, one end of the redistribution pad 216 may be formed to directly contact the chip pad 212. However, the present disclosure is not limited thereto, and the contact portion between the chip pad 212 and the stacked structure of the insulating pattern 214 and the redistribution pad 216, as well as the extension direction of the stacked structure of the insulating layer 214 and the redistribution pad 216, may be modified in various ways. As a result, the upper surface of the stacked structure of the insulating pattern 214 and the redistribution pad 216 may be located above the upper surface of the chip pad 212 and the upper surface of the passivation layer PL. Additionally, in a plan view, in the first direction, the redistribution pad 216 and the chip pad 212 may partially overlap.

[0076] As an example, a stacked structure of the insulating pattern 214 and the redistribution pad 216 can be formed by depositing an insulating material and a conductive material along the lower contour above the chip pad 112 and the passivation layer PL, and selectively etching the deposited materials. Alternatively, as another example, a stacked structure of the insulating pattern 214 and the redistribution pad 216 can be formed by forming the insulating pattern 214 along the lower contour above the chip pad 212 and the passivation layer PL, forming a photoresist pattern (not shown) having an opening exposing an area where the redistribution pad 216 is to be formed, and forming the redistribution pad 216 in the opening using an electroplating method. The photoresist pattern can be removed after the redistribution pad 216 is formed. The insulating pattern 214 can include various insulating materials such as polyimide or benzocyclobutene (BCB). The redistribution pad 216 can include a metal such as gold, silver, copper, or platinum, or an alloy thereof.

[0077] Although not shown, the insulating pattern 214 can be omitted. In this case, the redistribution pad 216 can be formed along the side surface and the upper surface of the passivation layer PL to be in direct contact with them while extending to the chip pad 212. Returning to Figure 4A and Figure 4B , the first bonding wire 220-1 can connect the pad 202 of the base layer 200 and the chip pad 212 of the first semiconductor chip 210-1 to each other. The first bonding wire 220-1 can include: a first ball bump 221-1 that is bonded to the chip pad 212 of the first semiconductor chip 210-1; a first bonding portion 225-1 that is bonded to the pad 202 of the base layer 200; and a first wire loop 223-1 that extends between the first ball bump 221-1 and the first bonding portion 225-1.

[0078] The second bonding wire 220-2 can connect the redistribution pad 216 of the first semiconductor chip 210-1 and the chip pad 212 of the second semiconductor chip 210-2 to each other. The second bonding wire 220-2 can include: a second ball bump 221-2 that is bonded to the chip pad 212 of the second semiconductor chip 210-2; an additional second ball bump 227-2 that is bonded to the redistribution pad 216 of the first semiconductor chip 210-1; a second wire loop 223-2 that extends from the additional second ball bump 227-2 to the second ball bump 221-2; and a second bonding portion 225-2 that is bonded to the second ball bump at one end of the second wire loop 223-2.

[0079] The third bonding wiring 220-3 can connect the redistribution pads 216 of the second semiconductor chip 210-2 and the chip pads 212 of the third semiconductor chip 210-3 to each other. The third bonding wiring 210-3 can include: a third bump 221-3 that is bonded to the chip pad 212 of the third semiconductor chip 210-3; an additional third bump 227-3 that is bonded to the redistribution pad 216 of the second semiconductor chip 210-2; a third wiring loop 223-3 that extends from the additional third bump 227-3 to the third bump 221-3; and a third joint 225-3 that is bonded to the third bump 221-3 at one end of the third wiring loop 223-3.

[0080] As described above, since the upper surface of the redistribution pad 216 is located above the upper surface of the chip pad 212 and the redistribution pad 216 extends outside the chip pad 212, the additional second bump 227-2 bonded to the redistribution pad 216 of the first semiconductor chip 210-1 can only partially contact the first bump 221-1 bonded to the chip pad 212 of the first semiconductor chip 210-1, and the additional third bump 227-3 bonded to the redistribution pad 216 of the second semiconductor chip 210-2 can only partially contact the second bump 221-2 bonded to the chip pad 212 of the second semiconductor chip 210-2. Even if the additional second bump 227-2 and the first bump 221-1 partially contact each other, the redistribution pad 216 of the first semiconductor chip 210-1 can contact the chip pad 212 of the first semiconductor chip 210-1 and can be electrically connected thereto. Therefore, the first bonding wiring 220-1 can be electrically connected to the second bonding wiring 220-2. Additionally, even if the additional third bump 227-3 and the second bump 221-2 partially contact each other, the redistribution pad 216 of the second semiconductor chip 210-2 can contact the chip pad 212 of the second semiconductor chip 210-2 and can be electrically connected thereto, and thus, the second bonding wiring 220-2 can be electrically connected to the third bonding wiring 220-3. In a plan view, since the chip pad 212 and the redistribution pad 216 partially overlap in a first direction, the first bump 221-1 and the additional second bump 227-2 can also partially overlap each other, and the second bump 221-2 and the additional third bump 227-3 can also partially overlap each other.

[0081] Reference will be made to Figure 4D describe in more detail the bumps and additional bumps connected to one chip pad portion A1.

[0082] Returning to reference Figure 4D, a ball bump 221 of a bonding wire can be bonded to the chip pad 212 of the chip pad portion A1, and an additional ball bump 227 of another bonding wire can be bonded to the redistribution pad 216 of the chip pad portion A1.

[0083] Here, the additional ball bump 227 can be in contact / bonded to both the upper surface of the redistribution pad 216 and a part of the ball bump 221 simultaneously. In this case, the force applied when bonding the additional ball bump 227 can be distributed to both the redistribution pad 216 and the ball bump 221, and the additional ball bump 227 can be stably supported without tilting to one side.

[0084] The portion of the ball bump 221 that contacts the additional ball bump 227 is denoted by the reference numeral P1. The upper surface of the redistribution pad 216 and the portion P1 of the ball bump 221 can be located at substantially the same height (see L1).

[0085] Figure 5A and Figure 5B are cross-sectional views illustrating examples of methods for forming bonding wires in semiconductor packages of Figure 4A and Figure 4B .

[0086] Referring to Figure 5A , a first bonding wire 220-1 that connects the chip pad 212 of the first semiconductor chip 210-1 to the pad 202 of the base layer 200 can be formed. This process can be substantially the same as the process of Figure 2A . That is, ball bonding can be performed to form a first ball bump 221-1 that is bonded to the chip pad 212 of the first semiconductor chip 210-1, a first wiring loop 223-1 that extends from the first ball bump 221-1 can be formed, and then, stitch bonding can be performed to form a first bonding portion 225-1 that is bonded to the pad 202 of the base layer 200.

[0087] Subsequently, the bonding tool CP can move above the chip pad 212 of the second semiconductor chip 210-2 to perform ball bonding, and thereby, a second ball bump 221-2 that is bonded to the chip pad 212 of the second semiconductor chip 210-2 can be formed (see ). Subsequently, the bonding tool CP can cut the wiring on the second ball bump 221-1 (see ).

[0088] Referring to Figure 5B , the bonding tool CP can move above the redistribution pad 216 of the first semiconductor chip 210-1 to perform ball bonding, and thus, an additional second ball bump 227-2 that is bonded to the redistribution pad 216 of the first semiconductor chip 210-1 can be formed (see ).

[0089] Subsequently, when the bonding head CP moves in the direction toward the chip pad 212 of the second semiconductor chip 210-2, a second wiring loop 223-2 extending from the additional second ball bump 227-2 can be formed (see ).

[0090] Subsequently, the bonding head CP can move above the chip pad 212 of the second semiconductor chip 210-2 to perform a wire bonding, and thereby a second bonding portion 225-2 bonded to the second ball bump 221-2 can be formed (see ). As a result, a second bonding wire 220-2 can be formed.

[0091] Other bonding wires for connecting semiconductor chips to each other can be formed by a process substantially the same as the process for forming the second bonding wire 220-2.

[0092] According to the semiconductor package and the bonding wire forming method described above, the following effects can be obtained.

[0093] According to the present embodiment, the connection between bonding wires can be performed without direct contact / bonding of the bonding wires as in the comparative example. In the present embodiment, the connection between bonding wires can be performed such that one end of one bonding wire is connected to a chip pad and the other end of the other bonding wire is connected to a redistribution pad, and the chip pad and the redistribution pad are connected to each other. Therefore, problems occurring in the comparative example, for example, a problem that the contact area between bonding wires decreases during forward bonding or a problem that bonding stress is applied to one chip pad multiple times during reverse bonding, and process defects resulting therefrom can all be solved.

[0094] In addition, by forming the redistribution pad to partially overlap with the chip pad, an increase in the area of the chip pad portion due to additionally forming the redistribution pad can be prevented as much as possible. If a redistribution pad extending in the offset direction is formed by using ordinary redistribution, the bonding stress may also decrease, but the offset value may increase because the redistribution pad must be exposed. This may cause an increase in the planar area of the semiconductor package. However, according to the present embodiment, since only the redistribution pad is formed without redistribution and a part of the chip pad is used as a bonding region to minimize the size of the redistribution pad, an increase in the offset value and an increase in the planar area of the semiconductor package can be minimized.

[0095] In addition, even if the redistribution pad partially overlaps with the chip pad, the upper surface of the redistribution pad can be located at a higher height than the upper surface of the chip pad, and thereby the influence between the bonding process to the redistribution pad and the bonding process to the chip pad can be minimized. That is, as an example, during the bonding process to the redistribution pad, an interference phenomenon in which the bonding tool contacts the wiring connected to the chip pad and the wiring is deformed may not occur.

[0096] Furthermore, since all problems occurring during forward bonding / reverse bonding can be solved, there is no limitation on the bonding wiring formation method in the present embodiment. In Figure 5A and Figure 5B the case where the second bonding wiring 220-2 and the third bonding wiring 220-3 are formed by the reverse bonding method has been described. In this case, since the height of the wiring loop is low, the interference between adjacent wirings can be reduced, and the movable space of the bonding tool can be increased. Therefore, the process freedom can be increased. However, the bonding wiring can be formed by the forward bonding method as shown in Figure 6 which will be described later.

[0097] Figure 6 is a cross-sectional view illustrating a semiconductor package and a bonding wiring formation method according to another embodiment of the present disclosure.

[0098] Referring to Figure 6 the semiconductor package of the present embodiment may include: a base layer 300; first to third semiconductor chips 310-1 to 310-3 stacked above one surface of the base layer 300; a first bonding wiring 320-1 connecting the base layer 300 and the first semiconductor chip 310-1 to each other; a second bonding wiring 320-2 connecting the first semiconductor chip 310-1 and the second semiconductor chip 310-2 to each other; and a third bonding wiring 320-3 connecting the second semiconductor chip 310-2 and the third semiconductor chip 310-3 to each other.

[0099] Chip pads 312 may be provided in a side edge region of the upper surface of each of the first to third semiconductor chips 310-1 to 310-3. In this case, the first to third semiconductor chips 310-1 to 310-3 may be stacked offset above the base layer 300 such that all the chip pads 312 are exposed.

[0100] In addition, on the upper surface of each of the first semiconductor chip 310-1 to the third semiconductor chip 310-3, a stacked structure of an insulating pattern 314 and a redistribution pad 316 may be formed. The stacked structure of the insulating pattern 314 and the redistribution pad 316 may extend outside the chip pad 312 while being in partial contact with the chip pad 312. In the present embodiment, the extending direction of the insulating pattern 314 and the redistribution pad 316 may be the same as the offset direction of the first semiconductor chip 310-1 to the third semiconductor chip 310-3.

[0101] The first bonding wiring 320-1 may connect the chip pad 312 of the first semiconductor chip 310-1 and the pad 302 of the base layer 300 to each other. The first bonding wiring 320-1 may include: a first ball bump 321-1 that is bonded to the chip pad 312 of the first semiconductor chip 310-1; a first bonding portion 325-1 that is bonded to the pad 302 of the base layer 300; and a first wiring loop 323-1 that extends between the first ball bump 321-1 and the first bonding portion 325-1. The first ball bump 321-1 may be formed by ball bonding, and the first bonding portion 325-1 may be formed by pin bonding.

[0102] The second bonding wiring 320-2 may connect the redistribution pad 316 of the first semiconductor chip 310-1 and the chip pad 312 of the second semiconductor chip 310-2 to each other. The second bonding wiring 320-2 may include: a second ball bump 321-2 that is bonded to the chip pad 312 of the second semiconductor chip 310-2; a second bonding portion 325-2 that is bonded to the redistribution pad 316 of the first semiconductor chip 310-1; and a second wiring loop 323-2 that extends between the second ball bump 321-2 and the second bonding portion 325-2. The second ball bump 321-2 may be formed by ball bonding, and the second bonding portion 325-2 may be formed by pin bonding.

[0103] The third bonding wiring 320-3 may connect the redistribution pad 316 of the second semiconductor chip 310-2 and the chip pad 312 of the third semiconductor chip 310-3 to each other. The third bonding wiring 320-3 may include: a third ball bump 321-3 that is bonded to the chip pad 312 of the third semiconductor chip 310-3; a third bonding portion 325-3 that is bonded to the redistribution pad 316 of the second semiconductor chip 310-2; and a third wiring loop 323-3 that extends between the third ball bump 321-3 and the third bonding portion 325-3. The third ball bump 321-3 may be formed by ball bonding, and the third bonding portion 325-3 may be formed by pin bonding.

[0104] Figure 7It is a cross-sectional view illustrating a semiconductor package and a method of forming bonding wirings according to another embodiment of the present disclosure.

[0105] Referring Figure 7 , the semiconductor package of the present embodiment may include: a base layer 400; first to third semiconductor chips 410-1 to 410-3 stacked above one surface of the base layer 400; a first bonding wiring 420-1 connecting the base layer 400 and the first semiconductor chip 410-1 to each other; a second bonding wiring 420-2 connecting the first semiconductor chip 410-1 and the second semiconductor chip 410-2 to each other; and a third bonding wiring 420-3 connecting the second semiconductor chip 410-2 and the third semiconductor chip 410-3 to each other.

[0106] Chip pads 412 may be provided in a side edge region of an upper surface of each of the first to third semiconductor chips 410-1 to 410-3. In this case, the first to third semiconductor chips 410-1 to 410-3 may be stacked offset above the base layer 400 such that all the chip pads 412 are exposed.

[0107] In addition, on an upper surface of each of the first to third semiconductor chips 410-1 to 410-3, a stacked structure of an insulating pattern 414 and a redistribution pad 416 may be formed. The stacked structure of the insulating pattern 414 and the redistribution pad 416 may extend outside the chip pad 412 while being in partial contact with the chip pad 412. In the present embodiment, the extending direction of the insulating pattern 414 and the redistribution pad 416 may be opposite to the offset direction of the first to third semiconductor chips 410-1 to 410-3.

[0108] The first bonding wiring 420-1 may connect the redistribution pad 416 of the first semiconductor chip 410-1 and the pad 402 of the base layer 400 to each other. The first bonding wiring 420-1 may include: a first ball bump 421-1 bonded to the redistribution pad 416 of the first semiconductor chip 410-1; a first bonding portion 425-1 bonded to the pad 402 of the base layer 400; and a first wiring loop 423-1 extending between the first ball bump 421-1 and the first bonding portion 425-1. The first ball bump 421-1 may be formed by ball bonding, and the first bonding portion 425-1 may be formed by pin bonding.

[0109] The second bonding wiring 420-2 can connect the chip pad 412 of the first semiconductor chip 410-1 and the redistribution pad 416 of the second semiconductor chip 410-2 to each other. The second bonding wiring 420-2 can include: a second ball bump 421-2 that is bonded to the redistribution pad 416 of the second semiconductor chip 410-2; an additional second ball bump 427-2 that is bonded to the chip pad 412 of the first semiconductor chip 410-1; a second wiring loop 423-2 that extends from the additional second ball bump 427-2 to the second ball bump 421-2; and a second bonding portion 425-2 that is bonded to the second ball bump 421-2 at one end of the second wiring loop 423-2. The second ball bump 421-2 and the additional second ball bump 427-2 can be formed by ball bonding, and the second bonding portion 425-2 can be formed by stitch bonding.

[0110] The third bonding wiring 420-3 can connect the chip pad 412 of the second semiconductor chip 410-2 and the redistribution pad 416 of the third semiconductor chip 410-3 to each other. The third bonding wiring 420-3 can include: a third ball bump 421-3 that is bonded to the redistribution pad 416 of the third semiconductor chip 410-3; an additional third ball bump 427-3 that is bonded to the chip pad 412 of the second semiconductor chip 410-2; a third wiring loop 423-3 that extends from the additional third ball bump 427-3 to the third ball bump 421-3; and a third bonding portion 425-3 that is bonded to the third ball bump 421-2 at one end of the third wiring loop 423-3. The third ball bump 421-3 and the additional third ball bump 427-3 can be formed by ball bonding, and the third bonding portion 425-3 can be formed by stitch bonding.

[0111] According to the present embodiment, all the effects described in the above embodiments of Figure 5A and Figure 5B can be obtained. In addition, the movement space of the bonding tool can be ensured to the maximum extent. In the present embodiment, different from Figure 4D , the ball bump (e.g., 421-2 in Figure 7 ) can simultaneously contact / bond to the upper surface of the redistribution pad 416 and a part of the additional ball bump (e.g., 427-3 in Figure 7 ). The portion of the additional ball bump that contacts the ball bump can be located at substantially the same height as the upper surface of the redistribution pad 416.

[0112] In Figure 7 , the case of forming the second bonding wiring 420-2 and the third bonding wiring 420-3 by the reverse bonding method has been described, but the forward bonding method described above can be used (see Figure 6)Form the second bonding wiring 420-2 and the third bonding wiring 420-3. In this case, although not shown, each of the second bonding wiring 420-2 and the third bonding wiring 420-3 may include: a ball bump that is bonded to a redistribution pad; a bonding portion that is bonded to a chip pad; and a wiring loop that extends between the ball bump and the bonding portion.

[0113] According to the above embodiments of the present disclosure, a semiconductor package capable of reducing process defects while meeting the requirements of high performance / high capacity can be provided.

[0114] Figure 8 A block diagram of an electronic system is illustrated, which includes a memory card 7800 that employs at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a non-volatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiments.

[0115] The memory 7810 may include a non-volatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 such that the stored data is read or data is stored in response to a read / write request from a host 7830.

[0116] Figure 9 A block diagram of an illustrative electronic system 8710 is shown, which includes at least one of the semiconductor packages according to the described embodiments. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 that provides a data movement path.

[0117] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands, etc. to be executed by the controller 8711.

[0118] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be mounted on an information processing system such as a mobile terminal or a desktop computer. The flash memory may form a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0119] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0120] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0121] If the electronic system 8710 represents equipment capable of performing wireless communication, the electronic system 8710 may be used in a communication system using the following technologies: CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0122] Although various embodiments have been described for exemplary purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined by the appended claims.

[0123] Cross-reference to related applications

[0124] This application claims priority to Korean Patent Application No. 10-2020-0176646, filed on December 16, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package, the semiconductor package comprising: A base layer; A first semiconductor chip to an Nth semiconductor chip, the first semiconductor chip to the Nth semiconductor chip being sequentially offset and stacked above the base layer such that a chip pad portion of a side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that is in partial contact with the chip pad and extends away from the chip pad, where N is a natural number greater than 1; and Bonding wirings, when k is a natural number greater than 1, the bonding wirings connect the chip pad of the kth semiconductor chip among the first semiconductor chip to the Nth semiconductor chip to the redistribution pad of the (k - 1)th semiconductor chip or the (k + 1)th semiconductor chip, and when k is 1, the bonding wirings connect the chip pad of the kth semiconductor chip to the pad of the base layer or the redistribution pad of the (k + 1)th semiconductor chip.

2. The semiconductor package according to claim 1, wherein, The chip pad portion further includes a passivation layer, the passivation layer having an opening exposing the chip pad, and wherein the redistribution pad extends on the passivation layer.

3. The semiconductor package according to claim 2, the semiconductor package further comprising: An insulating pattern, the insulating pattern being interposed between the redistribution pad and the passivation layer.

4. The semiconductor package according to claim 1, wherein, In a plan view, the redistribution pad and the chip pad portion overlap.

5. The semiconductor package according to claim 1, wherein The height of the upper surface of the redistribution pad is higher than the height of the upper surface of the chip pad.

6. The semiconductor package according to claim 1, wherein, The bonding wirings include: a ball bump that is bonded to one of the chip pad and the redistribution pad; a bonding portion that is bonded to the other of the chip pad and the redistribution pad; and a wiring loop that extends between the ball bump and the bonding portion.

7. The semiconductor package according to claim 1, wherein, The bonding wirings include: a ball bump that is bonded to one of the chip pad and the redistribution pad; an additional ball bump that is bonded to the other of the chip pad and the redistribution pad; a wiring loop that extends from the additional ball bump toward the ball bump; and a bonding portion that is bonded to the ball bump at one end of the wiring loop.

8. The semiconductor package according to claim 1, wherein, The redistribution pad extends in the offset direction of the first semiconductor chip to the Nth semiconductor chip, and wherein when k is a natural number greater than 1, the bonding wirings connect the chip pad of the kth semiconductor chip to the redistribution pad of the (k - 1)th semiconductor chip.

9. The semiconductor package according to claim 8, wherein, The bonding wirings include: a ball bump that is bonded to the chip pad of the kth semiconductor chip; a bonding portion that is bonded to the redistribution pad of the (k - 1)th semiconductor chip when k is a natural number greater than 1; and a wiring loop that extends between the ball bump and the bonding portion.

10. The semiconductor package according to claim 8, wherein, The bonding wiring includes: a ball bump that is bonded to the chip pad of the k-th semiconductor chip; an additional ball bump that is bonded to the redistribution pad of the (k-1)-th semiconductor chip when k is a natural number greater than 1; a wiring loop that extends from the additional ball bump toward the ball bump; and a bonding portion that is bonded to the ball bump at one end of the wiring loop.

11. The semiconductor package according to claim 10, wherein, In a plan view, when k is a natural number greater than 1, the additional ball bump bonded to the redistribution pad of the (k-1)-th semiconductor chip partially overlaps with the ball bump bonded to the chip pad of the (k-1)-th semiconductor chip.

12. The semiconductor package according to claim 10, wherein, The additional ball bump is simultaneously bonded to the upper surface of the redistribution pad and a part of the ball bump.

13. The semiconductor package according to claim 12, wherein, The upper surface of the redistribution pad and the part of the ball bump are at the same height.

14. The semiconductor package according to claim 1, wherein, The redistribution pad extends in a direction opposite to the offset direction of the first semiconductor chip to the N-th semiconductor chip, and The bonding wiring connects the chip pad of the k-th semiconductor chip to the redistribution pad of the (k + 1)-th semiconductor chip.

15. The semiconductor package according to claim 14, wherein, The bonding wiring includes: a ball bump that is bonded to the redistribution pad of the (k + 1)-th semiconductor chip; a bonding portion that is bonded to the chip pad of the k-th semiconductor chip; and a wiring loop that extends between the ball bump and the bonding portion.

16. The semiconductor package according to claim 14, wherein, The bonding wiring includes: a ball bump that is bonded to the redistribution pad of the (k + 1)-th semiconductor chip; an additional ball bump that is bonded to the chip pad of the k-th semiconductor chip; a wiring loop that extends from the additional ball bump toward the ball bump; and a bonding portion that is bonded to the ball bump at one end of the wiring loop.

17. The semiconductor package according to claim 16, wherein, In a plan view, the additional ball bump bonded to the chip pad of the k-th semiconductor chip partially overlaps with the ball bump bonded to the redistribution pad of the k-th semiconductor chip.

18. The semiconductor package according to claim 16, wherein, The ball bump is simultaneously bonded to the upper surface of the redistribution pad and a part of the additional ball bump.

19. The semiconductor package according to claim 18, wherein, The upper surface of the redistribution pad and the part of the additional ball bump are at the same height.

20. A method for manufacturing a semiconductor package, the method comprising the steps of: Forming a base layer; Forming a first semiconductor chip to an N-th semiconductor chip above the base layer, the first semiconductor chip to the N-th semiconductor chip being sequentially offset and stacked such that a chip pad portion of a side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that is in partial contact with the chip pad and extends away from the chip pad, where N is a natural number of 2 or greater; and Form a bonding wiring that, when k is a natural number greater than 1, connects the chip pad of the k-th semiconductor chip among the first to the N-th semiconductor chips to the redistribution pad of the (k - 1)-th semiconductor chip or the (k + 1)-th semiconductor chip, and when k is 1, connects the chip pad of the k-th semiconductor chip to the pad of the base layer or the redistribution pad of the (k + 1)-th semiconductor chip.

21. The method according to claim 20, wherein, The chip pad portion further includes a passivation layer having an opening exposing the chip pad, and wherein, the redistribution pad extends on the passivation layer.

22. The method according to claim 21, wherein, The chip pad portion further includes an insulating pattern interposed between the redistribution pad and the passivation layer.

23. The method according to claim 22, wherein, The insulating pattern and the redistribution pad are formed by depositing an insulating material and a conductive material above the upper surfaces of the passivation layer and the chip pad along the contours of the upper surfaces of the passivation layer and the chip pad, and selectively etching the insulating material and the conductive material.

24. The method according to claim 20, wherein The step of forming the bonding wiring includes the following steps: Form a ball bump bonded to one of the chip pad and the redistribution pad by performing ball bonding; Form a wiring loop extending from the ball bump toward the other of the chip pad and the redistribution pad; and Form a joint bonded to the other of the chip pad and the redistribution pad by performing stitch bonding.

25. The method according to claim 20, wherein The step of forming the bonding wiring includes the following steps: Form a ball bump bonded to one of the chip pad and the redistribution pad by performing ball bonding, and cut the wiring on the ball bump; Form an additional ball bump bonded to the other of the chip pad and the redistribution pad by performing ball bonding; Form a wiring loop extending from the additional ball bump toward the ball bump; and Form a joint bonded to the ball bump at one end of the wiring loop by performing stitch bonding.

26. The method according to claim 20, wherein The redistribution pad extends in the offset direction of the first to the N-th semiconductor chips, and the bonding wiring connects the chip pad of the k-th semiconductor chip to the redistribution pad of the (k - 1)-th semiconductor chip.

27. The method according to claim 26, wherein, The step of forming the bonding wiring includes the following steps: Form a ball bump bonded to the chip pad of the k-th semiconductor chip by performing ball bonding; Form a wiring loop extending from the ball bump toward the redistribution pad of the (k - 1)-th semiconductor chip, where k is a natural number greater than 1; and Form a joint bonded to the redistribution pad of the (k - 1)-th semiconductor chip by performing stitch bonding, where k is a natural number greater than 1.

28. The method according to claim 26, wherein The step of forming the bonding wiring includes the following steps: Form a ball bump bonded to the chip pad of the k-th semiconductor chip by performing ball bonding, and cut the wiring on the ball bump; Form an additional ball bump bonded to the redistribution pad of the (k - 1)-th semiconductor chip by performing ball bonding, where k is a natural number greater than 1; Form a wiring loop extending from the additional ball bump toward the ball bump; and Form a joint portion joined to the ball bump at one end of the wiring loop by performing a wire bonding.

29. The method according to claim 20, wherein, The redistribution pad extends in a direction opposite to the offset direction from the first semiconductor chip to the Nth semiconductor chip, and The bonding wiring connects the chip pad of the kth semiconductor chip to the redistribution pad of the (k + 1)th semiconductor chip.

30. The method according to claim 29, wherein The step of forming the bonding wiring includes the following steps: Form a ball bump joined to the redistribution pad of the (k + 1)th semiconductor chip by performing a ball bonding; Form a wiring loop extending from the ball bump toward the chip pad of the kth semiconductor chip; and Form a joint portion joined to the chip pad of the kth semiconductor chip by performing a wire bonding.

31. The method according to claim 29, wherein, The step of forming the bonding wiring includes the following steps: Form a ball bump joined to the redistribution pad of the (k + 1)th semiconductor chip by performing a ball bonding; Form an additional ball bump joined to the chip pad of the kth semiconductor chip by performing a ball bonding; Form a wiring loop extending from the additional ball bump toward the ball bump; and Form a joint portion joined to the ball bump at one end of the wiring loop by performing a wire bonding.

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