A demodulation circuit and method based on minimum mean square error algorithm

Abstract

The present invention relates to a demodulation circuit and method based on a minimum mean square error algorithm, which includes: a C / V conversion circuit, which is used to convert a received capacitive sensor signal into a voltage signal, and the voltage signal is a voltage signal after the basic capacitance value is offset; a digital demodulation circuit based on LMSD, which receives the voltage signal after the basic capacitance value is offset and transmitted by the C / V conversion circuit, and is used to iteratively demodulate the received voltage signal; a self-circulating digital control circuit, which is used to adjust the capacitance size of the offset capacitor array according to the amplitude component size of the digital demodulation circuit. The present invention partially offsets the basic capacitance value of the sensitive structure, and obtains a more accurate signal demodulation result through the improved LMSD iteration. The present invention can be widely used in the field of capacitive inertial sensor signal processing.

Description

Technical Field

[0001] The present invention relates to a sensor detection and integrated circuit, and in particular to a demodulation circuit and method based on a minimum mean square error algorithm for demodulating capacitive inertial sensor signals. Background Art

[0002] In order to obtain the signal of the capacitive inertial sensor, it is usually necessary to modulate the modulated signal onto a high-frequency carrier, and use the properties of high-frequency signals that are pure, easy to propagate, and have low attenuation to reduce the impact of low-frequency noise in the circuit on signal quality.

[0003] It is necessary to use a demodulation algorithm to extract the measurement signal from the modulated signal. Commonly used inertial sensor demodulation algorithms include multiplication phase-sensitive demodulation, recursive minimum variance demodulation, Kalman filtering, and minimum mean square error demodulation. Multiplication phase-sensitive demodulation multiplies the demodulated value and the reference signal and then passes it through a low-pass filter to obtain the signal amplitude. Recursive minimum variance demodulation, Kalman filtering, and minimum mean square error demodulation algorithms essentially obtain the best signal estimate by minimizing the mean square error. Compared with the classical multiplication phase-sensitive demodulation, which requires a high-order low-pass filter to filter out the frequency-multiplied components, the LMSD algorithm does not require a digital low-pass filter, which can simplify the calculation. When the traditional LMSD demodulation algorithm is directly used for capacitive sensors, due to the existence of the basic capacitance value of the sensor's sensitive structure, the voltage output range corresponding to the capacitance change in the C / V conversion circuit will be reduced, reducing the measurement resolution of the entire sensor. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a demodulation circuit based on the minimum mean square error algorithm, which combines a digitally controlled capacitor cancellation array and a LMSD-based demodulation algorithm to partially offset the basic capacitance value of the sensitive structure, and obtain a more accurate signal demodulation result through the improved LMSD iteration.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: a demodulation circuit based on the minimum mean square error algorithm, which includes: a C / V conversion circuit, which is used to convert the received capacitive sensor signal into a voltage signal, which voltage signal is a voltage signal after the basic capacitance value is offset; a digital demodulation circuit based on LMSD, which receives the voltage signal after the basic capacitance value is offset and transmitted by the C / V conversion circuit, and is used to iteratively demodulate the received voltage signal; a self-circulating digital control circuit, which is used to adjust the capacitance size of the offset capacitor array according to the amplitude component size of the digital demodulation circuit.

[0006] Furthermore, the C / V conversion circuit includes a cancellation capacitor array and a charge amplifier; the capacitive sensor signal is transmitted to the cancellation capacitor array, and the basic capacitance value in the sensitive structure is offset by the cancellation capacitor array, and the modulated signal is converted into a voltage signal by the charge amplifier.

[0007] Furthermore, the offset capacitor array uses a carrier wave with a phase opposite to that of the high-frequency carrier wave to achieve offset basic capacitance;

[0008] The offset capacitor array is composed of a plurality of capacitors connected in parallel with each other, and the capacitor gating is controlled by switches, and the state of the switches is controlled by a self-circulating digital control circuit.

[0009] Furthermore, the LMSD-based digital demodulation circuit performs single-cycle iterative calculation on the sampled signal, calculates 6 reference signal amplitude components, and realizes the update of the amplitude component result in a single clock cycle;

[0010] The LMSD-based digital demodulation circuit includes a filtering circuit, an error calculation circuit and a filter coefficient updating circuit; the filtering circuit includes a first multiplier array and a first adder array; one operand of each multiplier in the first multiplier array is a reference signal, and the other operand is an amplitude component, and the first adder array adds the results of the first multiplier array to obtain a filtered value;

[0011] The error calculation circuit obtains the error by subtracting the filtered value from the value of the sampled signal after AD conversion;

[0012] The filter coefficient updating circuit includes a second multiplier array and a second adder array, a multiplier in the second multiplier array is used to calculate the product of the step size and the error, and the calculation result is used as one of the operands of the remaining multipliers, and the other operands of the remaining multipliers are 6 reference signals in turn. The results calculated by the remaining multipliers are added to the amplitude components calculated last time to obtain the values ​​of the updated 6 reference signal amplitude components and output them.

[0013] Furthermore, the LMSD-based digital demodulation circuit demodulates and analyzes the signal output by the C / V conversion circuit; the output voltage signal of the C / V conversion circuit carries an error component modulated by a high-frequency carrier, and its voltage signal model is:

[0014]

[0015] Where a is the amplitude of the voltage signal model; carrier(·) is the function expression of the high-frequency carrier ω c and Respectively represent the angular frequency and initial phase of the carrier; ω r and are the angular frequency and initial phase of the resonant motion respectively; a0 is the component of the DC error, and its angular frequency and initial phase are also ω c and

[0016] Furthermore, the self-circulating digital control circuit includes a signal generator and a capacitance control module; the signal generator generates two high-frequency carriers, one carrier is used for the basic capacitance, and the other carrier with opposite phase is used to offset the capacitance array. When the value of the offset capacitance is equal to the basic capacitance value, the output voltage is directly proportional to the capacitance change of the sensitive structure; the capacitance combination is traversed to obtain the amplitude components of the amplitude components of the basic capacitance that are not offset in 256 LMSD demodulation modules, and the capacitance combination parameters with the smallest amplitude are found out, and configured through the capacitance control module.

[0017] Furthermore, it also includes a data smoothing circuit; the data smoothing circuit is connected between the LMSD-based digital demodulation circuit and the self-circulating digital control circuit; the data smoothing circuit is used to receive the amplitude component transmitted by the LMSD-based digital demodulation circuit, calculate the amplitude component result after exponential smoothing of 2, and use it for the self-circulating control module and output calculation.

[0018] A demodulation method based on a minimum mean square error algorithm is implemented based on a demodulation circuit of the minimum mean square error algorithm, and comprises: a capacitance change signal is modulated by a high-frequency carrier, and then passes through a capacitance cancellation array to cancel the basic capacitance value in a sensitive structure, and the modulated signal is converted into a voltage signal through a charge amplifier; a high-frequency signal is used to sample the voltage signal, and the sampled signal is demodulated by a digital demodulation circuit based on LMSD; the magnitude of the amplitude component of the basic capacitance that is not canceled by demodulation is fed back to a self-circulating digital control circuit, and the optimal parameters of the capacitance cancellation array are found for subsequent demodulation.

[0019] Further, the sampling signal is demodulated by a digital demodulation circuit based on LMSD, including:

[0020] Six reference signals are generated using two-frequency sine and cosine signals;

[0021] A cache register is set to store the data sampled and outputted by the ADC at each rising edge of the sampling clock, a cache register group is set to store 6 reference signals, and a reference signal amplitude component register group is set to store the reference signal amplitude component;

[0022] Use 6 multipliers to calculate x i *ω i The estimated value of the sampling signal is obtained by summing up, and the estimated value of the sampling signal is obtained by subtracting it from the sampling signal obtained by ADC sampling to obtain the iterative error, which is used to obtain the new ω i ; where xi Represents 6 reference signals, ω i is the amplitude component of the 6-channel reference signal, and the value of i ranges from 1 to 6;

[0023] At the next rising edge of the clock, the updated reference signal amplitude component is stored in the register group for the next round of iterative calculation, wherein the amplitude component of the base capacitance that has not been offset is fed back to the self-circulating digital control circuit;

[0024] The iterative error gradually approaches 0, at which time the stabilized amplitude component is calculated to obtain the correct signal amplitude; the update of the reference signal amplitude component and data output are completed within a single cycle.

[0025] Further, the method of finding the optimal parameters of the capacitance cancellation array by the self-circulating digital control circuit comprises the following steps:

[0026] use The size of the offset capacitor array control word is traversed through the control word; ω5 and ω6 represent the amplitude components of the basic capacitance without offset;

[0027] By finding the traversal process The capacitance combination with the smallest amplitude is used as the optimal parameter to optimally correct the capacitance value that is not completely offset after the capacitive inertial sensor is processed.

[0028] The present invention adopts the above technical solution, which has the following advantages:

[0029] 1. The present invention utilizes a compensation capacitor array to compensate for the basic capacitance value of the sensitive structure, thereby reducing the influence of the basic capacitance on the measurement accuracy and improving the gain coefficient of the entire sensor.

[0030] 2. The present invention adopts an integrated circuit design scheme. The parameters involved in signal generation can be configured by the CPU. By using the optimized and improved LMSD algorithm, the calculation and update of the reference signal amplitude component within a single clock cycle can be realized to meet the requirements of real-time and online applications.

[0031] 3. The present invention can feedback the amplitude component size of the basic capacitance value that has not been offset through iteratively calculated amplitude components, flexibly adjust the offset capacitance size by traversing the control word through a digital control circuit, and then determine the optimal control word state according to the size of the amplitude component to achieve the best correction of the basic capacitance.

[0032] In summary, the present invention can be widely applied to the field of capacitive inertial sensor signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1It is a block diagram of the overall architecture of the demodulation circuit of the minimum mean square error algorithm in an embodiment of the present invention;

[0034] Figure 2 is a principle block diagram of a cancellation capacitor array in an embodiment of the present invention;

[0035] Figure 3 It is a principle block diagram of a digital demodulation algorithm based on LMSD in an embodiment of the present invention;

[0036] Figure 4 It is a principle block diagram of a data smoothing circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0038] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0039] The present invention relates to a demodulation circuit based on a minimum mean square error algorithm, which includes a self-circulating digital control circuit, a capacitor cancellation array, a digital demodulation circuit based on LMSD, and a data smoothing circuit. The self-circulating digital control circuit evaluates the cancellation accuracy according to the size of the demodulation amplitude component and adjusts the switch state of the capacitor cancellation array; the capacitor cancellation array is used to cancel the basic capacitance of the sensitive structure; the digital demodulation circuit based on LMSD is used to iteratively calculate and demodulate the sampled signal; the data smoothing circuit is used to smooth the data output and reduce low-frequency noise. The present invention improves the flexibility and accuracy of circuit operation by adding an uncancelled capacitor amplitude component to the demodulation reference signal and feedback-adjusting the switch state of the capacitor cancellation array.

[0040] In one embodiment of the present invention, a demodulation circuit based on a minimum mean square error algorithm is provided. In this embodiment, Figure 1 As shown, the circuit includes: a C / V conversion circuit based on a cancellation capacitor, a digital demodulation circuit based on a LMSD, and a self-circulating digital control circuit.

[0041] The C / V conversion circuit is used to convert the received capacitive sensor signal into a voltage signal, which is a voltage signal after the basic capacitance value is offset;

[0042] The digital demodulation circuit based on LMSD receives the voltage signal transmitted by the C / V conversion circuit after the basic capacitance value is offset, and is used to iteratively demodulate the received voltage signal;

[0043] The self-circulating digital control circuit is used to adjust the capacitance of the offset capacitor array according to the amplitude component of the digital demodulation circuit.

[0044] In the above embodiment, the C / V conversion circuit includes a cancellation capacitor array and a charge amplifier. The capacitive sensor signal is transmitted to the cancellation capacitor array, and the cancellation capacitor array cancels the basic capacitance value in the sensitive structure, and the modulated signal is converted into a voltage signal through the charge amplifier.

[0045] Among them, the cancellation capacitor array uses a carrier with a phase opposite to that of the high-frequency carrier to achieve the purpose of canceling the basic capacitance. The cancellation capacitor array is composed of multiple capacitors connected in parallel, and the capacitor selection is controlled by a switch. The state of the switch is controlled by a self-circulating digital control circuit; that is, the control end of the switch is connected to an 8-bit digital signal, and it can be configured and selected by the control word of the CPU.

[0046] Preferably, Figure 2 As shown, the offset capacitor array consists of 8 parallel capacitors. The sizes of the offset capacitors are 1, 2, 4, 8, 16, 32, 64, and 128 times the unit capacitance value C. The on and off of the switches are controlled by registers. There are 256 combinations of the 8 capacitance sizes. When all capacitor switches are disconnected, the parallel capacitance is 0. When all switches are closed, the parallel capacitance reaches a maximum value of 255·C, that is, the adjustable capacitance range of the parallel capacitor is 0-255·C, and the adjustment accuracy is the unit capacitance value C. The size of the unit capacitance value C is selected according to actual conditions.

[0047] Preferably, the charge amplifier is a fully differential charge amplifier. A fully differential charge amplifier circuit is used to obtain a voltage output proportional to the input charge.

[0048] In the above embodiment, the digital demodulation circuit based on LMSD performs single-cycle iterative calculation on the sampled signal, calculates 6 reference signal amplitude components, and the circuit implements the update of the amplitude component result in a single clock cycle. Specifically, Figure 3 As shown, the digital demodulation circuit based on LMSD includes a filtering circuit, an error calculation circuit and a filter coefficient updating circuit.

[0049] The filtering circuit includes a first multiplier array and a first adder array; one operand in each multiplier in the first multiplier array is a reference signal, and the other operand is an amplitude component, and the first adder array adds the results of the first multiplier array to obtain a filtered value; in the present embodiment, preferably, the first multiplier array and the first adder array respectively include 6 multipliers and 5 adders; one operand in each multiplier is a reference signal, and the other operand is an amplitude component, and the 5 adders add the results of the 6 multipliers to obtain a filtered value.

[0050] The error calculation circuit obtains the error by subtracting the filtered value from the value of the sampled signal after AD conversion. In this embodiment, the signal collected by the capacitive sensor needs to be sampled and converted into a digital signal by an AD (analog-to-digital converter) before entering the error calculation circuit. Figure 1 The sampled signal is shown in .

[0051] The filter coefficient update circuit includes a second multiplier array and a second adder array, wherein a multiplier in the second multiplier array is used to calculate the product of the step length and the error, and the calculation result thereof is used as one of the operands of the remaining multipliers, and the other operands of the remaining multipliers are 6 reference signals in sequence, and the results calculated by the remaining multipliers are added to the amplitude components calculated last time to obtain the updated values ​​of the 6 reference signal amplitude components, and output them. In this embodiment, preferably, the second multiplier array and the second adder array respectively include 7 multipliers and 6 adders, wherein one multiplier is used to calculate the product of the step length and the error, and the calculation result thereof is used as one of the operands of the other 6 multipliers, and the other operands of the 6 multipliers are 6 reference signals in sequence, and the results calculated by the 6 multipliers are added to the amplitude components calculated last time to obtain the updated values ​​of the 6 reference signal amplitude components, and output them.

[0052] In this embodiment, the digital demodulation circuit based on LMSD performs demodulation analysis on the signal output by the C / V conversion circuit. The output voltage signal of the C / V conversion circuit carries an error component modulated by a high-frequency carrier, and its voltage signal model can be expressed by the following formula:

[0053]

[0054] Where a is the amplitude of the voltage signal model; carrier(·) is the function expression of the high-frequency carrier, which can be in the form of a square wave or a sine-cosine wave, where ω c and Respectively represent the angular frequency and initial phase of the carrier; ω r and are the angular frequency and initial phase of the resonant motion respectively; a0 is the component of the DC error, and its angular frequency and initial phase are also ω cand The voltage signal model can take into account the capacitance value that is not completely offset by the offset capacitor array, thereby improving the demodulation accuracy.

[0055] In this embodiment, in the digital demodulation circuit based on LMSD, the sampling signal is:

[0056] d(n)=y(n)+e(n)

[0057] Among them, d(n) is the sensor sampling signal, y(n) is the real signal value, and e(n) is the signal noise. In the demodulation process, it is necessary to use a linear combination of a set of orthogonal functions to fit the sensor sampling signal and minimize the fitting error.

[0058] In this embodiment, for the capacitive inertial sensor, 6 signals are used as reference signals in the demodulation process, and the reference signals x1(t) to x6(t) are selected as follows:

[0059]

[0060]

[0061]

[0062]

[0063]

[0064]

[0065] Among them, ω c and ω r denote the carrier frequency and resonant frequency respectively, and Represents the initial phase of the reference signal. The above reference signal is used to iteratively calculate the sampled signal, and W = [ω1, ω2, ω3, ω4, ω5, ω6] represents the amplitude components of the six signals. When the signal is a capacitive gyroscope signal, ω1, ω2, ω3, ω4 represent the amplitude components of the sensor signal, and through The amplitude a of the voltage signal model can be obtained by calculation using the formula; ω5 and ω6 represent the amplitude components of the basic capacitance that are not offset. The size of can reflect the size of the DC error component a0 caused by the uncompensated basic capacitance.

[0066] In the above embodiment, if Figure 2As shown, the self-circulating digital control circuit includes a signal generator and a capacitor control module. The signal generator generates two high-frequency carriers, one of which is used for the basic capacitor and the other with opposite phase is used to offset the capacitor array. When the value of the offset capacitor is equal to the basic capacitor value, the output voltage is proportional to the capacitance change of the sensitive structure. The self-circulating digital control circuit traverses the capacitor combination to obtain the amplitude of ω5 and ω6 in 256 LMSD demodulation modules, finds the capacitor combination parameters with the smallest amplitude, configures them through the capacitor control module, and uses them for actual circuit use.

[0067] In this embodiment, the self-circulating digital control circuit utilizes The size of the offset capacitor array control word is traversed through the control word. The size of the offset capacitor is 1, 2, 4, 8, 16, 32, 64, and 128 times the unit capacitance value C. There are 256 possible combinations of capacitors in parallel, and the adjustable range of capacitance is 0-255 C. By finding the traversal process, The capacitor combination with the smallest amplitude is used to optimally correct the capacitance value that is not completely offset after the capacitive inertial sensor is processed.

[0068] In each of the above embodiments, a data smoothing circuit is further included; the data smoothing circuit is connected between the LMSD-based digital demodulation circuit and the self-circulating digital control circuit. The data smoothing circuit is used to receive the amplitude component transmitted to by the LMSD-based digital demodulation circuit, and calculate 2 N The amplitude component result after times smoothing is used for the self-circulation control module and output calculation, that is, ω5 and ω6 are transmitted to the self-circulation control module, and ω1, ω2, ω3, and ω4 are directly output for calculation. Among them, the parameter N is a smoothing coefficient, which is not a fixed value and can be modified according to the implementation method of the embodiment.

[0069] In this embodiment, if Figure 4 As shown, the data smoothing circuit includes a state machine, a counter, an adder array and a data interception module. The preset smoothing coefficient N is input into the state machine to configure the smoothing module calculation parameters. The sum is accumulated through the adder array at the rising edge of the input clock. After the sum is accumulated to the count value, the accumulated value is intercepted at a high position through the data interception module. The calculation completion signal is valid, and the data is smoothed exponentially by 2. Smoothing of different magnifications can be achieved by adjusting the smoothing coefficient N.

[0070] In one embodiment of the present invention, a demodulation method based on a minimum mean square error algorithm is provided. The demodulation method is implemented based on the demodulation circuit based on the minimum mean square error algorithm in the above embodiments. The demodulation method comprises the following steps:

[0071] 1) The capacitance change signal is modulated by a high-frequency carrier and passes through a capacitance cancellation array to offset the basic capacitance value in the sensitive structure. The modulated signal is converted into a voltage signal by a charge amplifier;

[0072] 2) The voltage signal is sampled using a high-frequency signal, and the sampled signal is demodulated by a digital demodulation circuit based on LMSD;

[0073] 3) Feedback the magnitudes of the amplitude components ω5 and ω6 of the basic capacitance that are not offset by demodulation to the self-circulating digital control circuit to find out the optimal parameters of the capacitance offset array for subsequent high-precision demodulation.

[0074] In the above step 2), the sampled signal is demodulated by a digital demodulation circuit based on LMSD, which includes the following steps:

[0075] 2.1) Generate six reference signals using two-frequency sine and cosine signals.

[0076] 2.2) Setting a cache register to store the data sampled and output by the ADC at each rising edge of the sampling clock, setting a cache register group to store 6 reference signals, and setting a reference signal amplitude component register group to store the reference signal amplitude component;

[0077] 2.3) Use 6 multipliers to calculate x i *ω i The estimated value of the sampling signal is obtained by summing up, and the estimated value of the sampling signal is obtained by subtracting it from the sampling signal obtained by ADC sampling to obtain the iterative error, which is used to obtain the new ω i ;

[0078] Among them, x i Represents 6 reference signals, i ranges from 1 to 6, ω i is the filter coefficient in the LMSD algorithm, i ranges from 1 to 6, which is the amplitude component of the 6 reference signals. The final iteration is completed i It can reflect the size of a and a0 in the voltage signal model and achieve the purpose of demodulating the modulated signal.

[0079] 2.4) At the next clock rising edge, the updated reference signal amplitude component is stored in the register group for the next round of iterative calculation, where ω5 and ω6 are fed back to the self-circulating digital control circuit.

[0080] 2.5) The final iterative error continues to decrease and gradually approaches 0. At this time, the stabilized amplitude component is calculated to obtain the correct signal amplitude; the update of the reference signal amplitude component and data output are completed within a single cycle.

[0081] In the above step 3), the optimal parameters of the capacitor cancellation array are found by a self-circulating digital control circuit, including the following steps:

[0082] 3.1) Utilization The size of the offset capacitor array control word is traversed through the control word.

[0083] The sizes of the offset capacitors are 1, 2, 4, 8, 16, 32, 64, and 128 times the unit capacitance value C, respectively. There are 256 possible combinations of capacitors in parallel, and the adjustable range of the capacitor is 0-255·C.

[0084] 3.2) By finding the traversal process so that The capacitance combination with the smallest amplitude is used as the optimal parameter to optimally correct the capacitance value that is not completely offset after the capacitive inertial sensor is processed.

[0085] The method provided in this embodiment is used to execute the above-mentioned system embodiments. Please refer to the above-mentioned embodiments for the specific process and detailed contents, which will not be repeated here.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A demodulation circuit based on the minimum mean square error algorithm, It is characterized in that include: A C / V conversion circuit is used to convert the received capacitive sensor signal into a voltage signal, where the voltage signal is a voltage signal after the basic capacitance value is offset; A digital demodulation circuit based on LMSD receives a voltage signal transmitted by the C / V conversion circuit after the basic capacitance value is offset, and is used to iteratively demodulate the received voltage signal; A self-circulating digital control circuit is used to adjust the capacitance of the offset capacitor array according to the amplitude component of the digital demodulation circuit; The C / V conversion circuit includes a cancellation capacitor array and a charge amplifier; the capacitive sensor signal is transmitted to the cancellation capacitor array, the cancellation capacitor array cancels the basic capacitance value in the sensitive structure, and the modulated signal is converted into a voltage signal by the charge amplifier; The offset capacitor array uses a carrier wave with a phase opposite to that of the high-frequency carrier wave to achieve offset of the basic capacitance; The offset capacitor array is composed of a plurality of capacitors connected in parallel with each other, and the capacitor gating is controlled by switches, and the state of the switches is controlled by a self-circulating digital control circuit; The LMSD-based digital demodulation circuit performs single-cycle iterative calculation on the sampled signal, calculates 6 reference signal amplitude components, and realizes the update of the amplitude component result in a single clock cycle; The digital demodulation circuit based on LMSD includes a filtering circuit, an error calculation circuit and a filter coefficient updating circuit; The filtering circuit includes a first multiplier array and a first adder array; one operand of each multiplier in the first multiplier array is a reference signal, and the other operand is an amplitude component, and the first adder array adds the results of the first multiplier array to obtain a filtered value; The error calculation circuit obtains the error by subtracting the filtered value from the value of the sampled signal after AD conversion; The filter coefficient updating circuit comprises a second multiplier array and a second adder array, wherein a multiplier in the second multiplier array is used to calculate the product of the step length and the error, and the calculation result thereof is used as one of the operands of the remaining multipliers, and the other operands of the remaining multipliers are 6 reference signals in sequence, and the results calculated by the remaining multipliers are added to the amplitude components calculated last time to obtain the updated values ​​of the 6 reference signal amplitude components, and output them; The self-circulating digital control circuit includes a signal generator and a capacitance control module; the signal generator generates two high-frequency carriers, one carrier is used for the basic capacitance, and the other carrier with opposite phase is used for the offset capacitance array. When the value of the offset capacitance is equal to the basic capacitance value, the output voltage is in direct proportion to the capacitance change of the sensitive structure; the capacitance combination is traversed to obtain the amplitude components of the amplitude components of the basic capacitance that are not offset in 256 LMSD demodulation modules, and the capacitance combination parameters with the smallest amplitude are found out, and configured through the capacitance control module.

2. The demodulation circuit based on the minimum mean square error algorithm as claimed in claim 1, It is characterized in that The LMSD-based digital demodulation circuit demodulates and analyzes the signal output by the C / V conversion circuit; the output voltage signal of the C / V conversion circuit carries an error component modulated by a high-frequency carrier, and its voltage signal model is: Where a is the amplitude of the voltage signal model; carrier(·) is the function expression of the high-frequency carrier ω c and Respectively represent the angular frequency and initial phase of the carrier; ω r and are the angular frequency and initial phase of the resonant motion respectively; a 0 is the DC error component, whose angular frequency and initial phase are also ω c and 3. The demodulation circuit based on the minimum mean square error algorithm as claimed in claim 1, It is characterized in that It also includes a data smoothing circuit; the data smoothing circuit is connected between the LMSD-based digital demodulation circuit and the self-circulating digital control circuit; the data smoothing circuit is used to receive the amplitude component transmitted by the LMSD-based digital demodulation circuit, calculate the amplitude component result after exponential smoothing of 2, and use it for the self-circulating digital control circuit and output calculation.

4. A demodulation method based on a minimum mean square error algorithm, the method being implemented based on a demodulation circuit based on a minimum mean square error algorithm as claimed in any one of claims 1 to 3, It is characterized in that include: The capacitance change signal is modulated by a high-frequency carrier and passes through a capacitance cancellation array to offset the basic capacitance value in the sensitive structure. The modulated signal is converted into a voltage signal by a charge amplifier. The voltage signal is sampled using a high-frequency signal, and the sampled signal is demodulated by a digital demodulation circuit based on LMSD; The magnitude of the amplitude component of the basic capacitance that is not offset by demodulation is fed back to the self-circulating digital control circuit to find out the optimal parameters of the capacitance offset array for subsequent demodulation.

5. The demodulation method based on the minimum mean square error algorithm as claimed in claim 4, It is characterized in that The sampled signal is demodulated by a digital demodulation circuit based on LMSD, including: Six reference signals are generated using two-frequency sine and cosine signals; A cache register is set to store the data sampled and outputted by the ADC at each rising edge of the sampling clock, a cache register group is set to store 6 reference signals, and a reference signal amplitude component register group is set to store the reference signal amplitude component; Use 6 multipliers to calculate x i *ω i The estimated value of the sampled signal is obtained by summing it and subtracting it from the sampled signal obtained by ADC sampling to obtain the iterative error, which is used to obtain the new ω i ; where x i Represents 6 reference signals, ω i is the amplitude component of the 6-channel reference signal, and the value of i ranges from 1 to 6; At the next rising edge of the clock, the updated reference signal amplitude component is stored in the register group for the next round of iterative calculation, wherein the amplitude component of the base capacitance that has not been offset is fed back to the self-circulating digital control circuit; The iterative error gradually approaches 0, at which time the stabilized amplitude component is calculated to obtain the correct signal amplitude; the update of the reference signal amplitude component and data output are completed within a single cycle.

6. The demodulation method based on the minimum mean square error algorithm as claimed in claim 4, It is characterized in that The method of finding the optimal parameters of the capacitance cancellation array by the self-circulating digital control circuit comprises the following steps: use The size of the offset capacitor array control word is traversed through the control word; ω 5 ,ω 6 represents the magnitude component of the base capacitance without cancellation; By finding the traversal process The capacitance combination with the smallest amplitude is used as the optimal parameter to optimally correct the capacitance value that is not completely offset after the capacitive inertial sensor is processed.

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