Device Awareness Testing for Memory Cells

Abstract

Disclosed is a method for testing an integrated circuit device (1), the method comprising: performing defect modeling on the integrated circuit device (1); performing fault modeling on the integrated circuit device (1) based on information obtained from the defect modeling; performing test development based on information obtained from the fault modeling; and performing a test on the integrated circuit device (1). Performing defect modeling on the integrated circuit device (1) includes: performing physical defect analysis (10) on the integrated circuit device (1) to provide a set of effective technical parameters (Tp df ) modified from a set of defect-free technical parameters (Tp eff ) associated with the integrated circuit device (1); and using the set of effective technical parameters (Tp eff ) to perform electrical modeling (11) on the integrated circuit device (1) to provide a defect-parameterized electrical model (16; 17) based on the defect-free electrical model of the integrated circuit device (1). This method achieves parts-per-billion testing capabilities.

Description

Technical Field

[0001] The present invention relates to a method for testing integrated circuit devices. Background Art

[0002] In existing test methods for integrated circuit devices such as (semiconductor) memory cells, external resistors are used to model possible defects in a device (a part thereof), thereby only allowing linear defects to be modeled. For example, linear resistors are added to the transistor-level netlist for the simulation and testing of memory cells. This approach is insufficient to achieve a parts-per-billion fault detection level in advanced and novel semiconductor memory cells.

[0003] The article "Modelling and Diagnosis of Faults in Multilevel Memristor Memories" by Kannah Sachhidh et al. (DOI: 10.1109 / TCAD.2015.2394434) presents a test technique that simultaneously tests several memory cells by leveraging the sneak paths inherent in cross memories through an integrated solution for detecting and localizing faults in memristors. A hybrid diagnostic scheme is also proposed that uses a combination of sneak paths and March tests to reduce the diagnostic time. The proposed scheme supports and exploits sneak paths during fault detection and diagnosis modes while disabling sneak paths during normal operation. Compared to traditional March tests, the proposed hybrid scheme reduces the fault detection and diagnosis times by 24.69% and 28% respectively.

[0004] The article "Fault Detection and Diagnosis for Multi-Level Cell Flash Memories" by Robert R Martin et al. (DOI: 10.1109 / IMTC.2006.235838) provides a solution for testing and diagnosing MLC flash memory arrays. The proposed fault model takes into account many physical defects that cause state changes in the memory. The general test algorithm and the flash diagnostic (FDX) march algorithm proposed in this article are said to be the first ones for MLC flash. In addition, the complete fault coverage of the fault models proposed in this article has low complexity and low test time, making them an 'attractive' method for testing and diagnosing faults in multilevel flash memories. Summary of the Invention

[0005] The present invention seeks to provide a test method for testing integrated circuit devices to allow testing at the defects per billion (DPPB) level.

[0006] According to the present invention, there is provided a method as defined above, the method comprising: performing defect modeling on an integrated circuit device; performing fault modeling on the integrated circuit device based on information obtained from the defect modeling; performing test development based on information obtained from the fault modeling; and performing a test on the integrated circuit device. Performing defect modeling on the integrated circuit device includes: performing physical defect analysis on the integrated circuit device to provide a set of valid technical parameters modified from a set of defect-free technical parameters associated with the integrated circuit device; and using the set of valid technical parameters to perform electrical modeling of the integrated circuit device to provide a defect-parameterized electrical model based on the defect-free electrical model of the integrated circuit device, wherein fault modeling includes fault analysis based on the defect-parameterized electrical model of the integrated circuit device, and wherein fault analysis includes: defining a fault space that includes a description of a plurality of possible faults; and determining which of the plurality of possible faults can be sensitized during a test performed on the integrated circuit device.

[0007] This allows providing a test method that extends beyond unit-aware testing related to integrated circuit devices (e.g., (semiconductor) memory devices) as device-aware testing (DAT). The defect modeling of embodiments of the present invention does not assume that defects in an integrated circuit device (or its cells) can only be electrically modeled as linear resistors (as suggested by conventional methods), but combines and captures the impact of physical defects on the technical parameters of the integrated circuit device and subsequently on its electrical parameters. Once the defective electrical model is defined, system fault analysis (based on fault simulation) is performed to derive an appropriate fault model and subsequently a test solution. Thus, a highly reliable test method for achieving the defects per billion fault detection level can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be discussed in more detail below with reference to the drawings, in which:

[0009] Figure 1 a schematic representation of a defect modeling portion of an embodiment of device-aware testing according to the present invention is shown,

[0010] Figure 2 a flowchart of a fault modeling portion of an embodiment of device-aware testing according to the present invention is shown.

[0011] Figure 3 a flowchart of another method representing a fault modeling portion of another embodiment of device-aware testing according to the present invention is shown. DETAILED DESCRIPTION

[0012] Technological advancements have propelled the semiconductor industry to remarkable success in delivering larger, faster, and cheaper integrated circuits with high quality of service. Silicon technology has entered the nano era and is prototyping 5nm transistors. However, it is widely recognized that defects during the manufacturing process and variability in device characteristics, and their impact on the overall quality and reliability of the system, are major challenges, especially when considering high quality levels such as parts per billion defects (DPPB). Additionally, emerging failure mechanisms in the nano era have made the failure modes of chips dominated by transient, intermittent, and soft faults rather than hard and permanent faults. This shift in failure mechanisms may affect the way fault modeling is performed. It should be noted that an accurate fault model reflecting the true defects of the new technology is essential for developing high-defect coverage test solutions. High-quality testing is a very critical step in the entire design and manufacturing chain responsible for screening all defective chips before sale, as this is the last chance to deliver the required quality and reliability to the end customer. All of these indicate the necessity and importance of high-quality test solutions.

[0013] Embodiments of the present invention relate to a test method that extends beyond unit-aware testing related to integrated circuit device 1, hereinafter referred to as device-aware testing (DAT). Method embodiments include three steps: defect modeling, fault modeling, and test (or design for test (DfT)) development. Defect modeling in embodiments of the present invention does not assume that defects in integrated circuit device 1 (or its units) can only be electrically modeled as linear resistors (as suggested by traditional methods), but rather combines and captures the impact of physical defects on the technical parameters of integrated circuit device 1 and subsequently on its electrical parameters. Once the defective electrical model is defined, system fault analysis (based on fault simulation) is performed to derive an appropriate fault model and subsequently a test solution.

[0014] Generally, embodiments of the present invention relate to a method for testing integrated circuit device 1, the method comprising: performing defect modeling on integrated circuit device 1; performing fault modeling on integrated circuit device 1 based on information obtained from defect modeling; performing test development based on information obtained from fault modeling; and performing a test on integrated circuit device 1. Performing defect modeling on integrated circuit device 1 includes: performing physical defect analysis 10 of integrated circuit device 1 to provide a set of effective technical parameters Tp df (e.g., length, width, density, or cell structure) modified from a set of defect-free technical parameters Tp associated with integrated circuit device 1 eff ; and using the set of effective technical parameters Tp eff to perform electrical modeling 11 of integrated circuit device 1 to provide a defect-parameterized electrical model based on the defect-free electrical model of integrated circuit device 1 (e.g., current, impedance, voltage...).

[0015] Instead of using a fault model derived by injecting linear resistors into the transistor-level netlist representing the integrated circuit device 1, embodiments of the present invention first modify the electrical model of the defective device 1 (e.g., at the transistor level) by incorporating the effect of defects on the electrical parameters (models) of the device. In another embodiment, defect modeling of the integrated circuit device 1 includes defect modeling of portions of the integrated circuit device 1, e.g., at the cell level, cell block level, or at the transistor level. The electrical model is then used to perform circuit simulation to derive a fault model and then a test solution is derived. Embodiments of the present invention employ a three-step DAT method: defect modeling, fault modeling, and test development. One of the key differences is the defect modeling step, which takes into account physical defects and captures their impact on electrical parameters, thus enabling accurate fault modeling. The fault modeling systematically defines the complete (theoretical) memory fault space and then systematically performs fault analysis (using the defect modeling and circuit simulation of the first step) to verify this space. This step provides insights not only into the nature of the real faults but also into the best way to test them, which are used in the third step (test development) of the DAT. As an example, faults that result in an incorrect read value can be easily detected with a March test, since the March test can sensitize the faults, while faults that result in a random read value require specialized design for testability (DfT) to ensure their detection. Embodiments of the present invention have been applied to R-RAM and STT-MRAM memory devices and have demonstrated the superiority of the method compared to conventional memory test methods. The DAT can model and detect some of the device defects that cannot be detected by conventional methods. Thus, the amount of test escapes can be further reduced, and even the defects can be better diagnosed for rapid yield learning.

[0016] The present invention is applied to an integrated circuit device 1 associated with any memory technology, including emerging memory technologies such as PCM, R-RAM, and STT-MRAM. Two exemplary memory technologies are described herein: resistive random access memory (R-RAM) and spin transfer torque magnetic random access memory (STT-MRAM). The results show that for defects that cannot be detected by traditional methods, embodiments of the present invention can sensitize the faults, which means that traditional methods cannot produce high-quality test solutions required at the parts per billion defect (DPPB) level. At least for the two emerging memory technologies considered, the new method clearly sets a turning point for testing.

[0017] Traditional memory testing assumes that device defects can be modeled as linear resistors in series or parallel with the device. However, it has been shown that this approach is inaccurate, at least for emerging memory technologies such as R-RAM and STT-MRAM, resulting in incomplete or inaccurate fault modeling. Embodiments of the present invention for device-aware testing (DAT) aim to address this problem and establish steps to meet DPPB level requirements. First, physically model the defects in the integrated circuit device 1 and incorporate their electrical behavior into the device model. Second, integrate the model into a memory simulation platform to analyze the impact of the defects on memory behavior; this is done in a systematic manner by validating a predefined fault framework / space (e.g., using SPICE simulation). The result of this step provides insights into the nature of the real faults, which are used to develop optimal and appropriate test solutions (e.g., March tests, DfT).

[0018] Inaccurate defect modeling can lead to poor fault models, thus limiting the effectiveness of the proposed test solutions and DfT designs not only in terms of defect coverage but also in terms of test time. For example, tests targeted at a fault model that does not represent any real defect do not increase defect coverage while still consuming test time. To accurately model physical defects, the device model should incorporate the way in which the defect affects the technical parameters (e.g., length, width, density) of the integrated circuit device 1 and then affects the electrical parameters (e.g., critical switching current).

[0019] Figure 1 A flowchart of this modeling method is shown as a schematic representation of the defect modeling part of an embodiment of device-aware testing according to the present invention. The (defect-free) model 1a and the defective model 1b of the integrated circuit device 1 are used as basic inputs. The final possible output is an optimized defect-parameterized model 17 of the defective integrated circuit device 1. It should be noted that, in general, the integrated circuit device 1 as used herein can be a FinFET transistor, an STT-MRAM device, an R-RAM device, a PCM device, etc.

[0020] The method of the present invention for defect modeling includes three steps. Physical defect analysis and modeling 10 includes: Given a set of physical defects D = {d1, d2,..., d n}, each defect d i must be analyzed to fully understand the defect mechanism and identify its impact on each (critical) technical parameter Tp of the integrated circuit device 1. Due to this defect, one or more (defect-free) technical parameters Tp df will be modified, resulting in the so-called effective technical parameter Tp eff . This can be described by the following abstract function:

[0021] Tp eff (S i ) = f i (Tp df , S i ) (1)

[0022] where Tp df is the defect - free technical parameter, f i is the mapping function corresponding to the defect d i (i = 1……n), and S i = {x1, x2, ……, x t} is a set of parameters representing the size or strength of the defect d i .

[0023] To obtain the effective technical parameter Tp eff , the physical defect analysis 10 includes identifying a set of possible physical defects D (which may occur during the manufacture of the integrated circuit device) and their characteristics. For example, for a memory device, the possible physical defects D include one or more of the following: patterning defects in the R - RAM cells of the memory device, electrode roughness of the R - RAM cells of the memory device, pinhole defects in the STT - MRAM cells of the memory device, extreme thickness variations of the tunnel junctions in the defects in the STT - MRAM cells of the memory device, etc.

[0024] In the electrical modeling step 11 of the defective integrated circuit device 1, identify the effect of the modified technical parameter Tp eff from the previous step 10 on each of the key electrical parameters of the integrated circuit device 1 (e.g., using the electrical equation 15 as indicated). Thus, the resulting electrical parameters are quantified to describe the electrical behavior of the defective integrated circuit device 1 with the defect d i . One way to perform this operation is to modify the defect - free device electrical model and convert it into a defect - parameterized electrical model 16 by integrating equation (1) for each involved technical parameter Tp. This step gives the original defective device model 16 with effective electrical output parameters.

[0025] In the third step 12, further refinement can be carried out, that is, the defect modeling of the integrated circuit device 1 also includes the calibration 12 of the defect - parameterized electrical model 16. This can be achieved by fitting and optimizing the defect - parameterized electrical model 16 based on the actual measurements of the defective integrated circuit device 1, thereby obtaining the optimized defect - parameterized electrical model 17, as Figure 1As shown. If any physical or electrical parameter of the defective model does not accurately match the characteristic data, it is necessary to keep optimizing the device model until acceptable accuracy is obtained. By performing silicon data fitting and model optimization, an optimized defective parameterized electrical model 17 can be obtained, which enables accurate circuit simulation for fault modeling.

[0026] The second DAT step is fault modeling. In this step, the (optimized) defective models 16, 17 from the previous step are used to analyze the behavior of the integrated circuit device 1 in the presence of defects. The result of this analysis is used to develop high-quality tests. Thus, in another embodiment of the present invention, fault modeling 20 includes fault analysis 22 based on the defective parameterized electrical models 16; 17 of the integrated circuit device 1.

[0027] In an exemplary embodiment, a fault space is defined, which describes and classifies all possible faults of the target integrated circuit device (e.g., STT-MRAM, R-RAM, PCM, etc.). Second, a fault analysis method is described below (refer to Figure 2 in more detail), which determines which faults from the space are realistic for the considered defect, that is, which faults can be sensitized in the presence of such a defect. For this purpose, an embodiment is provided, in which fault analysis 22 includes: defining a fault space that includes a description of a plurality of possible faults 23, 24; and determining which of the plurality of possible faults 23, 24 can be sensitized during the test performed on the integrated circuit device 1.

[0028] In another exemplary embodiment, fault analysis 22 includes determining a list of possible faults 23, 27, and the list of possible faults includes easily detectable faults (e.g., strong faults) 23 and / or difficult-to-detect faults 27 (e.g., weak faults, faults that cause random reads, etc.). An easily detectable fault 23 is a functional fault that can be detected by applying an operation sequence to the integrated circuit device 1. A difficult-to-detect fault 27 is a fault that causes a parameter fault in the integrated circuit device 1 (e.g., a reduction in bit line current or a fault that causes random or unpredictable reads).

[0029] In an advantageous embodiment, the integrated circuit device 1 is a memory device 1. In another advantageous embodiment, the integrated circuit device is a logic device 1. In this regard, many embodiments and examples of the memory device 1 can be envisioned.

[0030] In one example, the analysis is limited to static and dynamic single - cell faults. A static fault is defined as a fault that can be sensitized by performing at most one operation, while a dynamic fault requires more than one operation to be sensitized. If a fault involves more than one cell, the fault is called a coupling fault. Strong faults can be systematically described using the fault primitive (FP) notation. The FP describes the difference between the observed behavior of memory device 1 and the expected behavior of the memory device, expressed as a triple (S / F / R), where

[0031] S represents the sequence of operations that sensitize the fault. The sequence has the form S = x0O1x……O n x n , where x is '0' or '1', and O is an operation with value r (read) or w (write), and 0 and 1 represent logic cell values. If n ≤ 1, the fault is static; otherwise, it is dynamic.

[0032] F describes the value stored in the cell after the execution of S. For traditional charge - based memories (e.g., SRAM), there are only two digital states, i.e., F is '0' or '1'. However, emerging memory technologies such as R - RAM and STT - MRAM use resistive storage elements; predefined resistance ranges determine the logical state of the cells in memory device 1. Due to defects or extreme process variations, the states of such memory devices 1 can be outside these ranges, and thus other (faulty) resistance states L, U, and H need to be defined. Measured resistance distributions of a large number of 60nm MTJ STT - MRAM memory devices 1 indicate that F is one of {0; 1; U; L; H}. Each point in the distribution represents a memory device 1, the R P of which is shown on the x - axis and the R AP is shown on the y - axis (resistance R P in parallel P state, resistance R AP in anti - parallel AP state). From a design perspective, the nominal R P is, for example, 2kΩ and the nominal R AP is 5kΩ, which ensures good read reliability at a tunneling magnetoresistance TMR = 150%. The resistance ranges for the two states 0 and 1 can be defined using the nominal value of 3σ. Alongside the devices 1 within the specification, there are also a large number of devices 1 outside the specification due to some defects or extreme process variations. These are: (1) extremely low resistance state 'L', (2) extremely high resistance state 'H', and (3) undefined state 'U'. It should be noted that the definitions of states '0' and '1' for STT - MRAM are different from those for R - RAM, where state '0' represents high resistance and '1' represents low resistance.

[0033] R describes the output of a read operation (if S is a read operation) and has the values '0',

[0034] '1', '?', or '-', where '?' represents a random read value (e.g., the sense current is very close to the sense amplifier reference current), and '-' indicates that R is not applicable, i.e., when S is a write operation.

[0035] Table I Single - cell static fault primitives

[0036]

[0037] Table I lists all single - cell static FPs and their names. The naming of FPs follows the following scheme:

[0038] FP = {Read - impact}{Behavior}{Initial - value} {F} (2)

[0039] Here, {Read - impact} is applicable only if the read - sensitization operation results in a faulty read: an incorrect (I) or random (R) read value. {Behavior} describes the behavior of the faulty cell: it indicates the nature of the operation (read (R) or write (W)) and the resulting fault consequence (destructive (D), transition (T), or none). For example, 'WDF' means a write - destructive fault. {Initial - value} describes the initial state of the cell and F is the value stored in the cell after the execution of S.

[0040] For example, RRDF01=(0r0 / 1 / ?) is a random - write - destructive fault that makes the cell go to '1' during a read of '0' and returns a random read value at the output. State faults are an exception to this scheme because no sensitization operation is performed. Their names follow the following scheme:

[0041] FP = SF{Initial - value} {F}

[0042] For dynamic faults, the name of the FP is prefixed with nd, where n represents the number of operations in S and F is based on the last operation in S. For example, (1r1w0 / L / -) is 2d - WTF1 L .

[0043] Integrated circuit faults can be classified into two types: strong faults and weak faults. A strong fault is a functional fault that can always be sensitized (and detected) by applying an operation sequence and can cause a functional error; for example, all FPs in Table I are strong faults. In contrast, weak faults do not cause FPs, but they can cause parametric faults, such as a reduction in bit-line current during a read operation. It should be noted that these faults cannot be detected by any operation sequence because they do not cause any functional errors. Obviously, these faults also need to be detected because they cause reliability problems (e.g., shorter lifetime, higher in-field failure rate). Depending on the effort required to detect a fault, faults can be further classified into easily detectable faults 23 and hard-to-detect faults 27. Detection of easily detectable faults 23 can be guaranteed simply by applying write and read operations (e.g., by using a March test). However, detection of hard-to-detect faults 27 cannot be guaranteed by the March test alone, and their detection requires additional effort; for example, using a dedicated circuit such as DfT. It should be noted that strong faults can include both easily detectable faults 23 and hard-to-detect faults 27, while weak faults are all hard-to-detect faults 27. Examples of strong hard-to-detect faults 27 are random read faults such as RRF11 and RRF00. For example, in an STT-MRAM with small defects, the bit-line current during a read can be very close to the reference current of the sense amplifier, resulting in random behavior between devices.

[0044] Once the defects are modeled and the fault framework is defined, system circuit simulation methods can be used to perform the verification of faults. In this description, this is limited to examples involving single-cell fault analysis. Examples of such fault analysis are shown in the figures of Figure 2 Fault analysis 20 can include seven steps: 1) circuit generation, 2) defect injection, 3) stimulus generation, 4) circuit simulation, 5) fault analysis, 6) fault primitive identification, and 7) defect size sweep, and steps 2 to 6 are repeated until all sizes are covered. It should be noted that in the described exemplary case, defect injection means changing the electrical models 16; 17 of the integrated circuit device 1 (e.g., R-RAM or STT-MRAM) to the defective device models 16; 17 obtained in step 1 of the DAT method embodiment, while defect size sweep means changing the size of the defect, which also modifies the electrical parameters of the defective device models 16; 17.

[0045] Figure 2A flowchart showing a fault analysis method that enables more insights into the nature of real faults and the ways to test them is presented. Given the defect list 21 and its size range, the seven steps of fault analysis should be performed first to verify the static single - cell FPs in Table I (i.e., n ≤ 1). The result will be a set of FPs associated with the size / range of the defects / parameters, which are classified as easily - detectable faults 23, remaining faults 24, and hard - to - detect faults 27. If an FP is not sensitized in the presence of a defect, the fault is considered weak and added to the list of remaining faults 24. Next, all the defects that lead to the remaining faults 24 will be further analyzed, but then using dynamic fault analysis, starting with n = 2. Some of the defects that lead to the remaining faults 24 can now trigger easily - detectable faults 23. For example, S = 0w0 causes a weak fault, while S = 0w0w0 causes an easily - detectable strong fault 23. Once the n = 2 operation single - cell fault analysis 22 is completed, a similar analysis can be performed for the defects that lead to the remaining faults 24 with n = 3 (via decision box 25). The process can be repeated by extending S, one operation at a time, until the considered n is reached. 最大 (End of fault analysis box 26). Each step in this process aims to reduce the set of remaining faults 24 and increase the set of easily - detectable faults 23. What remains at the end of the fault analysis is a (trimmed) set of hard - to - detect faults 27. This is a beneficial step that is not only conducive to optimizing the test cost but also to improving the overall product quality. The final result will be a set of faults 23 that can be easily detected by generating a March test, and another set of faults 27 that require special attention to ensure their detection (e.g., DfT, special tests, etc.).

[0046] The results of the fault analysis 20 contribute to the development of a high-quality and efficient test solution. All easily detectable faults 23 can be detected by applying appropriate test algorithms. The development of an optimized algorithm starts by identifying the minimum detection conditions for each of the faults 23 and then assembling them in the test algorithm. This will provide fault coverage for the easily detectable faults 23 at the lowest test cost. DfT schemes can also be incorporated to further optimize the test time, for example, DfT that enables simultaneous testing of many faults 23, parallel testing, etc. However, the hard-to-detect faults 27 require special attention. Special DfT schemes and tests may be needed. Examples are DfT schemes that can directly measure bit-line sweeps, modify operating conditions (such as weak write operations), stress tests, etc. The aim is to maximize the fault coverage for these faults 27 while maintaining an economically affordable test cost. Generally, therefore, the present invention also relates to an embodiment in which test development includes providing a test solution that includes a set of operations on the integrated circuit device 1 for each easily detectable fault 23 identified in the fault analysis 22, and the design of testability modifications (possibly in combination with a set of operations) for each hard-to-detect fault 27 on the integrated circuit device 1.

[0047] To further improve the verification of defects, Figure 3 A flowchart showing yet another method of fault analysis 22 is presented, which enables the verification of real faults using an exemplary system method. The fault analysis 22 includes a plurality of (operational) steps: i) circuit (netlist) generation 22a, ii) defect injection 22b, iii) stimulus generation 22c, iv) defect size sweep 22d), v) circuit simulation 22e, vi) analysis 22f, vii) fault primitive identification 22g, viii) fault primitive reporting 22h, ix) defect sweep completion 22i, x) stimulus completion 22j, and xi) defect completion 22k.

[0048] To elaborate Figure 3 the flowchart shown, the fault analysis 22 method starts with circuit (netlist) generation 22a, which provides a description of the circuit for later simulation purposes. Thereafter, given the defect list 21 (as Figure 2As shown, defect injection 22b is performed, followed by stimulus generation 22c. Next, a defect size sweep 22d of the (injected) defect occurs, thereby modifying the size of the defect. For example, for a resistance defect, the magnitude of the resistance is changed. Thereafter, circuit simulation 22e is performed, whereby the result of the circuit simulation 22e is examined in the (fault) analysis 22f step. Once the analysis 22f is completed, fault primitive identification 22g is performed to identify any differences between the observed circuit behavior and the expected circuit behavior. If a fault primitive is identified, then it is reported in the fault primitive reporting 22h step, and in the case where no fault primitive is identified, the fault primitive reporting 22h step is skipped.

[0049] Thereafter, if a further sweep of the defect size is required, then steps iv) to viii) are repeated, i.e., the defect size sweep 22d to the fault primitive reporting 22h. Otherwise, if no further sweep of the defect size is required, then this is marked as completed in the defect sweep complete 22i step. Similarly, in the next step, if other stimuli are considered, then steps iii) to ix) are repeated, i.e., the stimulus generation 22c to the defect sweep complete 22i, otherwise, this is marked as completed in the stimulus complete 22j step. As a final step, if other defects are to be injected, then steps ii) to x) are repeated, i.e., the defect injection 22b to the stimulus complete 22j. Otherwise, if all the required defects are injected and examined, then this is marked in the defect complete 22k step, and the fault analysis 22 is completed. As described above, the method for fault analysis 22 provides a systematic method for validating defects, thereby allowing an accurate and systematic framework for checking whether the defects are real. Thus, by performing an accurate fault analysis 20, this allows the derivation of appropriate and real fault modes, and thus the derivation of test solutions.

[0050] In the following description section, the embodiment of the DAT method of the present invention is applied to the R-RAM memory device 1 by following three main steps. However, for clarification and understanding, R-RAM manufacturing defects are discussed and representative defects are selected. The manufacturing process flow of the R-RAM memory device 1 fabricates transistors on a wafer in the front-end-of-line (FEOL) production stage. Then, the lower metal interconnect layer is deposited in the back-end-of-line (BEOL) stage. The R-RAM memory device 1 is typically constructed between two metal layers. After that, the remaining metal layers are deposited. The memory device 1 does not yet have conductive filaments (CFs), and thus, an initial CF formation step needs to be performed to achieve a functional memory device 1.

[0051] As an exemplary implementation of an embodiment of the present invention, defects resulting from the CF formation step are used as an example. During the formation step, initial CFs are generated in the oxide of the R-RAM device 1. The conditions of this step have a great impact on the performance of the device 1, and thus, this step may lead to defects. Some observations of the formation conditions can be made: the higher the formation current (I 形成 ), the lower the device resistance and the less the variation, and the variation of the formation current leads to more resistance variation. The variations in the geometry of the device 1 and the oxide defect density also affect the formation step. Two types of defects can result from the formation step: over-formation, where the CF is too large; and poor formation, where no CF is formed or only a very small CF is formed.

[0052] In the following paragraphs, the DAT method of the present invention is used to form defects (as a case study) and compared with the conventional method of modeling defects using linear resistors. For the DAT method, the input parameters of the R-RAM device 1 model are related to the formation current I 形成 , and thus the physical characteristics of the formation step that may lead to over-formation or poor formation are incorporated into the electrical model 16. The model 16 can be included in the netlist to observe its electrical effects. The formation current I 形成 is directly related to the shape of the CF, that is, it affects the key parameters of the R-RAM memory device 1: t ox (the thickness of the oxide layer between the top electrode TE and the bottom electrode BE), l CF (the length of the CF), l 间隙 (the length between the CF and the top electrode TE), Φ B (the width of the CF near the bottom electrode), and Φ T (the width of the part of the CF closest to the top electrode). It has been shown that l CF and Φ T have the greatest impact on the resistance of the R-RAM memory device 1. Therefore, these parameters are used to model the formation effect of the memory device 1.

[0053] To include the random variation of l CF , an additional parameter Δl CF (which sets the intensity of this variation) is included. These parameters are used to model the formation effect of the device 1. The physical defect modeling step can be mathematically expressed as follows:

[0054] l CF,eff (I 形成 ) = a1 exp(b1·R μ (I 形成 )) + c1 exp(d1·R μ (I 形成 )) (3)

[0055] Φ T,eff (I 形成 ) = a2 exp(b2·R μ (I 形成 )) + c2 exp(d2·R μ (I 形成 ))(4)

[0056] Δl CF,eff (I 形成 ) = a3 exp(b3·R μ (I 形成 )) + c3 exp(d3·R σ (R μ )) (5)

[0058] Here, a k , b k , c k , and d k (k = 1, 2, 3) are fitting parameters. R μ (I 形成 ) = f(I 形成 ), where f(I 形成 ) is a cubic Hermite interpolation from I 形成 to the median resistance, as described in the article "Fundamental variability limits of filament-based R-RAM" by A. Grossi et al. in IEDM, 2016, which is incorporated herein by reference. R σ (R μ ) is given by Equation (1) in this article.

[0059] The R-RAM device model disclosed by H. Li et al. in the article "ASPICE model of resistive random access memory for large-scale memory array simulation" in Electronics Letters, Vol. 35, No. 2, February 2014, takes l CF , Φ T , and Δl CFAs input parameters, the article is incorporated herein by reference. These three parameters define the switching behavior and resistance of the R-RAM device 1 and are thus well-suited for modeling the impact on the electrical behavior of the device. When the model is simulated in a netlist, the effects on electrical parameters (e.g., resistance, switching speed, and threshold) can be analyzed.

[0060] In the fitting and model optimization steps, the three adjustable parameters are calibrated such that the defective behavior of the R-RAM device 1 corresponds to the measurements of a real device. To achieve this, first analyze the influence of l CF , Φ T on the average resistance. Then these parameters are fitted to the measurements in the Grossi article and are thus linked to I 形成 . Analyze the effect of Δl CF and fit in a similar manner. I 形成 varies between 5 μA and 34:1 μA.

[0061] It should be noted that conventional resistance defect modeling methods model a forming defect as a resistor in parallel (R pd ) or in series (R sd ) with a defect-free R-RAM device 1.

[0062] In general, yet another embodiment is provided, where the memory device 1 is a resistive random access memory (R-RAM) cell, the technical parameter Tp includes one or more of the oxide thickness t ox , the conductive filament length l CF , the gap length l 间隙 , the top width Φ of the conductive filament T , the bottom width Φ of the conductive filament B , and the electrical parameters include the reset threshold V 重置 , the set threshold V 设定 , the reset resistance R HRS , the set resistance R LRS , the high-resistance state to low-resistance state switching delay t H→L , the low-resistance state to high-resistance state switching delay t L→H .

[0063] The next step of the present invention embodiment (i.e., fault modeling) includes fault analysis based on using the electrical model generated in the defect modeling step for forming defects. Static fault analysis is performed for two defect models, and then dynamic faults for the DAT method (and traditional methods) are analyzed. Since forming defects affect individual R-RAM device 1 cells, only single-cell faults are analyzed. The possible single-cell static faults are those listed in Table I; the dynamic fault space can be constructed by following the definitions described above.

[0064] Fault analysis for defect formation starts with the analysis of static faults. Table II lists all I 形成 , R pd and R sd static faults sensitized by both the DAT method and the conventional (conv.) method.

[0065] Table II Fault sensitization using device awareness and resistance defect models

[0066]

[0067] The unique faults (6 and 9 respectively) sensitized by the two methods and their overlapping faults (2) clearly show the differences between the methods. In the case tests using the conventional defect model, the unique DAT faults (6 out of 8 true faults, which corresponds to 75%) can lead to test omission. In addition, the conventional defect model method triggers 9 faults that are not real, thus resulting in wasted test time. It should be noted that only 2 common faults are observed between the two methods. The fault analysis then continues with two case studies, where the length of S is increased, i.e., dynamic faults are sensitized.

[0068] Table III Fault categories and FPs for R-RAM formation defect faults

[0069]

[0070] Table III shows the fault categories and FPs of the strong faults observed for varying I 形成 on the same row of the sensitization operation. The sequence is selected to show that as the length of S increases, more strong faults are sensitized. The longer the sensitization sequence, the stronger the faults become. It should be noted that the faults are still the hard-to-detect fault 27 (the bold name in Table III). This can be illustrated by the fact that lower I 形成 results in increased resistance of the R-RAM device 1 (both R LRS and R HRS ) or even poorly formed defects. Due to this increase, the cell cannot switch in the effective '1' region but instead switches to the 'U' region, while the cell that switches to the '0' region ends up in the 'H' region, as shown by the FP. It should be noted that although the faults are strong and hard to detect, they can still be captured more easily than weak faults. Table III further shows that the range of fault types is interrupted. This is caused by the random behavior of filament growth and breakage, which sometimes leaves the cell in an unpredictable state.

[0071] Table IV Fault categories and FPs for R-RAM series resistance faults

[0072]

[0073] For R in Table IV sd The application of the method to traditional resistor defects is shown. Also, strongly hard-to-detect faults are marked in boldface, while easy-to-detect faults are in regular font. Table IV also shows that as the length of S increases, the fault coverage increases. For example, for a defect size of R = 5,01 kΩ, strongly hard-to-detect faults (for sequence S = 1r1w0) and strongly easy-to-detect faults (for sequence S = 1r1w1w0) can be observed. The first sequence results in strongly hard-to-detect 2d-WTF1U faults, while the second sequence enhances the fault behavior and causes strongly easy-to-detect 3d-WTF11 faults.

[0074] For comparison, Table IV also shows the same sequences as shown in Table III. Here, it can be seen that the difference is that the resistor defect model cannot switch to the '0' state with increasing resistance, while the device-aware defect model shows that the device is still switching between states. This difference is caused by the fact that the series resistor reduces the voltage on R-RAM device 1 and thus never reaches the switching threshold. From the above, it can be concluded that the DAT method of the present invention and the conventional method result in the sensitization of different faults. The device-aware model can always indicate the switching of the cell, while the resistor defect model only shows switching behavior within a limited range of defects and thus does not correctly model the defect. Using an inappropriate defect model will result in low-quality testing that detects non-existing faults and misses existing faults. In addition, it can be concluded that the analysis method can increase the fault coverage by extending the length of S. Such an extension may cause the defect to transform the fault behavior from weakly hard-to-detect faults to strongly hard-to-detect faults and from strongly hard-to-detect faults to strongly easy-to-detect faults, thus increasing the detection probability.

[0075] The results from the previous step are used to develop the R-RAM test step. In the fault modeling step, it was observed that the faults caused by these defects are related to the R-RAM memory device 1 being in an incorrect state (i.e., 'U', 'L', or 'H'), thus causing hard-to-detect faults 24. Therefore, a DfT scheme that focuses on detecting whether the cell is in one of these states is needed. In the article "Testing open defects in memristor-based memories" by S. Hamdioui et al. in the IEEE Transactions on Computers, Vol. 64, No. 1, January 2015, a short write time and low write voltage DfT scheme that can be used to detect whether the resistance of the cell is in the 'U' state is described, and this article is incorporated herein by reference. It should be noted that modifications to this scheme will also allow the detection of cells in the 'L' and 'H' states. Conversely, R sdThe defect model sensitizes many unrealistic strong and easily detectable faults, e.g., IRF11 and WTF11. Although they can be easily detected by the elements in the March test, testing for them will still increase unnecessary test costs.

[0076] In the following paragraphs, for the memory device 1 based on STT-MRAM technology, the DAT method of the present invention is used and compared with the conventional method. Examples of STT-MRAM manufacturing defects are described, with particular emphasis on pinhole defects, which are then the subject of the application of the embodiments of the present invention.

[0077] The STT-MRAM manufacturing process mainly includes the table-mixed CMOS manufacturing steps and the integration of magnetic tunnel junction (MTJ) devices into the metal layer. The bottom-up manufacturing process and the vertical multi-layer structure of the STT-MRAM cell are known to those skilled in the art, see for example the article "Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic" by Y.J. Song et al. in IEDM, 2016, which is incorporated herein by reference. Based on the manufacturing stage, STT-MRAM defects can be classified into front-end-of-line (FEOL) defects and back-end-of-line (BEOL) defects. Since the MTJ is integrated into the metal layer during BEOL processing, BEOL defects can be further classified into MTJ manufacturing defects and metallization defects.

[0078] Table V STT-MRAM Defect Classification

[0079]

[0080] Table V lists some potential defects of the STT-MRAM memory device 1. Among these defects, pinhole defects in the MgO tunnel junction are regarded as one of the most important defects that may occur in the STT-MRAM memory device. Pinhole defects are formed due to unoptimized deposition processes. This may cause the formation of metal short circuits in the MgO tunnel junction due to boron diffusion into the MgO junction or other metal impurities. Therefore, this results in the degradation of both the resistance-area product (RA) and the tunneling magnetoresistance ratio (TMR) parameters. In addition, due to Joule heating and the electric field on the circumference of the pinhole, the area of small pinholes may grow. Therefore, if small pinhole defects cannot even be detected in the manufacturing test, they may cause premature breakdown of the electric field.

[0081] For the conventional resistor-based defect modeling method, the pinhole defect is modeled as a series resistor R sdor a parallel resistor R pd , which is similar to the case of modeling formation defects in the R-RAM memory device 1 as described above.

[0082] From a comprehensive theoretical study and experimental characterization of pinhole defects in various MTJ devices, it is evident that RA and TMR are two key technical parameters significantly affected by pinhole defects. Therefore, as the first part of the implementation of the DAT method, the effects of pinholes on these two technical parameters are modeled as follows.

[0083]

[0084] where A ph (ranging between 0 and 1) is the normalized pinhole area with respect to the cross-sectional area A of the MTJ device. RA df and TMR df are the RA and TMR parameters of the defect-free MTJ, respectively (i.e., when A ph = 0). RA bd is the RA obtained after breakdown.

[0085] As the next step in the example method, equations (6) and (7) are integrated into a defect-free MTJ compact model that has been calibrated with measurement data from good devices. In this way, the defect-free MTJ model is converted into a defective MTJ model that can predict the electrical impact of pinhole defects on the MTJ device. Additionally, the pinhole size can be tuned by varying the input variable A ph .

[0086] Then, fitting and model optimization are applied by performing electrical characterization on both good MTJ devices and devices with suspected pinhole defects. By fitting to the measured silicon data, the pinhole-parameterized MTJ compact model can be further optimized. By highlighting devices with suspected pinhole defects and the curve fitting method, the value RA bd = 0.41 Ω·μm 2 is obtained.

[0087] In general, yet another example is provided, where the memory device 1 is a spin-transfer torque magnetic random access memory (STT-MRAM) cell, the technical parameter Tp includes one or more of the resistance area product RA, the tunneling magnetoresistance ratio TMR, the anisotropic magnetic field H k of the free layer, the saturation magnetization M s of the free layer, and the barrier height φ of the tunnel junction, and the electrical parameters include the resistance R P in the P state, the resistance R AP in the AP state, the critical switching current I C , and the average switching time t W .

[0088] As a next step, the fault modeling method of the present embodiment is applied to the pinhole defect by performing a fault analysis in the DAT method manner.

[0089] Table VI Single-cell static fault modeling results of STT-MRAM memory devices

[0090]

[0091] Table VI shows that a large enough pinhole (A ph > 0.62%) causes the MTJ device to fall into the resistance range of the '0' state or even the 'L' state. The corresponding fault primitive FP is listed in Table VI. As the pinhole becomes smaller (A ph between 0.08% and 0.61%), R P is transformed into the 'L' state and R AP is transformed into the 'U' state. Depending on the exact MTJ resistance in the AP state, the read value can be in three cases: 1) '0', 2) random ('?'), and 3) '1'. In case 1) where R AP is significantly smaller than the resistance of the reference cell (i.e., A ph between 0.36% and 0.61%), the read value of the device in the AP state is '0'. In case 2) where R AP is close to the resistance of the reference cell (i.e., A ph between 0.33% and 0.35%), the read value can be random. In other words, the read operation is unstable, and thus both '0' and '1' are possible read values. In case 3) where R AP is much larger than the resistance of the reference cell (i.e., A ph between 0.08% and 0.32%), the readout is '1'. As the pinhole area becomes smaller between 0.05% and 0.07%, the expected '1' state is transformed into the 'U' state, while the expected '0' state remains correct. If the pinhole size is less than 0.04%, the device behaves normally and thus does not cause a decisive fault.

[0092] Conversely, based on R sd and R pdInjecting a defect-free netlist (i.e., the prior art method) to perform fault modeling, and the simulation results are also shown in Table VI. Comparing the fault modeling results based on the two defect modeling methods shows that the fault behavior of memory device 1 cannot be captured by the conventional resistor-based defect modeling method due to pinhole defects. It is clear from Table VI that no FPs sensitized by the pinhole defect model of the embodiments of the present invention are observed in the simulation results of the conventional method. This is because the MTJ device 1 is considered a black box in the conventional method. Therefore, only the '0' and '1' states are seen in the simulation. However, the simulation and measurement data using the embodiments of the present invention clearly show that pinhole defects can cause the device to enter the states 'U' and 'L'. This means that traditional methods relying on fault modeling and test development may lead to low-quality test solutions, which in turn means a higher number of omissions. The conventional method results in some fault primitives that cannot be applied to STT-MRAM (i.e., the calibration model based on pinhole defects, not found by our method). For example, using a series resistor R sd results in IRF00, while using a parallel resistor R pd results in WTF00. This may lead to tests targeting non-existing faults, which means a waste of test time.

[0093] Based on the simulation results using the calibrated pinhole defect model, it is obvious that the larger the pinhole, the greater the fault effect, and thus the easier it is to detect. As shown in Table VI, pinhole defects with a specific range of defect sizes can cause multiple faults. However, any test that can detect one of these faults can guarantee the detection of this specific pinhole defect. For example, when the pinhole area A ph is greater than 0.79%, there are eight sensitized fault primitives FPs. Among these FPs, SF1 L (marked in bold in the table) can be simply detected by a read '1' operation because these are strongly detectable faults. Therefore, for pinholes with A ph > 0.79%, is the detection condition in the March algorithm. The detection conditions for different pinhole sizes are listed in the last column of Table VI. Combining the last three rows in Table VI, it is obvious that any March test including the element can guarantee that A phPinhole defect detection of > 0.36% is an easily detectable fault. However, for smaller pinhole defects, the March test cannot guarantee their detection because the defects cause hard-to-detect faults. Due to the cumulative Joule heating, the area of small pinhole defects increases over time, so if not detected during manufacturing testing, they may cause premature breakdown of the field. This requires DfT design or stress testing dedicated to extremely small pinhole defects. One possible solution is to subject the STT-MRAM memory device 1 to a sequence of hammer write '1' operations with elevated voltage or extended pulse width to deliberately accelerate the growth of pinhole defects, thereby causing easily detectable faults. However, this method is prohibitively expensive for high-volume testing. Additionally, the amplitude and duration of the hammer write pulse need to be carefully tuned to avoid any unintentional damage to good memory devices 1 while maintaining acceptable test effectiveness and efficiency.

[0094] According to the present invention, exemplary embodiments of a device-aware testing method are described above, the device-aware testing method having three different and subsequent steps: defect modeling, fault modeling, and test development. Contrary to conventional resistance-based testing, the DAT embodiments result in an accurate fault model and thereby enable high-quality (close to DPPB level) testing.

[0095] As described above for R-RAM and STT-MRAM memory devices 1, the DAT embodiments described herein result in a more accurate fault model that reflects physical defects. Many sensitized faults are unique and cannot be observed by conventional resistor-based defect modeling methods. Thus, the present method clearly reduces the number of test escapes and increases test quality.

[0096] Accurately modeling defects and creating a fault dictionary for them can significantly accelerate the yield learning process. Since device-aware testing can be used to model each defect individually rather than using a resistance defect model for all defects, a unique fault signature can be created for each defect. This improves the yield learning curve because defects can be more accurately diagnosed based on the fault signature.

[0097] Currently, companies spend a large amount of time on functional testing (or system testing) to compensate for the fault coverage due to the limitations of traditional fault modeling and testing. The DAT embodiments of the present invention allow the development of appropriate and efficient structural testing that can be applied at the manufacturing stage; thus, significantly reducing the expensive test time spent on board-level testing.

[0098] Finally, the DAT embodiments are not limited to emerging memory device technologies, and the method can also be applied to the test generation of other circuits (e.g., SRAM and logic) and other types of devices (such as FinFET and PCM devices).

[0099] The present invention has been described above with reference to a plurality of exemplary embodiments shown in the accompanying drawings. Modifications and alternative implementations of some parts or elements are possible and are included within the scope of protection as defined by the appended claims.

Claims

1. A method for testing an integrated circuit device (1), the method comprising: Performing defect modeling on the integrated circuit device (1) based on the impact of physical defects on the technical parameters of the integrated circuit device (1) and subsequently on the electrical parameters of the integrated circuit device (1); Performing fault modeling on the integrated circuit device (1) based on the information obtained from the defect modeling; Performing test development based on the information obtained from the fault modeling; and Executing the test on the integrated circuit device (1), wherein the defect modeling comprises: Perform physical defect analysis (10) to provide a set of valid technical parameters (Tp df ) modified from a set of defect-free technical parameters (Tp eff ) associated with the integrated circuit device (1); and Use the set of valid technology parameters (Tp eff ) to perform electrical modeling (11) to provide a defect-parameterized electrical model (16; 17) based on a defect-free electrical model of the integrated circuit device (1), and wherein the fault modeling (20) comprises fault analysis (22) based on the defect parameterized electrical model (16; 17), and wherein the fault analysis (22) comprises: defining a fault space that includes a description of a plurality of possible faults (23, 24, 27); and determining which of the plurality of possible faults (23, 24, 27) are realistic for the physical defects during the execution of the test; wherein the fault analysis (22) comprises determining a list of possible faults (23, 24, 27), the list of possible faults including easily detectable faults (23) and / or difficult-to-detect faults (27), the easily detectable faults (23) being functional faults that can be detected by applying an operation sequence to the integrated circuit device (1), and the difficult-to-detect faults (27) being faults that cause parametric faults in the integrated circuit device (1).

2. The method according to claim 1, wherein performing defect modeling on the integrated circuit device (1) comprises performing defect modeling on a part of the integrated circuit device (1).

3. The method according to claim 1 or 2, wherein performing defect modeling on the integrated circuit device (1) further comprises calibration (12) of the defect parameterized electrical model (16; 17).

4. The method according to claim 1 or 2, wherein the physical defect analysis (10) comprises identifying a set of possible physical defects (D).

5. The method according to claim 1 or 2, wherein test development comprises providing a test plan that includes a set of operations on the integrated circuit device (1) for each easily detectable fault (23) identified in the fault analysis (22), and a design for testability modification of the integrated circuit device (1) for each difficult-to-detect fault (27).

6. The method according to claim 1, wherein the integrated circuit device (1) is a memory device (1).

7. The method according to claim 1 or 2, wherein the integrated circuit device (1) is a logic device (1).

8. The method according to claim 6, wherein the memory device (1) is a resistive random access memory (R-RAM) cell, The technical parameters include one or more of the following: oxide thickness (t ox ), conductive filament length (l CF ), gap length (l 间隙 ), top width of the conductive filament (Φ T ), bottom width of the conductive filament (Φ B ), and The electrical parameters include one or more of the following: reset threshold (V 重置 ), set threshold (V 设定 ), reset resistance (R HRS ), set resistance (R LRS ), high resistance state to low resistance state switching delay (t H→L ), low resistance state to high resistance state switching delay (t L→H ).

9. The method according to claim 6, wherein the memory device (1) is a spin transfer torque magnetic random access memory (STT-MRAM) cell, The technical parameters include one or more of the following: resistance area product (RA), tunneling magnetoresistance (TMR), anisotropic magnetic field (H k ) of the free layer, saturation magnetization (M s ) of the free layer, barrier height (φ) of the tunnel junction, and The electrical parameters include one or more of the following: the resistance in the P state (R P ), the resistance in the AP state (R AP ), the critical switching current (I C ), the average switching time (t W ).

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