Method for verifying external software modules for use by a system on a chip

Abstract

The present disclosure relates to a method for verifying an external software module for use by a system-on-chip. According to one aspect, a system-on-chip is proposed, comprising a memory storage, a computation circuit, a comparison circuit and a verification circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute a number of modified software modules from the external software module and to iteratively compute a check value until a final check value is obtained. Each check value is computed from a given modified software module and a previously computed check value starting from a predefined initial check value. The comparison circuit is configured to compare the final check value with an expected value stored in the system-on-chip. The verification circuit is configured to verify the external software module when the final check value is equal to the expected value.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to French application No. FR 2013782, filed on December 21, 2020, which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to a system on chip, and in particular embodiments to the verification of an external software module for use by a system on chip. BACKGROUND

[0004] An external software module is a software program (e.g., code, instructions, etc.) that is not initially provided to the system on chip but that can be injected into the system on chip. For example, an external software module can be used to implement a service that is not initially provided to the system on chip.

[0005] For example, for cost reasons, some systems on chip do not include a non-volatile memory, such as a flash memory or a ROM memory, for storing firmware that can be used to implement some special tasks, such as platform debugging, profiling, and reconfiguration, but also deep address / fault analysis. It can be advantageous to provide such firmware to the system on chip after field deployment.

[0006] However, for security reasons, it is advantageous for the system on chip to verify the external software module before implementing the external software module to ensure that the external software module is an authorized software module. To verify the external software module, the system on chip typically implements a complex method using high-level security services.

[0007] However, in low-cost systems on chip, there can be no security features, such as cryptographic features, in the hardware or software to implement some high-level security services. Thus, for such systems on chip, there are no features to verify the external software module. Moreover, in such systems on chip, certain areas of the system on chip can not be accessible outside the factory, as not all security programs are available. It would be advantageous to provide a method that is able to verify and authenticate an external software module for use by a system on chip. SUMMARY

[0008] According to one aspect, a method for verifying an external software module for use by a system on chip is proposed. The method comprises the following steps performed by the system on chip: obtaining the external software module; computing a number of modified software modules from the external software module; iteratively computing a check value until a final check value is obtained, each check value being computed from a predefined initial check value at least from a given modified software module and a previously computed check value; comparing the final check value with an expected value stored in the system on chip; and verifying the external software module when the final check value is equal to the expected value.

[0009] In an embodiment, the method comprises computing a first check value from the initial check value and the modified software module.

[0010] In an embodiment, the method comprises iteratively computing several check values, each check value being computed from at least one previously computed check value and the modified software module.

[0011] In an embodiment, the check value computation is iterated a predefined number of times until a final check value is obtained, and the final check value is compared to an expected value. The expected value is defined by the manufacturer of the system-on-chip from the certified software module.

[0012] In an embodiment, the expected value is computed from the certified software module in the same way as the final check value. If the final check value is equal to the expected value, the probability that the external software module is the certified software module is high, and the external software module is validated for use by the system-on-chip.

[0013] The iterations performed for the computation of the final check value reduce the probability of validating an external software module that is not the certified software module. The method advantageously allows validating an external software module in a simple and secure way.

[0014] Low-cost system-on-chips usually comprise a cyclic redundancy check circuit. In an embodiment, each check value is computed by using a cyclic redundancy check algorithm. Advantageously, by using a cyclic and redundancy check module, the system-on-chip does not require any additional security module. Thus, the method can be implemented on low-cost systems having a cyclic redundancy check circuit.

[0015] Alternatively, each check value is computed by using a hash algorithm. In an embodiment, each check value is also computed using the length of the external software module. Computing the check value using the length of the external software module advantageously increases the robustness of the method. Further, computing the check value using the length of the external software module is to prevent length extension attacks.

[0016] In an embodiment, to compromise the system-on-chip, a hacker must be able to generate a software module that has the same length as the certified external module and for which the system-on-chip can generate a final check value equal to the expected value of the certified external module. The probability of successfully developing such a software module is low.

[0017] In an embodiment, each modified software module is computed by a non-linear function. The use of a non-linear function guarantees a high independence between two successively generated modified software modules. Thus, it increases the robustness of the method.

[0018] Alternatively, each modified software module can be computed by a linear function.

[0019] Advantageously, the expected value is stored in a configuration bit of the system on chip or encoded at register transfer level.

[0020] In an embodiment, a system on chip is proposed. The system on chip comprises a memory configured to store an external software module and a computing circuit configured to: compute, from the external software module, a number of modified software modules; iteratively compute a check value until a final check value is obtained - each check value being computed from a predefined initial check value at least according to a given modified software module and a previously computed check value. The system on chip further comprises a comparison circuit configured to compare the final check value with an expected value stored in the system on chip and a verification circuit configured to verify the external software module when the final check value is equal to the expected value.

[0021] In an embodiment, the memory is a volatile memory.

[0022] In an embodiment, the system on chip comprises a processor for implementing the comparison circuit and the verification circuit.

[0023] In an embodiment, the computing circuit comprises a cyclic redundancy check circuit for computing each check value.

[0024] In an embodiment, the computing circuit comprises a hash circuit for computing each check value.

[0025] In an embodiment, the computing circuit is configured to compute each check value by using a length of the external software module.

[0026] In an embodiment, the computing circuit comprises a non-linear function circuit configured to compute each modified software module by a non-linear function.

[0027] In an embodiment, the non-linear function comprises a shift of bits of the modified software module.

[0028] In an embodiment, the expected value is stored in a configuration bit or encoded at register transfer level.

[0029] In an embodiment, a number of expected values are stored in the system on chip.

[0030] Different predefined expected values can be used to verify different external software modules that can provide different additional services to the system on chip. BRIEF DESCRIPTION OF DRAWINGS

[0031] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

[0032] Figure 1 is a flowchart of an embodiment method for verifying an external software module;

[0033] Figure 2 This is a diagram of a partial embodiment of a system-on-a-chip;

[0034] Figure 3 This is a timing diagram of an embodiment for obtaining the final verification value; and

[0035] Figure 4 This is a diagram of a partial embodiment of a system-on-a-chip. Detailed Implementation

[0036] Figure 1 A method for verifying external software modules received by a system-on-a-chip (SoC) for use by the SoC is illustrated, the method being implemented by the SoC. The external software module may be a software module that provides additional services to the SoC. In an embodiment, each external software module that the SoC can use is defined by the SoC manufacturer.

[0037] The system-on-chip (SoC) is configured to calculate a number of check values ​​CRC(k) based on an external software module, where k is an integer from 1 to N. Therefore, the SoC is configured to calculate a number of check values ​​CRC(k) from a first check value CRC(1) to a final check value CRC(N). The check values ​​are calculated based on a modified software module derived from the external software module received by the SoC.

[0038] The system-on-chip is configured to verify an external software module based on a calculated final checksum CRC(N). In an embodiment, the external software module is verified if the final checksum CRC(N) equals an expected value defined by the manufacturer.

[0039] In this embodiment, the number N is chosen to reduce the probability of obtaining the same final checksum for two different external software modules. The larger the value of N, the lower the probability of obtaining the same final checksum for two different software modules. In this embodiment, the number N is chosen to minimize the computation time of the final checksum. In this embodiment, the number N is greater than 10. In this embodiment, the number N is between 15 and 20.

[0040] like Figure 1 As shown, the method includes acquiring external software module 10 from the system-on-a-chip.

[0041] Next, the method includes an initialization step 11, in which the value k is initialized to 1, and an initial checksum CRC(0) and the number N of checksums to be calculated are defined. The initial checksum CRC(0) can be any value. In an embodiment, the initial checksum is randomly defined.

[0042] The method comprises a loop 12 for computing a check value from different modified software modules. In an embodiment, the loop comprises a step 13 in which a modified software module is computed from an external software module using a non-linear function.

[0043] In an embodiment, the modified software module is denoted SW_module#(k) = F[SW_module#(k-1)], where SW_module#(k) is the modified software module to compute, SW_module#(k-1) is the external software module when k is equal to 1 or the last computed modified software module when k is greater than or equal to 2, and F is a non-linear function.

[0044] In some embodiments, the modified software module is denoted SW_module#(k) = Fk[ESW_module], where SW_module#(k) is the modified software module to compute, ESW_module is the external software module, and Fk is a non-linear function depending on k.

[0045] In an embodiment, the external software module is formed from a binary data word which is modified by a non-linear function to obtain a modified data word forming the modified software module.

[0046] In some embodiments, the modified software module is computed from the external software module using a linear function. The function used to compute the modified software module allows to obtain a new modified software module different from the last computed modified software module.

[0047] The loop 12 comprises, at step 14, a computation of a check value CRC(k) from the modified software module, the last computed check value CRC(k-1) or the initial check value CRC(0), and the length (S) of the external software module. The length (S) of the external software module is the number of words constituting the external software module. In an embodiment, the check value is computed using a cyclic redundancy check algorithm such as the CRC-32 algorithm, the HASH algorithm, etc.

[0048] In an embodiment, the check value is computed from a concatenated binary word of the modified software module used to compute the check value, the previous check value, and the length (S) of the external software module.

[0049] In an embodiment, the check value CRC(k) is denoted as CRC(k) = CRC(SW_module#(k) | CRC(k-1) | S), where k is an integer between 1 and N, where SW_module#(k) is the modified software module, CRC(k-1) is the last computed check value from a previous modified software module SW_module#(k-1) or an initial check value CRC(0), and (S) is the length of the external software module.

[0050] At step 15, the number k is compared to the number N. If the number k is less than the number N, steps 13 to 15 are repeated to compute a new check value and the number k is incremented. However, when k is equal to N, this indicates that the last computed check value is the final check value. In this case, the method comprises a step 16 in which the final check value is compared to an expected value defined by the manufacturer. If the final check value CRC(N) is different from the expected value defined by the manufacturer, the external software module is rejected at step 17. If the final check value CRC(N) is equal to the expected value defined by the manufacturer, the external software module is validated at step 18. Once validated, the external software module can be used by the system on chip.

[0051] Advantageously, the use of the previous check value CRC(k-1) to compute a new check value guarantees a chained effect on the computation of each check value. Moreover, the use of the length (S) of the external software module to compute the check value increases the robustness of the method. Advantageously, the use of the length (S) of the external software module to compute the check value prevents length extension attacks.

[0052] Generally, to compromise the system on chip, a hacker must be able to generate a software module that has the same length as an authenticated external module and for which the system on chip can generate a final check value equal to the expected value of the authenticated external module.

[0053] Figure 2 An embodiment part of a system on chip configured to generate a final check value is illustrated. The system on chip comprises a finite state machine circuit (FSM), a volatile memory storage (MEM), a non-linear function circuit (NLFM), a multiplexer (MUX), a cyclic redundancy check circuit (CRCM) and a latch (LTCH).

[0054] The volatile memory storage (MEM) is configured to store an external software module (ESW) or program. The volatile memory storage (MEM) can be a RAM (“Random Access Memory”).

[0055] The finite state machine circuit (FSM) comprises different inputs and outputs. A first input is configured to receive a reset signal (RST). The reset signal (RST) is used to reset the finite state machine circuit (FSM).

[0056] A second input is configured to receive a system clock signal (SYS CLK). The finite state machine circuit (FSM) operates according to the system clock signal (SYS CLK).

[0057] The finite state machine circuit (FSM) further comprises an output configured to emit a clock signal (RCLK) to an input of a volatile memory storage device (MEM). The clock signal (RCLK) is generated by the finite state machine circuit (FSM).

[0058] The finite state machine circuit (FSM) further comprises an output configured to emit a signal (RSEL) to another input of the volatile memory storage device (MEM). The signal (RSEL) is used to select the volatile memory storage device (MEM).

[0059] The finite state machine circuit (FSM) further comprises an output configured to emit a read signal (RD) to another input of the volatile memory storage device (MEM). The read signal (RD) is used to indicate a read of the volatile memory storage device (MEM).

[0060] The finite state machine circuit (FSM) further comprises an output for delivering an address signal (ADDR) to another input of the volatile memory storage device (MEM). The address signal (ADDR) is an address of a data word of an external software module (ESW) in the volatile memory storage device (MEM).

[0061] An input of the finite state machine circuit (FSM) is configured to receive a number N of check values to be generated for obtaining a final check value.

[0062] The finite state machine circuit (FSM) further comprises an input configured to receive a signal (NXT) from an output of a non-linear function circuit (NLFM).

[0063] The finite state machine circuit (FSM) further comprises an input configured to receive a signal (PVS) from an output of the non-linear function circuit (NLFM).

[0064] The finite state machine circuit (FSM) further comprises an input configured to receive a signal (FRDY) from an output of the non-linear function circuit (NLFM).

[0065] The finite state machine circuit (FSM) further comprises an output configured to deliver a number k at the input of the non-linear function circuit (NLFM). The finite state machine circuit (FSM) is configured to increment the number k after each computation of a check value.

[0066] In an embodiment, the finite state machine circuit (FSM) is configured to initialize the number k to 1 to compute a first check value CRC(1).

[0067] The finite state machine circuit (FSM) comprises an output configured to emit a signal (SEL) to a multiplexer (MUX).

[0068] Another output of the finite state machine circuit (FSM) is configured to pulse the signal (LTCH_R) delivered to the latch (LTCH).

[0069] An output of the finite state machine circuit (FSM) is configured to emit a signal (CLK_CRC) to the cyclic redundancy check circuit (CRCM).

[0070] Another input of the finite state machine circuit (FSM) is configured to receive a signal (SW_L) corresponding to the length (S) of the external software module (ESW).

[0071] The finite state machine circuit (FSM) comprises an output configured to emit a signal (RDY) to a processor when a final check value has been computed.

[0072] The finite state machine circuit (FSM) is configured to implement a method for computing a final check value CRC(N).

[0073] The non-linear function circuit (NLFM) is configured to transform each data word (DAT) of the external software module (ESW) into a modified data word Fk(DAT). By doing so, the non-linear function circuit (NLFM) is configured to generate a modified software module formed of each modified data word Fk(DAT) generated from a data word (DAT) of the external software module (ESW).

[0074] In an embodiment, the system on chip is configured so that each modified software module is generated by the non-linear function circuit (NLFM) directly from the external software module (ESW).

[0075] In an embodiment, the non-linear function circuit (NLFM) is configured to implement a non-linear function. The non-linear function depends on the number k generated by the finite state machine circuit (FSM) to generate a different modified software module for each iteration of k. The non-linear function can comprise a shift of bits of a data word (DAT) of the external software module (ESW) received at the input of the non-linear function circuit (NLFM).

[0076] For example, the non-linear function can be expressed as Fk(DAT) = DAT « k, where Fk(DAT)LSB+k-m = not(DATMSB-m), m from 0 to k-1, where Fk(DAT) is a modified data word computed from a data word (DAT), Fk(DAT)LSB is the least significant bit of the modified data word Fk(DAT), DATMSB is the most significant bit of the data word (DAT).

[0077] The non-linear function can include performing an "exclusive OR" function between different data words (DAT) of the external software module (ESW). For example, the non-linear function can be expressed as: Fk[DAT(ADDR)] = DAT(ADDR-k) xor DAT(ADDR) xor DAT(ADDR+k) when ADDR ≥ k and ADDR < ADDR_max-k; Fk[DAT(ADDR)] = DAT(ADDR) xor M when ADDR < k or ADDR ≥ ADDR_MAX-k, where Fk[DAT(ADDR)] is a modified data word computed for a data word (DAT) stored at address ADDR, DAT(ADDR-1) is the previous data word in the memory, and DAT(ADDR+1) is the next data word in the memory, ADDR_MAX is the maximum data word address of the software module used to compute the new modified software module, the address ADDR is between 0 and the address ADDR_MAX, ADDR_MAX is equal to the length (S) of the external software module, and M is a constant, for example 0xA5.

[0078] The non-linear function circuit (NLFM) includes outputs for delivering signals (NXT), (PVS), and (FRDY) to the finite state machine circuit (FSM). The non-linear function circuit (NLFM) uses the signal (PVS) to request a data word stored in the volatile memory storage (MEM) at a previous address ADDR-k of the address ADDR of the data word (DAT) to the finite state machine circuit (FSM).

[0079] The non-linear function circuit (NLFM) uses the signal (NXT) to request a data word (DAT) stored in the volatile memory storage (MEM) at a next address ADDR+k of the address ADDR of the data word (DAT) to the finite state machine circuit (FSM).

[0080] The non-linear function circuit (NLFM) uses the signal (FRDY) to indicate to the finite state machine circuit (FSM) that the computed modified data word Fk(DAT) is available.

[0081] The non-linear function circuit (NLFM) further comprises an output for delivering the modified data word Fk(DAT) to a multiplexer (MUX).

[0082] The multiplexer (MUX) comprises different inputs for receiving the signal CRC(0), the modified data word Fk(DAT), the length of the external software module (ESW) (SW_L) and the last computed check value CRC(k-1).

[0083] The multiplexer (MUX) further comprises an output connected to the input of the cyclic redundancy check circuit (CRCM).

[0084] The multiplexer (MUX) further comprises an input for receiving a signal (SEL) from the finite state machine circuit (FSM). The signal (SEL) allows to select an input of the multiplexer (MUX) to be delivered at the output of the multiplexer (MUX).

[0085] The cyclic redundancy check circuit (CRCM) is configured to compute check values CRC(k). In an embodiment, the check values CRC(k) are computed from the modified data word Fk(DAT) computed by the non-linear function circuit (NLFM), the last computed check value or an initial check value and the length of the external software module (ESW) (SW_L).

[0086] In an embodiment, the modified data word Fk(DAT), the last check value CRC(k-1) or an initial check value CRC(0), and the length of the external software module (ESW) (SW_L) are provided to the cyclic redundancy check circuit (CRCM) through a multiplexer (MUX) controlled by the finite state machine circuit (FSM). In an embodiment, the cyclic redundancy check circuit (CRCM) can perform a CRC-32 algorithm.

[0087] The cyclic redundancy check circuit (CRCM) comprises an input for receiving a signal (CLK_CRC) generated by the finite state machine circuit (FSM).

[0088] The cyclic redundancy check circuit (CRCM) comprises an output for delivering the check values to an input of a latch (LTCH).

[0089] The cyclic redundancy check circuit (CRCM) is configured to compute a number of check values equal to the number N received at the input of the finite state machine circuit (FSM). The Nth check value is the final check value.

[0090] The latch (LTCH) is configured to temporarily store each check value computed by the cyclic redundancy check circuit (CRCM).

[0091] The latch (LTCH) also comprises an input for receiving a signal (LTCH_R) from the finite state machine circuit (FSM).

[0092] The latch (LTCH) comprises an output for delivering the last computed check value by the cyclic redundancy check circuit (CRCM) when the signal (LTCH_R) is asserted by the finite state machine circuit (FSM).

[0093] The output of the latch (LTCH) is connected to an input of the multiplexer (MUX) for delivering the signal CRC(k-1).

[0094] The output of the latch (LTCH) is also connected to the processor.

[0095] The latch (LTCH) is thus used for delivering the last computed check value CRC(k-1) to the multiplexer (MUX) for computing another check value CRC(k) by the cyclic redundancy check circuit (CRCM).

[0096] After the final check value CRC(N) is computed, the latch (LTCH) is configured to store the final check value before delivering it to the processor. When the final check value is available to the processor, the finite state machine circuit (FSM) is configured to assert the signal (RDY).

[0097] When the signal (RDY) is asserted, the processor is configured to receive the final check value. Then, the processor is configured to compare the final check value with a predefined expected value. The expected value is defined by the system-on-chip manufacturer according to the authorized external software module (ESW). In an embodiment, the expected value is stored in the system-on-chip. For example, the expected value can be stored in a configuration bit or encoded at the register transfer level (RTL).

[0098] If the final check value is equal to the expected value, it means that the probability that the external software module (ESW) provided to the system-on-chip is a higher probability that the external software module (ESW) provided to the system-on-chip is an authorized software module. In this case, the processor is configured to validate the external software module (ESW). Then, the external software module (ESW) can be used by the system-on-chip.

[0099] Otherwise, if the final check value is not equal to the expected value, it means that the external software module (ESW) provided to the system-on-chip is not an authorized software module. In this case, the processor is configured to reject the external software module (ESW). Thus, in this case, the system-on-chip cannot use the external software module (ESW).

[0100] Figure 3 It is shown that the system-on-chip comprises a cyclic redundancy check circuit (CRCM) for computing a check value CRC(k) from a data stream D(k) and a finite state machine circuit (FSM) for controlling the cyclic redundancy check circuit (CRCM). Figure 1An example of the timeline of the signals used for obtaining the final check value CRC(N) by the different elements of the system on a chip. Initially, an external software module (ESW) to be verified is stored in a volatile memory storage (MEM). In an embodiment, the external software module (ESW) is divided into several data words stored in the memory at different addresses. In one embodiment, each data word comprises 32 bits.

[0101] The length (S) of the external software module (ESW) is received by the finite state machine circuit (FSM) via the signal (SW_L). The number N of check values to be computed is also received by the finite state machine circuit (FSM).

[0102] In an initialization step, the finite state machine circuit (FSM) selects with the signal (SEL) the input of the multiplexer (MUX) receiving the initial check value CRC(0) which can be encoded in RTL. For example, the finite state machine circuit (FSM) selects with the value "Sel 0" of the signal (SEL) the input n°0 of the multiplexer. The initial check value CRC(0) can be equal to any value X.

[0103] The clock signal (CLK_CRC) is pulsed to provide the initial check value to the cyclic redundancy check circuit (CRCM). The finite state machine circuit (FSM) pulses the signal (LTCH_R) to store the signal CRC(0) in the latch (LTCH). This initial check value is used to compute the first check value CRC(1).

[0104] A modified data word Fk(DAT) of each word of the external software module (ESW) is computed to compute the check values.

[0105] In an embodiment, the finite state machine circuit (FSM) delivers the address of the data word (DAT) to the volatile memory storage (MEM). The finite state machine circuit (FSM) also pulses the signal (RD) to indicate a read of the data word (DAT) stored in the volatile memory storage (MEM) at the address delivered by the finite state machine circuit (FSM). In an embodiment, the read of the data word (DAT) starts at the rising edge of the clock signal (RCLK).

[0106] The finite state machine circuit (FSM) also asserts the signal (RSEL) to select the volatile memory storage (MEM).

[0107] Furthermore, the finite state machine circuit (FSM) selects with the signal (SEL) the input of the multiplexer (MUX) receiving the modified data word Fk(DAT). For example, the finite state machine circuit (FSM) selects with the value "Sel 1" of the signal (SEL) the input n°1 of the multiplexer.

[0108] The data word (DAT) is delivered by the volatile memory storage (MEM) to the non-linear function circuit (NLFM). Next, the non-linear function circuit (NLFM) computes a modified data word Fk(DAT) as a function of the data word (DAT) delivered by the volatile memory storage (MEM). In an embodiment, the computation of the modified data word Fk(DAT) is performed as a function of the system clock signal (SYS CLK).

[0109] In the case where the non-linear function circuit (NLFM) needs the previous or next data word of the external software module (ESW) to compute the modified data word Fk(DAT), the non-linear function circuit (NLFM) asserts the signal (PVS) or the signal (NXT).

[0110] When the finite state machine circuit (FSM) receives the signal (PVS) or the signal (NXT), the finite state machine circuit (FSM) requests a read of the data word stored at the previous or next address of the volatile memory storage (MEM). Then, the data word stored at the previous or next address is delivered to the non-linear function circuit (NLFM).

[0111] When the computation of the modified data word Fk(DAT) is finished, the non-linear function circuit (NLFM) asserts the signal (FRDY) to indicate to the finite state machine circuit (FSM) that the modified data word Fk(DAT) is available.

[0112] The finite state machine circuit (FSM) pulses the clock signal (CLK CRC) to deliver the modified data word Fk(DAT) to the cyclic redundancy check circuit (CRCM). When the modified data word Fk(DAT) has been computed for each data word (DAT) of the external software module (ESW), the modified software module is obtained.

[0113] For example, in Figure 3 The non-linear function circuit does not need the previous or next data word of the external software module. The modified data word F1(Data 0) is computed as a function of the data word (DAT) a 0 stored at the address 0x00...0 of the volatile memory, where k is equal to 1. The modified data word F1(Data S-1) is computed as a function of the data word (DAT) a S-1 stored at the address ADDR S-1 of the volatile memory, where k is equal to 1. The modified data words F1(Data 0) to F1(Data S-1) form a first modified software module.

[0114] The modified data word FN(Data 0) is computed from the data word (DAT) a 0 stored at the address 0x00...0 of the volatile memory, with k equal to N. The modified data word FN(Data S-1) is computed from the data word (DAT) a S-1 stored at the address ADDR S-1 of the volatile memory, with k equal to N. The modified data words FN(Data 0) to FN(Data S-1) form the final modified software module.

[0115] For the computation of the check value, when all the modified data words Fk(DAT) (i.e. the modified software module) have been delivered to the cyclic redundancy check circuit (CRCM), the finite state machine circuit (FSM) selects the input of the multiplexer (MUX) receiving the last computed check value CRC(k-1) or the initial check value CRC(0). For example, the finite state machine circuit (FSM) selects the input n°3 of the multiplexer with the value "Sel 3" of the signal (SEL).

[0116] The clock signal (CLK CRC) is pulsed by the finite state machine circuit (FSM). This allows the delivery of the last computed check value CRC(k-1) or the initial check value CRC(0) to the cyclic redundancy check circuit (CRCM) for the computation of a new check value.

[0117] The finite state machine circuit (FSM) selects the input of the multiplexer (MUX) receiving the software length (S) via the signal (SW L). For example, the finite state machine circuit (FSM) selects the input n°2 of the multiplexer with the value "Sel 2" of the signal (SEL).

[0118] The clock signal (CLK CRC) is pulsed by the finite state machine circuit (FSM), which allows the delivery of the software length (S) to the cyclic redundancy check circuit (CRCM) for the computation of a new check value.

[0119] The new check value is computed by the cyclic redundancy check circuit (CRCM) using all the computed modified data words Fk(DAT), the last computed check value CRC(k-1) or the initial check value CRC(0), and the software length (S).

[0120] For example, the first check value CRC(1) is computed from the modified data words F1(Data 0) to F1(Data S-1) of the first modified software module and also from the initial check value CRC(0) and the length (S) of the external software module.

[0121] The finite state machine circuit (FSM) pulses the signal (LTCH_R) to store the new check value in the latch (LTCH). The check value is computed until the final check value CRC(N) is obtained.

[0122] For example, the final check value CRC(N) is computed from the modified data words FN(Data 0) to FN(Data S-1) of the final modified software module and can also be computed from the previous check value CRC(N-1) and the length (S) of the external software module.

[0123] When the final check value has been computed, the finite state machine circuit (FSM) pulses the signal (LTCH_R) to store the final check value in the latch (LTCH). The finite state machine circuit (FSM) pulses the signal (RDY) to deliver the final check value CRC(N) to the processor. The processor uses the final check value to validate the external software module (ESW).

[0124] In an embodiment, the processor compares the final check value with a predefined expected value. If the final check value is equal to the expected value, the processor validates the external software module (ESW) and the system-on-chip can use the external software module (ESW). Otherwise, if the final check value is not equal to the expected value, the processor will reject the external software module (ESW) and the system-on-chip cannot use the external software module (ESW).

[0125] Figure 4 An embodiment of a part of a system-on-chip configured to generate a final check value is shown. Compared to the system-on-chip from Figure 1 The system-on-chip from Figure 4 provides another way of generating a modified software module by a non-linear function circuit (NLFM).

[0126] In an embodiment, the non-linear function circuit (NLFM) is configured to apply the exact same non-linear function to each data word (DAT) received at the input of the non-linear function circuit (NLFM). Thus, the non-linear function does not depend on the number k.

[0127] However, the system-on-chip is configured such that each modified software module is generated by the non-linear function circuit (NLFM) directly from the modified software module, the first modified software module being generated from the external software module.

[0128] In an embodiment, the volatile memory storage (MEM) is configured to store each modified software module. For example, the modified software modules can be stored in the memory banks TMP1 to TMPm.

[0129] Further, the non-linear function circuit (NLFM) is configured to receive data words (DAT) of the external software module (ESW) or of the modified software module stored in the volatile memory storage (MEM). The non-linear function circuit (NLFM) is configured to compute a modified data word F(DAT) from each data word (DAT) received at its input.

[0130] In an embodiment, the finite state machine circuit (FSM) is configured to select a data word (DAT) of the external software module (ESW) or of the modified software module to deliver to the non-linear function circuit (NLFM).

[0131] The modified data word F(DAT) obtained from a data word (DAT) of the external software module (ESW) or of a given modified software module forms a new modified software module.

[0132] The non-linear function circuit (NLFM) is configured to deliver each modified data word F(DAT) of the new modified software module to the volatile memory storage (MEM). The non-linear function circuit (NLFM) is further configured to assert a signal WR to indicate a write of the newly computed modified data word F(DAT). The non-linear function can include a shift of bits of the data word (DAT) of the external software module (ESW) or of the modified software module received at the input of the non-linear function circuit (NLFM).

[0133] For example, the non-linear function can be expressed as F(DAT) = DAT « 1 and F(DAT) LSB = not(DAT MSB ), where F(DAT) is the modified data word computed from the data word (DAT), F(DAT) LSB is the least significant bit of the modified data word F(DAT), DAT MSB is the most significant bit of the data word (DAT).

[0134] In an embodiment, the non-linear function includes performing an "exclusive OR" function between different data words.

[0135] For example, in this case, the non-linear function can be expressed as: when ADDR > 1 and ADDR < ADDR_MAX - 1, F[DAT(ADDR)] = DAT(ADDR - 1) xor DAT(ADDR) xor DAT(ADDR + 1); when ADDR = 0 or ADDR = ADDR_MAX, F[DAT(ADDR)] = DAT(ADDR) xor M, where F[DAT(ADDR)] is the modified data word calculated for the data word (DAT)(ADDR) stored at address ADDR, DAT(ADDR - 1) is the previous data word in the memory, DAT(ADDR + 1) is the next data word in the memory, ADDR_MAX is the maximum data word address of the software module for calculating the new modified software module, the address ADDR is between 0 and the address ADDR_MAX, ADDR_MAX is equal to the length of the external software module, and M is a constant, such as 0xA5.

[0136] Otherwise, calculate each check value in the same manner as in Figure 1 the embodiment.

[0137] In an embodiment, when the modified software module stored in the memory is no longer needed for calculating a new modified software module, each modified software module stored in the memory can be overwritten by the newly calculated modified software module. This allows minimizing the amount of memory required to store the software modules.

[0138] In an embodiment, some systems-on-chip can store different predefined expected values to verify different external software modules that can provide different additional services to the system-on-chip. Therefore, for each external software module that can be used by the system-on-chip, the predefined expected value is stored in the system-on-chip.

[0139] For example, a first expected value can be defined to verify an external software module that can be used to perform the HMAC-SHA256 function. A second expected value can be defined to verify an external software module that can be used to perform the AES function. A third expected value can be defined to verify an external software module that can be used to authorize an additional external software module selected by the user of the system-on-chip.

[0140] The present disclosure is susceptible to various changes and modifications that are obvious to those skilled in the art. For example, each check value can be calculated in a different manner from that described above.

[0141] In an embodiment, each check value can be calculated based on the modified software module calculated by the non-linear function circuit and can be calculated based on the result of an auxiliary function module that takes the last calculated check value and the length of the external software module as inputs.

[0142] Alternatively, each check value can be computed from the modified software module computed by the non-linear function circuit and can be computed from the result of an auxiliary function module that takes as input several already computed check values and the length of the external software module.

[0143] While the description has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. Wherever different embodiments are described, the same elements have been designated with the same reference numerals. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, as a person of ordinary skill in the art will readily appreciate from the disclosure hereof that processes, machines, manufacture, compositions of matter, means, methods or steps, currently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized. Accordingly, the appended claims are intended to include within their scope all processes, machines, manufacture, compositions of matter, means, methods or steps substantially as such.

[0144] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and it is intended to cover any and all modifications, variations, combinations or equivalents that fall within the scope of the present disclosure.

Claims

1. A method comprising: obtaining an external software module for use by a system on a chip; computing a number of modified software modules from a whole of the external software module; computing an iterative check value from an initial pre-defined check value to a final check value, each iterative check value after the initial pre-defined check value being computed from one or more modified software modules and a previously computed check value; comparing the final check value to an expected value stored in the system on a chip; and verifying the external software module for use by the system on a chip in response to the final check value being equal to the expected value. Each iterative check value is computed using a cyclic redundancy check algorithm.

2. The method of claim 1, wherein computing the iteration check value comprises: Each iterative check value is computed using a hash algorithm.

3. The method of claim 1, wherein computing the iteration check value comprises: Each iterative check value is computed using a length of the external software module.

4. The method of claim 1, wherein computing the iteration check value comprises: The number of modified software modules are computed using a non-linear function.

5. The method of claim 1, wherein computing a number of modified software modules comprises:

6. The method of claim 5, wherein the non-linear function comprises a shift of bits of a corresponding modified software module.

7. The method of claim 1, wherein the expected value stored in the system on a chip comprises the expected value stored in configuration bits of the system on a chip or the expected value stored in the system on a chip is encoded at a register transfer level.

8. A system on a chip comprising: a memory storage configured to store an external software module; a computing circuit configured to: compute a number of modified software modules from a whole of the external software module; compute an iterative check value from an initial pre-defined check value to a final check value, each iterative check value after the initial pre-defined check value being computed from one or more modified software modules and a previously computed check value; a comparing circuit configured to compare the final check value to an expected value stored in the system on a chip; and a verifying circuit configured to verify the external software module for use by the system on a chip in response to the final check value being equal to the expected value.

9. The system on a chip of claim 8, wherein the computing circuit comprises a cyclic redundancy check circuit configured to compute the iterative check values.

10. The system on a chip of claim 8, wherein the computing circuit comprises a hash circuit configured to compute the iterative check values.

11. The system on a chip of claim 8, wherein the computing circuit is configured to compute each iterative check value using a length of the external software module.

12. The system on a chip of claim 8, wherein the computing circuit comprises a non-linear function circuit configured to compute the number of modified software modules using a non-linear function.

13. The system on a chip of claim 12, wherein the non-linear function comprises a shift of bits of a corresponding modified software module.

14. The system on a chip of claim 8, wherein the expected value is stored in configuration bits of the system on a chip or is encoded at a register transfer level. ​ ​ 15. The system on chip of claim 8, wherein the memory storage device is configured to store a further external software module.

16. A device comprising a system on chip, the system on chip comprising: a memory storage device configured to store an external software module; a computing circuit configured to: compute a number of modified software modules from a whole of the external software module; compute an iterative check value iteratively from an initial predefined check value, each iterative check value after the initial predefined check value being computed from one or more modified software modules and a previously computed check value; a comparison circuit configured to compare the final check value to an expected value stored in the system on chip; and a verification circuit configured to verify the external software module for use by the system on chip in response to the final check value being equal to the expected value.

17. The device of claim 16, wherein the computing circuit comprises a cyclic redundancy check circuit configured to compute the iterative check value.

18. The device of claim 16, wherein the computing circuit comprises a hash circuit configured to compute the iterative check value.

19. The device of claim 16, wherein the computing circuit is configured to use a length of the external software module to compute each iterative check value.

20. The device of claim 16, wherein the computing circuit comprises a non-linear function circuit configured to use a non-linear function to compute the number of modified software modules. ​

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