Power ramping sequence control for memory devices

Abstract

This application relates to power ramp sequence control for memory devices. Memory devices are disclosed that support multiple power ramp sequences or modes. For example, a level shifter device is operatively connected to a memory macro in a memory device. The level shifter device receives at least one select signal. Based on a state of the at least one select signal, the level shifter device outputs one or more signals that cause or control a ramp up, a ramp down, or both a ramp up and a ramp down of a voltage signal in or received by the memory macro according to one or more power ramp modes.

Description

TECHNICAL FIELD

[0001] The present application relates generally to the field of memory devices, and more specifically to power ramping sequence control for memory devices. BACKGROUND

[0002] Memory devices are composed of large arrays of individual memory cells. One example of a memory device is a static random access memory (SRAM). Each memory cell in a memory device can store a "1" or "0" bit of data as an electrical high or low voltage state. Conventionally, eight (8) bits make up a byte of data. In each memory operation cycle, typically at least one byte is written to or read from the array. Memory cells are arranged at the intersection of vertical data lines (or bit lines) and horizontal word lines (or address lines). A word line enables a read or write operation. When one word line and one bit line or pair of bit lines are activated, a read or write cycle occurs.

[0003] Some power management schemes for memory devices only support first ramping up one power supply. For example, a power management scheme can only support a power ramping sequence that first ramps up a VDD voltage signal or a VDDM voltage signal. In some memory devices, a power management circuit or controller only supports one power ramping sequence or conforms to a specification for only one power ramping sequence. SUMMARY

[0004] According to an aspect of the present application, there is provided a device comprising: a memory macro configured to receive a first voltage signal and a second voltage signal, the memory macro comprising power management circuitry; and a level shifter device configured to provide a third signal to the power management circuitry to control the first voltage signal and the second voltage signal in the memory macro based on a fourth signal, wherein: when the fourth signal has a first logic state, the first voltage signal is ramped up before the second voltage signal is ramped up; and when the fourth signal has a second logic state, the second voltage signal is ramped up before the first voltage signal is ramped up.

[0005] According to an aspect of the present application, there is provided a method comprising: receiving a strobe signal at a level shifter device, the level shifter device operably connected to a memory macro; based on a signal level of the strobe signal having a first logic state: causing a first power ramping mode of a plurality of power ramping modes to be generated in the memory macro; and causing a second power ramping mode of the plurality of power ramping modes to be generated in the memory macro after the first power ramping mode.

[0006] According to one aspect of this application, an electronic device is provided, comprising: a power supply; a memory macro operatively connected to the power supply and configured to receive a first voltage signal and a second voltage signal, the memory macro including a power management circuitry system operable to ramp up and ramp down the first and second voltage signals according to at least one power ramping mode included in a plurality of power ramping modes; and a level shifter device operatively connected to the power management circuitry system in the memory macro and connected to the power supply, and configured to provide one or more signals to the power management circuitry system supporting the plurality of power ramping modes. Attached Figure Description

[0007] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A block diagram of an exemplary memory device according to some embodiments is shown, which may practice various aspects of the present disclosure;

[0009] Figure 2 A block diagram of an exemplary slant variable control system according to some embodiments is shown;

[0010] Figure 3 A block diagram illustrating a first example of a level shifter device operatively connected to a memory macro according to some embodiments is shown;

[0011] Figure 4 Illustrations are shown according to some embodiments Figure 3 A schematic diagram of a first example of a level shifter circuit shown;

[0012] Figure 5 Illustrations are shown according to some embodiments Figure 3 A schematic diagram of a second example of the level shifter circuit shown;

[0013] Figure 6 A block diagram illustrating a second example of a level shifter device operatively connected to a memory macro according to some embodiments is shown;

[0014] Figure 7 It is shown that some embodiments are suitable for use in Figure 6 A schematic diagram of an exemplary level shifter circuit used in the level shifter device shown;

[0015] Figure 8 A block diagram of a memory macro according to some embodiments is shown;

[0016] Figure 9 A block diagram of a system for power ramping mode control is shown in accordance with some embodiments;

[0017] Figure 10 A schematic diagram of a first example of a power management circuit suitable for use in power management circuitry is shown in accordance with some embodiments;

[0018] Figure 11 A schematic diagram of a second example of a power management circuit suitable for use in power management circuitry is shown in accordance with some embodiments;

[0019] Figure 12 A schematic diagram of a third example of a power management circuit suitable for use in power management circuitry is shown in accordance with some embodiments;

[0020] Figure 13 A schematic diagram of a fourth example of a power management circuit suitable for use in power management circuitry is shown in accordance with some embodiments;

[0021] Figure 14 An example level shifter device suitable for use with the power management circuits shown in Figures 10-13

[0022] Figure 15 An example timing diagram of a first power ramping mode is shown in accordance with some embodiments;

[0023] Figure 16 An example timing diagram of a second power ramping mode is shown in accordance with some embodiments;

[0024] Figure 17 An example flowchart of a method of operating a power ramping control system is shown in accordance with some embodiments; and

[0025] Figure 18 An example system that can include one or more memory devices is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0026] ​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature is described above or formed on a second feature. This can include embodiments where the first feature and the second feature are formed in direct contact with each other, as well as embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat certain

[0027] In addition, spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like) can be used herein for ease of describing one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms are not to be construed as limiting. Understanding that the devices can be oriented in other directions, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures.

[0028] Embodiments disclosed herein provide a memory device that supports multiple power ramping sequences. In a non-limiting embodiment, a circuit is operably connected to a memory macro in the memory device. One non-exclusive example of the circuit is a level shifter. Based on a state of at least one received strobe signal, the circuit outputs one or more signals that cause a voltage signal in or received by the memory macro to ramp up, ramp down, or both ramp up and ramp down according to one or more power ramping sequences. The power ramping sequences are also referred to herein as power ramping patterns.

[0029] In one embodiment, the memory device supports two power ramping sequences simultaneously. Additionally or alternatively, the memory device supports a bulk-off mode in which one or more power supplies (e.g., VDD) are turned off when the memory macro is in a sleep mode. The bulk-off mode saves additional power compared to the sleep mode and the shutdown mode. When in the bulk-off mode, data can be retained in the memory array (e.g., one or more memory cells) by turning on (e.g., setting to a high signal level) a second voltage signal (e.g., VDDM) when a first voltage signal (e.g., VDD) is turned off.

[0030] Reference is made below to Figures 1-18 These and other embodiments are discussed. However, a person of ordinary skill in the art will readily recognize from the detailed description given herein, and from the associated drawings, other ways and / or methods to produce the application.

[0031] Figure 1 A block diagram of an example memory device in which various aspects of the present disclosure can be practiced in accordance with some embodiments is shown. The memory device 100 includes memory cells 102 arranged in rows and columns to form a memory array 104. The memory device 100 can include any suitable number of rows and columns. For example, the memory device includes R rows and C columns, where R is an integer greater than or equal to 1 and C is an integer greater than or equal to 1. Other embodiments are not limited to rows and columns of memory cells 102. The memory cells 102 in the memory array 104 can be organized in any suitable arrangement.

[0032] Each row of memory cells 102 is operatively connected to one or more word lines (collectively, word lines 106). The word lines 106 are operatively connected to one or more row selection circuits (collectively, row selection circuits 108). The row selection circuits 108 select a particular word line 106 based on an address signal received on a signal line 110.

[0033] Each column of memory cells 102 is operatively connected to one or more bit lines (collectively, bit lines 112). The bit lines 112 are operatively connected to one or more column selection circuits (collectively, column selection circuits 114). The column selection circuits 114 select a particular bit line 112 based on a selection signal received on a signal line 116.

[0034] The peripheral circuitry 118 is operatively connected to the memory array 104 via one or more signal lines (collectively, signal lines 120). The peripheral circuitry 118 can include components (e.g., semiconductor devices) for driving the devices of the memory array 104 and / or various devices operable to access and / or control the memory array 104. In a non-limiting example, the peripheral circuitry 118 includes devices for performing read / write / erase operations in the memory cells 102 in the memory array 104. These devices include n-type transistors (e.g., n-FETs) and p-type transistors (e.g., p-FETs). The transistors can be configured as planar transistors or multi-gate transistors, such as fin-type multi-gate transistors (FinFET transistors), although embodiments are not limited to this implementation.

[0035] In one embodiment, the peripheral circuitry 118 includes header circuits 122 that are used to gate the supply of power signals (e.g., VDD and VDDM) to the memory array 104. When data is to be written to (e.g., the memory cells 102 are programmed) or read from the memory cells 102, the address of the memory cell is received on the signal lines 110. A select signal is received on the signal lines 116, and the bit line 112 associated with the memory cell to be accessed (read or written) is pre-charged by the peripheral circuitry 118 (e.g., by activating or deactivating the corresponding header circuit 122). When the bit line 112 is pre-charged, the row select circuit 108 activates or asserts the word line 106 associated with the address. Data is then written to or read from the memory cells 102.

[0036] The power management circuitry 124 includes power management circuits that are operably connected to various components in the memory device 100. In one embodiment, the power management circuitry 124 is operably connected to the header circuits 122 and the processing device 126. A level shifter (LS) device 128 is implemented in the processing device 126. As will be described in greater detail later, the level shifter device 128 receives a signal from a logic circuit 130 and responsively generates a signal that is received by the power management circuitry 124. The power management circuitry 124 ramps up, ramps down, or both ramps up and down a voltage signal in or received by the memory macro 132 according to one or more power ramp sequences.

[0037] The processing device 126 is operably connected to the memory macro 132. In an example embodiment, the memory macro 132 is a memory unit structure that includes various components of the memory device 100. In the illustrated embodiment, the memory macro 132 includes the memory array 104, the row select circuit 108, the column select circuit 114, the peripheral circuitry 118, and the power management circuitry 124. Within the memory macro 132, the processing device 126 is operably connected to at least one of the memory array 104, the row select circuit 108, the column select circuit 114, the peripheral circuitry 118, and the power management circuitry 124. The processing device 126 is operable to control one or more operations of the memory array 104, the row select circuit 108, the column select circuit 114, the peripheral circuitry 118, and / or the power management circuitry 124. Any suitable processing device can be used. Example processing devices include, but are not limited to, a central processing unit, a microprocessor, an application specific integrated circuit, a graphics processing unit, a field programmable gate array, or a combination thereof.

[0038] Power supply 134 is operatively connected to memory macro 132 and processing device 126. In some embodiments, power supply 134 is operatively connected to memory array 104, row selection circuit 108, column selection circuit 114, peripheral circuitry 118, and power management circuitry 124. In the illustrated embodiment, processing device 126 and power supply 134 are located outside of memory macro 132. In another embodiment, processing device 126 and / or power supply 134 can be disposed within memory macro 132. In yet another embodiment, processing device 126 and / or power supply 134 can be disposed in a separate circuitry and are operatively connected to memory device 100.

[0039] Memory device 100 is included in electronic device 136. Electronic device 136 can be any suitable electronic device. Exemplary electronic devices include, but are not limited to, computing devices such as laptop computers and tablet computers, cellular telephones, televisions, automobiles, stereo systems, and cameras.

[0040] Figure 2 A block diagram of an exemplary ramp control system is shown in accordance with some embodiments. Ramp control system 200 includes memory macro 132, level shifter device 202 operatively connected to memory macro 132, and logic circuit 204 operatively connected to level shifter device 202 and memory macro 132. Level shifter device 202 is Figure 1 Level shifter device 128 shown in FIG. 1. Logic circuit 204 is any suitable logic circuit(s). For example, in some embodiments, logic circuit 204 is an inverter or a buffer.

[0041] In one embodiment, level shifter device 202 operates at an interface between circuitry of a first voltage VI (referred to herein as a VI domain) and circuitry of a second voltage V2 (referred to herein as a V2 domain). For example, VI domain can be a VDD domain and V2 domain can be a VDDM domain. One or more level shifter circuits in level shifter device 202 are configured to receive one or more input signals (e.g., SD1 signal on signal line 210) and one or more strobe signals (e.g., ISOSRM signal on signal line 206a) in the VI domain and output one or more signals (e.g., SD2 signal) in the V2 domain. The signal(s) in the V2 domain are used to control ramping up and ramping down of VI signals and V2 signals in memory macro 132. In conjunction with Figure 4 、 Figure 5 and Figure 7 An exemplary level shifter circuit is described in more detail.

[0042] In one embodiment, the level shifter device 202 is operable to receive a select signal ISOSRM on signal line 206a. In another embodiment, the level shifter device 202 is operable to receive a select signal ISOSRM on signal line 206a and a select signal ISORET on signal line 206b. The ISOSRM signal and the ISORET signal can be generated by a processing device (e.g., the processing device 126 shown in FIG. 1) using a logic circuit 130. Figure 1

[0043] Based on the state or signal level of the select signal ISOSRM and the select signal ISORET, a level shifter circuit in the level shifter device 202 outputs a signal SD2 on signal line 208a. Non-limiting and non-exclusive exemplary level shifter circuits are shown in FIGS. 2A and 2B. Figure 4 Figure 5 Table 1 is a truth table for the level shifter circuit of FIG. 2A, showing the signal level of the SD2 signal based on various signal levels of the ISOSRM signal, the ISORET signal, and the SD1 signal. Figure 4 Figure 5

[0044] In embodiments where the level shifter device 202 receives the select signal ISOSRM, the level shifter device outputs a signal DSLP2 on signal line 208b. Non-limiting and non-exclusive exemplary level shifter circuits are shown in FIGS. 3A and 3B. Figure 7 Table 4 is a truth table for the level shifter circuit of FIG. 3A, showing the signal level of the DSLP2 signal based on various signal levels of the ISOSRM signal and the SD1 signal. Figure 7

[0045] The SD2 signal and the DSLP2 signal are in the V2 domain and produce different power saving modes in the memory macro 132. In one embodiment, the SD2 signal is associated with a shutdown mode that turns off power (e.g., voltage) to components in the peripheral circuitry and the memory array while leaving one or more power supplies (e.g., VDD, VDDM) on. The DSLP2 signal is associated with a sleep mode that turns off power to some components in the peripheral circuitry while leaving one or more power supplies (e.g., VDD, VDDM) on. A third power saving mode is a bulk shutdown mode that is configured to turn off one or more power supplies (e.g., VDD) when the memory macro 132 is in the sleep mode. The bulk shutdown mode saves additional power. The signals SD2 and DSLP2 also ramp up, ramp down, or both ramp up and ramp down the V1 voltage signal and the V2 voltage signal in the memory macro 132 or received by the memory macro 132 according to one or more power ramping sequences. The power ramping sequences are also referred to herein as power ramping modes. ​​​​​

[0046] The logic circuit 204 outputs one or more signals on the signal line 210, which are received by the level shifter device 202. Exemplary signals that can be received by the level shifter device 202 include, but are not limited to, a shutdown signal SD1 and a sleep signal DSLP1. The SD1 and DSLP1 signals are generated in the VI domain.

[0047] The logic circuit 204 also outputs one or more signals on the signal line (CNTL) 212, which are received by the memory macro 132. Exemplary signals that can be received by the memory macro 132 include, but are not limited to, control signals such as a clock signal, a chip enable signal, a write enable signal, and address signals.

[0048] An output signal Q and an output signal PUDELAY are output from the memory macro 132. The signal level or state of the output signal Q represents a data value in one or more memory cells. The output signal PUDELAY represents a start-up or power-up delay signal that propagates to other memory macros in the memory device. The output signal PUDELAY is used for sequential wake-up control of multiple macros to reduce simultaneous peak current at the chip level.

[0049] In a non-limiting example, the VI signal is a VDD voltage signal and the V2 signal is a VDDM voltage signal. In this exemplary embodiment, the level shifter device 202 outputs one or more signals on the signal line 208 that ramp up, ramp down, or both ramp up and ramp down the VI voltage signal and the V2 voltage signal in the memory macro 132 or received by the memory macro 132 according to one or more power ramping modes. For example, as shown in Table 2, when the signal level or state of the ISOSRM signal is in a first signal level or first logic state, a first power ramping mode ramps up the VDD voltage signal before ramping up the VDDM voltage signal and ramps down the VDD voltage signal after ramping down the VDDM voltage signal. When the signal level of the ISOSRM signal is in a second signal level or second logic state, a second power ramping mode ramps up the VDDM voltage signal before ramping up the VDD voltage signal and ramps down the VDDM voltage signal after ramping down the VDD voltage signal. In another embodiment, the first power ramping mode ramps up the VDD voltage signal before ramping up the VDDM voltage signal and the second power ramping mode ramps up the VDDM voltage signal before ramping up the VDD voltage signal.

[0050] Figure 3A block diagram showing a first example of a level shifter device operably connected to a memory macro according to some embodiments is shown. The level shifter device 202 includes a level shifter circuit 300. The level shifter circuit 300 receives a shutdown (SD1) signal in the V1 domain and outputs a shutdown signal (SD2) in the V2 domain. The level shifter circuit 300 receives the SD1 signal on a signal line 302, a strobe signal (ISOSRM signal) on a signal line 304, a strobe signal (ISORET signal) on a signal line 306. The level shifter circuit 300 outputs the SD2 signal on a signal line 308. The SD2 signal is received by the power management circuitry 124 in the memory macro 132 (e.g., Figure 1 and used to ramp up and ramp down the V1 and V2 signals in the memory macro 132 according to one or more power ramping modes.

[0051] As previously mentioned, in non-limiting embodiments, the ramping control system supports two power ramping modes. One power ramping mode is referred to herein as the DL mode and the other power ramping mode is referred to as the DM mode. Both the DL mode and the DM mode first ramp up a respective first voltage signal, second ramp up a respective second voltage signal (after the first voltage signal), and first ramp down the respective second voltage signal, second ramp down the respective first voltage signal (after the second voltage signal). For example, in the DL mode, the V1 signal (e.g., VDD voltage signal) is ramped up earlier and ramped down later than the V2 signal (e.g., VDDM voltage signal). In the DM mode, the V2 signal (e.g., VDDM voltage signal) is ramped up earlier and ramped down later than the V1 signal (e.g., VDD voltage signal). In one embodiment, the ISOSRM signal is configured to switch the power ramping mode between the DL mode and the DM mode, and the ISORET signal is configured to produce an optional bulk shutdown mode in the memory macro 132. As previously mentioned, the bulk shutdown mode is an additional power saving mode configured to shut off power (e.g., V1) when the memory macro is in a sleep mode.

[0052] Figure 4 A block diagram showing a second example of a level shifter device operably connected to a memory macro according to some embodiments is shown. Figure 3A schematic diagram of a first example of a level shifter circuit is shown in FIG. 3. The level shifter circuit 300a shown is operable to receive an SD1 signal at a VI domain and output an SD2 signal at a V2 domain. In the embodiment shown, the SD1 signal on signal line 302 and the ISOSRM signal on signal line 304 are input into a NOR (or NOT) gate 400. The SD1 signal is also input into an inverter 402. The ISORET signal on signal line 306 is input into an inverter 404. As previously discussed, the ISOSRM signal is operable to switch the power ramping mode in the memory macro between a DL mode and a DM mode, and the ISORET signal is configured to produce a bulk-off mode in the memory macro 132.

[0053] The output of the NOR gate 400 is input into an inverter 406. The output of the inverter 402 is connected to a terminal 408 of a transistor 410. One example of the transistor 410 is an n-type transistor (e.g., an NMOS transistor), although other embodiments are not limited to this type of transistor. Another terminal 412 of the transistor 410 is connected to a reference voltage 414. One example of the reference voltage 414 is a ground voltage. The ISOSRM signal is an input signal to a gate 416 of the transistor 410.

[0054] The output of the inverter 402 is also connected to a gate 418 of a transistor 420. One example of the transistor 420 is a p-type transistor (e.g., a PMOS transistor), although other embodiments are not limited to this type of transistor. A terminal 422 of the transistor 420 is connected to a V2 voltage source. In representative embodiments, the V2 voltage source is a VDDM voltage source. Another terminal 424 of the transistor 420 is connected to the reference voltage 414.

[0055] The output of the inverter 406 is connected to a gate 426 of another transistor 428. In the embodiment shown, the transistor 428 is a p-type transistor. A terminal 430 of the transistor 428 is connected to the V2 voltage source. Another terminal 432 of the transistor 420 is connected to the reference voltage 414.

[0056] The output of the inverter 404 and the output of the inverter 406 are input into a NAND (AND NOT) gate 434. The output of the NAND gate 434 is input into an inverter 436. The SD2 signal is output on signal line 308 from the inverter 436. As discussed in more detail later, Table 1 depicts a truth table for the level shifter circuit 300a, which shows various signal levels for the ISOSRM, ISORET, SD1, and SD2 signals.

[0057] Figure 5 A schematic diagram of a second example of a level shifter circuit is shown in FIG. 4. Figure 3 A schematic diagram of a second example of a level shifter circuit is shown in FIG. 4.Figure 5 The level shifter circuit 300b shown is... Figure 4 The level shifter circuit 300a shown is similar, except that the NAND gate 434 is omitted and an inverter 500, an AND gate 502, and a NOR gate 504 are added. Figure 4 Similar to the level shifter circuit 300a shown, the level shifter circuit 300b shown is operable to output an SD2 signal in the V2 domain. The ISOSRM signal is operable to switch the power ramp mode in the memory macro between DL and DM modes, and the ISORET signal is configured to generate a bulk shutdown mode in the memory macro 132.

[0058] The SD1 signal on signal line 302 is input to inverter 500, and the output of inverter 500 is input to inverter 402 and NOR gate 400. The output of inverter 404 and the ISOSRM signal are input to AND gate 502. In the illustrated embodiment, the output of AND gate 502 and the output of inverter 402 are input to NOR gate 504. Figure 4 Unlike the embodiment shown, the output of inverter 406 is connected only to the gate 426 of transistor 428. The output of inverter 406 is not input to NAND gate 434 because... Figure 5 NAND gate 434 is omitted in the embodiment shown.

[0059] As previously described, the depicted level shifter circuits 300a and 300b are operable to receive an SD1 signal in the V1 domain and output an SD2 signal in the V2 domain. In one embodiment, Figure 4 and 5 The level shifter circuits 300a and 300b shown herein operate using the truth table shown in Table 1.

[0060] Table 1

[0061] ISOSRM ISORET SD1 SD2 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0

[0062] Figure 6 A block diagram illustrating a second example of a level shifter device operatively connected to a memory macro according to some embodiments is shown. The level shifter device 202 includes a level shifter circuit 600 and... Figure 3 The level shifter circuit 300 is shown in the figure. For the sake of brevity, the description of the level shifter circuit 300 will not be repeated here.

[0063] The level shifter circuit 300 is operable to receive the SD1 signal generated in the V1 domain and output the SD2 signal in the V2 domain. The level shifter circuit 600 is operable to receive the DSLP1 signal generated in the V1 domain and output the DSLP2 signal in the V2 domain. The level shifter circuit 600 receives a sleep signal (the DSLP1 signal) on the signal line 602 and a strobe signal ISOSRM on the signal line 604. The signal line 604 can be the same signal line as the signal line 304, or the signal line 604 can be a different signal line than the signal line 304. The level shifter circuit 600 outputs the SD2 signal on the signal line 308 and the DSLP2 signal on the signal line 606. The SD2 and DSLP2 signals are received by the memory macro 132 (e.g., the power management circuitry 124 in Figure 1 ramps up and down the V1 and V2 signals in the memory macro 132 according to one or more power ramping modes.

[0064] In non-limiting embodiments, the level shifter circuits 300, 600 provide control over multiple power ramping modes. In a DL mode, the V1 signal (e.g., the VDD voltage signal) ramps up earlier and ramps down later than the V2 signal (e.g., the VDDM voltage signal). In a DM mode, the V2 signal (e.g., the VDDM voltage signal) ramps up earlier and ramps down later than the V1 signal (e.g., the VDD voltage signal). As previously described, in one embodiment, the ISOSRM signal is configured to switch the power ramping mode between the DL mode and the DM mode, and the ISORET signal is configured to generate an optional bulk-off mode in the memory macro 132.

[0065] In the illustrated embodiment, the level shifter circuit 600 receives one strobe signal, the ISOSRM signal. Table 2 is an exemplary mode support table for the level shifter circuit 600.

[0066] Table 2

[0067] ISOSRM Mode support 0 V1 ramp up / down 1 V2 ramp up / down

[0068] When the ISOSRM signal is at a low signal level, the V1 signal ramps up before the V2 signal and ramps down after the V2 signal ramps down (e.g., a DL mode). When the ISOSRM signal is at a high signal level, the V2 signal ramps up before the V1 signal and ramps down after the V1 signal ramps down (e.g., a DM mode).

[0069] In other embodiments, the level shifter circuits (e.g., Figure 4 and Figure 5The level shifter circuits 300a and 300b in the diagram receive two strobe signals, namely the ISOSRM and ISORET signals, and the SD1 and DSLP1 signals. Table 3 is an exemplary mode support table for the level shifter circuits.

[0070] Table 3

[0071]

[0072] The phrase "data crash" in Table 3 refers to the unpredictability of data stored in memory cells within the memory array. The phrase "data retention" means that data stored in memory cells within the memory array is retained. When the ISOSRM signal is at a low signal level, the SD2 signal follows the input SD1 signal, and the DSLP2 signal follows the input DSLP1 signal. Furthermore, the V1 signal rises before the V2 signal rises, and the V1 signal falls after the V2 signal falls. The V2 signal is in bulk shutdown mode.

[0073] When the ISOSRM signal is high and the ISORET signal is low, both the SD2 and DSLP2 signals are high. The V2 signal rises before the V1 signal rises and falls after the V1 signal falls. The V1 signal is in bulk shutdown mode, where data in one or more memory cells is corrupted.

[0074] When the ISOSRM signal and the ISORET signal are both high, the SD2 signal is low and the DSLP2 signal is high. The V2 signal rises before the V1 signal rises and falls after the V1 signal falls. The V1 signal is in bulk shutdown mode, where data in one or more memory cells is retained.

[0075] Figure 7 It is shown that some embodiments are suitable for use in Figure 6 This is a schematic diagram of an exemplary level shifter circuit used in the level shifter device shown. Level shifter circuit 600 receives a DSLP1 signal in the V1 domain and outputs a DSLP2 signal in the V2 domain. In the illustrated embodiment, the DSLP1 signal on signal line 602 and the ISOSRM signal on signal line 604 are input to NOR gate 700. The ISOSRM signal is operable to switch the power ramp mode in the memory macro between DL and DM modes.

[0076] The output of NOR gate 700 is input into inverter 702, and the output of inverter 702 is connected to gate 704 of transistor 706. One example of transistor 706 is a p-type transistor (e.g., a PMOS transistor), although other embodiments are not limited to this type of transistor. Terminal 708 of transistor 706 is connected to a V2 voltage source. In representative embodiments, the V2 voltage source is a VDDM voltage source. Another terminal 710 of transistor 706 is connected to a reference voltage 712. One example of reference voltage 712 is a ground voltage.

[0077] The DS LP1 signal on signal line 602 is also input into inverter 714. The output of inverter 714 is connected to gate 716 of another transistor 718. One example of transistor 718 is a p-type transistor, such as a PMOS transistor. Other embodiments are not limited to this type of transistor. Terminal 720 of transistor 718 is connected to the V2 voltage source. Another terminal 722 of transistor 718 is connected to reference voltage 712.

[0078] The output of inverter 714 is also connected to terminal 724 of transistor 726. One example of transistor 726 is an n-type transistor, such as an NMOS transistor. Other embodiments are not limited to this type of transistor. Another terminal 728 of transistor 726 is connected to reference voltage 712. The ISOSRM signal is an input signal to gate 730 of transistor 726.

[0079] As previously described, level shifter circuit 600 is operable to receive a DS LP1 signal in the VI domain and output a DS LP2 signal in the V2 domain. In one embodiment, Figure 7 Level shifter circuit 600 shown in FIG. 8 operates using the truth table shown in Table 4.

[0080] Table 4

[0081] ISOSRM DSLP1 DSLP2 0 0 0 0 1 1 1 0 1 1 1 1

[0082] Figure 8 A block diagram of an exemplary memory macro is shown in accordance with some embodiments. In one embodiment, memory macro 800 is a memory macro 132 shown in FIG. 8. Figure 1 In some embodiments, multiple level shifter circuits can be used to generate signals that control the power ramping mode of different regions or blocks of memory macro 800. Figure 14 A block diagram of a level shifter apparatus including four level shifter circuits is shown. As will be described in greater detail later, the outputs of the four level shifter circuits are input into Figures 10-13 corresponding power management circuits shown in FIG. 8 to control the power ramping mode of different blocks of memory macro 800.

[0083] An exemplary memory macro 800 includes memory array blocks 802 located at edges 804, 806 of the memory macro 800, memory array blocks 808 disposed at edges 806, 810 of the memory macro 800, and word line driver (WLDV) blocks 812 located between the memory array blocks 802, 808. In one embodiment, the memory array blocks 802, 808 are implemented as memory arrays 104 similar to those in Figure 1

[0084] A WLDV edge block 814 is disposed between edge 806 and WLDV block 812. A control (CNT) block 816 is located between edge 818 of the memory macro 800 and WLDV block 812. An input / output (IO) edge block 820 is disposed along edge 804 between memory array block 802 and edge 818. An IO block 822 is located along edge 818 between IO edge block 820 and CNT block 816. Another IO edge block 824 is disposed along edge 810 between memory array block 808 and edge 818. Another IO block 826 is located along edge 818 between IO edge block 824 and CNT block 816. In other embodiments, the arrangement of blocks can differ from that shown in Figure 8

[0085] Figure 9 A block diagram of an exemplary system for power ramping mode control is shown in accordance with some embodiments. The system 900 includes a VI domain 902, a level shifter device 202, power management circuitry 124, and pin circuitry 122. The VI domain 902 includes circuitry (e.g., logic circuit 904) that is powered using a VI voltage and operates. In one embodiment, the logic circuit 904 is the logic circuit 130 in Figure 1 Figure 1 The logic circuit 904 provides data to a processing device (e.g., processing device 126 in Figures 3-7 ) to cause one or more signals to be output by the VI domain 902, which are received by the level shifter device 202. Exemplary signals include, but are not limited to, a shutdown mode signal SD1, a plurality of sleep mode signals DSLP1, DSLPV1, and DSLPNDIO1, and an internal power down signal PD1 INT (see Figures 14-16

[0086] The level shifter device 202 includes one or more level shifter circuits that output one or more signals at a V2 domain. The V2 domain includes circuitry (not shown) that is powered using a V2 voltage and operates. In one embodiment, the level shifter device 202 is included in a processing device (e.g., processing device 126 in Figure 1 ​​​​processing device 126) shown in FIG. 8. The one or more signals output from the level shifter device 202 include the shutdown mode signal SD2 and the sleep mode signals DS LP2, DS LPV2, and DS LPNDIO2 (see Figures 3-7 and Figures 10-14 In one embodiment, the V1 domain is a VDD domain and the V2 domain is a VDDM domain.

[0087] The one or more signals output from the level shifter device 202 are received by the power management circuitry 124. As previously described, the power management circuitry 124 includes power management circuitry operably connected to individual block power management circuitry in the memory macro. In the illustrated embodiment, the power management circuitry 124 is operably connected between the pin circuitry 122 and the level shifter device 202. The pin circuitry 122 includes pin circuitry operably connected to one or more blocks in the memory macro (e.g., the memory macro 800 shown in FIG. 8). Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 9 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro. Figure 8 The pin circuitry 122 shown in FIG. 8 includes one or more WLDV edge pin circuitry (represented by the WLDV edge pin circuitry 906) operably connected to one or more WLDV edge blocks (e.g., the WLDV edge blocks 814 in FIG. 8) in the memory macro.

[0088] The power management circuits in the power management circuitry 124 output signals that turn on and off the select pin circuit 122. The operation of turning on and off the select pin circuit 122 ramps up and down the V1 and V2 signals in the memory macro according to one or more power ramping modes. In conjunction with Figures 10-13 An exemplary power management circuit is described.

[0089] Figure 10 A schematic diagram of an exemplary first power management circuit suitable for use in power management circuitry according to some embodiments is shown. As shown, the power management circuits 1000, 1002, 1004, 1006, 1008, 1010, 1012, 1014 are operably connected to the pin circuits 916a, 914a, 914b, 914c, 914d, 914e, 914f, 908, respectively. The pin circuits 916a, 914a, 914b, 914c, 914d, 914e, 914f, 908 are operably connected between V1 (e.g., VDDHD, VBL, VDDAI) and V2 (e.g., VDDM). Some or all of the power management circuits 1000, 1002, 1004, 1006, 1008, 1010, 1012, 1014 can be implemented in power management circuitry in a memory macro (e.g., the power management circuitry 124 in Figure 1 and Figure 9 the power management circuitry 124 in the memory macro 800), and some or all of the pin circuits 916a, 914a, 914b, 914c, 914d, 914e, 914f, 908 can be included in a pin circuit (e.g., the pin circuit in the memory macro 800). In one embodiment, the power management circuits 1000, 1002, 1004, 1006, 1008, 1010, 1012, 1014 operate in the V2 domain. Figure 1

[0090] The exemplary power management circuit 1000 is operably connected to the pin circuit 916a. In one embodiment, the pin circuit 916a is operably connected to one or more CNT blocks in a memory macro (e.g., the CNT blocks 816 in the memory macro 800). The power management circuit 1000 includes a NOR gate 1016 that receives an SD2 signal on a signal line 1018 from a level shifter circuit (e.g., the level shifter circuit shown in Figure 8 Figure 4 Figure 7 ​​​The SLP2D signal is received by the NOR gate 1016. The output of the NOR gate 1016 is operably connected to the input of an inverter 1022. The output of the inverter 1022 (the SLP2D signal on signal line 1024a) is operably connected to the input of the pin circuit 916a. In the illustrated embodiment, the pin circuit 916a is a p-type transistor 1025, although other embodiments are not limited to this configuration.

[0091] The pin circuit 916a is turned on to provide power (e.g., the V2 signal) to circuitry in the CNT block(s) of the memory macro (e.g., the CNT block 816 in the memory macro 800) and turned off to provide power (e.g., the VI signal). Based on the state of the SD2 and SLP2 signals received from the level shifter circuits on signal lines 1018, 1020, respectively, the power management circuit 1000 controls the power ramping mode(s) of the circuitry in the CNT block(s). For example, the pin circuit 916a is turned on when the signal levels of the SD2 and SLP2 signals are low (e.g., the signal level of the SLP2D signal is low) and turned off when at least one of the signal levels of the SD2 and SLP2 signals is high. Figure 8

[0092] The exemplary power management circuits 1002, 1004, 1006 are each operably connected to the pin circuits 914a, 914b, 914c, respectively. In one embodiment, the pin circuits 914a, 914b, 914c are operably connected to one or more IO blocks (e.g., the IO blocks 822, 826 in the memory macro 800) in the memory macro. Each exemplary power management circuit 1002, 1004, 1006 includes an inverter 1026 that receives a signal VHI on signal line 1028. In one embodiment, the VHI signal is received from the V2 power supply. The output of the inverter 1026 is operably connected to an input of a NOR gate 1030. Another input of the NOR gate 1030 (the NOR gate 1030 in the power management circuit 1002) receives the SLP2D signal on signal line 1024b. The NOR gate 1030 in the power management circuit 1004 receives the SLP2D signal on signal line 1024c and the NOR gate 1030 in the power management circuit 1006 receives the SLP2D signal on signal line 1024d. The SLP2D signal is output from the inverter 1022 in the power management circuit 1000. Figure 8

[0093] ​​The output of the NOR gate 1030 in each power management circuit 1002, 1004, 1006 is operatively connected to an input of the respective pin circuit 914a, 914b, 914c. In addition, the output of the NOR gate 1030 in the power management circuit 1002 is input into an inverter 1026 in the power management circuit 1004 (RC delay represented by dashed line 1032). The output of the NOR gate 1030 in the power management circuit 1004 is input into an inverter 1026 in the power management circuit 1006 (RC delay represented by dashed line 1034).

[0094] Each exemplary pin circuit 914a, 914b, 914c includes an inverter 1036 that receives the signal output from the NOR gate 1030. The output of the inverter 1036 is operatively connected to a transistor 1038 (e.g., the gate of the transistor 1038). In the illustrated embodiment, the transistor 1038 is a p-type transistor. The pin circuit 914a, 914b, 914c turns on to provide power (e.g., the V2 signal) to circuitry in the IO block(s) 822, 826 of the memory macro (e.g., Figure 8 and turns off to not provide power to circuitry in the IO block(s) 822, 826 of the memory macro (e.g., Figure 8 Based on the state of the SD2 signal and the DSLP2 signal received on the signal lines 1018, 1020, respectively, from the level shifter circuit, the power management circuit 1002, 1004, 1006 controls the power ramping mode(s) of the circuitry in the IO block(s). For example, the pin circuit 914a, 914b, 914c turns on when the signal levels of the SD2 signal and the DSLP2 signal are low and the signal level of the VHI signal is high. The pin circuit 914a, 914b, 914c turns off when at least one of the signal levels of the SD2 signal and the DSLP2 signal is high or when the signal level of the VHI signal is low.

[0095] Exemplary power management circuits 1008, 1010, 1012 are operatively connected to pin circuits 914d, 914e, 914f, respectively. In one embodiment, the pin circuits 914d, 914e, 914f are operatively connected to one or more IO blocks in the memory macro (e.g., Figure 8bit line precharge circuitry in the IO blocks 822, 826 in the memory macro 800). Each example power management circuit 1008, 1010, 1012 includes an output of an inverter 1040 operably connected to an input of a NOR gate 1042. Another input of the NOR gate 1042 (the NOR gate 1042 in the power management circuit 1008) receives SLP2D on the signal line 1024e. The NOR gate 1042 in the power management circuit 1010 receives the SLP2D signal on the signal line 1024f, and the NOR gate 1042 in the power management circuit 1012 receives the SLP2D signal on the signal line 1024g.

[0096] The output of the NOR gate 1042 in the power management circuits 1008, 1010, 1012 is operably connected to an input of a respective pin circuit 914d, 914e, 914f. Each example pin circuit 914d, 914e, 914f includes an inverter 1044 that receives the signal output from the NOR gate 1042. The output of the inverter 1044 is operably connected to an input of an OR gate 1046. The GLB_BLPREB signal is input into the other input of the OR gate 1046 on the signal line 1048. In a non-limiting example, the GLB_BLPREB signal is the signal output from the NOR gate 1042. The output of the OR gate 1046 is operably connected to a transistor 1050 (e.g., the gate of the transistor 1050). In the illustrated embodiment, the transistor 1050 is a p-type transistor.

[0097] The signal output from the NOR gate 1030 in the power management circuit 1006 is input into the inverter 1040 in the power management circuit 1008 (the RC delay is represented by the dashed line 1052). The output of the NOR gate 1042 in the power management circuit 1008 is input into the inverter 1040 in the power management circuit 1010 (the RC delay is represented by the dashed line 1054). The output of the NOR gate 1042 in the power management circuit 1010 is input into the inverter 1040 in the power management circuit 1012 (the RC delay is represented by the dashed line 1056).

[0098] The pin circuits 914d, 914e, 914f are turned on to power circuitry (e.g., bit line precharge circuitry) in the IO block(s) of the memory macro (e.g., the IO blocks 822, 826 in the memory macro 800). Figure 8The bit line pre-charge circuit(s) in the IO blocks 822, 826 in the memory macro 800 provide power (e.g., the V2 signal) to the circuitry in the IO block(s) of the memory macro and turn off to not provide power to the circuitry in the IO block(s) of the memory macro. The power management circuit 1008, 1010, 1012 controls the power ramp mode of the circuitry in the IO block(s) based on the state of the SD2 signal and the DSLP2 signal received on the signal lines 1018, 1020, respectively, from the level shifter circuit and the state of the signal output from the NOR gates 1030, 1042. For example, the pin circuit 914d, 914e, 914f is on when the signal levels of the SD2 signal and the DSLP2 signal are low, the signal level of the signal output from the NOR gate 1030 in the power management circuit 1006 is high, and the signal level of the GLB_BLPREB signal is low. The pin circuit 914d, 914e, 914f is off when at least one of the signal levels of the SD2 signal and the DSLP2 signal is high, when the signal level of the signal output from the NOR gate 1030 is low, or when the signal level of the GLB_BLPREB signal is high.

[0099] The exemplary power management circuit 1014 is operably connected to the pin circuit 908. In one embodiment, the pin circuit 908 is operably connected to the WLDV block(s) in the memory macro (e.g., the WLDV block 812 in the memory macro 800). Figure 8 The output of the NOR gate 1042 in the power management circuit 1012 is received by the input of the inverter 1058. The output of the inverter 1058 is operably connected to the WLDV pin circuit 908. In the illustrated embodiment, the pin circuit 908 is a p-type transistor 1060.

[0100] The pin circuit 908 is on to provide power (e.g., the V2 signal) to the circuitry in the WLDV block(s) of the memory macro (e.g., the WLDV block 812 in the memory macro 800) and is off to not provide power to the circuitry in the WLDV block(s) of the memory macro (e.g., the WLDV block 812 in the memory macro 800). Figure 8 The pin circuit 908 is on to provide power (e.g., the V2 signal) to the circuitry in the WLDV block(s) of the memory macro (e.g., the WLDV block 812 in the memory macro 800) and is off to not provide power to the circuitry in the WLDV block(s) of the memory macro (e.g., the WLDV block 812 in the memory macro 800). Figure 8The circuitry in the WLDV block 812 provides power (e.g., the V1 signal). Based on the states of the SD2 and DSLP2 signals received from the level shifter circuit on signal lines 1018 and 1020, respectively, and based on the signal level of the GLB_BLPREB signal output from the NOR gate 1042 in the power management circuit 1012, the power management circuit 1014 controls one or more power ramp modes for the circuitry in one or more WLDV blocks. For example, when the signal levels of the SD2 and DSLP2 signals are low and the signal level of the GLB_BLPREB signal output from the NOR gate 1042 in the power management circuit 1012 is high, the pin circuit 908 is turned on. When at least one of the signal levels of the SD2 and DSLP2 signals is high, or when the signal level of the GLB_BLPREB signal is low, the pin circuit 908 is turned off.

[0101] Figure 11 A schematic diagram of a second example of a power management circuit suitable for use in a power management circuitry system, according to some embodiments, is shown. Power management circuitry block 1100 includes power management circuits 1102, 1104, and 1106, respectively operably connected to pin circuits 910a, 910b, and 910c. In one embodiment, pin circuits 910a, 910b, and 910c are operably connected to one or more MA blocks in a memory macro (e.g., ...). Figure 8 MA blocks 802 and 808 in the memory macro. Pin circuits 910a, 910b, and 910c are operably connected between V1 (e.g., VDDAI) and V2 (e.g., VDDM). Some or all of the power management circuits 1102, 1104, and 1106 can be implemented in a power management circuit system within a memory macro (e.g., ...). Figure 1 and Figure 9 The power management circuit system 124 in the middle), and some or all of the pin circuits 910a, 910b, 910c can be included in the pin circuit (e.g., Figure 1 (Pin circuit 122 in the example). In the illustrated embodiment, power management circuits 1102, 1104, and 1106 operate in the V2 domain.

[0102] An exemplary power management circuit block 1100 includes an inverter 1108, which is connected on signal line 1110 from a level shifter circuit (e.g., Figure 7 The level shifter circuit shown receives the DSLPV2 signal. The output of inverter 1108 is input to AND gate 1112. The signal from the level shifter circuit (e.g., Figure 7The SLP2 signal from the level shifter circuit (e.g., the level shifter circuit shown in FIG. 10) is received on signal line 1114 by another input of AND gate 1112. The output of AND gate 1112 is received by an input of NOR gate 1116. The SD2 signal from the level shifter circuit (e.g., the level shifter circuit shown in FIG. 10) is received on signal line 1118 by another input of NOR gate 1116. Figure 4 The SLP2 signal from the level shifter circuit (e.g., the level shifter circuit shown in FIG. 10) is received on signal line 1114 by another input of AND gate 1112. The output of AND gate 1112 is received by an input of NOR gate 1116. The SD2 signal from the level shifter circuit (e.g., the level shifter circuit shown in FIG. 10) is received on signal line 1118 by another input of NOR gate 1116.

[0103] The output of NOR gate 1116 is input to inverter 1120. Inverter 1108, AND gate 1112, NOR gate 1116, and inverter 1120 are included in power management circuits 1102, 1104, 1106. The output of inverter 1120 (SLP2D_MCB) is input to power management circuits 1102, 1104, 1106 on signal lines 1122a, 1122b, 1122c, respectively. Exemplary power management circuit 1102 includes inverter 1124, which receives the SLP2D_MCB signal on signal line 1122a. The output of inverter 1124 is input to pin circuit 910a. Exemplary pin circuits 910a, 910b, 910c each include inverter 1126, which receives the output of inverter 1124. The output of inverter 1126 is input to transistor 1128. In the embodiment shown, transistor 1128 is a p-type transistor.

[0104] Power management circuit 1104 includes NOR gate 1130, which receives the SLP2D_MCB signal on signal line 1122b. Another input of NOR gate 1130 receives the output of inverter 1132. Another input of NOR gate 1130 receives signal SD_DLY1 on signal line 1134. The output of inverter 1124 in power management circuit 1102 is received as an input of inverter 1132 (dashed line 1136 represents an RC delay). The output of NOR gate 1130 is input to pin circuit 910b (e.g., to inverter 1126 of pin circuit 910b).

[0105] Power management circuit 1106 includes NOR gate 1138, which receives the SLP2D_MCB signal on signal line 1122c. Another input of NOR gate 1138 receives the output of inverter 1140. Another input of NOR gate 1138 receives signal SD_DLY2 on signal line 1142. The output of NOR gate 1130 in power management circuit 1104 is received as an input of inverter 1140 (dashed line 1144 represents an RC delay). The output of NOR gate 1138 is input to pin circuit 910c (e.g., to inverter 1126 of pin circuit 910c).

[0106] The SD_DLY1 signal and the SD_DLY2 signal are delayed signals of the SD2 signal, as shown in region 1146. The SD2 signal is input into a delay circuit to produce a first delay 1148. The first delay produces the SD_DLY1 signal. The SD_DLY1 signal is input into another delay circuit to produce a second delay 1150. The second delay 1150 produces the SD_DLY2 signal. A non-limiting example of a delay circuit is a buffer circuit. The SD_DLY1 signal and the SD_DLY2 signal are used to manage and isolate peak current levels in one or more MA pin circuits (e.g., pin circuits 910a, 910b, 910c) operably connected to one or more MA blocks (e.g., MA blocks 802, 808) in the memory macro. Figure 8

[0107] The pin circuits 910a, 910b, 910c are turned on to provide power (e.g., V2 signal) to circuitry in the respective MA block(s) (e.g., MA blocks 802, 808) of the memory macro, and turned off to not provide power to circuitry in the respective MA block(s) (e.g., MA blocks 802, 808) of the memory macro. Figure 8 Figure 8 The pin circuits 910a, 910b, 910c are turned on to provide power (e.g., V2 signal) to circuitry in the respective MA block(s) (e.g., MA blocks 802, 808) of the memory macro, and turned off to not provide power to circuitry in the respective MA block(s) (e.g., MA blocks 802, 808) of the memory macro.

[0108] The exemplary pin circuit 910b is turned on when the signal levels of the SLP2D_MCB signal and the SD_DLY1 signal are low. The exemplary pin circuit 910c is turned on when the signal levels of the SLP2D_MCB signal and the SD_DLY2 signal are low.

[0109] Figure 12 A schematic diagram illustrating a third example of a power management circuit suitable for use in power management circuitry, in accordance with some embodiments, is shown. The exemplary power management circuit 1200 is operably connected to a pin circuit 912. In one embodiment, the pin circuit 912 is operably connected to one or more IO edge blocks (e.g., IO edge blocks 804, 806) in a memory macro. Figure 8 ​​IO blocks (e.g., IO blocks 820, 824 in FIG. 8B) in the memory macro. The exemplary power management circuit 1202 is operably connected to pin circuit 914g and pin circuit 910d. Pin circuit 914g is operably connected to one or more IO blocks (e.g., IO blocks 822, 826 in FIG. 8B) in the memory macro, and pin circuit 910d is operably connected to one or more MA blocks (e.g., MA blocks 802, 808 in FIG. 8B) in the memory macro. In another embodiment, pin circuit 910d can be replaced with a pin circuit that is operably connected to one or more IO blocks. Pin circuits 914g, 910d are operably connected between VI (e.g., VDDAI) and V2 (e.g., VDDM). Some or all of power management circuits 1200, 1202 can be implemented in power management circuitry in the memory macro (e.g., power management circuitry 124 in FIG. 8B), and some or all of pin circuits 912, 910d, 914g can be included in pin circuits in the memory macro (e.g., pin circuits 122 in FIG. 8B). In one embodiment, power management circuits 1200, 1202 operate in the V2 domain. Figure 8 Figure 8 Figure 1 Figure 9 Figure 1

[0110] Power management circuit 1200 includes NOR gate 1204 that receives the SD2 signal on signal line 1206 and the SD_DLY2 signal on signal line 1208 (e.g., from region 1146 in FIG. 11). The output of NOR gate 1204 is input into inverter 1210. The output of inverter 1210 (the SD_DIO signal) is input into pin circuit 912. The exemplary pin circuit 912 is implemented as p-type transistor 1212, but other embodiments are not limited to this configuration. The exemplary pin circuit 912 is on when the signal level of the SD_DIO signal is low (e.g., when the signal levels of the SD2 signal and the SD_DLY2 signal are low). Figure 11

[0111] Power management circuit 1202 includes inverter 1214 that receives the DS LPNDIO2 signal on signal line 1216. The output of inverter 1214 is input into inverter 1218. The output of inverter 1218 (the DS LPNDIO_1 signal) is input into pin circuit 914g. In the illustrated embodiment, pin circuit 914g is n-type transistor 1220, and the output of inverter 1218 is received by the gate of n-type transistor 1220.

[0112] ​​​​​​An exemplary pin circuit 910d includes a p-type transistor 1222 connected in parallel with an n-type transistor 1224. The p-type transistor 1222 is also connected in parallel with a pin circuit 914g (e.g., transistor 1220). The gate of the p-type transistor 1222 is operatively connected to a first terminal 1226 of the pin circuit 914g. The gate of the n-type transistor 1224 is operatively connected to a second terminal 1228 of the pin circuit 914g. Furthermore, a terminal 1230 of the pin circuit 912 is operatively connected to the second terminal 1228 of the pin circuit 914g. Exemplary pin circuits 914g and 910d are turned on when the signal level of the DSLPNDIO_1 signal is high (e.g., when the signal level of the DSLPNDIO2 signal is high).

[0113] Figure 13 A schematic diagram of a fourth example of a power management circuit suitable for use in a power management circuitry system, according to some embodiments, is shown. In one embodiment, the power management circuitry 1300 is a wake-up circuit connected to a main control circuit, and the output of the power management circuitry 1300 is used as an isolation control signal to prevent potential leakage during power-off. The power management circuitry 1300 can be implemented in a power management circuitry system within a memory macro (e.g., Figure 1 and Figure 9 (Power management circuitry system 124 in the V2 domain). In one embodiment, the power management circuitry 1300 operates in the V2 domain.

[0114] The power management circuit 1300 includes a NOR gate 1302, which receives power from... Figure 10 The signal output from inverter 1058 shown is used as the input signal (dashed line 1304 indicates RC delay). NOR gate 1302 receives the signal from... Figure 11 The signal output from inverter 1126 in power management circuit 1106 shown is used as the input signal (dashed line 1306 indicates RC delay). NOR gate 1302 receives the signal from power management circuit 1000 ( Figure 10 The SLP2D signal output by inverter 1022 in the NOR gate is used as the input signal on signal line 1308. The output of NOR gate 1302 is operatively connected to the input of inverter 1310. Inverter 1310 outputs a wake-up signal on signal line 1312.

[0115] Figure 14 The following are examples of suitable applications for use with [the following] according to some embodiments. Figures 10-13 An exemplary level shifter device used in conjunction with the power management circuitry shown is included. Level shifter device 1400 includes four level shifter circuits 1402, 1404, 1406, and 1408. In one embodiment, level shifter device 1400 is... Figure 1The level shifter device 128 is shown. Each level shifter circuit 1402, 1404, 1406, 1408 receives data from the V1 domain (e.g., Figure 9 The signal in the V1 domain (902) is output and the signal in the V2 domain is output.

[0116] The level shifter circuit 1402 receives the SD1 signal from the V1 domain and outputs the SD2 signal in the V2 domain. The SD2 signal is used by the power management circuit 1000. Figure 10 ), 1100 ( Figure 11 ) and 1200 ( Figure 12 The input signal in ). In one embodiment, the level shifter circuit 1402 is implemented as Figure 4 The level shifter circuit 300a shown is illustrated.

[0117] The level shifter circuit 1404 receives the DSLP1 signal from the V1 domain and outputs the DSLP2 signal in the V2 domain. The DSLP2 signal is used by the power management circuit 1000. Figure 10 ) and 1100 ( Figure 11 The input signal in ). In one embodiment, the level shifter circuit 1406 is implemented as Figure 7 The level shifter circuit 600 shown is illustrated.

[0118] The level shifter circuit 1406 receives the DSLPLV1 signal from the V1 domain and outputs the DSLPLV2 signal in the V2 domain. The DSLPLV2 signal is used by the power management circuit 1100. Figure 11 The input signal in ). In one embodiment, the level shifter circuit 1406 is implemented as Figure 7 The level shifter circuit 600 shown is illustrated.

[0119] The level shifter circuit 1408 receives the DSLPNDIO1 signal from the V1 domain and outputs the DSLPNDIO2 signal in the V2 domain. The DSLPNDIO2 signal is used by the power management circuit 1200. Figure 12 The input signal in ). In one embodiment, the level shifter circuit 1408 is implemented as Figures 3-5 The level shifter circuit 600 shown is illustrated.

[0120] In the level shifter circuit including the output SD2 signal ( Figure 10 In the embodiments of ), Figure 11 The power management circuit shown does not include NOR gate 1016 and inverter 1022, and the SD2 signal is received on signal lines 1024a-1024g. Figure 12The power management circuit shown in FIG. 11 does not include inverter 1108, AND gate 1112, NOR gate 1116, and inverter 1120. SD2 signal is received on signal lines 1122a, 1122b, 1122c. The power management circuit 1202 in FIG. 12 can be omitted Figures 6-7

[0121] In embodiments that include a level shifter circuit that outputs SD2 signal and a level shifter circuit that outputs DSLP2 signal, Figure 11 Figure 12 The power management circuit shown in FIG. 11 does not include inverter 1108 and AND gate 1112. SD2 signal and DSLP2 signal are received by NOR gate 1116. Figure 15 Inverter 1214 in power management circuit 1202 in FIG. 12 receives DSLP2 signal.

[0122] Figure 16 An exemplary timing diagram for a first power ramping mode is shown in accordance with some embodiments. The embodiment shown depicts a DL mode in which the VI voltage signal ramps up before the V2 voltage signal ramps up, and the VI voltage signal ramps down after the V2 voltage signal ramps down.

[0123] At time tO, SD1 signal, DSLP1 signal (if used), VI signal, V2 signal, and PD1 INT signal are at a low signal level (e.g., logic state 0). PD1 INT signal is an internal power down control signal in the VI domain that can be used to power down the VI domain during a shutdown mode, sleep mode, bulk-off mode Figure 10 (bulk-off mode shown in FIG. 10), and / or time periods when the V2 signal is ramping up and down. Signal Q output from the memory macro is also at a low signal level. As previously mentioned, in one embodiment, VI voltage signal is VDD voltage signal and V2 signal is VDDM voltage signal.

[0124] At time tl, VI signal and PD1 INT signal begin to ramp up to a high signal level (e.g., logic state 1). As previously mentioned, in a DL mode, VI signal ramps up before V2 signal. In one embodiment, logic circuit 904 provides SD1 signal to buffer circuit to output PD1 INT signal, where PD1 INT signal ramps up. Level shifter device 128 and power management circuitry 124 (e.g., Figure 9 shown in FIG. 12) cause VI signal to ramp up. SD1 / DSLP1 signal, V2 signal, and Q signal remain at a low signal level.

[0125] ​​At time t2, the SD1 signal (and the DSLP1 signal if the DSLP1 signal is also used) begins to ramp up to a high signal level. For example, the logic circuit 904 Figure 4 ) causes the SD1 signal and the DSLP1 signal to ramp up. The SD1 signal is received by the level shifter circuits 300a, 300b Figure 5 and Figure 6 ) and the DSLP1 signal is received by the level shifter circuit 600 Figure 1 ). The V1 signal and the PD1 INT signal are at a high signal level. The V2 signal and the Q signal remain at a low signal level.

[0126] Between time t2 and time t3, the V2 signal ramps up to a high signal level and the SD1 / DSLP1 signal(s) ramps down to a low signal level. In one embodiment, the level shifter device 128 Figure 10 ) and the power management circuitry 124 (e.g., the power management circuit shown in Figure 1 ) cause the V2 signal to ramp up based on data received from the logic circuit 130 and the logic circuit 904 causes the SD1 signal to ramp down. Further, the PD1 INT signal begins to ramp down to a low signal level once the V2 signal is at a high signal level. In one embodiment, the SD1 signal and the DSLP1 signal ramp up to a high signal level and ramp down to a low signal level between time t2 and t3 to reduce or avoid leakage on the V1 supply rail.

[0127] At time t3, the SD1 signal (and the DSLP1 signal if the DSLP1 signal is also used) is at a low signal level. The V1 signal and the V2 signal are at a high signal level. The PD1 INT signal is gradually ramping down to a low signal level or is at a low signal level. Between time t3 and time t4, a read operation or a write operation is performed and the signal Q (represented as the Q signal ramping up to a high signal level in the illustrated embodiment) is output by the memory macro. However, the value or signal level of the Q signal can be a low signal level (e.g., logic state 0) or a high signal level (e.g., logic state 1) as shown, depending on the data stored in the accessed memory cell.

[0128] At time t4, the SD1 signal and the DSLP1 signal ramp up to a high signal level. For example, the logic circuit 904 causes the SD1 signal and the DSLP1 signal to ramp up. The V1 signal, the V2 signal, and the Q signal remain at a high signal level. Between time t4 and time t5, the SD1 / DSLP1 signal(s) ramps up to a high signal level to reduce or avoid leakage on the V1 supply rail.

[0129] Between time t4 and time t6, the Q signal ramps down to a low signal level. When the V1 and V2 signals are at a high signal level, the signal level of the Q signal is indeterminate because the signal level can be either high or low (0 / 1). In the illustrated embodiment, the indeterminacy of the Q signal is represented by the three lines in region 1500.

[0130] Between time t5 and t6, the V2 signal ramps down to a low voltage signal. In one embodiment, the level shifter device 128 Figure 10 ) and the power management circuitry 124 (e.g., the power management circuit shown in Figure 1 ) causes the V2 signal to ramp down based on data received from the logic circuit 130. After the V2 signal is at a low signal level, the SD1 / DSLP1 signal(s), the V1 signal, and the PD1 INT signal ramp down to a low signal level. For example, the logic circuit 904 causes the SD1 / DSLP1 signal(s) to ramp down and provides the SD1 signal to the buffer circuit. The PD1 INT signal is output from the buffer circuit. Thus, the PD1 INT signal ramps down. The level shifter device 128 Figure 10 ) and the power management circuitry 124 (e.g., the power management circuit shown in Figure 16 ) causes the V1 signal to ramp down. After time t6, the SD1 / DSLP1 signal(s), the V1 signal, the V2 signal, the PD1 INT signal, and the Q signal are all at a low signal level.

[0131] Figure 1 An exemplary timing diagram for a second power ramping mode is shown in accordance with some embodiments. The illustrated embodiment depicts a DM mode in which the V2 voltage signal ramps up before the V1 voltage signal ramps up and the V2 voltage signal ramps down after the V1 voltage signal ramps down. The timing diagram also shows the execution of a bulk-off mode. As previously mentioned, the bulk-off mode is an additional power saving mode in which the V1 power is turned off when the memory macro is in a sleep mode.

[0132] At time t0, the ISOSRM signal, the ISORET signal, the SD1 signal, the DSLP1 signal, the V2 signal, the V1 signal, the PD1 INT signal, the PD2 INT signal, and the Q signal are at a low signal level (e.g., logic state 0). The PD2 INT signal is an internal power down signal in the V2 domain that is used to power down the V2 domain during the time period in which the V1 signal and the V2 signal are ramping up or down.

[0133] At time t1, the ISOSRM signal, the V2 signal, and the PD2 INT signal begin to ramp up to a high signal level (e.g., logic state 1). In one embodiment, the processing device 126 Figure 10) causes the ISOSRM signal to ramp up, and the level shifter device 128 and power management circuitry 124 (e.g., the power management circuit shown in Figure 4 , causes the V2 signal to ramp up. Although not shown in Figure 5 and Figure 9 , the SD1 signal input is also used to output the PD2 INT signal from a level shifter device (e.g., the level shifter device 128). The ISORET signal, the SD1 signal, the DSLP1 signal, the V1 signal, the PD1 INT signal, and the Q signal remain at a low signal level. In one embodiment, the SIOSRM signal must be at a high signal level during the entire V2 signal and V1 signal ramp up time period (time t1 to time t3) to reduce or prevent DC current at the level shifter circuit(s).

[0134] At time t2, the SD1 signal and the V1 signal begin to ramp up to a high signal level. As previously described, the logic circuit 904 Figure 10 ) causes the SD1 signal to ramp up, and the level shifter device 128 and power management circuitry 124 (e.g., the power management circuit shown in Figure 1 , causes the V1 signal to ramp up. In one embodiment, the SD1 signal ramps up to a high signal level to reduce or avoid leakage of V2 on the supply rail. The SIOSRM signal, the V2 signal, and the PD2 INT signal remain at a high signal level. The ISORET signal, the DSLP1 signal, and the Q signal remain at a low signal level.

[0135] Between time t2 and t3, the V1 signal ramps up to a high signal level, and while V1 is ramping up, the input(s) of the level shifter circuit(s) are in a floating state. Thus, in one embodiment, the V1 to V2 domain interface is isolated to prevent DC current in the level shifter circuit.

[0136] At time t3, the ISORET signal, the DSLP1 signal, and the Q signal remain at a low signal level. The SD1 signal, the PD1 INT signal, the V2 signal, the V1 signal, and the PD2 INT signal remain at a high signal level, and the SIOSRM signal begins to ramp down to a low signal level. The processing device 126 Figure 9 ) causes the SIOSRM signal to ramp down based on data received from the logic circuit 130.

[0137] Between time t3 and t4, the SD1 signal and the SIOSRM signal ramp down to a low signal level, and the PD1 INT and PD2 INT signals begin to ramp down to a low signal level. The logic circuit 904 Figure 1 ) causes the SD1 signal and the PD1 INT signal to ramp down, and the processing device 126 Figure 1) ramps down the ISOSRM signal and the level shifter device 128 ramps down the PD2 INT signal.

[0138] At time t4, the ISOSRM signal, the ISORET signal, the SD1 signal, the DSLP1 signal, and the Q signal are at a low signal level. The V1 signal and the V2 signal remain at a high signal level.

[0139] Between time t4 and time t5, the ISOSRM signal, the ISORET signal, and the DSLP1 signal ramp up to a high signal level. In one embodiment, the processing device 126 ( Figure 9 ) ramps up the ISOSRM signal and the ISORET signal, and the logic circuit 904 ( Figure 15 ) ramps down the DSLP1 signal. A read or write operation can be performed between time t4 and t5, which is indicated by the ramping up and down of the Q signal. Similar to Figure 1 , the value or signal level of the Q signal can be a low signal level (e.g., logic state 0) or a high signal level (e.g., logic state 1), depending on the data stored in the accessed memory cell.

[0140] At time t5, the ISOSRM signal, the ISORET signal, the DSLP1 signal, the V2 signal, and the V1 signal are at a high signal level. The SD1 signal remains at a low signal level. The ISORET signal places the memory macro in a bulk-off mode. The bulk-off mode is depicted between time t5 and t6, where the V1 signal is turned off when the V2 signal is at a high signal level. Thus, between time t4 and t7, the PD1 INT signal ramps up and down for the bulk-off mode, and the PD2 INT signal ramps up and down due to the transition in the V1 signal.

[0141] Between time t5 and t6, the ISORET signal ramps up to a high signal level and the DSLP1 signal ramps down to a low signal level when the V1 signal is off. Between time t5 and t6, data is retained in the one or more memory cells when the ISORET signal and the ISOSRM signal are at a high signal level. Further, the signal levels of the ISOSRM and ISORET signals are high when the signal level of the DSLP signal is high to cover the period of V2 high and V1 low to retain data in the memory cell(s). In one embodiment, the processing device 126 ( Figure 9 ) ramps up the ISORET signal, and the logic circuit 904 ( Figure 9 ) ramps down the DSLP1 signal.

[0142] Between times t6 and t7, the ISOSRM signal, the ISORET signal, the SD1 signal, and the DSLP1 signal are at a low signal level, and the V1 signal and the V2 signal are at a high signal level. During this time, a read or write operation can be performed, as indicated by the Q signal transitioning to a high signal level. However, as previously mentioned, the value or signal level of the Q signal can be a low signal level (e.g., logic state 0) or a high signal level (e.g., logic state 1), depending on the data stored in the accessed memory cell.

[0143] Between times t7 and t8, the SD1 signal ramps up to a high signal level, which causes the Q signal to ramp down to a low signal level. In one embodiment, the logic circuit 904 Figure 1 ) causes the SD1 signal to ramp up. The V1 signal and the V2 signal are at a high signal level. The ISOSRM signal, the ISORET signal, and the DSLP signal are at a low signal level.

[0144] Between times t8 and time t9, the ISORET signal, the DSLP1 signal, and the Q signal are at a low signal level. The SD1 signal and the V1 signal ramp down to a low signal level. As previously mentioned, in the DM mode, the V1 signal ramps down before the V2 signal ramps down. Between times t8 and time t10, the high signal level of the ISOSRM signal remains at a high signal level to reduce or prevent DC current in the level shifter circuit(s).

[0145] Between times t9 and t10, the ISOSRM signal, the V2 signal, and the PD2 INT signal ramp down. The processing device 126 Figure 10 ) causes the ISOSRM signal to ramp down, the level shifter device 128 causes the PD2 INT signal to ramp down, and the level shifter device 128 and the power management circuitry 124 (e.g., the power management circuit shown in Figure 17 ) causes the V2 signal to ramp down. After time t10, the ISOSRM signal, the ISORET signal, the SD1 signal, the DSLP1 signal, the V2 signal, the V1 signal, the SD2 signal, and the Q signal are at a low signal level.

[0146] Figure 16An exemplary flowchart depicting a method of operating a power ramp control system in accordance with some embodiments is shown. Initially, at block 1700, a strobe signal is received by a level shifter device. In one embodiment, the strobe signal is the ISOSRM signal. At block 1702, it is determined whether the state of the strobe signal is in a first state (e.g., the signal level is low) or a second state (e.g., the signal level is high). If the state of the strobe signal is in the first state, the process proceeds to block 1704, where a first power ramp mode is generated in or for the memory macro. Then, the method optionally continues at block 1706, where a second power ramp mode is generated in or for the memory macro.

[0147] In one embodiment, the first power ramp mode (block 1704) is the DM mode, and the second power ramp mode (block 1706) is the DL mode. In the DM mode, the V2 signal is ramped up before the VI signal is ramped up, and the VI signal is ramped down before the V2 signal is ramped down. In the DL mode, the VI signal is ramped up before the V2 signal is ramped up, and the V2 signal is ramped down before the VI signal is ramped down. Figure 15 An exemplary timing diagram for the DM mode is shown, and Figure 17 An exemplary timing diagram for the DL mode is shown. In another embodiment, the first power ramp mode (block 1704) is the DL mode, and the second power ramp mode (block 1706) is the DM mode.

[0148] If the state of the strobe signal is in the second state, the process proceeds to block 1708, where the second power ramp mode is generated in or for the memory macro. Then, the method optionally continues at block 1710, where the first power ramp mode is generated in or for the memory macro. As previously described, in one embodiment, the second power ramp mode (block 1708) is the DL mode, and the first power ramp mode (block 1710) is the DM mode. Alternatively, in another embodiment, the second power ramp mode (block 1708) is the DM mode, and the first power ramp mode (block 1710) is the DL mode.

[0149] Figures 10-13 It is described that only one power ramp mode is performed (either block 1704 or block 1708 is performed), or a bidirectional power ramp mode is performed (where both block 1704 and 1706 are performed, or both block 1708 and 1710 are performed). As previously described, a bidirectional power ramp mode combines two or more power ramp modes simultaneously. For example, Figure 15The power management circuit shown in the middle supports a bidirectional power ramping mode that concurrently controls the first power ramping mode and the second power ramping mode. In a non-limiting example, in the first power ramping mode, VI ramps up before V2 ramps up, and VI ramps down after V2 ramps down (as shown in the left side of Figure 16 the figure). In the second power ramping mode, V2 ramps up before VI ramps up, and V2 ramps down after VI ramps down (as shown in the right side of Figure 18 the figure). Embodiments can cause the first power ramping mode to be initially performed, and the second power ramping mode to be performed after the first power ramping mode; or cause the second power ramping mode to be initially performed, and the first power ramping mode to be performed after the second power ramping mode.

[0150] Figure 18 An example system that can include one or more memory devices is shown in accordance with some embodiments. The system 1800 includes an electronic device 1802. In an example configuration, the electronic device 1802 includes at least one processing device 1804 and at least one memory device 1806. The memory device 1806 can include a plurality of data files and executable instructions of program modules, for example: executable instructions associated with an operating system (OS) 1808; one or more software programs (apps) 1810 suitable for parsing received input, determining a subject matter of the received input, determining an action to associate with the input, and the like; and memory operations 1812 for performing some or all of the memory operations disclosed herein. When executed by the processing device(s) 1804, the executable instructions can perform and / or cause to be performed aspects including, but not limited to, those described herein. In one embodiment, the memory device 1806 and / or the memory device 1814 stores one or more strobe signals, sleep signal(s), power-off signals, and / or memory output signals.

[0151] For example, the OS (operating system) 1808 can be suitable for controlling the operation of the electronic device 1802. Moreover, embodiments can be practiced in conjunction with a graphics library, other operating systems, or any other application programs, and are not limited to any particular application or system. The electronic device 1802 can have additional features or functionality. For example, the electronic device 1802 can also include additional removable and / or non-removable data storage devices 1814, such as magnetic disks, optical disks, tape, and / or memory cards or sticks. The memory device 1806 and / or the data storage device 1814 can be implemented as a memory device disclosed herein. For example, the memory device 1806 and / or the data storage device 1814 can be an SRAM device.

[0152] The electronic device 1802 can have additional features or functionality. For example, the electronic device 1802 can also include additional removable and / or non-removable data storage devices 1814, such as magnetic disks, optical disks, tape, and / or memory cards or sticks. The memory device 1806 and / or the data storage device 1814 can be implemented as a memory device disclosed herein. For example, the memory device 1806 and / or the data storage device 1814 can be an SRAM device.

[0153] The electronic device 1802 can also have one or more input device(s) 1816 and one or more output device(s) 1818. Exemplary input device(s) 1816 include, without limitation, a keyboard, touchscreen, mouse, pen, voice or speech input device, and / or touch, force, and / or gesture input device. The output device(s) 1818 can be one or more displays, speakers, printers, headphones, tactile or haptic feedback devices, and the like. The electronic device 1802 can include one or more communication devices 1820 allowing communication with other electronic devices. Exemplary communication devices 1820 include, without limitation, radio frequency (RF) transmitter, receiver, and / or transceiver circuitry (e.g., WiFi), universal serial bus (USB), parallel, and / or serial ports, cellular devices, near field communication devices, and short-range wireless devices.

[0154] The electronic device 1802 also includes a power supply 1822, which can be implemented as one or more batteries or supplemental battery or charging cradle for charging the battery.

[0155] The system memory device 1806 and the storage device(s) 1814 can include, without limitation, volatile memory (e.g., random access memory), non-volatile memory (e.g., read-only memory), flash memory, or any combination of such memories. For example, the system memory device 1806 and the storage device(s) 1814 can each be RAM, ROM, electrically erasable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic disks storage or other magnetic storage devices, or any other medium that can be used to store information and that can be accessed by the electronic device 1802. In some examples, any such memory or storage can be part of the electronic device 1802 or operatively connected to the electronic device 1802.

[0156] Furthermore, embodiments can be practiced in an electrical circuit comprising discrete electronic elements, packaged or integrated electronic chips containing logic gates, a circuit utilizing a microprocessor, or by using one or more computers. For example, embodiments of the present disclosure can be practiced via a system-on-a-chip (SOC) where each or various components illustrated in FIG. 18 can be integrated onto a single integrated circuit. Such an SOC device can include one or more processing units, graphics units, communications units, system virtualization units, and various application functionality all of which are integrated (or “burned”) onto the chip substrate as a single integrated circuit. Use of an SOC can result in one chip substrate containing complete circuits including one or more processors or CPUs, graphics processors or GPUs, communications units, system virtualization units, and various application functionality. Examples of such SOC devices include Apple® A4® and A5® chips available from Apple® Inc. of Cupertino, California. Figure 4 Each or multiple components shown in FIG. 18 can be integrated onto a single integrated circuit. Such an SOC device can include one or more processing units, graphics units, communications units, system virtualization units, and various application functionality all of which are integrated (or “burned”) onto the chip substrate as a single integrated circuit.

[0157] When operating via a SOC, the functionality described herein with respect to memory operations can operate via dedicated logic integrated with other components of the electronic device 1802 on a single integrated circuit (chip). Embodiments of the present disclosure can also be practiced using other technologies capable of performing logical operations such as, for example, AND, OR, and NOT, including but not limited to, mechanical, optical, fluidic, and quantum technologies. In addition, embodiments can be practiced within general purpose computers or in any other circuits or systems.

[0158] In some embodiments, the electronic device 1802 optionally accesses (optional connection and access represented by dashed line 1824) one or more server-computing devices (represented by server-computing device 1826) through wired and / or wireless connection to one or more networks (represented by network 1828). The server-computing device 1826 can interact with various programs or services stored on one or more storage devices (represented by storage device 1830) and executed by the server-computing device 1826.

[0159] In one or more embodiments, the network 1828 illustrates any type of network, such as, for example, an intranet and / or a distributed computing network (e.g., the Internet). The electronic device 1802 can be a personal or handheld computing device or a desktop computing device. For example, the electronic device 1802 can be a smartphone, a tablet, a wearable device, a desktop computer, a laptop computer, and / or a server (individually or in combination). This list of electronic devices is for example purposes only and should not be viewed as limiting.

[0160] Although the figures depict certain components, circuits, values, signal levels, and timing diagrams, other embodiments are not limited to these components, circuits, values, signal levels, and timing diagrams. For example, Figure 5 , Figure 7 and Figures 10-13 depict a schematic diagram of an exemplary level shifter circuit, and ​ show a schematic diagram of an exemplary power management circuit. Other embodiments are not limited to these implementations of level shifter devices and / or power management circuits. Level shifter devices and / or power management circuits can be constructed from different types of logic circuits, circuits, and / or components and combinations thereof.

[0161] In one aspect, an apparatus includes a memory macro and a level shifter apparatus. The memory macro includes power management circuitry. The memory macro is configured to receive a first voltage signal and a second voltage signal. The level shifter apparatus is configured to provide a third signal to the power management circuitry to control the first voltage signal and the second voltage signal in the memory macro based on a fourth signal. The first voltage signal is ramped before the second voltage signal is ramped when the fourth signal has a first logic state. The second voltage signal is ramped before the first voltage signal is ramped when the fourth signal has a second logic state.

[0162] In another aspect, the memory macro is operably connected to the level shifter apparatus. A method includes receiving a strobe signal by the level shifter apparatus. A first power ramping mode of a plurality of power ramping modes is caused in the memory macro based on a signal level of the strobe signal having a first logic state. A second power ramping mode of the plurality of power ramping modes is caused in the memory macro after the first power ramping mode is caused.

[0163] In yet another aspect, an electronic apparatus includes a power supply, a memory macro operably connected to the power supply, and a level shifter apparatus operably connected to power management circuitry in the memory macro and the power supply. The memory macro is configured to receive a first voltage signal and a second voltage signal. The power management circuitry is operable to cause the first voltage signal and the second voltage signal to ramp up and ramp down according to at least one power ramping mode included in a plurality of power ramping modes. The level shifter apparatus is operable to provide one or more signals to the power management circuitry that support the plurality of power ramping modes.

[0164] Some examples are given below.

[0165] Example 1. An apparatus comprising:

[0166] a memory macro configured to receive a first voltage signal and a second voltage signal, the memory macro including power management circuitry; and

[0167] a level shifter apparatus configured to provide a third signal to the power management circuitry to control the first voltage signal and the second voltage signal in the memory macro based on a fourth signal,

[0168] wherein:

[0169] the first voltage signal is ramped before the second voltage signal is ramped when the fourth signal has a first logic state; and

[0170] the second voltage signal is ramped before the first voltage signal is ramped when the fourth signal has a second logic state.

[0171] Example 2. The apparatus of Example 1, wherein the memory macro comprises a static random access macro, the static random access macro comprising a static random access memory array and peripheral circuitry.

[0172] Example 3. The apparatus of Example 2, wherein the peripheral circuitry comprises pin circuitry operably connected to respective ones of the power management circuitry.

[0173] Example 4. The apparatus of Example 1, wherein the first voltage signal is a VDD voltage signal and the second voltage signal is a VDDM voltage signal.

[0174] Example 5. The apparatus of Example 1, wherein the level shifter apparatus is configured to simultaneously incorporate a plurality of power ramping modes.

[0175] Example 6. The apparatus of Example 1, wherein the level shifter apparatus is configured to generate a shutdown signal.

[0176] Example 7. The apparatus of Example 1, wherein the level shifter apparatus is configured to generate a shutdown signal and a sleep signal.

[0177] Example 8. The apparatus of Example 1, wherein the level shifter apparatus is configured to float the first voltage signal in a bulk power down mode.

[0178] Example 9. The apparatus of Example 1, wherein the level shifter apparatus comprises four level shifter circuits, wherein one level shifter circuit outputs a shutdown signal and three level shifter circuits each output a sleep signal.

[0179] Example 10. A method comprising:

[0180] receiving a strobe signal at a level shifter apparatus, the level shifter apparatus operably connected to a memory macro;

[0181] based on a signal level of the strobe signal having a first logic state:

[0182] causing a first power ramping mode of a plurality of power ramping modes to be generated in the memory macro; and

[0183] causing a second power ramping mode of the plurality of power ramping modes to be generated in the memory macro after the first power ramping mode.

[0184] Example 11. The method of Example 10, wherein:

[0185] the first power ramp mode causes the first voltage signal to ramp up before the second voltage signal ramps up and the second voltage signal to ramp down before the first voltage signal ramps down; and

[0186] the second power ramp mode causes the second voltage signal to ramp up before the first voltage signal ramps up.

[0187] Example 12. The method of example 10, wherein:

[0188] the first power ramp mode causes the first voltage signal to ramp up before the second voltage signal ramps up; and

[0189] the second power ramp mode causes the second voltage signal to ramp up before the first voltage signal ramps up.

[0190] Example 13. An electronic device comprising:

[0191] a power supply;

[0192] a memory macro operably connected to the power supply and configured to receive a first voltage signal and a second voltage signal, the memory macro comprising power management circuitry operable to cause the first voltage signal and second voltage signal to ramp up and down according to at least one power ramp mode included in a plurality of power ramp modes; and

[0193] a level shifter device operably connected to the power management circuitry in the memory macro and to the power supply and configured to provide one or more signals to the power management circuitry supporting the plurality of power ramp modes.

[0194] Example 14. The electronic device of example 13, wherein the plurality of power ramp modes comprises a first power ramp mode and a second power ramp mode.

[0195] Example 15. The electronic device of example 14, wherein:

[0196] the first power ramp mode causes the first voltage signal to ramp up before the second voltage signal ramps up; and

[0197] the second power ramp mode causes the second voltage signal to ramp up before the first voltage signal ramps up.

[0198] Example 16. The electronic device of example 15, wherein the first voltage signal is a VDD voltage signal and the second voltage signal is a VDDM voltage signal.

[0199] Example 17. The electronic device of example 14, wherein the level shifter device is configured to support a bidirectional mode power ramping mode that incorporates the first power ramping mode and the second power ramping mode.

[0200] Example 18. The electronic device of example 13, wherein the memory macro comprises a static random access macro.

[0201] Example 19. The electronic device of example 13, wherein the level shifter device comprises a plurality of level shifter circuits that generate the power off signal and the one or more sleep signals.

[0202] Example 20. The electronic device of example 13, wherein the level shifter device is configured to generate at least one of the power off signal or the sleep signal.

[0203] For example, aspects of the disclosure are described above with reference to block and / or operational diagram illustrations of methods, systems, and computer program products according to aspects of the present disclosure. The functions / acts shown in the blocks can occur out of the order described in the flowcharts. For example, two blocks shown in succession can in fact be executed substantially concurrently or can sometimes be executed in the reverse order, depending upon the functionality / acts involved.

[0204] The foregoing is a summary of several features of the embodiments. Those skilled in the art will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or for achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize from consideration of the embodiments of the present disclosure that the embodiments can be readily combined, substituted, and / or modified without departing from the spirit and scope of the disclosure.

Claims

1. A device for power swashplate sequential control, comprising: A memory macro is configured to receive a first voltage signal and a second voltage signal, the memory macro including a power management circuitry system; as well as A level shifter device is configured to provide a third signal to the power management circuitry system, causing the power management circuitry system to control the power ramping sequence of the first voltage signal and the second voltage signal in the memory macro based on the third signal. in: When the third signal has a first logic state, the first voltage signal rises before the second voltage signal rises; and When the third signal has a second logic state, the second voltage signal rises before the first voltage signal rises.

2. The device according to claim 1, wherein, The memory macro includes a static random access macro, which includes a static random access memory array and a peripheral circuit system.

3. The device according to claim 2, wherein, The peripheral circuit system includes a pin circuit that is operatively connectable to a corresponding power management circuit in the power management circuit system.

4. The device according to claim 1, wherein, The first voltage signal is a VDD voltage signal, and the second voltage signal is a VDDM voltage signal.

5. The device according to claim 1, wherein, The level shifter device is configured to incorporate multiple power ramp modes simultaneously.

6. The device according to claim 1, wherein, The level shifter device is configured to generate a shutdown signal.

7. The device according to claim 1, wherein, The level shifter device is configured to generate a power-off signal and a sleep signal.

8. The device according to claim 1, wherein, The level shifter device is configured to float the first voltage signal in a bulk shutdown mode.

9. The device according to claim 1, wherein, The level shifter device includes four level shifter circuits, wherein one level shifter circuit outputs a power-off signal, and the other three level shifter circuits each output a sleep signal.

10. A method for power swashplate sequential control, comprising: A strobe signal is received at a level shifter device, which is operatively connected to a memory macro. The signal level of the strobe signal has a first logic state: The first power ramp mode among multiple power ramp modes is generated in the memory macro; and The second power ramp mode among the plurality of power ramp modes is generated in the memory macro after the first power ramp mode. in: The first power ramp mode causes the first voltage signal received by the memory macro to ramp up before the second voltage signal received by the memory macro ramps up; and The second power ramp mode causes the second voltage signal to ramp before the first voltage signal ramps up.

11. The method of claim 10, wherein: The first power ramping mode causes the second voltage signal to ramp down before the first voltage signal ramps down; and The second power ramping mode causes the first voltage signal to ramp down before the second voltage signal ramps down.

12. An electronic device, comprising: power supply; A memory macro, operatively connected to the power supply and configured to receive a first voltage signal and a second voltage signal, the memory macro including a power management circuitry system operable to ramp up and ramp down the first and second voltage signals according to at least one power ramping mode included in a plurality of power ramping modes. as well as A level shifter device, operatively connected to the power management circuitry in the memory macro and to the power supply, is configured to provide one or more signals to the power management circuitry supporting the multiple power ramp modes. The plurality of power ramping modes include a first power ramping mode and a second power ramping mode. in: The first power ramp mode causes the first voltage signal to ramp before the second voltage signal ramps; and The second power ramp mode causes the second voltage signal to ramp before the first voltage signal ramps up.

13. The electronic device according to claim 12, wherein, The first voltage signal is a VDD voltage signal, and the second voltage signal is a VDDM voltage signal.

14. The electronic device according to claim 12, wherein, The level shifter device is configured to support a bidirectional power ramp mode that combines the first power ramp mode and the second power ramp mode.

15. The electronic device according to claim 12, wherein, The memory macros include static random access macros.

16. The electronic device according to claim 12, wherein, The level shifter device includes multiple level shifter circuits that generate a power-off signal and one or more sleep signals.

17. The electronic device according to claim 12, wherein, The level shifter device is configured to generate at least one of a power-off signal or a sleep signal.

Images