Method for manufacturing three-dimensional semiconductor structure and three-dimensional semiconductor structure

Abstract

A method for manufacturing a three-dimensional semiconductor structure, comprising forming a first insulating layer on a liner, and providing at least one channel hole on the first insulating layer, each channel hole penetrating the first insulating layer and exposing the liner; sequentially stacking a first epitaxial layer and a second epitaxial layer in each channel hole, wherein the first epitaxial layer is an unevenly doped layer to form a source region or a drain region with a lower resistance; forming a second insulating layer and a sacrificial layer alternately stacked on the first insulating layer; and gradually generating a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked on the second epitaxial layer; the present invention also provides a three-dimensional semiconductor structure manufactured by the three-dimensional semiconductor structure manufacturing method.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a three-dimensional semiconductor structure and a three-dimensional semiconductor structure manufactured by using the manufacturing method. Background Art

[0002] In recent years, in order to meet customers' demand for high-performance and low-cost microelectronics, semiconductor devices need to be highly integrated. The integration of a typical two-dimensional or planar semiconductor structure is mainly determined by the area occupied by the unit memory cell, and the integration is affected by the technical level of forming fine patterns. However, extremely expensive process equipment is required to improve the fineness of the pattern, so the increase in cost limits the development of high integration of two-dimensional or planar semiconductor structures. Therefore, three-dimensional semiconductor structures came into being. Compared with two-dimensional semiconductor structures, three-dimensional semiconductor structures have better performance and integration.

[0003] A three-dimensional semiconductor structure generally includes a plurality of stacked layers arranged in a stacked manner, and the plurality of stacked layers may include a plurality of three-dimensional vertical transistors. In the existing three-dimensional semiconductor structure, a plurality of stacked layers are etched to form a channel hole, and a semiconductor material is formed in the channel hole to form the drain region and the source region of the three-dimensional vertical transistor. However, the channel hole formed by etching a plurality of stacked groups is relatively slender, and it is difficult to keep it upright and aligned, and it becomes skewed and offset, making the drain region, source region and gate region related structures of the transistor easily asymmetric or offset. Since the source region and the drain region of a general three-dimensional semiconductor structure have a high resistance value and are difficult to form by ion implantation, and when the three-dimensional semiconductor structure includes a plurality of stacked layers arranged in a stacked manner, the higher series resistance value of the source region and the drain region is likely to affect the operating current and response speed of the transistor. Summary of the invention

[0004] In view of this, it is necessary to provide a method for manufacturing a three-dimensional semiconductor structure, which comprises:

[0005] Providing a liner, depositing a first insulating layer on the liner, and opening at least one channel hole on the first insulating layer, each channel hole penetrating the first insulating layer and exposing the liner;

[0006] In each channel hole, a first epitaxial layer and a second epitaxial layer with uneven doping are sequentially stacked, wherein the first epitaxial layer is used to form a source region or a drain region;

[0007] Forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, and stacking another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer and exposing the another first epitaxial layer relative to the second insulating layer, and stacking another second epitaxial layer on the another first epitaxial layer;

[0008] Referring to the previous step, a plurality of sacrificial layers and a plurality of second insulating layers are alternately formed on the second insulating layer, and a plurality of first epitaxial layers and a plurality of second epitaxial layers are alternately generated on the further second epitaxial layer.

[0009] The present invention also provides a three-dimensional semiconductor structure, and the three-dimensional semiconductor structure is manufactured by the three-dimensional semiconductor structure manufacturing method.

[0010] Compared with the prior art, in the method for manufacturing the three-dimensional semiconductor structure, there is no need to open a channel hole passing through the first insulating layer and the multiple second insulating layers, and there is no need to form multiple first epitaxial layers and multiple second epitaxial layers in the channel hole; instead, only a channel hole passing through the first insulating layer is formed, and a first epitaxial layer and a second epitaxial layer stacked in the channel hole are formed, and subsequently another first epitaxial layer is directly grown on the second epitaxial layer and another second epitaxial layer is directly grown on the first epitaxial layer, so that the multiple first epitaxial layers and the multiple second epitaxial layers can be easily stacked and faced, and even with the increase in the number of layers of the second insulating layer, the multiple first epitaxial layers and the multiple second epitaxial layers formed by the method for manufacturing the three-dimensional semiconductor structure can maintain stacking and facing each other, so that the multiple first epitaxial layers and the multiple second epitaxial layers are upright and not skewed structures. In the three-dimensional semiconductor structure, the first epitaxial layer can be used as a source region or a drain region. The unevenly doped first epitaxial layer is beneficial to reducing the resistance value of the drain region or the drain region, and the three-dimensional semiconductor structure including multiple stacked layers can maintain a lower series resistance value of the source region and the drain region, which is beneficial to increase the operating current of the transistor and improve the response speed of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The figure is a flow chart of a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0012] Figure 2 It is a schematic diagram of forming a first insulating layer on a liner and opening a channel hole on the first insulating layer in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0013] Figure 3 It is a schematic diagram of forming a first epitaxial layer and a second epitaxial layer in a stacked arrangement in a channel hole in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0014] Figure 4A It is a schematic diagram of forming a sacrificial layer covering a second epitaxial layer on a first insulating layer in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0015] Figure 4BFIG. 4 is a schematic diagram of planarizing a sacrificial layer in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0016] Figure 4C It is a schematic diagram of growing another first epitaxial layer on the second epitaxial layer in the method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0017] Figure 4D It is a schematic diagram of forming a second insulating layer covering another first epitaxial layer on a sacrificial layer in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0018] Figure 4E It is a schematic diagram of planarizing the second insulating layer in the method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0019] Figure 4F It is a schematic diagram of forming another second epitaxial layer on another first epitaxial layer in the method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0020] Figure 5 It is a schematic diagram of forming a plurality of second insulating layers, a plurality of first epitaxial layers and a plurality of second epitaxial layers in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0021] Fig. 6A It is a schematic diagram of forming a gate hole and a gate channel in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0022] Figure 6B It is a schematic diagram of forming a dielectric layer in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0023] Figure 6C It is a schematic diagram of forming a gate in a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention.

[0024] Main component symbols

[0025]

[0026]

[0027] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0028] The accompanying drawings illustrate embodiments of the present invention, which may be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present invention more comprehensive and complete and to enable those skilled in the art to more fully understand the scope of the present invention. In the drawings, the dimensions of layers and regions are exaggerated for clarity.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention relates. It should also be understood that terms such as those defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and should not be interpreted in an overly idealized or overly formal sense, unless explicitly defined herein.

[0030] Reference Figure 1 The method for manufacturing a three-dimensional semiconductor structure provided by an embodiment of the present invention includes steps S1 to S4. Steps S1 to S4 are as follows:

[0031] Step S1: providing a liner, depositing a first insulating layer on the liner, and opening at least one channel hole on the first insulating layer, wherein each channel hole penetrates the first insulating layer and exposes the liner.

[0032] Step S2: sequentially stacking a first epitaxial layer and a second epitaxial layer with uneven doping in each channel hole, wherein the first epitaxial layer is used to form a source region or a drain region.

[0033] Step S3: forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, and stacking another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer and exposing the another first epitaxial layer relative to the second insulating layer, and stacking another second epitaxial layer on the another first epitaxial layer.

[0034] Step S4: Referring to the previous step, a plurality of sacrificial layers and a plurality of second insulating layers are alternately formed in sequence on the second insulating layer, and a plurality of first epitaxial layers and a plurality of second epitaxial layers are alternately generated in sequence on the further second epitaxial layer.

[0035] The following describes a method for manufacturing a three-dimensional semiconductor structure according to an embodiment of the present invention in conjunction with specific drawings.

[0036] Please refer to step S1 Figure 2 , a first insulating layer 11 is deposited on the liner 10 , and at least one channel hole 12 is opened on the first insulating layer 11 , each channel hole 12 penetrates the first insulating layer 11 and exposes the liner 10 .

[0037] In this embodiment, the first insulating layer 11 is patterned by a yellow light etching process to form at least one channel hole 12. The etching can be dry etching or wet etching. The liner 10 can be, but is not limited to, a single crystal silicon substrate, a single crystal germanium-based semi-conductor or a single crystal silicon germanium substrate. The first insulating layer 11 is an insulating material, which can be, but is not limited to, SiO2.

[0038] Please refer to step S2 Figure 3 , a first epitaxial layer 13 and a second epitaxial layer 14 are sequentially stacked in each channel hole 12. Specifically, a first epitaxial layer 13 is grown on the liner 10 exposed in the channel hole 12 by a selective epitaxial growth process, and the first epitaxial layer 13 is substantially flush with the first insulating layer 11. A second epitaxial layer 14 is then grown on the first epitaxial layer 13 by a selective epitaxial growth process, and the first epitaxial layer 13 and the second epitaxial layer 14 are stacked up and down and face each other, forming a vertical and non-skewed structure.

[0039] In this embodiment, the first epitaxial layer 13 and the second epitaxial layer 14 are both made of semiconductor materials, and the semiconductor material can be one or a combination of silicon, germanium, silicon-germanium and indium gallium zinc oxide. The first epitaxial layer 13 includes two lightly doped semiconductor layers and one heavily doped semiconductor layer to form an unevenly doped semiconductor material layer, and the heavily doped semiconductor layer is located in the middle of the two lightly doped semiconductor layers. The first epitaxial layer is used to form a source region or a drain region. The second epitaxial layer 14 is a lightly doped semiconductor layer, which is used to form a channel region under the gate region. The first epitaxial layer and the second epitaxial layer can be N-type semiconductor layers or P-type semiconductor layers, or the same type of semiconductor layers. In this embodiment, a second epitaxial layer 14 and two first epitaxial layers 13 arranged in contact on both sides of the second epitaxial layer 14 belong to the same transistor 19. Specifically, the gate region of the transistor 19 includes the second epitaxial layer 14, and the source region or the drain region of the transistor 19 includes one of the two first epitaxial layers 13. Since the first epitaxial layer 13 and the second epitaxial layer 14 are stacked up and facing each other, the source region and the drain region of the transistor 19 can also be stacked up and facing each other.

[0040] In one embodiment, the step of sequentially stacking a first epitaxial layer 13 and a second epitaxial layer 14 comprises: sequentially forming a first epitaxial layer 13 of a non-uniform N-type doped semiconductor material and a second epitaxial layer 14 of a P-type or N-type lightly doped semiconductor material. In this embodiment, the step of forming the first epitaxial layer 13 of a non-uniform N-type doped semiconductor material comprises: sequentially forming a first doped layer 131 of a N-type lightly doped semiconductor material, a second doped layer 132 of a N-type heavily doped semiconductor material, and a third doped layer 133 of a N-type lightly doped semiconductor material, as stacked. Figure 3 As shown. In a modified embodiment, the step of forming the first epitaxial layer 13 of the semiconductor material of uneven N-type doping includes: sequentially forming a first doping layer 131 of a P-type lightly doped semiconductor material, a second doping layer 132 of an N-type heavily doped semiconductor material, and a third doping layer 133 of a P-type lightly doped semiconductor material, wherein the N-type dopant of the second doping layer 132 diffuses into the first doping layer 131 and the third doping layer 133 to form the first epitaxial layer 13 of the semiconductor material of uneven N-type doping. In the above embodiment, the first doping layer 131, the third doping layer 133, and the second epitaxial layer 14 are lightly doped and the semiconductor dopant may be, but not limited to, phosphorus, boron, or indium, and the second doping layer 132 is heavily doped and the semiconductor dopant may be, but not limited to, phosphorus, nitrogen, or arsenic. In the above embodiment, a second epitaxial layer 14 and two first epitaxial layers 13 disposed on both sides of the second epitaxial layer 14 in contact with each other belong to the same N-type transistor 191. When the non-uniform N-doped semiconductor material first epitaxial layer 13 formed by this method constitutes the source region or the drain region of the N-type transistor 191 , the resistance of the source region or the drain region of the N-type transistor 191 can be reduced.

[0041] In another embodiment, the step of sequentially stacking a first epitaxial layer 13 and a second epitaxial layer 14 comprises: sequentially forming a first epitaxial layer 13 of an unevenly P-type doped semiconductor material and a second epitaxial layer 14 of an N-type or P-type lightly doped semiconductor material. In this embodiment, the step of forming the first epitaxial layer 13 of an unevenly P-type doped semiconductor material comprises: sequentially forming a first doped layer 131 of a P-type lightly doped semiconductor material, a second doped layer 132 of a P-type heavily doped semiconductor material, and a third doped layer 133 of a P-type lightly doped semiconductor material, as shown in FIG. Figure 3As shown. In a modified embodiment, the step of forming the first epitaxial layer 13 of the semiconductor material of non-uniform P-type doping includes: sequentially forming a first doping layer 131 of N-type lightly doped semiconductor material, a second doping layer 132 of P-type heavily doped semiconductor material, and a third doping layer 133 of N-type lightly doped semiconductor material, wherein the P-type dopant of the second doping layer 132 diffuses into the first doping layer 131 and the third doping layer 133 to form the first epitaxial layer 13 of P-type doped semiconductor material. In the above embodiment, the first doping layer 131, the third doping layer 133, and the second epitaxial layer 14 are lightly doped and the semiconductor dopant may be, but not limited to, phosphorus, nitrogen, or arsenic, and the second doping layer 132 is heavily doped and the semiconductor dopant may be, but not limited to, phosphorus, boron, or indium. In the above embodiment, a second epitaxial layer 14 and two first epitaxial layers 13 contacting and arranged on both sides of the second epitaxial layer 14 belong to the same P-type transistor 192. When the first epitaxial layer 13 of semiconductor material with uneven P-type doping is formed by this method to constitute the source region or the drain region of the P-type transistor 192 , the resistance of the source region or the drain region of the P-type transistor 192 can be reduced.

[0042] Please refer to step S3 Figures 4A to 4F .

[0043] like Figure 4A and Figure 4B As shown, the step of forming a sacrificial layer 15 on the first insulating layer 11 includes: depositing the sacrificial layer 15 covering the second epitaxial layer 14 on the first insulating layer 11 ; and planarizing the sacrificial layer 15 so that the second epitaxial layer is exposed relative to the sacrificial layer 15 .

[0044] like Figure 4C As shown, another first epitaxial layer 13 is stacked on the second epitaxial layer 14. In this embodiment, the first epitaxial layer 13 is grown on the second epitaxial layer 14 exposed relative to the sacrificial layer 15 by a selective epitaxial growth process, and the second epitaxial layer 14 and the first epitaxial layer 13 are stacked up and down and face each other.

[0045] like Figure 4D and Figure 4E As shown, the step of forming a second insulating layer 16 on a sacrificial layer 15 includes: depositing the second insulating layer 16 covering the further first epitaxial layer 13 on the sacrificial layer 15 and planarizing the second insulating layer 16 so that the first epitaxial layer 13 is exposed relative to the second insulating layer 16.

[0046] like Figure 4FAs shown, a second epitaxial layer is generated on the first epitaxial layer 13 by a selective epitaxial growth process, and the stacking generates a second epitaxial layer. The first epitaxial layer 13 and the second epitaxial layer 14 are stacked up and down and face each other, and both are stacked up and down and face each other with the first epitaxial layer 13 and the second epitaxial layer 14 formed in step S1.

[0047] In this embodiment, chemical mechanical polishing (CMP) is used to planarize the second insulating layer 16 and the sacrificial layer 15. In one embodiment, if the second insulating layer 16 and the sacrificial layer 15 are formed by an area selective deposition (ASD) process, the CMP planarization step can be omitted.

[0048] Please refer to step S4 Figure 5 . After completing steps S1 and S2 and looping step S3, another sacrificial layer 15 is deposited on the second insulating layer 16 formed by step S3, the another sacrificial layer 15 is planarized so that the another second epitaxial layer 14 formed by step S3 is exposed relative to the another sacrificial layer 15, and another first epitaxial layer 13 is grown on the another second epitaxial layer 14 by a selective epitaxial growth process, and the another first epitaxial layer 13 and the another second epitaxial layer 14 are stacked up and down and face each other. In this way, the first insulating layer 11 located on the liner 10, the multiple second insulating layers 16 and the multiple sacrificial layers 15 that are alternately stacked, and the multiple first epitaxial layers 13 and the multiple second epitaxial layers 14 that are alternately stacked are formed; the multiple first epitaxial layers 13 and the second epitaxial layers 14 penetrate the first insulating layer 11, the multiple second insulating layers 16, and the multiple sacrificial layers 15.

[0049] In one embodiment, the plurality of first epitaxial layers 13 and the plurality of second epitaxial layers 14 located at different layers and stacked may form a plurality of stacked P-type transistors 192 and / or a plurality of stacked N-type transistors 191. Specifically, the plurality of N-type transistors 191 form a first stacked region, and the plurality of P-type transistors 192 form a second stacked region, and the first stacked region and the second stacked region are separated by an insulating layer.

[0050] The method for manufacturing a three-dimensional semiconductor structure according to the embodiment of the present invention further includes: after completing step S4, opening a gate hole 17 in the plurality of second insulating layers 16 and the plurality of sacrificial layers 15, wherein the gate hole 17 penetrates the plurality of second insulating layers 16 and the plurality of sacrificial layers 15 and exposes the first insulating layer 11; then removing all the plurality of sacrificial layers 15, and filling the position of the gate hole 17 and the plurality of sacrificial layers 15 after removal with a conductive material to form a gate 21. Please refer to this step. FIG. 6A to FIG. 6C .

[0051] like Fig. 6A As shown, the multiple second insulating layers 16 and the multiple sacrificial layers 15 alternately stacked are patterned by yellow light etching method to form the gate hole 17. The multiple sacrificial layers 15 are removed by etching method through the gate hole 17 to form the gate channel 18. In this embodiment, under the same etching conditions, the etching rate of each sacrificial layer 15 is higher than the etching rate of the first insulating layer 11 and each second insulating layer 16, that is, the etching selectivity ratio of each sacrificial layer 15 to the first insulating layer 11 is greater than 1, that is, the etching selectivity ratio of each sacrificial layer 15 to each second insulating layer 16 is greater than 1, so that the first insulating layer 11 and each second insulating layer 16 can be retained when the multiple sacrificial layers 15 are removed. Each second insulating layer 16 and the first insulating layer 11 are both insulating materials, and each sacrificial layer 15 is an insulating material or a non-insulating material. In one embodiment, the first insulating layer 11 and each second insulating layer 16 are SiO2, and each sacrificial layer 15 is silicon nitride SiN.

[0052] like Figure 6B As shown, after removing the multiple sacrificial layers 15 and before forming the gate 21, the method for manufacturing the three-dimensional semiconductor also includes: forming a gate channel 18 by removing the multiple sacrificial layers 15, conformally forming a thin dielectric layer 20 on the side walls 181 where the first insulating layer 11 and the multiple second insulating layers 16 are respectively in contact with the gate channel 18, and forming a dielectric layer 20 on the side walls 171 where the first insulating layer 11 and the multiple second insulating layers 16 are respectively in contact with the gate hole 17.

[0053] like Figure 6C As shown, after forming the dielectric layer 20, a conductive material is filled in the gate channel 18 and the gate hole 17 to form a gate 21. In this embodiment, the dielectric layer 20 is an insulating material, which may be, but not limited to, SiO2 or SiN. The conductive material forming the gate 21 may be, but not limited to, at least one of a doped semiconductor (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal or a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0054] In this embodiment, the dielectric layer 20, the first insulating layer 11, each second insulating layer 16 and each sacrificial layer 15 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric material (SOD) or any combination thereof.

[0055] In one embodiment, the second insulating layer 16 is formed last.

[0056] In summary, in the method for manufacturing the three-dimensional semiconductor structure, it is not necessary to open a channel hole penetrating the first insulating layer 11 and the plurality of second insulating layers 16, and it is not necessary to form a plurality of first epitaxial layers 13 and a plurality of second epitaxial layers 14 in the channel hole. Instead, only a channel hole 12 penetrating the first insulating layer 11 is formed, and a first epitaxial layer 13 and a second epitaxial layer 14 are stacked in the channel hole 12. Subsequently, another first epitaxial layer 13 is directly grown on the second epitaxial layer 14, and another second epitaxial layer 14 is directly grown on the first epitaxial layer 13. It is easy to realize that the plurality of first epitaxial layers 13 and the plurality of second epitaxial layers 14 are stacked and aligned vertically, that is, a structure that is upright and not skewed is formed. Then, even with the increase in the number of layers of the second insulating layer 16, the plurality of first epitaxial layers 13 and the plurality of second epitaxial layers 14 formed by the method for manufacturing the three-dimensional semiconductor structure can maintain the stacking alignment, so that the plurality of first epitaxial layers 13 and the plurality of second epitaxial layers 14 are upright and not skewed structures. In the three-dimensional semiconductor structure, the first epitaxial layer 13 can be used as a source region or a drain region. The non-uniformly doped first epitaxial layer 13 formed by a selective growth process is conducive to reducing the resistance value of the drain region or the drain region, and the three-dimensional semiconductor structure including multiple stacked layers can maintain a lower series resistance value of the source region and the drain region, thereby facilitating increasing the working current of the transistor and improving the response speed of the transistor. In this embodiment, since the multiple first epitaxial layers 13 and the multiple second epitaxial layers 14 of semiconductor material are formed by a selective epitaxial growth process, the multiple first epitaxial layers 13 and the multiple second epitaxial layers 14 stacked are not restricted by the channel hole 12, and the channel hole 12 can be reduced to a certain extent.

[0057] The embodiment of the present invention also provides a three-dimensional semiconductor structure 100, which is manufactured by the above-mentioned three-dimensional semiconductor structure manufacturing method. The three-dimensional semiconductor structure 100 can be a memory, including a dynamic random access memory and a static random access memory. The three-dimensional semiconductor structure 100 can also be a complementary metal oxide semiconductor.

[0058] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a three-dimensional semiconductor structure, characterized in that: include: Providing a liner, depositing a first insulating layer on the liner, and opening at least one channel hole on the first insulating layer, each channel hole penetrating the first insulating layer and exposing the liner; In each channel hole, a first epitaxial layer and a second epitaxial layer with uneven doping are sequentially stacked, wherein the first epitaxial layer is used to form a source region or a drain region; Forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, and stacking another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer and exposing the another first epitaxial layer relative to the second insulating layer, and stacking another second epitaxial layer on the another first epitaxial layer; as well as Referring to the previous step, a plurality of sacrificial layers and a plurality of second insulating layers are alternately formed on the second insulating layer, and a plurality of first epitaxial layers and a plurality of second epitaxial layers are alternately generated on the further second epitaxial layer.

2. The method for manufacturing a three-dimensional semiconductor structure according to claim 1, wherein: The step of sequentially stacking a first epitaxial layer and a second epitaxial layer includes: forming the first epitaxial layer of an uneven N-type doped semiconductor material and forming the second epitaxial layer of a P-type or N-type lightly doped semiconductor material.

3. The method for manufacturing a three-dimensional semiconductor structure according to claim 2, wherein: The step of forming the first epitaxial layer of the non-uniform N-type doped semiconductor material includes: sequentially forming a first doped layer of a P-type lightly doped semiconductor material, a second doped layer of an N-type heavily doped semiconductor material, and a third doped layer of a P-type lightly doped semiconductor material that are stacked, and the N-type dopant of the second doped layer diffuses into the first doped layer and the third doped layer to form the first epitaxial layer of the N-type lightly doped semiconductor material; or, the step of forming the first epitaxial layer of the non-uniform N-type doped semiconductor material includes: sequentially forming a first doped layer of a N-type lightly doped semiconductor material, a second doped layer of an N-type heavily doped semiconductor material, and a third doped layer of an N-type lightly doped semiconductor material that are stacked.

4. The method for manufacturing a three-dimensional semiconductor structure according to claim 1, wherein: The step of sequentially stacking a first epitaxial layer and a second epitaxial layer includes: forming the first epitaxial layer of an uneven P-type doped semiconductor material and forming the second epitaxial layer of an N-type or P-type lightly doped semiconductor material.

5. The method for manufacturing a three-dimensional semiconductor structure according to claim 4, characterized in that: The step of forming the first epitaxial layer of the semiconductor material of uneven P-type doping includes: sequentially forming a first doped layer of the semiconductor material of N-type lightly doped, a second doped layer of the semiconductor material of P-type heavily doped, and a third doped layer of the semiconductor material of N-type lightly doped, and the P-type dopant of the second doped layer diffuses into the first doped layer and the third doped layer to form the first epitaxial layer of the semiconductor material of N-type lightly doped; or, the step of forming the first epitaxial layer of the semiconductor material of uneven P-type doping includes: sequentially forming a first doped layer of the semiconductor material of P-type lightly doped, a second doped layer of the semiconductor material of P-type heavily doped, and a third doped layer of the semiconductor material of P-type lightly doped.

6. The method for manufacturing a three-dimensional semiconductor structure according to claim 1, wherein: The step of forming a sacrificial layer on the first insulating layer includes: depositing the sacrificial layer on the first insulating layer, and flattening the sacrificial layer to expose the second epitaxial layer relative to the sacrificial layer; the step of forming a sacrificial layer on a second insulating layer includes: depositing the sacrificial layer on the first insulating layer, and flattening the sacrificial layer to expose the second epitaxial layer relative to the sacrificial layer; the step of forming the second insulating layer on the sacrificial layer includes: depositing the second insulating layer on the sacrificial layer, and flattening the second insulating layer to expose the first epitaxial layer relative to the second insulating layer.

7. The method for manufacturing a three-dimensional semiconductor structure according to claim 1, wherein: The method for manufacturing the three-dimensional semiconductor structure also includes: opening a gate hole in the multiple second insulating layers and the multiple sacrificial layers, the gate hole penetrating the multiple second insulating layers and the multiple sacrificial layers and exposing the first insulating layer; then removing all the multiple sacrificial layers, and filling the gate hole and the position after all the multiple sacrificial layers are removed with conductive material to form a gate.

8. The method for manufacturing a three-dimensional semiconductor structure according to claim 7, wherein: After removing the multiple sacrificial layers and before forming the gate, the method for manufacturing the three-dimensional semiconductor also includes: forming a gate channel by removing the multiple sacrificial layers, forming a dielectric layer on the side walls where the first insulating layer and the multiple second insulating layers are respectively in contact with the gate channel, and forming a dielectric layer on the side walls where the first insulating layer and the multiple second insulating layers are respectively in contact with the gate hole.

9. The method for manufacturing a three-dimensional semiconductor structure according to claim 8, wherein: Each of the first epitaxial layers and each of the second epitaxial layers are formed by a selective epitaxial growth process; under the same etching conditions, the etching rate of each sacrificial layer is higher than the etching rate of the first insulating layer and each of the second insulating layers.

10. A three-dimensional semiconductor structure, characterized in that: The three-dimensional semiconductor structure is manufactured by the method for manufacturing a three-dimensional semiconductor structure according to any one of claims 1 to 9.

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