Three-dimensional memory and its manufacturing method

Abstract

This disclosure provides a three-dimensional memory and a method for manufacturing the same. The method includes: sequentially forming a first semiconductor layer and a stacked structure on a substrate; forming a first via through the stacked structure and the first semiconductor layer, with its bottom remaining within the substrate; performing a first oxidation process on the first semiconductor layer exposed by the sidewalls of the first via to form a first oxide layer; wherein, along the radial direction of the first via, the first oxide layer protrudes toward the axis of the first via; filling the first via with the first oxide layer to form a functional layer; filling the first via with the functional layer to form a channel layer; wherein the channel layer and the first oxide layer are separated by the functional layer, and the bottom of the channel layer is located above the first semiconductor layer; and removing the substrate, the first oxide layer, and a portion of the functional layer to expose the bottom of the channel layer.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and more particularly to a three-dimensional memory and a method for manufacturing the same. Background Technology

[0002] With the continuous improvement of semiconductor manufacturing processes, feature sizes are becoming smaller and smaller, leading to higher storage densities in memory devices. To meet the demand for even higher storage densities, three-dimensional memory devices have been developed. 3D NAND flash memory has gained widespread application due to its advantages such as fast write speed, simple erase operation, and higher storage density.

[0003] In related technologies, multiple vias or trenches are formed through a stacked structure by etching, and these vias or trenches are then filled to form the relevant functional structure. However, with the increase in memory integration and bit density, the number of layers in the stacked structure continues to increase, making the etching process more difficult to control. Multiple vias or trenches extend into the substrate structure supporting the stacked structure, forming multiple grooves of varying depths within the substrate, resulting in poor uniformity of the vias or trenches, and consequently, poor uniformity of the relevant functional structure. Therefore, how to control the depth of the multiple vias or trenches to improve their uniformity, and thus improve the uniformity of the relevant functional structure, has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a three-dimensional memory and a method for manufacturing the same.

[0005] According to a first aspect of the present disclosure, a method for manufacturing a three-dimensional memory is provided, comprising:

[0006] A first semiconductor layer and a stacked structure are sequentially formed on a substrate;

[0007] A first through-hole is formed, penetrating the stacked structure and the first semiconductor layer, with its bottom remaining within the substrate;

[0008] A first oxidation process is performed on the first semiconductor layer exposed on the sidewall of the first via to form a first oxide layer; wherein, along the radial direction of the first via, the first oxide layer protrudes toward the axis of the first via;

[0009] The first through-hole on which the first oxide layer is formed is filled to form a functional layer;

[0010] A first via on which the functional layer is formed is filled to form a channel layer; wherein the channel layer and the first oxide layer are separated by the functional layer, and the bottom of the channel layer is located above the first semiconductor layer;

[0011] Remove the substrate, the first oxide layer, and a portion of the functional layer to expose the bottom of the trench layer.

[0012] According to a second aspect of the present disclosure, a three-dimensional memory is provided, comprising:

[0013] First semiconductor layer;

[0014] A stacked structure is located above the first semiconductor layer;

[0015] At least two memory structures extend through the stacked structure and are electrically connected to the first semiconductor layer; wherein each memory structure includes a channel layer, and the bottom of the channel layer of each memory structure is substantially flush with the bottom.

[0016] In this embodiment of the present disclosure, a first oxide layer is formed by performing a first oxidation treatment on the first semiconductor layer exposed on the sidewall of the first through hole. Since the first oxide layer protrudes toward the axis of the first through hole, the first through hole at the location penetrating the first semiconductor layer can be partially or completely sealed.

[0017] In this embodiment of the present disclosure, even if the first via extends into the substrate and forms grooves of varying depths in the substrate, since the first via at the location penetrating the first semiconductor layer is partially or completely sealed, and the channel layer and the first oxide layer are separated by a functional layer, the bottom of the channel layer is located above the first semiconductor layer, that is, the channel layer will not extend into the grooves in the substrate.

[0018] When the bottom of the channel layer is exposed by removing the substrate, the first oxide layer, and part of the functional layer, only the functional layer and the channel layer above the first semiconductor layer can be retained. The vias actually used for filling (i.e., the vias that ultimately retain the functional layer and the channel layer) are located above the first semiconductor layer. The grooves formed in the substrate will not affect the vias actually used for filling. In this way, the depth of the vias actually used for filling can be controlled to ensure the uniformity of the depth of the vias actually used for filling, thereby improving the uniformity of the height of the functional structure formed in the vias, which is beneficial to improving the operating performance of the three-dimensional memory. Attached Figure Description

[0019] Figure 1a and Figure 1b This is a schematic diagram illustrating a method for manufacturing a three-dimensional memory according to an exemplary embodiment;

[0020] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0021] Figures 3 to 13 This is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;

[0022] Figures 14 to 30 This is a schematic diagram of another method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;

[0023] Figure 31 This is a schematic diagram of the structure of a three-dimensional memory according to an embodiment of the present disclosure;

[0024] Figure 32 This is a schematic diagram of another three-dimensional memory structure according to an embodiment of the present disclosure. Detailed Implementation

[0025] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0026] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0027] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0028] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0029] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0030] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0031] Figure 1a This is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment. (Refer to...) Figure 1a As shown, the fabrication of a three-dimensional memory includes at least the following steps:

[0032] Step 1: Form a stacked structure on the substrate structure; wherein the stacked structure includes an insulating layer and a sacrificial layer that are stacked alternately.

[0033] For example, refer to Figure 1a As shown, the substrate structure includes a substrate 10 and a semiconductor layer 11. In some embodiments, the substrate structure may further include a dielectric layer located between the substrate 10 and the semiconductor layer 11. The stacked structure includes an insulating layer 12 and a sacrificial layer 13 that are alternately stacked.

[0034] Step 2: Form through holes or trenches that penetrate the stacked structure.

[0035] For example, refer to Figure 1a As shown, a through-hole 14 is formed through the stacked structure using dry and / or wet etching processes. The through-hole 14 can extend toward the substrate structure. In a specific example, etching can continue downwards based on the through-hole 14, so that the through-hole 14 extends to the substrate 10 and forms a gouging in the substrate 10. This through-hole extending to the substrate can serve as a channel hole (CH) for a three-dimensional memory.

[0036] Step 3: Form a functional structure that fills the through holes or trenches.

[0037] For example, relevant functional structures can be formed in vias or trenches by filling them with dielectric and / or insulating and / or semiconductor and / or conductive materials.

[0038] For example, vias may include channel vias, and by filling the channel vias with a composite film layer of oxide-nitride-oxide-polysilicon, a storage structure can be formed in the channel vias to enable the reading or writing of information.

[0039] For example, through-holes may also include virtual channel holes, in which a support structure can be formed to provide good support by filling the virtual channel holes with dielectric and / or insulating materials.

[0040] For example, through holes may also include contact through holes, in which a contact structure can be formed by sequentially filling insulating material and conductive material into the contact through hole, for leading out peripheral circuits.

[0041] For example, the trench may include a gate gap, and a gate gap structure can be formed in the gate gap by sequentially filling the gate gap with spacer material and conductive material, so as to be used as a common source of the three-dimensional memory.

[0042] The above are merely examples to convey this disclosure to those skilled in the art. However, this disclosure is not limited thereto and may also include other through holes or trenches that penetrate the stacked structure, and further include other functional structures formed by filling through holes or trenches.

[0043] As memory integration and bit density increase, the number of stacked layers continues to rise, making etching process control more challenging, particularly controlling the channel profile (CH profile). Low-temperature etching processes offer significant advantages in controlling the CH profile.

[0044] However, low-temperature etching processes have limited selectivity in etching the constituent materials of the stacked structure (e.g., silicon nitride and silicon oxide) and the constituent materials of the substrate structure (e.g., polysilicon). Specifically, the etching rate of the low-temperature etching process for the stacked structure is very close to that for the substrate structure, resulting in deeper gouging in the substrate structure (e.g., the substrate) and poor uniformity of the channel depth (e.g., ...). Figure 1b As shown in the figure, this leads to poor uniformity in the height of related functional structures (e.g., storage structures, support structures, contact structures, or gate gap structures).

[0045] Furthermore, poor uniformity in the depth of the grooves formed in the substrate structure will have an extremely negative impact on the 3D memory. Specifically, the grooves formed in the substrate structure will affect the subsequent processing, leading to a decrease in the operational performance of the 3D memory.

[0046] In view of this, embodiments of the present disclosure provide a three-dimensional memory and a method for manufacturing the same.

[0047] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of this disclosure. (Refer to...) Figure 2 As shown, the method includes the following steps:

[0048] S100: A first semiconductor layer and a stacked structure are sequentially formed on a substrate;

[0049] S200: A first via is formed that penetrates the stacked structure, the first semiconductor layer, and has its bottom end within the substrate;

[0050] S300: A first oxidation process is performed on the first semiconductor layer exposed on the sidewall of the first via to form a first oxide layer; wherein, along the radial direction of the first via, the first oxide layer protrudes toward the axis of the first via;

[0051] S400: Fill the first through-hole where the first oxide layer has been formed to form a functional layer;

[0052] S500: Fill the first via with the functional layer to form a channel layer; wherein the channel layer and the first oxide layer are separated by the functional layer, and the bottom of the channel layer is located above the first semiconductor layer;

[0053] S600: Remove the substrate, the first oxide layer, and part of the functional layer to expose the bottom of the trench layer.

[0054] In this embodiment of the present disclosure, a first oxide layer is formed by performing a first oxidation treatment on the first semiconductor layer exposed on the sidewall of the first through hole. Since the first oxide layer protrudes toward the axis of the first through hole, the first through hole at the location penetrating the first semiconductor layer can be partially or completely sealed.

[0055] In this embodiment of the present disclosure, even if the first via extends into the substrate and forms grooves of varying depths in the substrate, since the first via at the location penetrating the first semiconductor layer is partially or completely sealed, and the channel layer and the first oxide layer are separated by a functional layer, the bottom of the channel layer is located above the first semiconductor layer, that is, the channel layer will not extend into the grooves in the substrate.

[0056] When the bottom of the channel layer is exposed by removing the substrate, the first oxide layer, and part of the functional layer, only the functional layer and the channel layer above the first semiconductor layer can be retained. The vias actually used for filling (i.e., the vias that ultimately retain the functional layer and the channel layer) are located above the first semiconductor layer. The grooves formed in the substrate will not affect the vias actually used for filling. In this way, the depth of the vias actually used for filling can be controlled to ensure the uniformity of the depth of the vias actually used for filling, thereby improving the uniformity of the height of the functional structure formed in the vias, which is beneficial to improving the operating performance of the three-dimensional memory.

[0057] Figures 3 to 13 This is a schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of this disclosure. The following will be combined with... Figure 2 , Figures 3 to 13 This disclosure will be further explained in more detail.

[0058] First, combined Figure 3 and Figure 4 As shown, step S100 is performed: a first semiconductor layer 103 and a stacked structure 106 are sequentially formed on the substrate 101.

[0059] The substrate 101 is composed of elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this embodiment, the substrate 101 is a silicon substrate.

[0060] The first semiconductor layer 103 is composed of materials such as polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon. In this embodiment, the first semiconductor layer 103 is a doped polycrystalline silicon layer.

[0061] The stacked structure 106 includes an insulating layer 107 and a sacrificial layer 108 that are alternately stacked. The insulating layer 107 is composed of materials such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the insulating layer 107 may be a silicon oxide layer. The sacrificial layer 108 is composed of materials such as silicon nitride or silicon oxynitride. In this embodiment, the sacrificial layer 108 may be a silicon nitride layer.

[0062] It should be noted that in the back-gate process, the sacrificial layer is used to replace the conductive layer. In the front-gate process, the stacked structure may also include alternately stacked insulating and conductive layers. The conductive layer serves as the word line of the three-dimensional memory, and read, write, and erase operations of the memory are achieved by applying different control voltages to the conductive layer. The number of sacrificial or conductive layers in the stacked structure includes 8, 16, 32, 64, 96, 128, or 256 layers, etc., and this disclosure does not impose any limitation.

[0063] In some embodiments, the first semiconductor layer 103 includes: a first doped semiconductor layer; S100 includes:

[0064] A first semiconductor material layer is formed on the substrate;

[0065] A doping process is performed on the first semiconductor material layer to form a first doped semiconductor layer.

[0066] For example, a thin film deposition process can be used to form a first semiconductor material layer on a substrate. Thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0067] For example, the first semiconductor material layer can be doped using an ion implantation process or an ion diffusion process to increase the oxidation rate of the first semiconductor layer. It is understood that, under the same oxidation atmosphere or conditions, the oxidation rate of the first doped semiconductor layer is greater than the oxidation rate of the first semiconductor material layer.

[0068] The first semiconductor material layer is composed of polycrystalline silicon or amorphous silicon, and the first doped semiconductor layer is composed of doped polycrystalline silicon or doped amorphous silicon. In this embodiment, the first semiconductor material layer is a polycrystalline silicon layer, and the first doped semiconductor layer is a doped polycrystalline silicon layer.

[0069] In some embodiments, the doping process performed on the first semiconductor material layer includes: partial doping of the first semiconductor material layer, or complete doping of the first semiconductor material layer. It should be understood that when the first semiconductor material layer is partially doped, the first semiconductor layer includes a first intrinsic semiconductor layer and a first doped semiconductor layer; when the first semiconductor material layer is completely doped, the fully doped first semiconductor layer is the first doped semiconductor layer. The choice can be made according to actual needs, and this disclosure does not impose any limitations.

[0070] In some embodiments, the oxidation rate of the first doped semiconductor layer is controlled by controlling parameters of the ion implantation process, such as the concentration of doped particles, the ion implantation time, and the ion implantation energy. These parameters control the concentration of doped particles, and / or the number of doped particles, and / or the position of the doped particles. The doped particles in the first doped semiconductor layer include boron ions, phosphorus ions, or arsenic ions.

[0071] In some embodiments, S100 includes:

[0072] A first semiconductor material layer is formed on the substrate;

[0073] Annealing is performed on the first semiconductor material layer to form the first semiconductor layer.

[0074] For example, a high-temperature annealing process can be used to anneal the first semiconductor material layer. Specifically, ammonia (NH3) or hydrogen (H2) can be used to anneal the first semiconductor material layer.

[0075] The first semiconductor material layer is composed of materials such as polycrystalline silicon or amorphous silicon. In this embodiment, the first semiconductor material layer is a polycrystalline silicon layer.

[0076] It should be noted that due to uneven stress distribution, the first semiconductor material layer may warp, affecting the flatness of the surface of the first semiconductor material layer and the deposition of subsequent film layers. Annealing can reduce the warping of the first semiconductor layer and reduce its impact on the deposition of subsequent film layers.

[0077] In some embodiments, the first semiconductor material layer may be doped first, followed by annealing to form a first semiconductor layer including the first doped semiconductor layer. This reduces the overall warpage of the first semiconductor layer, while annealing further promotes the diffusion of dopants, increasing the oxidation rate of the first semiconductor layer and facilitating subsequent oxidation processes.

[0078] In some embodiments, refer to Figure 3 As shown, step S100 further includes:

[0079] A first protective layer 102 is formed on a substrate 101; wherein, the first protective layer 102 is located between the substrate 101 and the first semiconductor layer 103, and the first protective layer 102 is used to protect the surface of the substrate 101;

[0080] A second protective layer 104 is formed on the first semiconductor layer 103; wherein the second protective layer 104 is located between the first semiconductor layer 103 and the second semiconductor layer 105, and the second protective layer 104 is used to protect the surface of the first semiconductor layer 103.

[0081] The first protective layer 102 and the second protective layer 104 are composed of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The materials of the first protective layer 102 and the second protective layer 104 can be the same or different. In this embodiment, both the first protective layer 102 and the second protective layer 104 can be silicon oxide layers.

[0082] In some embodiments, the above method further includes:

[0083] A second semiconductor layer is formed, wherein the second semiconductor layer is located between the first semiconductor layer and the stacked structure.

[0084] For example, combined Figure 3 and Figure 4 As shown, a thin-film deposition process can be used to form a second semiconductor layer 105 on the second protective layer 104, and a stacked structure 106 can be formed on the second semiconductor layer 105. The thin-film deposition process includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0085] In some embodiments, the method further includes: performing a pretreatment on the second semiconductor layer before forming the first via; wherein the pretreatment is used to reduce the oxidation rate of the second semiconductor layer.

[0086] It is understandable that, under the same oxidizing atmosphere or oxidizing conditions, the oxidation rate of the pretreated second semiconductor layer is less than that of the untreated second semiconductor layer.

[0087] In this embodiment of the disclosure, the oxidation rate of the second semiconductor layer is reduced by pretreatment. During subsequent oxidation processing, the probability of the upper and / or lower surfaces of the second semiconductor layer being oxidized can be reduced. This ensures that the thickness change of the second semiconductor layer is small. In subsequent fabrication processes, this helps to reduce the probability that the second semiconductor layer, as an etch barrier layer, will be etched through, thereby reducing damage to other film layers (e.g., the insulating layer 107 at the bottom of the stacked structure 106).

[0088] Furthermore, by reducing the oxidation rate of the second semiconductor layer through pretreatment, the difference between the oxidation rates of the first and second semiconductor layers can be increased, so that the oxidation rate of the first semiconductor layer is greater than that of the second semiconductor layer, which is beneficial to the execution of subsequent oxidation processes.

[0089] In some embodiments, the second semiconductor layer includes: a second doped semiconductor layer;

[0090] The formation of the second semiconductor layer includes:

[0091] Forming a second semiconductor material layer;

[0092] The above-mentioned preprocessing of the second semiconductor layer includes:

[0093] An in-situ doping process is performed on the second semiconductor material layer to form a second doped semiconductor layer.

[0094] For example, a gas containing dopant particles can be introduced during the deposition of the second semiconductor material layer. This allows for in-situ doping during the growth of the second semiconductor material layer, improving its stability and reducing its oxidation rate. It is understood that, under the same oxidizing atmosphere or conditions, the oxidation rate of the second doped semiconductor layer is lower than that of the second semiconductor material layer.

[0095] The second semiconductor material layer comprises polycrystalline silicon or amorphous silicon, and the second doped semiconductor layer comprises in-situ doped polycrystalline silicon or in-situ doped amorphous silicon. In this embodiment, the second semiconductor material layer is a polycrystalline silicon layer, and the second doped semiconductor layer is an in-situ doped polycrystalline silicon layer.

[0096] In some embodiments, the concentration of dopant particles in the second doped semiconductor layer is controlled by controlling the time of introduction of the gas including dopant particles and the reaction parameters of the deposition apparatus (e.g., temperature, pressure, etc.), thereby controlling the oxidation rate of the second doped semiconductor layer. The dopant particles in the second doped semiconductor layer include nitrogen particles. The doping gas may include a nitrogen-containing gas, such as nitrogen gas.

[0097] In this embodiment, by performing in-situ doping on the second semiconductor material layer, a second doped semiconductor layer with an oxidation rate lower than that of the second semiconductor material layer can be formed. Furthermore, the in-situ doping process can be completed within the deposition chamber of the second semiconductor material layer, making it compatible with the thin film deposition process of the second semiconductor material layer without requiring additional steps.

[0098] In some embodiments, the second semiconductor layer further includes: a second intrinsic semiconductor layer;

[0099] The formation of the second semiconductor layer further includes:

[0100] A second intrinsic semiconductor layer is formed on the second doped semiconductor layer.

[0101] For example, after the second doped semiconductor layer is formed, the gas containing doped particles can be stopped from being introduced into the deposition chamber of the deposition apparatus, while the reaction gas for the second semiconductor material layer continues to be introduced into the deposition chamber. In this way, a second intrinsic semiconductor layer can be formed on the second doped semiconductor layer. It is understood that the oxidation rate of the second doped semiconductor layer is less than the oxidation rate of the second intrinsic semiconductor layer.

[0102] The constituent materials of the second intrinsic semiconductor layer include polycrystalline silicon or amorphous silicon, etc. In this embodiment, the second intrinsic semiconductor layer is a polycrystalline silicon layer.

[0103] In this embodiment of the disclosure, forming a second intrinsic semiconductor layer on the second doped semiconductor layer facilitates the deposition of subsequent film layers (e.g., insulating layer or sacrificial layer), thereby improving the quality of the film layers subsequently deposited on the second semiconductor layer.

[0104] In some embodiments, forming the second semiconductor layer includes:

[0105] A second semiconductor material layer is formed on the first semiconductor layer;

[0106] Annealing is performed on the second semiconductor material layer to form the second semiconductor layer.

[0107] For example, a high-temperature annealing process can be used to anneal the second semiconductor material layer. Specifically, ammonia or hydrogen can be used to anneal the second semiconductor material layer.

[0108] The second semiconductor material layer is composed of materials such as polycrystalline silicon or amorphous silicon. In this embodiment, the second semiconductor material layer is a polycrystalline silicon layer.

[0109] Similarly, due to uneven stress distribution, the second semiconductor material layer may warp, affecting the flatness of the surface of the second semiconductor material layer and the deposition of subsequent film layers. Annealing can reduce the warping of the second semiconductor layer and reduce its impact on the deposition of subsequent film layers.

[0110] In some embodiments, the second semiconductor material layer may be subjected to in-situ doping followed by annealing to form a second semiconductor layer including the second doped semiconductor layer. This reduces the overall warpage of the second semiconductor layer.

[0111] Then, refer to Figure 4 As shown, step S200 is performed: forming a first through-hole 109 that penetrates the stacked structure 106, the first semiconductor layer 103, and whose bottom remains in the substrate 101.

[0112] For example, an etching process can be used to form a first via 109 that penetrates the stacked structure 106, the second semiconductor layer 105, the second protective layer 104, the first semiconductor layer 103, the first protective layer 102, and whose bottom end rests within the substrate 101. The etching process includes any one or a combination of dry etching and wet etching.

[0113] Understandably, the sidewall of the first via 109 exposes the stacked structure 106, the second semiconductor layer 105, the second protective layer 104, the first semiconductor layer 103, the first protective layer 102, and a portion of the substrate 101.

[0114] The first via 109 may include a channel via, a virtual channel via, or a contact via. For example, by filling a composite film layer of oxide-nitride-oxide-polysilicon into the channel via, a storage structure can be formed in the channel via for reading or writing information. By filling a virtual channel via with a dielectric material and / or an insulating material, a support structure can be formed in the virtual channel via for providing good support. By filling a contact via with a conductive material, a conductive contact structure can be formed in the contact via for achieving electrical connection. In this example, the first via 109 is a channel via.

[0115] Next, step S300 is performed: the first semiconductor layer exposed on the sidewall of the first via is subjected to a first oxidation process to form a first oxide layer; wherein, along the radial direction of the first via, the first oxide layer protrudes toward the axis of the first via.

[0116] For example, a first oxidation process is performed on the first semiconductor layer 103 exposed on the sidewall of the first via 109 to form such a... Figure 5 The first oxide layer 110 is shown.

[0117] In some embodiments, refer to Figure 5 As shown, the first oxide layer 110 includes a first interlayer portion and a first protrusion portion; wherein, the first interlayer portion is located between the first protective layer 102 and the second protective layer 104; and the first protrusion portion is located within the first through hole 109.

[0118] It should be emphasized that the first interlayer portion and the first protrusion portion are integral structures, both being the first oxide layer 110. The difference in location between different parts of the first oxide layer 110 is only used to distinguish them. It can be understood that the first protrusion portion can reduce the radial width of the first via 109 at the location of the first semiconductor layer 103.

[0119] The first oxidation treatment includes any one or a combination of wet oxidation, thermal oxidation, or plasma thermal oxidation, with wet oxidation being preferred in this embodiment. Taking wet oxidation as an example, the thickness of the interlayer portion and the protruding portion depends on the wet oxidation process conditions, including the concentration of the wet oxidant, the time of the wet oxidation treatment, and the temperature of the wet oxidation treatment.

[0120] The first oxide layer is composed of oxides. In this example, the first oxide layer is a silicon oxide layer.

[0121] In some embodiments, S200 includes: forming a first via through the stacked structure, the second semiconductor layer, the first semiconductor layer, and having its bottom end within the substrate;

[0122] The method further includes: after forming the first via, performing a second oxidation process on the second semiconductor layer exposed on the sidewall of the first via to form a second oxide layer; wherein, along the radial direction of the first via, the width of the second oxide layer is smaller than the width of the first oxide layer; the second oxidation process and the first oxidation process are performed simultaneously.

[0123] For example, when performing a first oxidation process on the first semiconductor layer 103 exposed on the sidewall of the first via 109, a second oxidation process can be performed on the second semiconductor layer 105 exposed on the sidewall of the first via 109 to form such a... Figure 5 The second oxide layer 111 is shown. It is understood that in this example, the first and second oxidation processes can be performed simultaneously. In other examples, the first and second oxidation processes can be performed separately, and this disclosure does not impose any limitations on this.

[0124] In some embodiments, refer to Figure 5 As shown, the second oxide layer 111 includes: a second interlayer portion and a second protrusion portion; wherein, the second interlayer portion is located between the second protective layer 104 and the insulating layer 107; and the second protrusion portion is located within the first through hole 109.

[0125] It should be emphasized that the second interlayer portion and the second protrusion portion are integral structures, both being the second oxide layer 111. The difference in location between different portions of the second oxide layer 111 is only used to distinguish them. It can be understood that the second protrusion portion can reduce the radial width of the first via 109 at the location of the second semiconductor layer 105.

[0126] In some embodiments, the width of the second oxide layer 111 is smaller than the width of the first oxide layer 110, including: along the radial direction of the first through hole 109, the width of the second protrusion is smaller than the width of the first protrusion.

[0127] In some embodiments, the width of the second oxide layer 111 is smaller than the width of the first oxide layer 110, including: along the radial direction of the first through hole 109, the width of the second interlayer portion is smaller than the width of the first interlayer portion.

[0128] In some embodiments, the width of the first oxide layer located within the first via 109 is less than or equal to the width of the first via; the top surface of the first oxide layer is substantially flush with the top surface of the first semiconductor layer. In one example, the width of the first protrusion is less than the width of the first via, and the first protrusion seals the bottom portion of the first via, meaning the aperture of the first via located at the first semiconductor layer is smaller than the aperture of the first via located at the stacked structure location. In another example, the width of the first protrusion is equal to the width of the first via, and the first protrusion completely seals the bottom of the first via.

[0129] Here, "the top surface of the first oxide layer is substantially flush with the top surface of the first semiconductor layer" includes: the top surface of the first oxide layer is completely flush with the top surface of the first semiconductor layer, or the distance between the top surface of the first oxide layer and the top surface of the first semiconductor layer is very small and can be ignored.

[0130] It should be noted that when the first semiconductor layer exposed on the sidewall of the first via is subjected to a first oxidation process to form a first oxide layer 110, a second oxide layer 111 is also formed on the surface of the second semiconductor layer exposed on the sidewall of the first via, and an oxide thin layer 112 is formed on the surface of a portion of the substrate. Since the substrate includes a silicon substrate, the first semiconductor layer includes a first doped semiconductor layer (e.g., doped polysilicon), the second semiconductor layer includes a second doped semiconductor layer (e.g., in-situ doped polysilicon), the oxidation rate of the first semiconductor layer is greater than the oxidation rate of the second semiconductor layer, and the oxidation rate of the first semiconductor layer is greater than the oxidation rate of the substrate, such that the width of the first oxide layer formed after the first oxidation process is greater than the width of the second oxide layer, and the width of the first oxide layer is greater than the width of the oxide thin layer.

[0131] Next, steps S400 and S500 are performed: the first via with the first oxide layer is filled to form a functional layer;

[0132] A first via with a functional layer is filled to form a channel layer; wherein the channel layer and the first oxide layer are separated by a functional layer, and the bottom of the channel layer is located above the first semiconductor layer.

[0133] For example, combined Figure 5 and Figure 6As shown, a thin-film deposition process can be used to form a functional layer covering the sidewalls and bottom of the first via 109. A channel layer 116 and a filling layer 117 are formed in the first via with the functional layer. The functional layer includes a barrier layer 113, a storage layer 114, and a tunneling layer 115 sequentially covering the sidewalls and bottom of the first via. The barrier layer 113 may include any one or any combination of silicon oxide, silicon oxynitride, and a high dielectric material (dielectric constant greater than 3.7). The storage layer 114 may include any one or any combination of silicon nitride, silicon oxynitride, and silicon. The tunneling layer 115 may include any one or any combination of silicon oxide and silicon oxynitride. In this embodiment, the functional layer is a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0134] The channel layer 116 may include any one or any combination of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The filling layer 117 is composed of an insulating material (e.g., silicon oxide or other dielectric materials). The filling layer 117 may completely or partially fill the first via. When the filling layer partially fills the first via, a structure is formed within the first via as shown in the image. Figure 6 The gap shown.

[0135] In some embodiments, when the first oxide layer 110 protrudes toward the axis of the first via, the portion of the first via that penetrates the first semiconductor layer can be sealed. When a functional layer is formed in the first via, the entire first via that penetrates the first semiconductor layer can be sealed, so that the bottom of the formed channel layer 116 is located above the first semiconductor layer. The channel layer and the first oxide layer are separated by a functional layer, so that the channel layer does not extend into the first via located in the substrate.

[0136] In some embodiments, after the trench layer is formed and before step S600 is performed, the method further includes:

[0137] A groove is formed that runs through the stacked structure and rests at the bottom within the substrate;

[0138] By using grooves, the sacrificial layer is removed to form a gap between adjacent insulating layers; wherein the sidewalls of the gap expose the functional layer;

[0139] A conductive layer is formed to fill the gaps.

[0140] Figure 6Cross-sectional views of the three-dimensional memory in the yoz and xoz planes are shown respectively. A groove extending through the stacked structure and into the substrate 101 at the bottom can be formed by dry etching and / or wet etching. The groove extends in a direction parallel to the x-axis, and its depth extends in the z-direction. A sacrificial layer can be removed through the groove to form a gap between two adjacent insulating layers, exposing a barrier layer 113 on the sidewalls of the gap. A conductive material is then filled into the gap to form a conductive layer 118, which serves as the word line of the three-dimensional memory. The constituent materials of the conductive layer 118 include conductive materials such as tungsten, cobalt, nickel, titanium, or polysilicon.

[0141] In some embodiments, the method further includes filling the grooves to form a gate gap structure. (See reference...) Figure 6 As shown, the gate linegage structure includes an electrically insulating layer 119 and a conductive layer 120. The electrically insulating layer 119 is located between the conductive layer 120 and the stacked structure, and also between the substrate 101 and the conductive layer 120. The electrically insulating layer 119 can be made of silicon oxide, and the conductive layer 120 can be made of tungsten or polysilicon. It is understood that the gate linegage structure including the electrically insulating layer 119 and the conductive layer 120 can be used as the common source of a three-dimensional memory.

[0142] In other examples, insulating material (e.g., silicon oxide) or semiconductor material (e.g., polysilicon) may be filled into the groove where the electrical isolation layer 119 is formed to form a gate gap structure, which can be used to support the stacked structure or adjust stress.

[0143] In some embodiments, the stacked structure includes a core region and a step region; the method further includes:

[0144] Support pillars are formed in the stepped region; wherein the bottom of the support pillars is located in the substrate;

[0145] Contact pillars are formed in the first dielectric layer covering the stepped region; wherein the contact pillars are electrically connected to the second semiconductor layer.

[0146] For example, etching and deposition processes can be used to form materials such as... Figure 6 The support post 121 and contact post 122 are shown. The support post 121 is made of insulating materials, such as any one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. The contact post 122 is made of conductive materials, such as tungsten, copper, or aluminum.

[0147] Finally, step S600 is performed: the substrate, the first oxide layer, and part of the functional layer are removed to expose the bottom of the trench layer.

[0148] For example, refer to Figure 6As shown, the substrate 101, the first protective layer 102, the first semiconductor layer 103, the second protective layer 104, the first oxide layer 110, and some functional layers can be removed by wet etching and / or dry etching to form a structure as shown. Figure 9 The structure shown.

[0149] In some embodiments, S600 includes:

[0150] Perform the first etching to remove the substrate and expose the first oxide layer or functional layer;

[0151] A second etching is performed to remove the first oxide layer and part of the functional layer to expose the bottom of the channel layer and the second semiconductor layer.

[0152] For example, combined Figure 6 and Figure 7 As shown, a first etching is performed to remove the substrate 101 from the side of the substrate 101 relatively away from the stacked structure, exposing the oxide thin layer 112 and the first protective layer 102. For example, an etchant with a high etch selectivity relative to the oxide thin layer 112 and the first protective layer 102 can be used to remove the substrate 101, and then the oxide thin layer 112 and the first protective layer 102 can be removed to expose the first oxide layer 110 (e.g., ...). Figure 7 (As shown).

[0153] It should be emphasized that, since the gate gap structure and the bottom of the support pillar 121 extend into the substrate, the electrical isolation layer 119 and the support pillar 121 are simultaneously exposed after the substrate 101 is removed. Because the constituent materials of the electrical isolation layer 119 and the support pillar 121 are the same as those of the oxide thin layer 112 and the first protective layer 102, the electrical isolation layer 119 and part of the support pillar 121 are simultaneously removed during the removal of the oxide thin layer 112 and the first protective layer 102, thereby forming... Figure 7 The structure shown.

[0154] For example, refer to Figure 7 As shown, the first semiconductor layer 103 is removed, exposing the second protective layer 104. It should be emphasized that, since both the first semiconductor layer 103 and the conductive layer 120 are composed of polycrystalline silicon, during the removal of the first semiconductor layer 103, a portion of the conductive layer 120 is also removed, thus forming the following... Figure 8 The structure shown.

[0155] For example, refer to Figure 8 As shown, a second etching is performed to remove the first oxide layer 110 and part of the functional layer, exposing the bottom of the channel layer 116 and the second semiconductor layer 105.

[0156] In some embodiments, the etching rate of the second etching on the first oxide layer and a portion of the functional layer is greater than the etching rate of the second etching on the channel layer and the second semiconductor layer. For example, an etchant with a high etch selectivity relative to the channel layer 116 and the second semiconductor layer 105 may be used to remove the first oxide layer 110 and a portion of the functional layer to expose the bottom of the channel layer 116 and the second semiconductor layer 105.

[0157] It should be emphasized that, since the materials constituting the second protective layer 104, the electrical isolation layer 119, and the support pillar 121 are all silicon oxide, the second protective layer 104, part of the electrical isolation layer 119, and part of the support pillar 121 are simultaneously removed during the removal of the first oxide layer 110 and the functional layer, thus forming... Figure 9 The structure shown.

[0158] Understandably, during the second etching process, since the etching rate of the second etching on the first oxide layer and some functional layers is greater than the etching rate of the second etching on the channel layer and the second semiconductor layer, the second semiconductor layer can be used as an etch stop layer to avoid over-etching of the stacked structure and the functional layers located in the stacked structure. In this way, the height of the functional layers and the channel layer located in the stacked structure can be controlled to ensure the uniformity of the height of the functional layers and the channel layer located in the stacked structure, thereby improving the operating performance of the three-dimensional memory.

[0159] Furthermore, by forming a second semiconductor layer between the first semiconductor layer and the stacked structure, the second semiconductor layer can protect the stacked structure. Specifically, during the second etching process to remove the first oxide layer and part of the functional layer, the second semiconductor layer acts as an etch stop layer, preventing the bottommost insulating layer of the stacked structure from being etched, thereby controlling the uniformity of the thickness of the bottommost insulating layer in the stacked structure.

[0160] In some embodiments, after exposing the bottom of the channel layer 116, the method further includes:

[0161] Reference Figure 10 As shown, a third semiconductor layer 123 is formed that is electrically connected to the bottom of the channel layer 116;

[0162] Reference Figure 13 As shown, a first conductive structure 127 is formed that is electrically connected to the third semiconductor layer 123; and a second conductive structure 128 is formed that is electrically connected to the bottom of the contact post 122.

[0163] For example, combined Figure 9 and Figure 10As shown, after exposing the bottom of the channel layer 116, a third semiconductor layer 123 is formed, covering the second semiconductor layer 105, the remaining functional layers, the bottom of the channel layer 116, the remaining electrical isolation layer 119, the remaining conductive layer 120, and the remaining contact pillars 121. The constituent materials of the third semiconductor layer 123 include: monocrystalline silicon, polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon, etc.

[0164] Exemplarily, an etching process (e.g., dry etching and / or wet etching) is performed to form a contact via 124 penetrating the third semiconductor layer 123 and a portion of the second semiconductor layer 105 (e.g., ...). Figure 11 As shown, the contact via 124 exposes the bottom of the contact post 122. A thin-film deposition process is performed to form a dielectric material layer covering the third semiconductor layer 123 and the contact via 124. It is understood that the dielectric material layer also covers the bottom of the contact post 122. The dielectric material layer covering the bottom of the contact post 122 is removed by dry etching and / or wet etching to form a layer as shown. Figure 11 The dielectric layer 125 is shown.

[0165] For example, trenches 126 penetrating the dielectric layer 125 can be formed by dry etching and / or wet etching (e.g., Figure 12 As shown, trench 126 exposes a portion of the third semiconductor layer 123. By filling the trench 126 and the contact via 124 where the dielectric layer 125 is formed with conductive material, a first conductive structure 127 and a second conductive structure 128 are formed, respectively.

[0166] It should be emphasized that the first conductive structure 127 and the second conductive structure 128 can be formed simultaneously or sequentially, and this disclosure does not impose any restrictions. Preferably, the first conductive structure 127 and the second conductive structure 128 are formed simultaneously, which can reduce the manufacturing steps of the three-dimensional memory and save production costs.

[0167] The dielectric layer 125 is composed of insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0168] The constituent materials of the first conductive structure and the second conductive structure include conductive materials, such as tungsten, monocrystalline silicon, polycrystalline silicon or doped polycrystalline silicon, etc. The constituent materials of the first conductive structure and the second conductive structure can be the same or different. It is understood that when the first conductive structure and the second conductive structure are formed at the same time, the constituent materials of the first conductive structure and the second conductive structure are the same.

[0169] Figures 14 to 29 This is a schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of this disclosure. The following will be combined with... Figure 2 , Figures 14 to 29 This disclosure will be further explained in more detail.

[0170] First, combined Figure 14 and Figure 15 As shown, step S100 is performed: a first semiconductor layer 203 and a stacked structure 206 are sequentially formed on the substrate 201.

[0171] The substrate 201 is composed of materials including: elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this embodiment, the substrate 201 is a silicon substrate.

[0172] The first semiconductor layer 203 is composed of materials such as polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon. In this embodiment, the first semiconductor layer 203 is a doped polycrystalline silicon layer.

[0173] The stacked structure 206 includes an insulating layer 207 and a sacrificial layer 208 that are alternately stacked. The insulating layer 207 is composed of materials such as silicon oxide, silicon nitride, or silicon oxynitride; in this embodiment, the insulating layer 207 may be a silicon oxide layer. The sacrificial layer 208 is composed of materials such as silicon nitride or silicon oxynitride; in this embodiment, the sacrificial layer 208 may be a silicon nitride layer.

[0174] It should be noted that in the back-gate process, the sacrificial layer is used to replace the conductive layer. In the front-gate process, the stacked structure may also include alternately stacked insulating and conductive layers. The conductive layer serves as the word line of the three-dimensional memory, and read, write, and erase operations of the memory are achieved by applying different control voltages to the conductive layer. The number of sacrificial or conductive layers in the stacked structure includes 8, 16, 32, 64, 96, 128, or 256 layers, etc., and this disclosure does not impose any limitation.

[0175] In some embodiments, the first semiconductor layer 203 includes: a first doped semiconductor layer; S100 includes:

[0176] A first semiconductor material layer is formed on the substrate;

[0177] A doping process is performed on the first semiconductor material layer to form a first doped semiconductor layer.

[0178] For example, a thin film deposition process can be used to form a first semiconductor material layer on a substrate. Thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0179] For example, the first semiconductor material layer can be doped using an ion implantation process or an ion diffusion process to increase the oxidation rate of the first semiconductor layer. It is understood that, under the same oxidation atmosphere or conditions, the oxidation rate of the first doped semiconductor layer is greater than the oxidation rate of the first semiconductor material layer.

[0180] The first semiconductor material layer is composed of polycrystalline silicon or amorphous silicon, and the first doped semiconductor layer is composed of doped polycrystalline silicon or doped amorphous silicon. In this embodiment, the first semiconductor material layer is a polycrystalline silicon layer, and the first doped semiconductor layer is a doped polycrystalline silicon layer.

[0181] In some embodiments, the doping process performed on the first semiconductor material layer includes: partial doping of the first semiconductor material layer, or complete doping of the first semiconductor material layer. It should be understood that when the first semiconductor material layer is partially doped, the first semiconductor layer includes a first intrinsic semiconductor layer and a first doped semiconductor layer; when the first semiconductor material layer is completely doped, the fully doped first semiconductor layer is the first doped semiconductor layer. The choice can be made according to actual needs, and this disclosure does not impose any limitations.

[0182] In some embodiments, the oxidation rate of the first doped semiconductor layer is controlled by controlling parameters of the ion implantation process, such as the concentration of doped particles, the ion implantation time, and the ion implantation energy. These parameters control the concentration of doped particles, and / or the number of doped particles, and / or the position of the doped particles. The doped particles in the first doped semiconductor layer include boron ions, phosphorus ions, or arsenic ions. In some embodiments, S100 includes:

[0183] A first semiconductor material layer is formed on the substrate;

[0184] Annealing is performed on the first semiconductor material layer to form the first semiconductor layer.

[0185] For example, a high-temperature annealing process can be used to anneal the first semiconductor material layer. Specifically, ammonia or hydrogen can be used to anneal the first semiconductor material layer.

[0186] The first semiconductor material layer is composed of materials such as polycrystalline silicon or amorphous silicon. In this embodiment, the first semiconductor material layer is a polycrystalline silicon layer.

[0187] It should be noted that due to uneven stress distribution, the first semiconductor material layer may warp, affecting the flatness of the surface of the first semiconductor material layer and the deposition of subsequent film layers. Annealing can reduce the warping of the first semiconductor layer and reduce its impact on the deposition of subsequent film layers.

[0188] In some embodiments, the first semiconductor material layer may be doped first, followed by annealing to form a first semiconductor layer including the first doped semiconductor layer. This reduces the overall warpage of the first semiconductor layer, while annealing further promotes the diffusion of dopants, increasing the oxidation rate of the first semiconductor layer and facilitating subsequent oxidation processes.

[0189] In some embodiments, refer to Figure 14 As shown, step S100 further includes:

[0190] A first protective layer 202 is formed on a substrate 201; wherein, the first protective layer 202 is located between the substrate 201 and the first semiconductor layer 203, and the first protective layer 202 is used to protect the surface of the substrate 201;

[0191] A second protective layer 204 is formed on the first semiconductor layer 203; wherein the second protective layer 204 is located between the first semiconductor layer 203 and the second semiconductor layer 205, and the second protective layer 204 is used to protect the surface of the first semiconductor layer 203.

[0192] The first protective layer 202 and the second protective layer 204 are composed of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The materials of the first protective layer 202 and the second protective layer 204 can be the same or different. In this embodiment, both the first protective layer 202 and the second protective layer 204 can be silicon oxide layers.

[0193] In some embodiments, the above method further includes:

[0194] A second semiconductor layer is formed, wherein the second semiconductor layer is located between the first semiconductor layer and the stacked structure.

[0195] For example, combined Figure 14 and Figure 15 As shown, a thin-film deposition process can be used to form a second semiconductor layer 205 on the second protective layer 204, and a stacked structure 206 can be formed on the second semiconductor layer 205. The thin-film deposition process includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0196] In some embodiments, the method further includes: performing a pretreatment on the second semiconductor layer before forming the first via; wherein the pretreatment is used to reduce the oxidation rate of the second semiconductor layer.

[0197] It is understandable that, under the same oxidizing atmosphere or oxidizing conditions, the oxidation rate of the pretreated second semiconductor layer is less than that of the untreated second semiconductor layer.

[0198] In this embodiment of the disclosure, the oxidation rate of the second semiconductor layer is reduced by pretreatment. During subsequent oxidation processing, the probability of the upper and / or lower surfaces of the second semiconductor layer being oxidized can be reduced. This ensures that the thickness change of the second semiconductor layer is small. In subsequent fabrication processes, this helps to reduce the probability that the second semiconductor layer, as an etch barrier layer, will be etched through, thereby reducing damage to other film layers (e.g., the insulating layer 207 at the bottom of the stacked structure 206).

[0199] Furthermore, by reducing the oxidation rate of the second semiconductor layer through pretreatment, the difference between the oxidation rates of the first and second semiconductor layers can be increased, so that the oxidation rate of the first semiconductor layer is greater than that of the second semiconductor layer, which is beneficial to the execution of subsequent oxidation processes.

[0200] In some embodiments, the second semiconductor layer includes: a second doped semiconductor layer;

[0201] Forming a second semiconductor layer includes:

[0202] Forming a second semiconductor material layer;

[0203] Preprocessing is performed on the second semiconductor layer, including:

[0204] An in-situ doping process is performed on the second semiconductor material layer to form a second doped semiconductor layer.

[0205] For example, a gas containing dopant particles can be introduced during the deposition of the second semiconductor material layer. This allows for in-situ doping during the growth of the second semiconductor material layer, improving its stability and reducing its oxidation rate. It is understood that, under the same oxidizing atmosphere or conditions, the oxidation rate of the second doped semiconductor layer is greater than that of the second semiconductor material layer.

[0206] The second semiconductor material layer comprises polycrystalline silicon or amorphous silicon, and the second doped semiconductor layer comprises in-situ doped polycrystalline silicon or in-situ doped amorphous silicon. In this embodiment, the second semiconductor material layer is a polycrystalline silicon layer, and the second doped semiconductor layer is an in-situ doped polycrystalline silicon layer.

[0207] In some embodiments, the concentration of dopant particles in the second doped semiconductor layer is controlled by controlling the time of introduction of the gas including dopant particles and the reaction parameters of the deposition apparatus (e.g., temperature, pressure, etc.), thereby controlling the oxidation rate of the second doped semiconductor layer. The dopant particles in the second doped semiconductor layer include nitrogen particles. The doping gas may include a nitrogen-containing gas, such as nitrogen gas.

[0208] In this embodiment, by performing in-situ doping on the second semiconductor material layer, a second doped semiconductor layer with an oxidation rate lower than that of the second semiconductor material layer can be formed. Furthermore, the in-situ doping process can be completed within the deposition chamber of the second semiconductor material layer, making it compatible with the thin film deposition process of the second semiconductor material layer without requiring additional steps.

[0209] In some embodiments, the second semiconductor layer further includes: a second intrinsic semiconductor layer;

[0210] The formation of the second semiconductor layer further includes:

[0211] A second intrinsic semiconductor layer is formed on the second doped semiconductor layer.

[0212] For example, after the second doped semiconductor layer is formed, the gas containing doped particles can be stopped from being introduced into the deposition chamber of the deposition apparatus, while the reaction gas for the second semiconductor material layer continues to be introduced into the deposition chamber. In this way, a second intrinsic semiconductor layer can be formed on the second doped semiconductor layer. It is understood that the oxidation rate of the second doped semiconductor layer is less than the oxidation rate of the second intrinsic semiconductor layer.

[0213] The constituent materials of the second intrinsic semiconductor layer include polycrystalline silicon or amorphous silicon, etc. In this embodiment, the second intrinsic semiconductor layer is a polycrystalline silicon layer.

[0214] In this embodiment of the disclosure, forming a second intrinsic semiconductor layer on the second doped semiconductor layer facilitates the deposition of subsequent film layers (e.g., insulating layer or sacrificial layer), thereby improving the quality of the film layers subsequently deposited on the second semiconductor layer.

[0215] In some embodiments, forming the second semiconductor layer includes:

[0216] A second semiconductor material layer is formed on the first semiconductor layer;

[0217] Annealing is performed on the second semiconductor material layer to form the second semiconductor layer.

[0218] For example, a high-temperature annealing process can be used to anneal the second semiconductor material layer. Specifically, ammonia or hydrogen can be used to anneal the second semiconductor material layer.

[0219] The second semiconductor material layer is composed of materials such as polycrystalline silicon or amorphous silicon. In this embodiment, the second semiconductor material layer is a polycrystalline silicon layer.

[0220] Similarly, due to uneven stress distribution, the second semiconductor material layer may warp, affecting the flatness of the surface of the second semiconductor material layer and the deposition of subsequent film layers. Annealing can reduce the warping of the second semiconductor layer and reduce its impact on the deposition of subsequent film layers.

[0221] In some embodiments, the thickness of the first semiconductor layer 203 is greater than the thickness of the second semiconductor layer 205. For example, the ratio of the thickness of the first semiconductor layer 203 to the thickness of the second semiconductor layer 205 is greater than a preset value. Here, the preset value can be set according to the actual application, and this disclosure does not limit it.

[0222] In this embodiment, by setting the thickness of the first semiconductor layer to be greater than the thickness of the second semiconductor layer, the bottom of the subsequently formed gate gap structure and the bottom of the contact pillars can be located within the first semiconductor layer. During the subsequent removal of the substrate to expose the bottom of the channel layer, the probability of the bottom of the gate gap structure and the bottom of the contact pillars being removed can be reduced, thereby protecting the insulating layer, conductive layer, or word line layer in the stacked structure.

[0223] Then, refer to Figure 15 As shown, step S200 is performed: forming a first through-hole 209 that penetrates the stacked structure 206, the first semiconductor layer 203, and whose bottom remains in the substrate 201.

[0224] For example, a first via 209 can be formed through an etching process, penetrating the stacked structure 206, the second semiconductor layer 205, the second protective layer 204, the first semiconductor layer 203, the first protective layer 202, and with its bottom remaining within the substrate 201. The etching process includes any one or a combination of dry etching and wet etching.

[0225] Understandably, the sidewall of the first via 209 exposes the stacked structure 206, the second semiconductor layer 205, the second protective layer 204, the first semiconductor layer 203, the first protective layer 202, and a portion of the substrate 201.

[0226] The first via 209 may include a channel via, a virtual channel via, or a contact via. For example, by filling a composite film layer of oxide-nitride-oxide-polysilicon into the channel via, a storage structure can be formed in the channel via for reading or writing information. By filling a virtual channel via with a dielectric material and / or an insulating material, a support structure can be formed in the virtual channel via for providing good support. By filling a contact via with a conductive material, a conductive contact structure can be formed in the contact via for achieving electrical connection. In this example, the first via 209 is a channel via.

[0227] Next, step S300 is performed: the first semiconductor layer exposed on the sidewall of the first via is subjected to a first oxidation process to form a first oxide layer; wherein, along the radial direction of the first via, the first oxide layer protrudes toward the axis of the first via.

[0228] For example, a first oxidation process is performed on the first semiconductor layer 203 exposed on the sidewall of the first via 209 to form such a... Figure 16a The first oxide layer 210 shown, or, formed as... Figure 16b The first oxide layer 210' shown.

[0229] In some embodiments, refer to Figure 16a As shown, the first oxide layer 210 includes a first interlayer portion and a first protrusion portion; wherein, the first interlayer portion is located between the first protective layer 202 and the second protective layer 204; and the first protrusion portion is located within the first through hole 209.

[0230] It should be emphasized that the first interlayer portion and the first protrusion portion are an integral structure, both being the first oxide layer 210. The difference in location between different parts of the first oxide layer 210 is only used to distinguish them. It can be understood that the first protrusion portion can reduce the radial width of the first via 209 at the location of the first semiconductor layer 203.

[0231] In some embodiments, refer to Figure 16a As shown in 16b, the first semiconductor layer between two adjacent first vias may be partially or completely oxidized. It should be understood that when the first semiconductor layer between two adjacent first vias is partially oxidized, a portion of the first semiconductor layer is still retained.

[0232] In some embodiments, whether the first semiconductor layer between two adjacent first vias is partially or completely oxidized depends on the width of the first semiconductor layer between the two adjacent first vias and the oxidation rate of the first semiconductor layer. It should be understood that the smaller the width of the first semiconductor layer between two adjacent first vias, and / or the greater the oxidation rate of the first semiconductor layer, the more of the first semiconductor layer between the two adjacent first vias is oxidized, and the less of the first semiconductor layer is retained.

[0233] The first oxidation treatment includes any one or a combination of wet oxidation, thermal oxidation, or plasma thermal oxidation, with wet oxidation being preferred in this embodiment. Taking wet oxidation as an example, the thickness of the interlayer portion and the protruding portion depends on the wet oxidation process conditions, including the concentration of the wet oxidant, the time of the wet oxidation treatment, and the temperature of the wet oxidation treatment.

[0234] The first oxide layer is composed of oxides. In this example, the first oxide layer is a silicon oxide layer.

[0235] In some embodiments, S200 includes: forming a first via through the stacked structure, the second semiconductor layer, the first semiconductor layer, and having its bottom end within the substrate;

[0236] The method further includes: after forming the first via, performing a second oxidation process on the second semiconductor layer exposed on the sidewall of the first via to form a second oxide layer; wherein, along the radial direction of the first via, the width of the second oxide layer is smaller than the width of the first oxide layer; the second oxidation process and the first oxidation process are performed simultaneously.

[0237] For example, when performing a first oxidation process on the first semiconductor layer 203 exposed on the sidewall of the first via 209, a second oxidation process can be performed on the second semiconductor layer 205 exposed on the sidewall of the first via 209 to form such a... Figure 16a or Figure 16b The second oxide layer 211 is shown. It is understood that in this example, the first and second oxidation processes can be performed simultaneously. In other examples, the first and second oxidation processes can be performed separately, and this disclosure does not impose any limitations thereon.

[0238] In some embodiments, refer to Figure 16a or Figure 16b As shown, the second oxide layer 211 includes: a second interlayer portion and a second protrusion portion; wherein, the second interlayer portion is located between the second protective layer 204 and the insulating layer 207; and the second protrusion portion is located within the first through hole 209.

[0239] It should be emphasized that the second interlayer portion and the second protrusion portion are integral structures, both being the second oxide layer 211. The difference in location between different portions of the second oxide layer 211 is only used to distinguish them. It can be understood that the second protrusion portion can reduce the radial width of the first via 209 at the location of the second semiconductor layer 205.

[0240] In some embodiments, the width of the second oxide layer 211 is smaller than the width of the first oxide layer 210, including: along the radial direction of the first through hole 209, the width of the second protrusion is smaller than the width of the first protrusion.

[0241] In some embodiments, the width of the second oxide layer 211 is smaller than the width of the first oxide layer 210, including: along the radial direction of the first through hole 209, the width of the second interlayer portion is smaller than the width of the first interlayer portion.

[0242] In some embodiments, the width of the first oxide layer located within the first through hole 209 is less than or equal to the width of the first through hole;

[0243] The top surface of the first oxide layer is basically flush with the top surface of the first semiconductor layer.

[0244] For example, refer to Figure 16aAs shown, the width of the first protrusion is equal to the width of the first through hole 209, and the top surface of the first oxide layer 210 is basically flush with the top surface of the first semiconductor layer 203. It can be understood that in this example, the first protrusion completely seals the bottom of the first through hole.

[0245] For example, refer to Figure 16b As shown, the width of the first protrusion is less than the width of the first via 209, and the top surface of the first oxide layer 210' is basically flush with the top surface of the first semiconductor layer 203. It can be understood that in this example, the first protrusion seals the bottom part of the first via, that is, the diameter of the first via located at the first semiconductor layer is smaller than the diameter of the first via located at the stacked structure.

[0246] Here, "the top surface of the first oxide layer is substantially flush with the top surface of the first semiconductor layer" includes: the top surface of the first oxide layer is completely flush with the top surface of the first semiconductor layer, or the distance between the top surface of the first oxide layer and the top surface of the first semiconductor layer is very small and can be ignored.

[0247] It should be noted that when the first semiconductor layer exposed on the sidewall of the first via is subjected to a first oxidation process to form a first oxide layer 210, a second oxide layer 211 is also formed on the surface of the second semiconductor layer exposed on the sidewall of the first via, and an oxide thin layer 212 is formed on the surface of a portion of the substrate. Since the substrate includes a silicon substrate, the first semiconductor layer includes a first doped semiconductor layer (e.g., doped polysilicon), the second semiconductor layer includes a second doped semiconductor layer (e.g., in-situ doped polysilicon), the oxidation rate of the first semiconductor layer is greater than the oxidation rate of the second semiconductor layer, and the oxidation rate of the first semiconductor layer is greater than the oxidation rate of the substrate, such that the width of the first oxide layer formed after the first oxidation process is greater than the width of the second oxide layer, and the width of the first oxide layer is greater than the width of the oxide thin layer.

[0248] It should be noted that the following will be based on Figure 16a This explanation uses an example as an illustration; however, this disclosure is not limited to this, and may also include... Figure 16b The example executes subsequent processes.

[0249] Next, steps S400 and S500 are performed: the first via with the first oxide layer is filled to form a functional layer;

[0250] A first via with a functional layer is filled to form a channel layer; wherein the channel layer and the first oxide layer are separated by a functional layer, and the bottom of the channel layer is located above the first semiconductor layer.

[0251] For example, combined Figure 16a and Figure 17As shown, a thin-film deposition process can be used to form a functional layer covering the sidewalls and bottom of the first via 209. A channel layer 216 and a filling layer 217 are formed in the first via with the functional layer. The functional layer includes a barrier layer 213, a storage layer 214, and a tunneling layer 215 sequentially covering the sidewalls and bottom of the first via. The barrier layer 213 may include any one or any combination of silicon oxide, silicon oxynitride, and a dielectric material with a high dielectric constant (dielectric constant greater than 3.7). The storage layer 214 may include any one or any combination of silicon nitride, silicon oxynitride, and silicon. The tunneling layer 215 may include any one or any combination of silicon oxide and silicon oxynitride. In this embodiment, the functional layer is a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0252] The channel layer 216 may include any one or any combination of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The filling layer 217 is composed of an insulating material (e.g., silicon oxide or other dielectric materials). The filling layer 217 may completely or partially fill the first via. When the filling layer partially fills the first via, a structure is formed within the first via. Figure 17 The gap shown.

[0253] Finally, step S600 is performed: the substrate, the first oxide layer, and part of the functional layer are removed to expose the bottom of the trench layer.

[0254] In some embodiments, S600 includes:

[0255] Perform the first etching to remove the substrate and expose the first oxide layer or functional layer;

[0256] A second etching is performed to remove the first oxide layer and part of the functional layer to expose the bottom of the channel layer and the second semiconductor layer.

[0257] For example, when the width of the first protrusion is equal to the width of the first through hole 209, that is, when the first protrusion completely seals the bottom of the first through hole, a shape like this can be formed. Figure 22a The structure shown is referenced. Figure 22a As shown, a first etching is performed to remove substrate 201 from the side of substrate 201 that is relatively far from the stacked structure, exposing oxide thin layer 212 and first protective layer 202 (as shown). Figure 23a As shown, the first protective layer 202 can be used to protect the remaining first semiconductor layer 203 during the removal of the substrate 201. For example, the substrate 201 can be removed using an etchant with a high etch selectivity compared to the oxide thin layer 212 and the first protective layer 202, and then the first oxide layer 210 can be exposed by removing the oxide thin layer 212 and the first protective layer 202.

[0258] For example, when the width of the first protrusion is less than the width of the first through hole 209, that is, when the first protrusion seals the bottom portion of the first through hole, a structure like this can be formed. Figure 22b The structure shown undergoes a first etching process to remove the substrate from the side of the substrate relatively far from the stacked structure, exposing a thin oxide layer and a first protective layer (such as...). Figure 23b As shown in the figure, the functional layer can be exposed by removing the oxide thin layer and the first protective layer.

[0259] It should be noted that when the first via at the location of the first semiconductor layer is completely sealed, the functional layer and channel layer formed by filling will not extend into the substrate (e.g., Figure 22a As shown). When the first via portion penetrating the first semiconductor layer is sealed, because the channel layer and the first oxide layer are separated by a functional layer, that is, the functional layer and the first oxide layer can completely seal the first via portion penetrating the first semiconductor layer (as shown). Figure 22b As shown), by subsequently removing the substrate, the first oxide layer, and part of the functional layer, it can be ensured that the functional layer and the channel layer are located above the first semiconductor layer. The vias actually used for filling (i.e., the vias that ultimately retain the functional layer and the channel layer) are located above the first semiconductor layer. The grooves formed in the substrate will not affect the vias actually used for filling. In this way, the depth of the vias actually used for filling can be controlled to ensure the uniformity of the depth of the vias actually used for filling, thereby improving the uniformity of the height of the functional structure formed in the via.

[0260] For example, refer to Figure 23a As shown, a second etching is performed to remove the first oxide layer 210 and part of the functional layer, forming as shown. Figure 24 The back via 231 shown exposes the bottom of the channel layer 216 and the second semiconductor layer 205.

[0261] In some embodiments, the etching rate of the second etching on the first oxide layer and a portion of the functional layer is greater than the etching rate of the second etching on the channel layer and the second semiconductor layer. For example, an etchant with a higher etch selectivity than the channel layer 216 and the second semiconductor layer 205 can be used to remove the first oxide layer 210 and a portion of the functional layer to expose the bottom of the channel layer 216 and the second semiconductor layer 205. Since the etching rate of the second etching on the first oxide layer 210 and a portion of the functional layer is greater than the etching rate of the channel layer 216 and the second semiconductor layer 205, the second etching can stop at the surface of the second semiconductor layer 205 relatively close to the first semiconductor layer 203 and the bottom of the channel layer 216.

[0262] It should be emphasized that, since the constituent materials of the oxide thin layer 212, the first protective layer 202, and the second protective layer 204 all include silicon oxide, during the removal of the first oxide layer 210 and the functional layer, the oxide thin layer 212, the first protective layer 202, and part of the second protective layer 204 are simultaneously removed, thus forming a structure as shown in the image. Figure 24 The structure shown.

[0263] For example, plasma etching or gas etching can be used to remove the oxide thin layer 212, the first protective layer 202, the first oxide layer 210, part of the second protective layer 204, and part of the functional layer in one step, which can greatly simplify the fabrication process of the three-dimensional memory. In addition, since the oxide thin layer 212, the first protective layer 202, the first oxide layer 210, the second protective layer 204, and the functional layer all include silicon oxide layers, it is beneficial to control the etching conditions (including process parameters, etching gas, etc.) of plasma etching or gas etching.

[0264] Understandably, during the second etching process, since the etching rate of the second etching on the first oxide layer and some functional layers is greater than the etching rate of the second etching on the channel layer and the second semiconductor layer, the second semiconductor layer can be used as an etch stop layer to avoid over-etching of the stacked structure and the functional layers located in the stacked structure. In this way, the height of the functional layers and the channel layer located in the stacked structure can be controlled to ensure the uniformity of the height of the functional layers and the channel layer located in the stacked structure, thereby improving the operating performance of the three-dimensional memory.

[0265] Furthermore, by forming a second semiconductor layer between the first semiconductor layer and the stacked structure, the second semiconductor layer can protect the stacked structure. Specifically, during the second etching process to remove the first oxide layer and part of the functional layer, the second semiconductor layer acts as an etch stop layer, preventing the bottommost insulating layer of the stacked structure from being etched, thereby controlling the uniformity of the thickness of the bottommost insulating layer in the stacked structure.

[0266] It should be emphasized that in this example, the first etching is used to remove the substrate and can be a global etching, while the second etching is used to remove the first oxide layer and part of the functional layer and can be a local etching, for example, by forming a mask layer including a mask pattern to perform the second etching.

[0267] In some embodiments, after forming the trench layer and before removing the substrate, the first oxide layer, and a portion of the functional layer to expose the bottom of the trench layer, the method further includes:

[0268] A groove is formed that runs through the stacked structure and rests at the bottom within the first semiconductor layer;

[0269] By using grooves, the sacrificial layer is removed to form a gap between adjacent insulating layers; wherein the sidewalls of the gap expose the functional layer;

[0270] A conductive layer is formed to fill the gaps.

[0271] Figure 17 Cross-sectional views of the three-dimensional memory in the yoz and xoz planes are shown respectively. A recess 229 extending through the stacked structure and into the first semiconductor layer 203 can be formed by dry etching and / or wet etching. The recess extends in a direction parallel to the x-axis, and its depth extends in the z-direction. The sidewalls of the recess 229 expose the stacked structure and a portion of the first semiconductor layer 203.

[0272] For example, the sacrificial layer can be removed through the groove 229 to form a gap between two adjacent insulating layers. The gap communicates with the groove 229, and the sidewalls of the gap expose a functional layer. Specifically, the sidewalls of the gap expose a barrier layer 213. The gap is filled with a conductive material to form a conductive layer 218, which serves as a word line for a three-dimensional memory.

[0273] The conductive layer 218 is composed of conductive materials, such as tungsten, cobalt, nickel, titanium, or polycrystalline silicon.

[0274] It should be noted that, since the first semiconductor layer 203 is relatively thick, the bottom of the groove 229 can be kept within the first semiconductor layer 203 and will not extend into the substrate 201. That is, when the groove 229 is etched, no gouging will be formed in the substrate. When the substrate is removed from the back side in the subsequent process, the weak point in the substrate can be reduced, which is beneficial to improving the process window for removing the substrate and functional layer from the back side.

[0275] In some embodiments, after forming the gap and before forming the conductive layer, the method further includes: sequentially depositing a dielectric layer and an adhesive layer along the groove and the gap, wherein the dielectric layer is used to isolate the functional layer from the conductive layer, and the adhesive layer is used to increase the adhesion of the conductive layer.

[0276] Exemplarily, a dielectric layer (not shown in the figure) and an adhesive layer 2181 (such as) may be deposited along the grooves and gaps. Figure 19 As shown, conductive material is filled into the gap between the dielectric layer and the adhesive layer to form a conductive layer 218. The dielectric layer comprises materials with high dielectric constants (dielectric constant greater than 3.7), such as alumina, hafnium oxide, or titanium oxide. The adhesive layer 2181 comprises metal nitrides, such as tungsten nitride, titanium nitride, or tantalum nitride.

[0277] It should be emphasized that after removing the sacrificial layer to form the gap, a single film layer (e.g., metallic tungsten) can be filled into the gap, or a composite film layer (e.g., alumina / metallic tungsten, titanium nitride / metallic tungsten, alumina / titanium nitride / metallic tungsten, etc.) can be filled into the gap, and this disclosure does not impose any limitations.

[0278] In some embodiments, refer to Figure 17 As shown, after forming the groove 229 and before removing the sacrificial layer, the above method further includes:

[0279] A third oxidation process is performed on the first semiconductor layer 203 exposed by the groove 229 to form a third oxide layer 230 covering the sidewalls of the first semiconductor layer exposed by the groove (e.g., Figure 18 (As shown).

[0280] The third oxidation treatment includes any one or a combination of thermal oxidation or plasma thermal oxidation processes, with thermal oxidation being preferred in this embodiment. The constituent material of the third oxide layer 230 includes oxides. In this example, the third oxide layer is a silicon oxide layer.

[0281] It should be noted that acidic solutions (e.g., phosphoric acid) are typically used to remove the sacrificial layer. In this embodiment of the present disclosure, a third oxide layer is formed on the surface of the first semiconductor layer exposed by the groove before removing the sacrificial layer, which can prevent the first semiconductor layer from being corroded by the acidic solution and reduce the formation of defects in the first semiconductor layer.

[0282] In some embodiments, combined with Figure 19 and Figure 20 As shown, the above method further includes: removing the adhesive layer 2181 covering the sidewall of the groove and the third oxide layer;

[0283] The grooves containing the third oxide layer are filled to form a gate gap structure.

[0284] For example, refer to Figure 19 As shown, when a third oxide layer 230 is formed on the surface of the first semiconductor layer 203, the adhesive layer 2181 simultaneously covers the third oxide layer 230. The adhesive layer 2181 covering the sidewalls of the trench and the third oxide layer 230 can be removed simultaneously by dry etching to form a structure as shown. Figure 20 The structure shown. The filled grooves form the grid line gap structure. (Refer to...) Figure 21 As shown, the gate linegage structure includes an electrically insulating layer 219 and a conductive layer 220. The electrically insulating layer 219 is located between the conductive layer 220 and the stacked structure, and also between the first semiconductor layer 203 and the conductive layer 220. The electrically insulating layer 219 can be made of silicon oxide, and the conductive layer 220 can be made of tungsten or polycrystalline silicon. It is understood that the gate linegage structure including the electrically insulating layer 219 and the conductive layer 220 can be used as the common source of a three-dimensional memory.

[0285] In other examples, the grooves in which the electrical isolation layer 219 is formed may be filled with insulating material (e.g., silicon oxide) or semiconductor material (e.g., polysilicon) to form a gate gap structure, which can be used to support the stacked structure or adjust stress.

[0286] In another example, refer to Figure 19 As shown, the grooves formed with the third oxide layer 230 and the adhesive layer 2181 can be filled to form a gate gap structure. It should be understood that, in this example, the adhesive layer 2181 covering the sidewalls of the groove can be retained.

[0287] In some embodiments, the stacked structure includes a core region and a step region; the method further includes:

[0288] Forming conductive contact pillars that penetrate the first dielectric layer covering the stepped area;

[0289] A third semiconductor layer is formed that is electrically connected to the bottom of the channel layer;

[0290] A second dielectric layer is formed covering the first semiconductor layer and the third semiconductor layer;

[0291] A first trench and a second trench are formed that penetrate the second dielectric layer; wherein the first trench exposes the third semiconductor layer; and the second trench exposes the contact pillars.

[0292] A first conductive structure is formed to fill the first trench;

[0293] A second conductive structure is formed to fill the second trench.

[0294] For example, multiple steps can be formed at the ends of the stacked structure by a trim-etch process. The area in the three-dimensional memory that includes multiple steps can be defined as a step region. The multiple steps in the step region can serve as a landing layer for word lines in the three-dimensional memory to bring out the word lines (i.e., conductive layer 218) in the three-dimensional memory.

[0295] For example, refer to Figure 22a As shown, conductive contact pillars 222 can be formed through the first dielectric layer covering the step region before removing the substrate, the first oxide layer, and part of the functional layer. It is understood that when forming the contact pillars 222, the second semiconductor layer can be used as an etch stop layer to reduce the etch penetration of the contact pillars 222 through the second semiconductor layer. In one example, the bottom of the contact pillar 222 may be located on the surface of the second semiconductor layer; in another example, the bottom of the contact pillar 222 may also be located within the second semiconductor layer.

[0296] The components of contact post 222 include conductive materials, such as tungsten, copper, or aluminum.

[0297] For example, refer to Figure 25 As shown, after exposing the bottom of the channel layer, a third semiconductor material layer 223' covering the second semiconductor layer, the functional layer, the channel layer, and the first semiconductor layer can be formed, referring to... Figure 26 As shown, a third semiconductor layer 223 electrically connected to the bottom of the channel layer is formed by planarization treatment (e.g., chemical mechanical polishing), and the bottom surface of the third semiconductor layer 223 is substantially flush with the bottom surface of the first semiconductor layer.

[0298] The materials that make up the third semiconductor layer include: monocrystalline silicon, polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon, etc.

[0299] For example, refer to Figure 27 As shown, dry etching and / or wet etching can be performed to form a through silicon contact (TSC) 224 that penetrates the first semiconductor layer 203, the second protective layer and the second semiconductor layer from the side of the first semiconductor layer 203 that is relatively far away from the contact post 222. The through silicon contact 224 exposes the bottom of the contact post 222.

[0300] For example, refer to Figure 28 As shown, a second dielectric material layer is formed covering the third semiconductor layer, the first semiconductor layer, and the through-silicon via 224. It is understood that the second dielectric material layer also covers the bottom of the contact post. The second dielectric material layer covering the bottom of the contact post is removed by dry etching and / or wet etching to form a second dielectric layer 225 covering the third semiconductor layer, the first semiconductor layer, and the sidewall of the through-silicon via 224. Based on the second dielectric layer 225 covering the sidewall of the through-silicon via 224, a second trench can be formed in the through-silicon via 224, and the second trench exposes the bottom of the contact post.

[0301] For example, refer to Figure 29 As shown, a first trench 226 penetrating the second dielectric layer 225 can be formed by dry etching and / or wet etching, exposing a portion of the third semiconductor layer. By filling the first trench 226 and the second trench with conductive material, a first conductive structure 227 (e.g., ...) can be formed in the first trench 226. Figure 30 As shown), a second conductive structure 228 is formed in the second trench 127 (as shown). Figure 30 (As shown).

[0302] It should be emphasized that the first trench and the second trench can be formed simultaneously or sequentially, and the first trench and the second trench can be filled with conductive material simultaneously or separately; this disclosure does not impose any limitations here. Preferably, the first trench and the second trench are formed simultaneously and filled with conductive material simultaneously, which can reduce the manufacturing steps of the three-dimensional memory and save production costs.

[0303] The constituent materials of the second dielectric layer 225 include insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0304] The constituent materials of the first conductive structure and the second conductive structure include conductive materials, such as tungsten, monocrystalline silicon, polycrystalline silicon or doped polycrystalline silicon, etc. The constituent materials of the first conductive structure and the second conductive structure can be the same or different. It is understood that when the first trench and the second trench are filled with conductive materials at the same time, the constituent materials of the first conductive structure and the second conductive structure are the same.

[0305] In some embodiments, the method further includes:

[0306] A virtual via is formed in the step region; wherein the bottom of the virtual via is located within the first semiconductor layer;

[0307] Fill the virtual through-holes to form a support column.

[0308] For example, refer to Figure 17 As shown, a virtual via can be formed through a first dielectric layer covering the step region, a stacked structure of the step region, a second semiconductor layer, a second protective layer, and part of the first semiconductor layer 203 by dry etching and / or wet etching. By filling the virtual via with insulating material, a support pillar 221 can be formed.

[0309] Understandably, the support pillar 221 can be formed before the sacrificial layer is removed, thus ensuring that the stacked structure is supported and prevented from collapsing when the sacrificial layer is removed through the groove, thereby improving the yield of the 3D memory.

[0310] Figure 31 This is a schematic diagram illustrating the structure of a three-dimensional memory 300 according to an embodiment of the present disclosure. (Refer to...) Figure 31 As shown, the three-dimensional memory 300 includes:

[0311] First semiconductor layer 301;

[0312] The stacked structure 306 is located above the first semiconductor layer 301;

[0313] At least two memory structures 311 extend through the stacked structure 306 and are electrically connected to the first semiconductor layer 301; wherein each memory structure 311 includes a channel layer 310, and the bottom of the channel layer 310 of each memory structure 311 is substantially flush.

[0314] The constituent materials of the first semiconductor layer 301 include: polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon, etc.

[0315] The stacked structure 306 includes alternately stacked insulating layers 304 and conductive layers 305. The conductive layers 305 serve as word lines of the three-dimensional memory, and read, write, and erase operations of the memory are achieved by applying different control voltages. The number of conductive layers 305 in the stacked structure 306 may include 8, 16, 32, 64, 96, 128, or 256 layers, etc., and this disclosure does not impose any limitation.

[0316] The insulating layer 304 is composed of materials such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the insulating layer 304 may be a silicon oxide layer. The conductive layer 305 is composed of conductive materials such as tungsten, cobalt, nickel, titanium, aluminum oxide, hafnium oxide, tungsten nitride, titanium nitride, or polycrystalline silicon. The conductive layer 305 may be a single film layer (e.g., a tungsten metal layer) or a composite film layer (e.g., an aluminum oxide / tungsten metal composite film layer, a titanium nitride / tungsten metal composite film layer, an aluminum oxide / titanium nitride / tungsten metal composite film layer, etc.). This disclosure does not impose any limitations on this.

[0317] The memory structure 311 includes a functional layer and a channel layer 310. The functional layer includes a barrier layer 307, a memory layer 308, and a tunneling layer 309. The barrier layer 307 may include any one or any combination of silicon oxide, silicon oxynitride, and a high dielectric material (dielectric constant greater than 3.7). The memory layer 308 may include any one or any combination of silicon nitride, silicon oxynitride, and silicon. The tunneling layer 309 may include any one or any combination of silicon oxide and silicon oxynitride. In this embodiment, the functional layer is a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO). The channel layer 310 includes any one or any combination of monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

[0318] The bottom of the channel layer 310 of each memory structure 311 is substantially flush, including: the plane containing the bottom of the channel layer 310 of each memory structure 311 is completely flush, or the spacing between the planes containing the bottom of the channel layer 310 of each memory structure 311 is very small and negligible.

[0319] In this embodiment of the disclosure, by setting the bottom of the channel layer of each memory structure to be basically flush, the uniformity of the channel layer height of each memory structure can be improved, thereby improving the uniformity of the memory structure height and which is beneficial to improving the operational performance of the three-dimensional memory.

[0320] In some embodiments, refer to Figure 31 As shown, the bottom of the functional layers of each storage structure 311 is substantially flush. For example, the bottom of the barrier layer 307 of each storage structure 311 is substantially flush, the bottom of the storage layer 308 of each storage structure 311 is substantially flush, and the bottom of the tunneling layer 309 of each storage structure 311 is substantially flush.

[0321] In this embodiment of the disclosure, by setting the bottom of the functional layer of each storage structure to be basically flush, the uniformity of the storage structure height can be further improved, which is beneficial to further improving the operational performance of the three-dimensional memory.

[0322] In some embodiments, the three-dimensional memory 300 further includes:

[0323] The second semiconductor layer 302 is arranged in parallel with the first semiconductor layer 301; wherein the thickness of the first semiconductor layer 301 is greater than the thickness of the second semiconductor layer 302, and the bottom surface of the first semiconductor layer 301 is basically flush with the bottom surface of the second semiconductor layer 302.

[0324] The stacked structure 306 is also located on top of the second semiconductor layer 302;

[0325] The storage structure 311 extends through the stacked structure 306 located above the first semiconductor layer 301.

[0326] For example, combined Figures 24 to 26 It can be seen that during the second etching process, since the first oxide layer and the second protective layer are removed, the resulting back-facing via 231 penetrates the first semiconductor layer and the second protective layer. Therefore, the thickness of the third semiconductor layer 223 formed after filling the back-facing via 231 is greater than the thickness of the first semiconductor layer. Combined with... Figure 25 and Figure 26 As shown, after planarization, the bottom surface of the third semiconductor layer 223 is basically flush with the bottom surface of the first semiconductor layer. That is, as... Figure 31 As shown, the thickness of the first semiconductor layer 301 is greater than the thickness of the second semiconductor layer 302, and the bottom surface of the first semiconductor layer 301 is basically flush with the bottom surface of the second semiconductor layer 302.

[0327] The second semiconductor layer 302 is composed of materials including polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon. The first semiconductor layer 301 and the second semiconductor layer 302 may be composed of the same or different materials; this disclosure does not impose any limitations. It is understood that by employing the manufacturing method of the three-dimensional memory in the embodiments of this disclosure, a structure such as... Figure 31 The three-dimensional memory 300 shown has good uniformity in the height of the storage structure 311, which can improve the operating performance of the three-dimensional memory.

[0328] In some embodiments, refer to Figure 31 As shown, the bottom of the channel layer 310 is located above the second semiconductor layer 302 and is electrically connected to the first semiconductor layer 301.

[0329] In some embodiments, refer to Figure 31 As shown, the three-dimensional memory 300 also includes:

[0330] Stop layer 303 is located between first semiconductor layer 301 and stacked structure 306;

[0331] The memory structure 311 further includes a functional layer surrounding the channel layer 310; wherein the bottom of the functional layer is flush with the bottom surface of the stop layer 303; and the bottom of the channel layer 310 is located between the bottom surface of the stop layer 303 and the top surface of the second semiconductor layer 302.

[0332] For example, combined Figure 24 It is understood that during the second etching, the second semiconductor layer 205 can be used as an etching stop layer to avoid over-etching of the stacked structure and the functional layers located in the stacked structure. It is also understood that the second etching stops at the second semiconductor layer 205; therefore, the bottom of the remaining functional layers is flush with the bottom surface of the second semiconductor layer 205, i.e., as shown below. Figure 31 As shown, the bottom of the functional layer is flush with the bottom surface of the stop layer 303.

[0333] Furthermore, since the etching rate of the second etching on the first oxide layer and part of the functional layer is greater than the etching rate of the second etching on the channel layer, the channel layer 216 located between the first semiconductor layer 203 and the second semiconductor layer 205 can be preserved, i.e., as shown in the figure. Figure 31 As shown, the bottom of the channel layer 310 is located between the bottom surface of the stop layer 303 and the top surface of the second semiconductor layer 302.

[0334] The materials that make up the stop layer 303 include: polycrystalline silicon, amorphous silicon, doped polycrystalline silicon, or doped amorphous silicon.

[0335] In some embodiments, refer to Figure 31 As shown, the three-dimensional memory 300 also includes:

[0336] The gate gap structure penetrates the stacked structure 306 located on the second semiconductor layer 302 and includes: an electrical isolation layer 312 and a conductive layer 313; wherein the electrical isolation layer 312 is located between the stacked structure 306 and the conductive layer 313.

[0337] For example, refer to Figure 31 As shown, the gate gap structure penetrates the stacked structure 306 located on the second semiconductor layer 302 and the second semiconductor layer 302. The electrical isolation layer 312 is also located between the second semiconductor layer 302 and the conductive layer 313. The width of the electrical isolation layer 312 in the second semiconductor layer 302 is greater than the width of the electrical isolation layer 312 in the stacked structure 306.

[0338] In some embodiments, the three-dimensional memory 300 includes a core region and a step region;

[0339] The conductive contact post 315 penetrates the first dielectric layer and the stacked structure 306 covering the stepped area;

[0340] The first conductive structure 316 is electrically connected to the side of the first semiconductor layer 301 that is away from the stacked structure 306.

[0341] The second conductive structure 317 is electrically connected to the conductive contact post 315 on the side closest to the second semiconductor layer 302.

[0342] For example, refer to Figure 31 As shown, the region in the three-dimensional memory 300 that includes multiple storage structures 311 can be defined as the core region, and the region in the three-dimensional memory 300 that includes multiple steps can be defined as the step region. The core region is used for information storage and retrieval, and the step region is used to bring out the conductive layer 305 of the core region.

[0343] The conductive contact post 315 penetrates the first dielectric layer covering the stepped area and the lowest insulating layer 304 of the laminated structure 306. The constituent materials of the contact post 315 include conductive materials, such as tungsten, copper, or aluminum.

[0344] The first conductive structure 316 may include a first conductive pillar and a first conductive layer, wherein the first conductive pillar is located in a second dielectric layer covering the first semiconductor layer 301, and the first conductive layer is electrically connected to the side of the first semiconductor layer 301 that is relatively far away from the stacked structure 306 through the first conductive pillar. The constituent materials of the first conductive structure 316 include tungsten, copper, or aluminum, etc.

[0345] The second conductive structure 317 may include a second conductive pillar and a second conductive layer, wherein the second conductive pillar is located in a second dielectric layer covering the second semiconductor layer 302, and the second conductive layer is electrically connected to the side of the contact pillar 315 that is relatively close to the second semiconductor layer 302 through the second conductive pillar. The constituent materials of the second conductive structure 317 include tungsten, copper, or aluminum, etc.

[0346] It is understood that, in the embodiments of this disclosure, the provision of a first conductive structure and a second conductive structure enables the electrical connection between the three-dimensional memory and the external control circuit, thereby enabling the reading, writing, and erasing operations of the three-dimensional memory.

[0347] In some embodiments, the three-dimensional memory 300 further includes:

[0348] Support column 314, located in the stepped area, is used to support the stacked structure 306.

[0349] The supporting pillar 314 is composed of insulating and / or conductive materials. For example, the supporting pillar 314 may include any one or a combination of silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon or amorphous silicon. In the embodiments of this disclosure, the supporting pillar 314 may include an oxide layer and voids.

[0350] Figure 32 This is a schematic diagram illustrating the structure of a three-dimensional memory 400 according to an embodiment of this disclosure. (Refer to...) Figure 32 As shown, the three-dimensional memory 400 includes:

[0351] Semiconductor layer 401;

[0352] The stacked structure 406 is located on top of the semiconductor layer 401;

[0353] At least two memory structures 411 extend through the stacked structure 406 and are electrically connected to the semiconductor layer 401; wherein each memory structure 411 includes a channel layer 410, the bottom of the channel layer 410 of each memory structure being substantially flush.

[0354] The constituent materials of semiconductor layer 401 can be the same as those of the first semiconductor layer 301, the constituent materials of stacked structure 406 can be the same as those of stacked structure 306, the constituent materials of memory structure 411 can be the same as those of memory structure 311, and the constituent materials of channel layer 410 can be the same as those of channel layer 310. These details will not be elaborated further here.

[0355] It needs to be emphasized that, with Figure 31 The three-dimensional memory 300 shown is different, Figure 32 The three-dimensional memory shown only includes semiconductor layer 401, and does not include... Figure 31 The second semiconductor layer 302 in the middle.

[0356] It is understood that, by employing the manufacturing method of the three-dimensional memory in the embodiments of this disclosure, a structure such as... Figure 32 The three-dimensional memory 400 shown has good uniformity in its storage structure 411, which improves the overall performance of the three-dimensional memory.

[0357] In some embodiments, refer to Figure 32 As shown, the bottom of the channel layer 410 is located within the semiconductor layer 401 and is electrically connected to the semiconductor layer 401.

[0358] In some embodiments, refer to Figure 32 As shown, the three-dimensional memory 400 also includes:

[0359] Stop layer 403 is located between semiconductor layer 401 and stacked structure 406;

[0360] The storage structure 411 also includes a functional layer surrounding the channel layer 410; wherein the bottom of the functional layer is flush with the bottom surface of the stop layer 403.

[0361] The composition of the stop layer 403 can be the same as that of the stop layer 303. The functional layers include a barrier layer 407, a storage layer 408, and a tunneling layer 409. The composition of the barrier layer 407 can be the same as that of the barrier layer 307, the composition of the storage layer 408 can be the same as that of the storage layer 308, and the composition of the tunneling layer 409 can be the same as that of the tunneling layer 309. These details will not be elaborated further here.

[0362] In some embodiments, refer to Figure 32 As shown, the three-dimensional memory 400 also includes:

[0363] The gate gap structure extends through the stacked structure 406 located on the semiconductor layer 401 and includes an electrical isolation layer 412 and a conductive layer 413; wherein the electrical isolation layer 412 is located between the stacked structure 406 and the conductive layer 413.

[0364] The composition of the electrical isolation layer 412 can be the same as that of the electrical isolation layer 312, and the composition of the conductive layer 413 can be the same as that of the conductive layer 313, which will not be described in detail here.

[0365] It needs to be emphasized that, with Figure 31 The three-dimensional memory 300 shown is different, Figure 32 The gate gap structure in the three-dimensional memory 400 shown extends into the semiconductor layer 401.

[0366] In some embodiments, the three-dimensional memory 400 includes: a core region and a step region;

[0367] The conductive contact post 415 penetrates the first dielectric layer and the stacked structure 406 covering the stepped area;

[0368] The first conductive structure 416 is electrically connected to the side of the semiconductor layer 401 that is away from the stacked structure 406.

[0369] The second conductive structure 417 is electrically connected to the conductive contact post 415 on the side closest to the semiconductor layer 401.

[0370] The material of the conductive contact post 415 can be the same as that of the conductive contact post 315, the material of the first conductive structure 416 can be the same as that of the first conductive structure 316, and the material of the second conductive structure 417 can be the same as that of the second conductive structure 317. These details will not be repeated here.

[0371] In some embodiments, the three-dimensional memory 400 further includes:

[0372] Support column 414, located in the stepped area, is used to support the stacked structure 406.

[0373] The materials used to construct support column 414 can be the same as those used to construct support column 314, and will not be described again here. It should be emphasized that... Figure 31 The three-dimensional memory 300 shown is different, Figure 32 The support pillars 414 in the three-dimensional memory 400 shown extend into the semiconductor layer 401.

[0374] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A first semiconductor layer and a stacked structure are sequentially formed on a substrate; A first through-hole is formed, penetrating the stacked structure and the first semiconductor layer, with its bottom remaining within the substrate; A first oxidation process is performed on the first semiconductor layer exposed on the sidewall of the first via to form a first oxide layer; wherein, along the radial direction of the first via, the first oxide layer protrudes toward the axis of the first via; The first through-hole on which the first oxide layer is formed is filled to form a functional layer; A first via on which the functional layer is formed is filled to form a channel layer; wherein the channel layer and the first oxide layer are separated by the functional layer, and the bottom of the channel layer is located above the first semiconductor layer; Remove the substrate, the first oxide layer, and a portion of the functional layer to expose the bottom of the trench layer.

2. The method according to claim 1, characterized in that, The first semiconductor layer includes: a first doped semiconductor layer; The step of sequentially forming a first semiconductor layer and a stacked structure on a substrate includes: A first semiconductor material layer is formed on the substrate; The first semiconductor material layer is subjected to a doping process to form the first doped semiconductor layer.

3. The method according to claim 1, characterized in that, The method further includes: A second semiconductor layer is formed, wherein the second semiconductor layer is located between the first semiconductor layer and the stacked structure; The removal of the substrate, the first oxide layer, and a portion of the functional layer to expose the bottom of the trench layer includes: Perform a first etching to remove the substrate and expose the first oxide layer or the functional layer; A second etching is performed to remove the first oxide layer and a portion of the functional layer to expose the bottom of the channel layer and the second semiconductor layer.

4. The method according to claim 3, characterized in that, The formation of the first via through the stacked structure, the first semiconductor layer, and with its bottom remaining within the substrate includes: A first through-hole is formed, penetrating the stacked structure, the second semiconductor layer, the first semiconductor layer, and with its bottom remaining within the substrate; The method further includes: Before forming the first via, a pretreatment is performed on the second semiconductor layer; wherein the pretreatment is used to reduce the oxidation rate of the second semiconductor layer; After the first via is formed, a second oxidation process is performed on the second semiconductor layer exposed on the sidewall of the first via to form a second oxide layer; wherein, along the radial direction of the first via, the width of the second oxide layer is smaller than the width of the first oxide layer; the second oxidation process is performed simultaneously with the first oxidation process.

5. The method according to claim 4, characterized in that, The second semiconductor layer includes: a second doped semiconductor layer; The formation of the second semiconductor layer includes: Forming a second semiconductor material layer; The preprocessing of the second semiconductor layer includes: An in-situ doping process is performed on the second semiconductor material layer to form the second doped semiconductor layer.

6. The method according to claim 5, characterized in that, The second semiconductor layer further includes: a second intrinsic semiconductor layer; The formation of the second semiconductor layer further includes: The second intrinsic semiconductor layer is formed on the second doped semiconductor layer.

7. The method according to claim 3, characterized in that, The thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

8. The method according to claim 3, characterized in that, The formation of the second semiconductor layer includes: A second semiconductor material layer is formed on the first semiconductor layer; Annealing is performed on the second semiconductor material layer to form the second semiconductor layer.

9. The method according to claim 1, characterized in that, The step of sequentially forming a first semiconductor layer and a stacked structure on a substrate includes: A first semiconductor material layer is formed on the substrate; Annealing is performed on the first semiconductor material layer to form the first semiconductor layer.

10. The method according to claim 1, characterized in that, The width of the first oxide layer located within the first through hole is less than or equal to the width of the first through hole; The top surface of the first oxide layer is substantially flush with the top surface of the first semiconductor layer.

11. The method according to claim 1, characterized in that, The stacked structure includes: an insulating layer and a sacrificial layer that are alternately stacked; After forming the channel layer, and before removing the substrate, the first oxide layer, and a portion of the functional layer to expose the bottom of the channel layer, the method further includes: A groove is formed that extends through the stacked structure and rests at the bottom within the first semiconductor layer; The sacrificial layer is removed through the groove to form a gap between adjacent insulating layers; wherein the sidewalls of the gap expose the functional layer. A conductive layer is formed to fill the gap.

12. The method according to claim 11, characterized in that, After the groove is formed, and before the sacrificial layer is removed, the method further includes: A third oxidation process is performed on the first semiconductor layer exposed by the groove to form a third oxide layer covering the sidewalls of the first semiconductor layer exposed by the groove.

13. The method according to claim 1, characterized in that, The method further includes: A third semiconductor layer is formed that is electrically connected to the bottom of the channel layer.

14. A three-dimensional memory, characterized in that, include: First semiconductor layer; A stacked structure is located above the first semiconductor layer; At least two memory structures extend through the stacked structure and are electrically connected to the first semiconductor layer; wherein each memory structure includes a channel layer, and the bottom of the channel layer of each memory structure is substantially flush with the bottom. A stop layer is located between the first semiconductor layer and the stacked structure.

15. The three-dimensional memory according to claim 14, characterized in that, The three-dimensional memory also includes: A second semiconductor layer is disposed in parallel with the first semiconductor layer; wherein the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer, and the bottom surface of the first semiconductor layer is substantially flush with the bottom surface of the second semiconductor layer; The stacked structure is also located on the second semiconductor layer; The storage structure extends through the stacked structure located above the first semiconductor layer.

16. The three-dimensional memory according to claim 15, characterized in that, The bottom of the channel layer is located above the second semiconductor layer and is electrically connected to the first semiconductor layer.

17. The three-dimensional memory according to claim 15, characterized in that, The three-dimensional memory also includes: A functional layer surrounds the channel layer; wherein the bottom of the functional layer is flush with the bottom surface of the stop layer; the bottom of the channel layer is located between the bottom surface of the stop layer and the top surface of the second semiconductor layer.

Images