Light detection device and light detection system

Abstract

The present invention discloses a light detection device and a light detection system, in which, in a plan view, a first semiconductor region of a first conductive type overlaps with at least a portion of a third semiconductor region, a second semiconductor region overlaps with at least a portion of a fourth semiconductor region of a second conductive type, a height of a potential of the third semiconductor region with respect to a charge of the first conductive type is lower than a height of a potential of the fourth semiconductor region, and a difference between a height of a potential of the first semiconductor region and a height of a potential of the third semiconductor region is greater than a difference between a height of a potential of the second semiconductor region and a height of a potential of the fourth semiconductor region.

Description

[0001] This application is a divisional application of the invention patent application with application date of October 13, 2017, application number 201710949673.5, and invention name “Light detection device and light detection system”. Technical Field

[0002] Aspects of various embodiments are directed to a light detection device and a light detection system that perform photoelectric conversion. Background Art

[0003] Conventionally, it is known to use avalanche (electron avalanche) to double a light detecting device capable of detecting weak light at a single photon level.

[0004] In the specification of US Pat. No. 9,209,336, a single photon avalanche diode (SPAD) is discussed in which a photocarrier originating from a single photon causes avalanche amplification in a PN junction region of a semiconductor region constituting a photoelectric converter.

[0005] In the SPAD discussed in the specification of U.S. Patent No. 9,209,336, a P-type semiconductor region with a high impurity concentration is arranged on the surface of a semiconductor substrate, and an N-type semiconductor region is arranged below the P-type semiconductor region. The N-type semiconductor region is arranged to be included in an N-type epitaxial layer. The P-type semiconductor region and the N-type semiconductor region constitute a PN junction, and a high reverse bias voltage is applied to the PN junction.

[0006] In the SPAD discussed in the specification of U.S. Patent No. 9,209,336, the region where the charge is detected is the PN junction region. A strong electric field is generated in the region where the charge is detected, so there is a possibility of a tunnel effect by the strong electric field in the PN junction. The charge generated by the tunnel effect may become noise by being detected as a false signal in the region where the charge is detected. The charge generated by the tunnel effect increases in proportion to the area of ​​the region where the charge is detected.

[0007] On the other hand, if the area of ​​the region where the charge is detected is reduced, the charge generated by the tunnel effect can be suppressed. However, if the area of ​​the region where the charge is detected is reduced, there is a possibility that the light detection efficiency is reduced. Summary of the invention

[0008] According to one aspect of the embodiments, a device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, and a pixel unit having a plurality of pixels including an avalanche diode arranged on the semiconductor substrate, wherein the avalanche diode includes: a first semiconductor region of a first conductivity type arranged in a first depth; a second semiconductor region arranged to contact the first semiconductor region; a third semiconductor region arranged in a second depth deeper than the first depth relative to the first surface; a fourth semiconductor region of a second conductivity type arranged to contact the third semiconductor region, the second conductivity type being a conductivity type opposite to the first conductivity type; and a fifth semiconductor region arranged in a third depth deeper than the second depth relative to the first surface, and wherein the avalanche diode includes: In the embodiment of the present invention, in a plan view, the first semiconductor region overlaps with at least a portion of the third semiconductor region, the second semiconductor region overlaps with at least a portion of the fourth semiconductor region, and the third semiconductor region and the fourth semiconductor region overlap with the fifth semiconductor region, the height of the potential of the third semiconductor region with respect to charges of the first conductivity type is lower than the height of the potential of the fourth semiconductor region with respect to charges of the first conductivity type, and the difference between the height of the potential of the first semiconductor region with respect to charges of the first conductivity type and the height of the potential of the third semiconductor region with respect to charges of the first conductivity type is greater than the difference between the height of the potential of the second semiconductor region with respect to charges of the first conductivity type and the height of the potential of the fourth semiconductor region with respect to charges of the first conductivity type.

[0009] Further features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic cross-sectional view of an avalanche diode.

[0011] Figure 2A and 2B is a schematic plan view of an avalanche diode.

[0012] Figure 3 is the potential diagram of an avalanche diode.

[0013] Figure 4 is a block diagram of a light detection device.

[0014] Figure 5 is a block diagram of a pixel including an equivalent circuit.

[0015] Figure 6 is a schematic cross-sectional view of an avalanche diode.

[0016] Figures 7A to 7C is a schematic plan view of an avalanche diode.

[0017] Figures 8A to 8DA method of manufacturing an avalanche diode is shown.

[0018] Fig. 9A and 9B is the equivalent circuit diagram.

[0019] Fig.10 is a schematic cross-sectional view of an avalanche diode.

[0020] Fig.11 is a schematic cross-sectional view of an avalanche diode.

[0021] Fig.12 is a schematic cross-sectional view of an avalanche diode.

[0022] Fig.13A and 13B is a schematic plan view of an avalanche diode.

[0023] Fig.14 is a schematic cross-sectional view of an avalanche diode.

[0024] Fig.15A and 15B is a schematic plan view of an avalanche diode.

[0025] Fig.16 is a schematic cross-sectional view of an avalanche diode.

[0026] Fig.17 is a block diagram of the light detection system.

[0027] Fig.18 is a block diagram of the light detection system.

[0028] Fig.19A and 19B is a block diagram of the light detection system.

[0029] Fig. 20 is a schematic cross-sectional view of an avalanche diode. DETAILED DESCRIPTION

[0030] Various exemplary embodiments, features, and aspects of the disclosure will be described in detail below with reference to the drawings.

[0031] Will refer to Figures 1 to 3 A light detection device according to an exemplary embodiment is described. The light detection device according to the present exemplary embodiment has a pixel including an avalanche diode. The conductivity type of the charge used as the signal charge in a pair of charges generated in the avalanche diode is referred to as a first conductivity type. The opposite conductivity type of the first conductivity type is referred to as a second conductivity type.

[0032] Figure 11 is a schematic cross-sectional view of an avalanche diode according to the present exemplary embodiment. The avalanche diode in the present exemplary embodiment is arranged in a semiconductor substrate 15. The semiconductor substrate 15 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front side of the semiconductor substrate 15, and the second surface is the back side of the semiconductor substrate 15. In the present exemplary embodiment, the depth direction is defined as the direction from the first surface toward the second surface. The gate electrode of the transistor and the multilayer interconnection structure are arranged on the front side of the semiconductor substrate 15.

[0033] exist Figure 1 In the embodiment, a first semiconductor region 71 of the first conductivity type, a second semiconductor region 76 , a third semiconductor region 74 , a fourth semiconductor region 72 of the second conductivity type, and a fifth semiconductor region 75 are arranged in a region surrounded by the isolation portion 16 .

[0034] The first semiconductor region 71 and the second semiconductor region 76 are arranged in the first depth X. The first semiconductor region 71 and the second semiconductor region 76 are in contact. The second semiconductor region 76 is arranged between the first semiconductor region 71 and the isolation portion 16. Here, the first semiconductor region 71 and the second semiconductor region 76 are arranged in the first depth X means that, for example, a region of the highest implanted impurity concentration (peak) is arranged in the first depth X. However, the peak does not necessarily need to be arranged in the first depth X, and a design error or a manufacturing error is allowed.

[0035] The third semiconductor region 74 and the fourth semiconductor region 72 are arranged at a second depth Y relative to the first surface that is deeper than the first depth X. The third semiconductor region 74 and the fourth semiconductor region 72 are in contact.

[0036] The first semiconductor region 71 overlaps at least a portion of the third semiconductor region 74, and the second semiconductor region 76 overlaps at least a portion of the fourth semiconductor region 72. The fourth semiconductor region 72 is arranged between the third semiconductor region 74 and the isolation portion 16.

[0037] The fifth semiconductor region 75 is arranged at a third depth Z deeper than the second depth Y with respect to the first surface. The third semiconductor region 74 and the fourth semiconductor region 72 overlap with the fifth semiconductor region 75 .

[0038] Figure 2A and 2B It is a schematic plan view. Figure 2A shows a schematic plan view at a first depth X, Figure 2B A schematic plan view at a second depth Y is shown.

[0039] like Figure 2AAs shown, the first semiconductor region 71 is included in the second semiconductor region 76 in the first depth X. The second semiconductor region 76 is included in the isolation portion 16 .

[0040] like Figure 2B As shown, the third semiconductor region 74 is included in the fourth semiconductor region 72 at the second depth Y. The fourth semiconductor region 72 is included in the isolation portion 16. Figures 1 to 2B It can be seen that the first semiconductor region 71 overlaps at least a portion of the third semiconductor region 74, and the third semiconductor region 74 and the fourth semiconductor region 72 overlap the fifth semiconductor region 75 in a plan view.

[0041] Figure 3 A potential diagram showing an avalanche diode. Figure 3 Show Figure 1 2. An example of potential distribution of line segment JK and line segment GH in the cross-sectional view shown. Dotted line 20 shows the potential distribution of line segment GH, and solid line 21 shows the potential distribution of line segment JK. Here, the potential observed from the electron as signal charge is shown. If the signal charge is composed of holes, the relationship of the potential level is opposite.

[0042] In addition, Figure 3 The depths X, Y, Z, and W correspond to Figure 1 Each depth shown, and depth W is any depth between depth Y and depth Z.

[0043] The potential level of the XH level shows the potential level of the fourth semiconductor region 72. The potential level of the H level shows the potential level of the third semiconductor region 74. The potential level of the M level shows the potential level of the second semiconductor region 76. The potential level of the L level shows the potential level of the first semiconductor region 71. Here, it is assumed that the potential level of the second semiconductor region 76 is lower than the potential level of the third semiconductor region 74, but the relationship may be reversed.

[0044] The dotted line 20 shows a potential level between the XH level and the H level in the depth Z. As the depth approaches the depth W from the depth Z, the potential gradually decreases. Then, as the depth approaches the depth Y from the depth W, the potential gradually increases to reach the XH level in the depth Y. As the depth approaches the depth X from the depth Y, the potential gradually decreases. The potential reaches the M level in the depth X.

[0045] The solid line 21 shows the potential level between the XH level and the H level in the depth Z. Before the depth approaches the depth Y from the depth Z, the potential gradually decreases. When the depth approaches the depth Y, the potential level starts to drop sharply to reach the potential level of the H level in the depth Y. Before the depth approaches the depth X from the depth Y, the potential level drops sharply. Then, the potential level reaches the L level in the depth X.

[0046] The potentials of the dotted line 20 and the solid line 21 have almost the same level at the depth Z, and have a potential gradient gradually decreasing toward the first surface side of the semiconductor substrate 15 in the region indicated by the line segment GH and the line segment JK. Therefore, the charges generated in the light detecting device move to the first surface side due to the gradual potential gradient.

[0047] As the depth approaches the depth Y from the depth W, the solid line 21 has a potential gradient that gradually decreases, and the charge moves to the first surface side. On the other hand, the dotted line 20 forms a potential gradient that acts as a potential barrier for the charge moving to the first surface. The potential barrier (the fourth semiconductor region 72) inhibits the charge from moving from the fifth semiconductor region 75 to the second semiconductor region 76. Since the potential in the direction of movement from the line segment GH to the line segment JK is lower than the potential barrier, from the depth W to the depth Y, the charge present on the line segment GH can easily move to the vicinity of the line segment JK in the process of moving to the first surface.

[0048] The charges that have moved to the vicinity of the region indicated by the line segment JK are accelerated by the steep potential gradient (i.e., the strong electric field from depth Y to depth X), and the accelerated charges reach the first semiconductor region 71. Avalanche amplification occurs in the region from depth Y to depth X. In the region indicated by the line segment GH, on the contrary, compared to the region indicated by the line segment JK (or in particular, the region from depth Y to depth X of the line segment JK), the potential distribution is such that avalanche breakdown does not occur or avalanche breakdown is unlikely to occur. As an example of realizing such a structure, a structure is adopted in which the difference between the potential level of the first semiconductor region 71 and the potential level of the third semiconductor region 74 is greater than the difference between the potential level of the second semiconductor region 76 and the potential level of the fourth semiconductor region 72.

[0049] By adopting such a potential structure, when compared with a conventional structure in which avalanche breakdown occurs through an avalanche diode, noise charges generated by the above-mentioned tunnel effect can be reduced. In addition, according to the avalanche diode in this exemplary embodiment, degradation of sensitivity is not caused. This is because the potential structure allows the signal charge existing in the region of the fifth semiconductor region 75 overlapping the fourth semiconductor region 72 to be easily moved to the first semiconductor region via the third semiconductor region 74.

[0050] More specifically, this is because the potential level of the third semiconductor region 74 is lower than the potential level of the fourth semiconductor region 72. That is, the fourth semiconductor region 72 acts as a potential barrier for signal charges present in the fifth semiconductor region 75, and as a result, the charges can easily move to the first semiconductor region 71 via the third semiconductor region 74.

[0051] exist Figure 3 , the potential structure when the third semiconductor region 74 is a P-type semiconductor region is shown, but if the third semiconductor region 74 is an N-type semiconductor region, then as a potential level, the dotted line 20 is still higher than the solid line 21 at the position Y. In addition, the potential structure when the second semiconductor region 76 is an N-type semiconductor region is shown, but if the second semiconductor region 76 is a P-type semiconductor region, then as a potential level, the dotted line 20 is still higher than the solid line 21 at the position Y.

[0052] Incidentally, the entire area of ​​the first semiconductor region 71 in the plan view overlaps with the third semiconductor region 74. According to this structure, the first semiconductor region 71 and the fourth semiconductor region 72 do not form a PN junction. Therefore, avalanche amplification occurs in the PN junction between the first semiconductor region 71 and the fourth semiconductor region 72, thereby suppressing the generation of noise caused by the tunnel effect.

[0053] Hereinafter, the exemplary embodiments of the present disclosure will be described using specific exemplary embodiments. In each exemplary embodiment, a structure in which the signal charge is composed of electrons is described, but each exemplary embodiment is applicable even if the signal charge is composed of holes. However, in this case, the relationship between each semiconductor region and the potential is opposite.

[0054] Will refer to Figures 4 to 9B A first exemplary embodiment of a light detection device to which the present disclosure can be applied is described. Figures 1 to 3 Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted.

[0055] Figure 4 is a block diagram of a light detection device 1010 of the first exemplary embodiment. The light detection device 1010 includes a pixel unit 106 , a control pulse generation unit 109 , a horizontal scanning circuit unit 104 , a column circuit 105 , a signal line 107 , and a vertical scanning circuit unit 103 .

[0056] A plurality of pixels 100 are arranged in a matrix shape in a pixel unit 106. One pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 converts light into an electric signal. The pixel signal processing unit 102 outputs the converted electric signal to a column circuit 105.

[0057] The vertical scanning circuit unit 103 receives the control pulse supplied from the control pulse generating unit 109 to supply the control pulse to each pixel 100. As the vertical scanning circuit unit 103, a logic circuit such as a shift register or an address decoder is used.

[0058] The signal line 107 supplies a signal output from the pixel 100 selected by the vertical scanning circuit unit 103 to a subsequent circuit of the pixel 100 as a potential signal.

[0059] The signal of each pixel 100 is input to the column circuit 105 via the signal line 107 to perform predetermined processing. The predetermined processing includes noise removal and amplification of the input signal, and conversion to a form for output outside the sensor. For example, the column circuit includes a parallel-serial conversion circuit.

[0060] The horizontal scanning circuit unit 104 supplies a control pulse to the column circuit 105 to sequentially output the signals processed by the column circuit 105 to the output circuit 108 .

[0061] The output circuit 108 includes a buffer amplifier, a differential amplifier, and the like, and outputs the signal output from the column circuit 105 to a recording unit or a signal processing unit outside the light detection device 1010 .

[0062] exist Figure 4 In the embodiment, the pixel 100 may be arranged one-dimensionally in the pixel unit 106, or the pixel unit 106 may include only a single pixel. In addition, a plurality of pixel columns may be divided into blocks to arrange the vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the column circuit 105, and the pixel unit 106 in each block. In addition, the vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the column circuit 105, and the pixel unit 106 may be arranged in each pixel column.

[0063] The function of the pixel signal processing unit 102 does not necessarily need to be provided to each of all pixels 100, and, for example, one pixel signal processing unit 102 may be shared by a plurality of pixels 100 to sequentially perform signal processing. In order to increase the aperture ratio of the photoelectric conversion element 101, the pixel signal processing unit 102 may be provided on a semiconductor substrate different from the photoelectric conversion element 101. In this case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are electrically connected via a connection line provided for each pixel. The vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the signal line 107, and the column circuit 105 may also be provided on different semiconductor substrates as described above.

[0064] Figure 5 An example of a block diagram of a pixel 100 including an equivalent circuit according to the present exemplary embodiment is shown. Figure 5In the embodiment of the present invention, one pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102 .

[0065] The photoelectric conversion element 101 includes a photoelectric conversion unit 201 and a control unit 202 .

[0066] The photoelectric conversion unit 201 generates a pair of charges according to incident light by photoelectric conversion. For the photoelectric conversion unit 201, an avalanche diode is used.

[0067] A potential based on a potential VH higher than the potential VL supplied to the anode is supplied to the cathode of the photoelectric conversion unit 201. Then, a potential is supplied to the anode and cathode of the photoelectric conversion unit 201 so that a reverse bias is applied to allow the photoelectric conversion unit 201 to function as an avalanche diode. By performing photoelectric conversion while supplying such a potential of a reverse bias, charges generated by incident light cause avalanche amplification, generating an avalanche current.

[0068] If the potential difference between the anode and cathode is greater than the breakdown voltage when a reverse bias potential is supplied, the avalanche diode performs Geiger mode operation. A photodiode that detects weak signals at a single photon level at high speed using Geiger mode operation is a single photon avalanche diode (SPAD).

[0069] If the potential difference between the anode and cathode of the photoelectric conversion unit 201 is above the potential difference at which the charge generated in the photoelectric conversion unit 201 causes avalanche amplification, and is equal to or less than the breakdown voltage, the avalanche diode enters the linear mode. An avalanche diode that performs light detection in the linear mode is called an avalanche photodiode (APD). In this exemplary embodiment, the photoelectric conversion unit 201 can operate as an avalanche diode in any mode. The potential difference that causes avalanche amplification will be described below.

[0070] The control unit 202 is connected to the photoelectric conversion unit 201 and a power supply voltage supplying a high potential VH. The control unit 202 has a function of replacing any change in the avalanche current generated by the photoelectric conversion unit 201 with a voltage signal. In addition, the control unit 202 is used as a load circuit (quenching circuit) during signal amplification by avalanche amplification to suppress avalanche amplification by suppressing the voltage supplied to the photoelectric conversion unit 201 (quenching operation). As the control unit 202, for example, a resistance element or an active quenching circuit that actively suppresses avalanche amplification by detecting an increase in avalanche current and performing feedback control is used.

[0071] The pixel signal processing unit 102 includes a waveform shaping unit 203, a counter circuit 209, and a selection circuit 206. The waveform shaping unit 203 shapes the voltage change obtained when the photon level signal is detected to output a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 203. An example of using one inverter as the waveform shaping unit 203 is shown, but a circuit in which a plurality of inverters are connected in series or other circuits having a waveform shaping effect may also be used.

[0072] The pulse signal output from the waveform shaping unit 203 is counted by the counter circuit 209. In the case of an N-bit counter (N: a positive integer), the counter circuit 209 can count the pulse signal of 2 to the power of N up to about a single photon. The count signal is held as a detection signal. When the control pulse pRES is supplied through the drive line 207, the detection signal held in the counter circuit 209 is reset.

[0073] The control pulse pSEL is transmitted from the drive line 208 via the Figure 4 The vertical scanning circuit unit 103 in the embodiment is supplied to the selection circuit 206 to switch the electrical connection and non-connection between the counter circuit 209 and the signal line 107. For example, as the selection circuit 206, a transistor or a buffer circuit that outputs a signal from a pixel is used.

[0074] Incidentally, the electrical connection can be switched by arranging a switch such as a transistor between the control unit 202 and the photoelectric conversion unit 201 or between the photoelectric conversion element 101 and the pixel signal processing unit 102. Similarly, the supply of the high potential VH supplied to the control unit 202 or the low potential VL supplied to the photoelectric conversion element 101 can be electrically switched by using a switch such as a transistor.

[0075] In the pixel unit 106 where a plurality of pixels 100 are arranged in a matrix shape, a captured image can be acquired by a rolling shutter operation in which the count of the counter circuit 209 is sequentially reset for each row and the detected signal held in the counter circuit 209 is sequentially output for each row.

[0076] Alternatively, the captured image may be acquired by a global electronic shutter operation in which the counts of the counter circuits 209 of all pixel rows are reset simultaneously and the detection signals held in the counter circuits 209 are sequentially output for each row. When the global electronic shutter operation is performed, it is preferable to provide a unit for switching between a case where counting is performed and a case where counting is not performed by the counter circuit 209. For example, the unit to be switched is the above-mentioned switch.

[0077] In the present exemplary embodiment, there is shown a structure in which a captured image is acquired by using the counter circuit 209. However, instead of the counter circuit 209, the light detecting device 1010 that acquires pulse detection timing may be configured by using a time-to-digital converter (TDC) and a memory.

[0078] In this case, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by TDC. The control pulse pREF (reference signal) is transmitted from the drive line Figure 4 The vertical scanning circuit unit 103 in the control circuit 200 is supplied to the TDC to measure the timing of the pulse signal. When the signal output from each pixel via the waveform shaping unit 203 is set to a relative time with respect to the input timing of the control pulse pREF, the TDC acquires the signal as a digital signal.

[0079] For example, a delay line system in which buffer circuits are connected in series to generate delay or a ring TDC system in which delay lines are connected like a ring is used as a circuit of TDC. Although other systems can be used, a circuit system capable of achieving a time resolution equal to or higher than the time resolution of the photoelectric conversion unit 201 is used.

[0080] The digital signal indicating the pulse detection timing obtained by the TDC is stored in one or more memories. When a plurality of memories are arranged, the output to the signal line 107 can be controlled for each memory by supplying a plurality of signals to the selection circuit 206 when the digital signal stored in the memory is output to the signal line 107.

[0081] Will refer to Figures 6 to 7C A schematic cross-sectional view and a schematic plan view of an avalanche diode according to the present exemplary embodiment are described. Figure 6 In the layout Figure 1 An N-type semiconductor region 1 is arranged in the region of the first semiconductor region 71 in the Figure 1 An N-type semiconductor region 6 is arranged in the region of the second semiconductor region 76. Figure 6 In the layout Figure 1 An N-type semiconductor region 4 is arranged in the region of the third semiconductor region 74, and Figure 1 A P-type semiconductor region 2 is arranged in the region of the fourth semiconductor region 72. Figure 6 In the layout Figure 1 An N-type semiconductor region 5 is arranged in the region of the fifth semiconductor region 75 .

[0082] First, refer to Figure 6 The cross-sectional structure of the isolation portion 16 and the photoelectric conversion region surrounded by the isolation portion 16 are described.

[0083] An isolation portion 16 that separates each of the plurality of pixels 100 is arranged on the semiconductor substrate 15 on which the plurality of pixels 100 are arranged.

[0084] The isolation portion 16 is formed by a P-type semiconductor region arranged from the first surface in the depth direction. More specifically, the P-type semiconductor region 3 and the P-type semiconductor region 7 are arranged in sequence from the first surface along the depth direction and are in contact with the isolation portion 16. The P-type semiconductor region 3 is electrically connected to the P-type semiconductor region 7, the P-type semiconductor region 8 described below, and the P-type semiconductor region 2 described below.

[0085] The impurity concentration of the P-type semiconductor region 3 is higher than the impurity concentrations of the P-type semiconductor region 7, the P-type semiconductor region 8, and the P-type semiconductor region 2. Therefore, for example, connecting the P-type semiconductor region 3 and the contact plug 17 can make the contact resistance lower than the contact resistance connecting the P-type semiconductor region 7 and the contact plug 17.

[0086] The N-type semiconductor region 1 is a region having an impurity concentration higher than that of each of the N-type semiconductor region 6, the N-type semiconductor region 4, and the N-type semiconductor region 5 described below. By adopting such an impurity concentration, the electric field of the depletion layer generated in the N-type semiconductor region 1 can be made strong. Incidentally, a potential as a reverse bias with respect to the isolation portion 16 is supplied to the N-type semiconductor region 1.

[0087] The impurity concentration of the N-type semiconductor region 4 is set lower than the impurity concentration of the N-type semiconductor region 1. Therefore, the charges near the N-type semiconductor region 4 are made to move to the N-type semiconductor region 1 more easily.

[0088] The impurity concentration of the N-type semiconductor region 6 is set to be lower than the impurity concentration of the N-type semiconductor region 1. For example, when the impurity concentration of the N-type semiconductor region 1 is 6.0×10 18 [atms / cm 3 ] or more, the impurity concentration of the N-type semiconductor region 6 is set to 1.0×10 16 [atms / cm 3 ] and above and 1.0×10 18 [atms / cm 3 ]the following.

[0089] exist Figure 6 In the figure, it is shown that Figure 1 The structure in which the N-type semiconductor region 6 having no impurity concentration gradient is arranged in the second semiconductor region 76 in FIG. Figure 1The semiconductor region arranged in the region where the second semiconductor region 76 is arranged is a region having an impurity concentration gradient. By adopting a structure in which the region between the N-type semiconductor region 1 and the P-type semiconductor region 3 has an impurity concentration gradient, a strong electric field that may be generated between the N-type semiconductor region 1 and the P-type semiconductor region 3 can be weakened when compared with a case where the N-type semiconductor region 6 has no impurity concentration gradient.

[0090] Two examples of regions having an impurity concentration gradient will be described. The first example is a case where an N-type semiconductor region having an impurity concentration lower than that of the N-type semiconductor region 1 is arranged in a region near the N-type semiconductor region 1, and an N-type semiconductor region having an impurity concentration lower than that of the above-mentioned N-type semiconductor region is arranged in a region near the isolation portion 16. The second example is a case where an N-type semiconductor region having an impurity concentration lower than that of the N-type semiconductor region 1 is arranged in a region near the N-type semiconductor region 1, and a P-type semiconductor region having an impurity concentration lower than that of the P-type semiconductor region 3 is arranged in a region near the isolation portion 16. More specifically, as Fig. 20 As shown, a P-type semiconductor region 2000 having an impurity concentration lower than that of the P-type semiconductor region 3 is provided between the P-type semiconductor region 3 and the N-type semiconductor region 6 .

[0091] Next, the impurity concentration of the P-type semiconductor region 2 is set to be lower than the impurity concentration of the P-type semiconductor region 7. The P-type semiconductor region 2 and the N-type semiconductor region 4 form a PN junction. Due to the PN junction, the entire region of the N-type semiconductor region 4 becomes a depletion layer region. In addition, the depletion layer region extends to reach a portion of the N-type semiconductor region 1. A strong electric field is induced in the extended depletion layer region. Due to the strong electric field, avalanche amplification occurs in the depletion layer region extending to the portion of the N-type semiconductor region 1, and a current based on the amplified charge is output from the conductor 9. That is, in the present exemplary embodiment, the light detection region becomes the depletion layer region in the portion of the N-type semiconductor region 1.

[0092] In the present exemplary embodiment, the N-type semiconductor region 4 is formed of an N-type region instead of a P-type region, because thereby charges can be taken from a deeper portion by widening the depletion layer deeper into the N-type semiconductor region 5 .

[0093] Furthermore, if the N-type semiconductor region 6 should be a P-type semiconductor region, a depletion layer region may be formed between the P-type semiconductor region and the N-type semiconductor region 1, so that avalanche amplification may occur between the P-type semiconductor region and the N-type semiconductor region 1. In the present exemplary embodiment, the N-type semiconductor region 1 is formed of N type because if the depletion layer region is widened to contact the first surface of the semiconductor substrate 15, noise increases.

[0094] In addition, the impurity concentrations of the N-type semiconductor region 1, the N-type semiconductor region 4, and the P-type semiconductor region 2 are set so that the N-type semiconductor region 1 is not completely depleted when a potential difference is supplied that causes avalanche amplification in a depletion layer region generated in a portion of the N-type semiconductor region 1. This is because if the depletion layer region is widened to contact the first surface of the semiconductor substrate 15, noise may be generated on the first surface of the semiconductor substrate 15. On the other hand, the impurity concentration is set so that the N-type semiconductor region 4 is completely depleted.

[0095] The condition that the N-type semiconductor region 4 is completely depleted is shown in Formula 1. In this case, the impurity concentration of the N-type semiconductor region 4 is the impurity concentration Nd, the impurity concentration of the P-type semiconductor region 2 is the impurity concentration Na, and the basic charge is the basic charge q. In addition, the dielectric constant of the semiconductor is the dielectric constant ε, the potential difference of the PN junction between the N-type semiconductor region 4 and the P-type semiconductor region 2 is the potential difference V, and the length of the N-type semiconductor region 4 surrounded by the P-type semiconductor region 2 is the length D.

[0096] [Mathematical formula 1]

[0097]

[0098] Assume that the impurity concentration of the incompletely depleted N-type semiconductor region 1 is, for example, 6.0×10 18 [atms / cm 3 ] or more. In this case, the impurity concentration of the P-type semiconductor region 2 that satisfies this depletion condition is 1.0×10 16 [atms / cm 3 ] As for the impurity concentration of the N-type semiconductor region 4, the impurity concentration that satisfies this depletion condition is 1.0×10 17 [atms / cm 3 ] or less. However, the impurity concentration is not limited to the above impurity concentration.

[0099] Then, the potential difference between the N-type semiconductor region 1 and the isolation portion 16 is set so that the electric field in the depth direction induced in the extended depletion layer is sufficiently large. Here, the potential difference that makes the electric field sufficiently large is a potential difference at which the charges affected by the electric field cause avalanche amplification. That is, the potential difference is the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3, at which the photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD).

[0100] More specifically, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is greater than 6 V. In this case, as described above, the N-type semiconductor region 4 electrically connected to the N-type semiconductor region 1 completely becomes a depletion layer region, and a strong electric field that can cause avalanche amplification is generated in the depletion layer region extending to a portion of the N-type semiconductor region 1.

[0101] In one embodiment, if the impurity concentration that satisfies the above-mentioned depletion condition is considered, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 is greater than or equal to 10 V and less than or equal to 30 V. At this time, for example, a potential greater than or equal to 10 V is supplied to the N-type semiconductor region 1, and a potential less than or equal to 0 V is supplied to the P-type semiconductor region 3. However, if the potential difference is greater than or equal to 6 V, the potential value is not limited to the above-mentioned value.

[0102] In addition, the depletion layer formed between the P-type semiconductor region 2 and the N-type semiconductor region 6 may extend to the N-type semiconductor region 1 to cause avalanche amplification. In this case, if the N-type semiconductor region 1 is completely depleted, noise may be generated. Therefore, the impurity concentration of the N-type semiconductor region 1 is set so that the N-type semiconductor region 1 is not completely depleted.

[0103] Incidentally, according to the present exemplary embodiment, charges are generated in the N-type semiconductor region 5 and collected and read in the N-type semiconductor region 1. That is, charges generated in the first conductivity type semiconductor region are read from the first conductivity type semiconductor region.

[0104] In contrast, the device discussed in the specification of U.S. Patent No. 9,209,336 reads the charges generated in the N-type epitaxial layer 2 from the p-type anode region 14 after avalanche amplification at the interface between the N-type epitaxial layer 2 and the p-type anode region 14. That is, the charges generated in the semiconductor region of the first conductivity type are read from the semiconductor region of the second conductivity type. Also in this respect, the present exemplary embodiment is different from the device discussed in the specification of U.S. Patent No. 9,209,336.

[0105] exist Figure 6In the example, it is assumed that the N-type semiconductor region 5 having an impurity concentration lower than that of the N-type semiconductor region 1 is arranged directly below the N-type semiconductor region 1 having a high impurity concentration without providing the P-type semiconductor region 2 and the N-type semiconductor region 4. In this case, it is possible to generate charges in the N-type semiconductor region 5 and read the charges from the N-type semiconductor region 1, but it is difficult to achieve avalanche amplification under voltage conditions equivalent to those of the present exemplary embodiment. This is because most of the potential difference applied between the N-type semiconductor region 1 and the P-type semiconductor region 3 is applied to the depletion layer region of the N-type semiconductor region 5, and thus the potential difference applied to the avalanche amplification region near the N-type semiconductor region 1 becomes smaller. On the other hand, in the present exemplary embodiment, the N-type semiconductor region 5 is surrounded by the P-type semiconductor region in all directions except for the position in contact with the N-type semiconductor region 4, and therefore the potential of the N-type semiconductor region 5 is closer to the level of the surrounding P-type semiconductor region than the potential of the N-type semiconductor region 1. That is, by suppressing the excessive expansion of the depletion layer to the deeper part of the substrate in the P-type semiconductor region 2, most of the above-mentioned applied potential difference can be concentrated on the avalanche amplification region near the N-type semiconductor region 1. As a result, avalanche amplification of photocarriers can be performed at lower voltages.

[0106] Next, the impurity concentration of the N-type semiconductor region 5 is equal to or lower than the impurity concentration of the N-type semiconductor region 4. For example, the impurity concentration of the N-type semiconductor region 5 is 1.0×10 17 [atms / cm 3 ] or less. Due to “equal to or less than”, the impurity concentrations of the N-type semiconductor region 5 and the N-type semiconductor region 4 can be equal. In addition, at least, the impurity concentration of the N-type semiconductor region 5 should be less than the impurity concentration of the N-type semiconductor region 1.

[0107] exist Figure 6 , a region of the same impurity concentration is shown as an example of the N-type semiconductor region 5. However, it is better that the N-type semiconductor region 5 has an impurity concentration gradient so that a potential structure that enables charges to move to the first surface side of the semiconductor substrate 15 is realized. By adopting such an impurity concentration gradient, charges can be easily moved to the N-type semiconductor region 1.

[0108] If the impurity concentration gradient enables a potential structure that allows charges to move to the first surface side of the semiconductor substrate 15, then in the area where the N-type semiconductor region 5 is arranged, the first surface side can be an N-type semiconductor region and the second surface side can be a P-type semiconductor region.

[0109] Alternatively, a P-type semiconductor region having an impurity concentration lower than that of the P-type semiconductor region 2 may be arranged instead of the N-type semiconductor region 5. In this case, it is better to have an impurity concentration gradient so that a potential structure that allows charges to move to the first surface side of the semiconductor substrate 15 is achieved.

[0110] For example, a P-type semiconductor region has a first region, a second region arranged at a deeper position than the first region relative to a first surface, and a third region arranged at a deeper position than the second region relative to the first surface. Then, if the first region has a first impurity concentration, the second region has a second impurity concentration, and the third region has a third impurity concentration, the first impurity concentration < the second impurity concentration < the third impurity concentration can be set. Incidentally, the first impurity concentration is lower than the impurity concentration of the P-type semiconductor region 2. Here, the P-type semiconductor region arranged instead of the N-type semiconductor region 5 is divided into three regions, but the present exemplary embodiment is not limited to such an example.

[0111] The P-type semiconductor region 8 is arranged at a deeper position than the N-type semiconductor region 5, and defines the depth of the photoelectric conversion region. The N-type semiconductor region 5 forms a PN junction with each of the P-type semiconductor region 2, the P-type semiconductor region 7, and the P-type semiconductor region 8. The impurity concentration of the P-type semiconductor region 8 is set to be higher than the impurity concentration of the P-type semiconductor region 2. Therefore, the charges generated near the P-type semiconductor region 8 can easily move in the direction of the first surface.

[0112] The contact plug 18 is connected to the N-type semiconductor region 1, and the wire 9 is connected to the contact plug 18. In addition, the contact plug 17 is connected to the P-type semiconductor region 3, and the wire 10 is connected to the contact plug 17. Then, the wire 9 or the wire 10 is connected to the control unit 202 such as a resistance element to perform a quenching operation. In the following, it is assumed that the control unit 202 is connected to the wire 9.

[0113] exist Figure 6 In FIG. 1 , it is assumed that the contact plug 17 and the conductive line 10 are arranged on the first surface side. However, the contact plug 17 and the conductive line 10 may also be arranged on the second surface side.

[0114] In one embodiment, when the contact plug 17 and the conductive line 10 are arranged on the second surface side, the impurity concentration of the region of the P-type semiconductor region 8 where the contact plug 17 is arranged is higher than the impurity concentration of the P-type semiconductor region 7. That is, this region becomes the P-type semiconductor region 3. In this case, the contact plug 17 is not connected to the P-type semiconductor region 3 arranged on the first surface side, and therefore, it is better to set the impurity concentration to a comparable level of the P-type semiconductor region 7. Therefore, the electric field generated between the P-type semiconductor region 3 and the N-type semiconductor region 1 can be weakened.

[0115] When the isolation portion 16 has a dielectric isolation portion on the first surface side, the contact plug 17 and the conductive line 10 are also arranged on the second surface side. In this case, the isolation portion 16 is arranged so that the dielectric isolation portion, the P-type semiconductor region 7, and the P-type semiconductor region 3 are placed on top of each other in sequence from the first surface in the depth direction.

[0116] Next, we will refer to Figures 7A to 7C describe Figure 6 The planar structure of the isolation portion 16 and the photoelectric conversion region surrounded by the isolation portion 16 at any depth of the cross-sectional structure in FIG. Figures 7A to 7C , the boundary of each semiconductor region is depicted as a circle, but the boundary is not limited to such an example.

[0117] Fig. 7A Shows Figure 6 Schematic plan view of line segment AB at a depth X of . The N-type semiconductor region 1 is included in the N-type semiconductor region 6. The N-type semiconductor region 6 is included in the P-type semiconductor region 3. In addition, the area of ​​the N-type semiconductor region 6 is larger than that of the N-type semiconductor region 1.

[0118] Figure 7B Shows Figure 6 Schematic plan view of a line segment CD at a depth Y of . The N-type semiconductor region 4 is included in the P-type semiconductor region 2 . The P-type semiconductor region 2 is included in the P-type semiconductor region 3 .

[0119] Figure 7C Shows Figure 6 Schematic plan view of a line segment EF at a depth Z of φ. The N-type semiconductor region 5 is included in the P-type semiconductor region 7 .

[0120] By the way, when Figure 7B Placed in Figure 7C When the top of the semiconductor region 1 is formed, the N-type semiconductor region 4 and the P-type semiconductor region 2 overlap with the N-type semiconductor region 5 in a plan view.

[0121] In addition, when Fig. 7A Placed in Figure 7B When the top of the semiconductor region 1 is formed, in a plan view, the N-type semiconductor region 1 overlaps with at least a portion of the N-type semiconductor region 4 , and the N-type semiconductor region 6 overlaps with at least a portion of the P-type semiconductor region 2 .

[0122] Next, we will refer to Figures 8A to 8D Described in Figure 6 A method for manufacturing an avalanche diode is shown in the schematic cross-sectional view. Processes not specifically mentioned in sequence may be interchanged as appropriate. Figures 8A to 8D The process whose description is omitted herein can be applied to a known manufacturing method.

[0123] like Fig. 8A As shown, P-type impurity ion implantation (hereinafter referred to as ion implantation) is performed in the region to be the N-type semiconductor region 5 from a direction perpendicular to the first surface of the semiconductor substrate 15. Therefore, the P-type semiconductor region 8 is formed at a deep position from the first surface of the semiconductor substrate 15.

[0124] Next, if Figure 8B As shown, a mask 77 is formed on the first surface of the semiconductor substrate 15. The mask 77 has an opening 30. Then, by performing P-type ion implantation from a direction perpendicular to the first surface of the semiconductor substrate 15, the P-type semiconductor region 3 and the P-type semiconductor region 7 are formed to be arranged in sequence from the first surface. At this time, a portion of the P-type semiconductor region 7 and the P-type semiconductor region 8 are connected. In addition, the impurity concentration of the P-type semiconductor region 3 is set to be higher than the impurity concentration of the P-type semiconductor region 7. More specifically, for example, a method of performing multiple ion implantations with different amounts of ion implantation energy can be used.

[0125] Next, the mask 77 is removed and the mask 78 is disposed. The mask 78 has an opening 32. Then, as Figure 8C As shown, a region to be a P-type semiconductor region 2 is formed by performing P-type ion implantation from a direction parallel to a direction perpendicular to the first surface of the semiconductor substrate 15. Then, a region to be an N-type semiconductor region 6 is formed by performing N-type ion implantation at a position shallower than the position where the P-type ion implantation has been performed to form the region to be a P-type semiconductor region 2. Here, the region to be an N-type semiconductor region 6 is formed after the region to be a P-type semiconductor region 2 is formed, but the order may be reversed.

[0126] Next, the mask 78 is removed and the mask 73 is disposed. The mask 73 has an opening 33. Fig.8D As shown, by performing N-type ion implantation at a depth of the region to be the P-type semiconductor region 2 arranged in a direction parallel to the direction perpendicular to the first surface of the semiconductor substrate 15, an N-type semiconductor region 4 is formed in a portion of the region to be the P-type semiconductor region 2.

[0127] Then, N-type semiconductor region 1 is formed by performing N-type ion implantation on the first surface side of semiconductor substrate 15 from a direction parallel to the direction perpendicular to the first surface of semiconductor substrate 15. Here, N-type semiconductor region 4 is formed first, but N-type semiconductor region 1 may also be formed first.

[0128] Therefore, when ion implantation is performed using impurity ions of the same conductivity type, diffusion of the impurity ions in a direction parallel to the first surface as the incident plane is greater when ion implantation is performed at a deep position relative to the first surface than when ion implantation is performed at a shallow position relative to the first surface. That is, when ion implantation is performed using the same mask, the N-type semiconductor region 1 is included in the N-type semiconductor region 4 in a plan view.

[0129] Impurity ions having different thermal diffusion coefficients can be used as impurity ions implanted to form N-type semiconductor region 1 and N-type semiconductor region 4. According to such a structure, the degree of freedom in potential design of regions where N-type semiconductor region 1 and N-type semiconductor region 4 are arranged is improved.

[0130] exist Fig.8D In the present embodiment, if different masks are used for ion implantation when forming the N-type semiconductor region 1 and the N-type semiconductor region 4, positional shift may occur, and thus a tunnel effect may occur due to the asymmetric electric field distribution. On the other hand, according to the manufacturing method according to this exemplary embodiment, the N-type semiconductor region 1 and the N-type semiconductor region 4 are formed using the same mask, thereby suppressing the positional shift in the two semiconductor regions, and thus suppressing the tunnel effect that may be caused by the positional shift.

[0131] Next, we will refer to Fig. 9A and 9B The control unit 202 according to the present exemplary embodiment is described. In the present exemplary embodiment, the control unit 202 has two structures. Fig. 9A As shown, the first structure is a structure in which the control unit 202 is arranged on the cathode side to which the high potential VH of the photoelectric conversion unit 201 is supplied. Fig. 9B As shown, the second structure is a structure in which the control unit 202 is arranged on the anode side to which the low potential VL of the photoelectric conversion unit 201 is supplied.

[0132] exist Fig. 9A and Fig. 9B In the structure, after the input potential of the waveform shaping unit 203 is changed due to the avalanche current, a fixed time is required to return to the bias of the initial state of the photoelectric conversion unit 201 through the voltage drop of the control unit 202. The period required to return to the bias state capable of detecting the charge after the charge is detected once is called the dead time. The number of charges that can be counted per unit time increases, and the dynamic range as a light detection device increases as the dead time decreases.

[0133] As an example, when the control unit 202 is a resistive element, the dead time (τd [s]) of the avalanche diode according to the present exemplary embodiment is determined by the product of the resistance (R [Ω]) and capacitance (C [F]) at the input terminal. In the following formula, the PN junction capacitance of the photoelectric conversion unit 201 is denoted as Cpd, the capacitance of the well of the photoelectric conversion unit 201 is denoted as Cw, and the parasitic capacitance of the wiring / diffusion layer is denoted as C.

[0134] In Fig. 9A case, the dead time is determined by Equation 2:

[0135] [Equation 2]

[0136] τd = R(Cpd + C)…(Equation 2)

[0137] In Fig. 9B case, the dead time is determined by Equation 3:

[0138] [Equation 3]

[0139] τd = R(Cpd + Cw + C)…(Equation 3)

[0140] The PN junction capacitance Cpd of the photoelectric conversion unit 201 is the PN junction capacitance of the light detection region that senses a strong electric field to cause avalanche amplification. Therefore, the PN junction capacitance Cpd varies proportionally with the area of the light detection region. That is, if the area of the light detection region is increased to improve the light detection efficiency, the PN junction capacitance Cpd increases, resulting in an increase in the dead time. As a result, the dynamic range decreases.

[0141] In other words, there is a trade-off between the light detection efficiency and the dynamic range. On the other hand, according to the pixel structure in the present exemplary embodiment, the area of the light detection region can be reduced while ensuring a large area of the photoelectric conversion region. Therefore, Cpd can be reduced and the dead time can be reduced. Thus, high light detection efficiency and a wide dynamic range can be achieved simultaneously.

[0142] Since the improvement effect of the dynamic range caused by the pixel structure according to the present exemplary embodiment is Fig. 9A more significantly shown in the structure of Fig. 9B than in Fig. 9A and Fig. 9B For example, if the ratio of Cpd of the SPAD structure according to the present exemplary embodiment to Cpd of the conventional SPAD structure is A (0 < A < 1), then

[0143] [Equation 4]

[0144] Δ1 = (1 - A)Cpd / (ACpd + C)…(Equation 4)

[0145] [Mathematical formula 5]

[0146] Δ2=(1-A)Cpd / (ACpd+Cw+C)…(Formula 5)

[0147] In equations 4 and 5, the calculation is performed using the fact that the dynamic range is inversely proportional to the dead time. As is apparent from the above equations, Δ1>Δ2 is satisfied.

[0148] From the above, it can be seen that when Fig. 9A and Fig. 9B When the structure of is applied to the structure according to the present exemplary embodiment, the improvement rate of the dynamic range is Fig. 9A In principle Fig. 9B higher.

[0149] The description has been provided so far on the assumption that the control unit 202 is a resistance element, but this is also true when the control unit 202 is an active quench circuit.

[0150] As can be seen from the above, when the control unit 202 for a pixel according to the present exemplary embodiment is arranged on the cathode side of the photoelectric conversion unit 201 rather than the anode side, the effect of improving the dynamic range can be made greater.

[0151] According to the structure of this exemplary embodiment, it is possible to suppress the degradation of light detection efficiency by forming a path for charge movement. That is, it is possible to reduce noise while suppressing the degradation of light detection efficiency.

[0152] Fig.10 is a schematic cross-sectional view of an avalanche diode according to a second exemplary embodiment. Figure 4 , Figure 5 , Figures 8A to 8D as well as Fig. 9A and 9B Same as in the first exemplary embodiment. Figures 1 to 9B Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted. Fig.10 The difference is that in Figure 6 The P-type semiconductor region 24 is arranged in the region where the N-type semiconductor region 4 is arranged.

[0153] exist Fig.10In the embodiment, the N-type semiconductor region 1 and the P-type semiconductor region 24 form a PN junction. In addition, the P-type semiconductor region 3 is electrically connected to the P-type semiconductor region 24 via the P-type semiconductor region 2. Therefore, the potential of the P-type semiconductor region 24 is the reverse bias potential of the N-type semiconductor region 1. Then, a strong electric field is induced in the PN junction region of the N-type semiconductor region 1 and the P-type semiconductor region 24. Avalanche amplification is caused by the strong electric field in the PN junction region, and a current based on the amplified charge is output from the wire 9 or the wire 10. That is, in the present exemplary embodiment, the light detection region is the PN junction region of the N-type semiconductor region 1 and the P-type semiconductor region 24. If configured in this way, the potential difference required to cause avalanche amplification can be made smaller than that in the first exemplary embodiment. That is, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in the present exemplary embodiment can be made smaller than the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in the first exemplary embodiment.

[0154] exist Fig.10 In the embodiment, the impurity concentration of the P-type semiconductor region 24 is lower than the impurity concentration of the P-type semiconductor region 2 and the impurity concentration of the P-type semiconductor region 7. Figure 3 The above-described potential relationship shown also applies to the present exemplary embodiment.

[0155] The impurity concentration of the N-type semiconductor region 1 is set so that when a potential that generates avalanche amplification in the PN junction is supplied, as described above, the N-type semiconductor region 1 is not completely depleted.

[0156] In the present exemplary embodiment, the impurity concentration at which the N-type semiconductor region 1 is not completely depleted is, for example, 6.0×10 18 [atms / cm 3 Then, the impurity concentration of the P-type semiconductor region 24 is 1.0×10 17 [atms / cm 3 ] or less. This is because, if the depletion layer region is widened to contact the first surface of the semiconductor substrate 15, noise may be generated on the first surface of the semiconductor substrate 15. However, the impurity concentration is not limited to the above example.

[0157] More specifically, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is 6 V or more when the photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD).

[0158] In one embodiment, if the above impurity concentration relationship is considered to be satisfied, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is 10 V or more. In this case, for example, a potential of 10 V or more is supplied to the N-type semiconductor region 1, and a potential of 0 V or less is supplied to the P-type semiconductor region 24 via the P-type semiconductor region 2. However, if the potential difference is 6 V or more, the potential is not limited to the above value.

[0159] When applied in this exemplary embodiment Figures 8A to 8D In the manufacturing method shown in the figure, a P-type semiconductor region 24 is formed by performing N-type ion implantation so that Fig.8D The impurity concentration in a portion of the region to be the P-type semiconductor region 2 is locally reduced.

[0160] Furthermore, in the present exemplary embodiment, similar effects to those in the first exemplary embodiment are achieved.

[0161] Fig.11 is a schematic cross-sectional view of an avalanche diode according to a third exemplary embodiment. Figures 1 to 10 Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted.

[0162] Fig.11 and Figure 6 The potential in the region where the N-type semiconductor region 5 is arranged is different in that the height of the potential of the region farther from the isolation portion 16 in the direction parallel to the first surface is lower than the height of the potential of the region closer to the isolation portion 16 .

[0163] exist Fig.11 In the embodiment, the N-type semiconductor region 28 is arranged in a region closer to the isolation portion 16 in a direction parallel to the first surface, and the N-type semiconductor region 27 is arranged in a region farther from the isolation portion 16 .

[0164] In the present exemplary embodiment, by creating an impurity concentration relationship in which the potential height in the N-type semiconductor region 27 is lower than the potential height in the N-type semiconductor region 28 , charges are made more movable from the N-type semiconductor region 28 to the N-type semiconductor region 27 .

[0165] In other words, the potential height in the region farther from the isolation portion 16 in the direction parallel to the first surface (N-type semiconductor region 27 ) is lower than the potential height in the region closer to the isolation portion 16 (N-type semiconductor region 28 ).

[0166] Therefore, the impurity concentration of the N-type semiconductor region 28 is lower than that of the N-type semiconductor region 27. Then, the impurity concentration of the N-type semiconductor region 27 is made lower than that of the N-type semiconductor region 4 to form a potential gradient for the light detection region.

[0167] If a P-type semiconductor region is arranged instead of the N-type semiconductor region 27 , a P-type semiconductor region having an impurity concentration higher than that of the alternatively arranged P-type semiconductor region is arranged instead of the N-type semiconductor region 28 .

[0168] According to such a structure, if the direction from the position where the isolation portion 16 is arranged toward the position where the N-type semiconductor region 27 is arranged is defined as the in-plane direction, an electric field in the in-plane direction is induced by adopting an impurity distribution that allows charges to move in the in-plane direction. Charges generated deep inside the semiconductor substrate 15 move in the in-plane direction through this electric field.

[0169] According to such a structure, for example, the time required for charges generated deep inside the semiconductor substrate 15 to move to the light detection region can be reduced.

[0170] Furthermore, as described above, a potential is adopted that allows charges to easily move from a deep position to a shallow position of the first surface of the semiconductor substrate 15. By adopting such a potential relationship, the time required for charges to move to the light detection region can be further reduced.

[0171] This exemplary embodiment can be applied to all exemplary embodiments.

[0172] Fig.12 is a schematic cross-sectional view of an avalanche diode according to a fourth exemplary embodiment. Figures 1 to 11 Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted.

[0173] Fig.12 and Figure 6 The P-type semiconductor region 2 in FIG. 1 is different in that a P-type semiconductor region 2B and a P-type semiconductor region 2A having different depths are arranged.

[0174] exist Fig.12 , the P-type semiconductor region 2 includes a P-type semiconductor region 2B and a P-type semiconductor region 2A. The P-type semiconductor region 2A is arranged between the N-type semiconductor region 6 in the first depth X and the P-type semiconductor region 3 constituting the isolation portion 16. The P-type semiconductor region 2B is arranged between the N-type semiconductor region 5 and the N-type semiconductor region 4 in the second depth Y. A portion of the P-type semiconductor region 2A is in contact with the N-type semiconductor region 5, and the other region of the P-type semiconductor region 2A is in contact with the P-type semiconductor region 2B.

[0175] Next, we will refer to Fig.13A and 13B describe Fig.12 The planar structure of the isolation portion 16 and the photoelectric conversion region surrounded by the isolation portion 16 at any depth of the cross-sectional structure in FIG. Fig.13A and 13B In FIG. 1 , the boundary of each semiconductor region is depicted as a circle, but the boundary is not limited to such an example. Incidentally, a schematic plan view of the line segment EF in the depth Z is similar to Figure 7C , so it is omitted.

[0176] Fig.13A Shows Fig.12 Schematic plan view of line segment AB in a first depth X of FIG. N-type semiconductor region 1 is included in N-type semiconductor region 6 . N-type semiconductor region 6 is included in P-type semiconductor region 2A. P-type semiconductor region 2A is included in P-type semiconductor region 3 .

[0177] Fig. 13B Shows Fig.12 Schematic plan view of a line segment CD in a second depth Y of FIG. The N-type semiconductor region 4 is included in the P-type semiconductor region 2B. The P-type semiconductor region 2B is included in the N-type semiconductor region 5. The N-type semiconductor region 5 is included in the P-type semiconductor region 3.

[0178] when Fig.13A Placed in Fig. 13B When the top of the P-type semiconductor region 2A overlaps with the P-type semiconductor region 2B and the N-type semiconductor region 5.

[0179] According to the structure of this exemplary embodiment, Figure 6 A part of the region where the P-type semiconductor region 2 is arranged in the second depth Y is changed to the N-type semiconductor region 5. Therefore, especially when the front illumination type is adopted, the light detection efficiency of the short wavelength light can be improved.

[0180] This exemplary embodiment can be applied to all exemplary embodiments.

[0181] Fig.14 is a schematic cross-sectional view of an avalanche diode according to a fifth exemplary embodiment. Figures 1 to 13B Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted. Fig.14 and Figure 6 The difference is that a plurality of N-type semiconductor regions 1 and a plurality of N-type semiconductor regions 4 are arranged.

[0182] Fig.14 The structure in which each pair of the N-type semiconductor region 1 and the N-type semiconductor region 4 is arranged is shown, but the number of regions is not limited to two as long as more than one region is provided.

[0183] The N-type semiconductor region 1A is surrounded by the N-type semiconductor region 6 . Similarly, the N-type semiconductor region 1B is surrounded by the N-type semiconductor region 6 .

[0184] The N-type semiconductor region 4A is surrounded by the P-type semiconductor region 2 . Similarly, the N-type semiconductor region 4B is surrounded by the P-type semiconductor region 2 .

[0185] Next, we will refer to Fig.15A and 15B describe Fig.14 The planar structure of the isolation portion 16 and the photoelectric conversion region surrounded by the isolation portion 16 at any depth of the cross-sectional structure in FIG. Fig.15A and 15B In FIG. 1 , the boundary of each semiconductor region is depicted as a circle, but the boundary is not limited to such an example. Incidentally, a schematic plan view of the line segment EF in the depth Z is similar to Figure 7C , so it is omitted.

[0186] Fig.15A Shown in Fig.14 Schematic plan view of line segment AB at a depth X of . The N-type semiconductor region 1A and the N-type semiconductor region 1B are both included in the N-type semiconductor region 6. The N-type semiconductor region 6 is included in the P-type semiconductor region 3. The area of ​​the N-type semiconductor region 6 is larger than that of the N-type semiconductor region 1A or the N-type semiconductor region 1B.

[0187] Fig. 15B Shows Fig.14 Schematic plan view of a line segment CD at a depth Y of . The N-type semiconductor region 4A and the N-type semiconductor region 4B are both included in the P-type semiconductor region 2 . The P-type semiconductor region 2 is included in the P-type semiconductor region 7 .

[0188] when Fig. 15B Placed in Figure 7C When the top of the N-type semiconductor region 4A, the N-type semiconductor region 4B and the P-type semiconductor region 2 overlap with the N-type semiconductor region 5.

[0189] In addition, when Fig.15A Placed in Fig. 15B When the N-type semiconductor region 1A is at the top of the N-type semiconductor region 4A in a plan view, the N-type semiconductor region 1B overlaps with at least a portion of the N-type semiconductor region 4B in a plan view. As described above, all regions in the N-type semiconductor region 1 overlap with the N-type semiconductor region 4 in a plan view as if included therein.

[0190] when Fig.15A Placed in Fig. 15B When the top of the N-type semiconductor region 6 is formed, the N-type semiconductor region 6 overlaps with at least a portion of the P-type semiconductor region 2.

[0191] According to the structure in this exemplary embodiment, the average moving distance of the charges generated in the photoelectric conversion region to the light detection region can be shortened by each of the N-type semiconductor regions 1 and the N-type semiconductor regions 4 arranged at a plurality of positions. Therefore, the time required for charge detection of the charges generated at a deep position in the photoelectric conversion region can be reduced.

[0192] This exemplary embodiment can be applied to all exemplary embodiments.

[0193] Fig.16 is a schematic cross-sectional view of an avalanche diode and a control unit according to a sixth exemplary embodiment. Figures 1 to 15B Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted.

[0194] exist Fig.16 , the photoelectric conversion unit 201 and the control unit 202 are arranged on different semiconductor substrates. The structure of the avalanche diode constituting the photoelectric conversion unit 201 is similar to the structure in the first exemplary embodiment. A plurality of units of the photoelectric conversion unit 201 are arranged on the semiconductor substrate 15. Here, as an example, a structure in which two avalanche diodes are arranged is shown. The control unit 202 and the wire 1107 connected to the control unit 202 are arranged on the semiconductor substrate 1102. Here, a structure in which the control unit 202 and the wire 1107 are arranged on the semiconductor substrate 1102 is shown, but other circuits may also be arranged.

[0195] The avalanche diode according to the present exemplary embodiment is configured as a back-side illumination type. Light enters from the N-type semiconductor region 5 in the direction toward the N-type semiconductor region 1. In this case, the light enters the N-type semiconductor region 5 through the microlens 1103 and the color filter 1104.

[0196] As described above, photoelectric conversion occurs in the N-type semiconductor region 5, and the generated charge moves to the N-type semiconductor region 1 through the N-type semiconductor region 4. Avalanche amplification is caused by the electric field between the N-type semiconductor region 1 and the depletion layer generated between the P-type semiconductor region 2 and the N-type semiconductor region 4, so that current flows to the wire 9.

[0197] The wire 9 is connected to the control unit 202 provided on the semiconductor substrate 1102 produced separately via the connection portion 1105 .

[0198] The signal detected for each avalanche diode is processed by a scanning circuit or the like provided in the periphery of the pixel region of the semiconductor substrate 1102. Incidentally, the scanning circuit may also be arranged on a semiconductor substrate different from the semiconductor substrate 15 and the semiconductor substrate 1102.

[0199] According to the structure in the present exemplary embodiment, a semiconductor substrate 1102 different from the semiconductor substrate 15 on which the avalanche diode is arranged is stacked on the semiconductor substrate 15. Then, by arranging a processing circuit such as the control unit 202 on the stacked semiconductor substrate 1102, the light detection efficiency can be improved by increasing the aperture ratio of the avalanche diode.

[0200] When the microlens 1103 is arranged on each avalanche diode in the present exemplary embodiment, a positional relationship is adopted such that the optical axis of the microlens 1103 is included in the N-type semiconductor region 4 in a plan view. If, for example, vertical light enters the central region of the photoelectric conversion element 101, the distribution of the generation probability of the signal charge within the N-type semiconductor region 5 is the largest near the optical axis of the microlens 1103. Here, the optical axis of the microlens 1103 is an axis that passes through the center of the microlens 1103 in a plan view and is perpendicular to the semiconductor substrate 15.

[0201] According to the structure of the present exemplary embodiment, if the optical axis of the microlens 1103 is two-dimensionally included in the N-type semiconductor region 4, charges are more likely to be generated at a position of the N-type semiconductor region 5 close to the N-type semiconductor region 4 in a plan view. Then, the generation probability of charges generated at a position farther in two dimensions can be reduced, so that the degradation of the time resolution before the charges are detected in the light detection region can be suppressed by the charges generated at a shallow position from the first surface of the semiconductor substrate 15 and the charges generated at a deep position thereof.

[0202] In the present exemplary embodiment, a back-side illumination type photodiode is configured, but the front-side illumination type can also achieve the effect according to the present exemplary embodiment, that is, high light detection efficiency and low direct current resistance (DCR) are simultaneously achieved. However, in the present exemplary embodiment, since the photoelectric conversion unit is configured to be formed on the back side, the back-side illumination type can detect the charge generated near the uppermost surface (light incident side) of the substrate more effectively than the front-side illumination type. That is, from the viewpoint of being able to achieve high light detection efficiency in a wide wavelength range from short wavelengths to long wavelengths, for the photoelectric conversion unit 201 of the present exemplary embodiment, the back-side illumination type is adopted.

[0203] This exemplary embodiment can be applied to all exemplary embodiments.

[0204] In the seventh exemplary embodiment, an example of a light detection system using the light detection device 1010 according to each exemplary embodiment will be described. Fig.17 An invisible light detection system and a medical diagnosis system such as positron emission tomography (PET) are described as examples of the light detection system. Figures 1 to 16Units with similar functions are given similar reference numerals, and their detailed descriptions are omitted. Incidentally, the pixel 100 according to the present exemplary embodiment includes a TDC and a memory instead of Figure 5 Here, a description is provided assuming that the TDC is the TDC 204 and the memory is the memory 205.

[0205] Fig.17 1 is a block diagram showing the structure of the invisible light detection system. The invisible light detection system includes a wavelength conversion unit 1201 , a data processing unit 1207 , and a plurality of light detection devices 1010 .

[0206] The illumination source object 1200 emits light of a wavelength range as invisible light. The wavelength conversion unit 1201 receives light of a wavelength range of invisible light emitted from the illumination source object 1200 and emits visible light.

[0207] The photoelectric conversion unit 201 into which the visible light emitted from the wavelength conversion unit 1201 has entered performs photoelectric conversion, and the light detection device 1010 holds a digital signal based on a signal according to the charge after the photoelectric conversion in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. A plurality of light detection devices 1010 may be formed as one device or a plurality of devices arranged.

[0208] The plurality of digital signals of the plurality of light detection devices 1010 held in the memory 205 are subjected to signal processing by the data processing unit 1207. Here, as the signal processing unit, a combination process of a plurality of images obtained from the plurality of digital signals is performed.

[0209] Next, as a specific example of the invisible light detection system, the structure of a medical diagnosis system such as PET will be described.

[0210] The subject as the irradiation source object 1200 emits radiation pairs from inside the body. When the radiation pairs emitted from the subject enter, the wavelength conversion unit 1201 constitutes a scintillator, and the scintillator emits visible light.

[0211] The photoelectric conversion unit 201 into which the visible light emitted from the scintillator has entered performs photoelectric conversion, and the light detection device 1010 holds a digital signal based on a signal according to the charge after the photoelectric conversion in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. That is, the light detection device 1010 is arranged to detect the arrival time of the radiation pair emitted from the object, and detect the visible light emitted from the scintillator and hold the digital signal in the memory 205.

[0212] The digital signals of the plurality of light detection devices 1010 held in the memory 205 are subjected to signal processing by the data processing unit 1207. Here, as a signal processing unit, a combination process such as image reconstruction is performed using a plurality of images obtained from the plurality of digital signals to form an image inside the subject.

[0213] In the eighth exemplary embodiment, an example of a light detection system using the light detection device 1010 according to each exemplary embodiment will be described. Figures 1 to 16 Like reference numerals are attached to units with similar functions, and detailed descriptions thereof are omitted.

[0214] exist Fig.18 A distance detection system will be described as an example of a light detection system. Incidentally, the pixel 100 according to the present exemplary embodiment includes a TDC and a memory instead of Figure 5 Here, a description is provided assuming that the TDC is the TDC 204 and the memory is the memory 205.

[0215] Will refer to Fig.18 An example of a block diagram of a distance detection system according to the present exemplary embodiment is described. The distance detection system includes a light source control unit 1301 , a light emitting unit 1302 , an optical member 1303 , a light detection device 1010 , and a distance calculation unit 1309 .

[0216] The light source control unit 1301 controls driving of the light emitting unit 1302. When receiving a signal from the light source control unit 1301, the light emitting unit 1302 emits short pulses (series) of light in the photographing direction.

[0217] The light emitted from the light emitting unit 1302 is reflected by the subject 1304. The reflected light is received by the photoelectric conversion unit 201 of the light detection device 1010 through the optical member 1303, and a signal based on the photoelectrically converted charge is input to the TDC 204 via the waveform shaping unit 203.

[0218] The TDC 204 compares the signal obtained from the light source control unit 1301 and the signal input from the waveform shaping unit 203. Then, the TDC 204 digitally converts the time from the emission of pulse light from the light emitting unit 1302 to the reception of reflected light reflected by the object 1304 with high accuracy. The digital signal output from the TDC 204 is held in the memory 205.

[0219] The distance calculation unit 1309 calculates the distance from the light detection device 1010 to the object 1304 based on the digital signals from the plurality of measurements held in the memory 205. The distance detection system can be applied as, for example, an in-vehicle system.

[0220] Next, Fig.19A and 19B The Figure 5 An example of a light detection system with a counter circuit 209 in FIG. Fig.19A and 19B , a light detection system associated with a vehicle-mounted camera is shown as an example of the light detection system.

[0221] The light detection system 1000 is a light detection system including a focusing pixel and an imaging pixel according to the present disclosure. The light detection system 1000 includes an image processing unit 1030 that performs image processing on a plurality of digital signals acquired by the light detection device 1010. In addition, the light detection system 1000 includes a parallax calculation unit 1040 that calculates parallax (phase difference between parallax images) based on a plurality of image data acquired by the image processing unit 1030.

[0222] The light detection system 1000 further includes: a distance measurement unit 1050 that calculates the distance to the target object based on the calculated parallax; and a collision determination unit 1060 that determines whether a collision is likely to occur based on the calculated distance. Here, the parallax calculation unit 1040 and the distance measurement unit 1050 are examples of a distance information acquisition unit that acquires distance information to the target object. That is, the distance information is information about parallax, defocus amount, distance to the target object, etc.

[0223] The collision determination unit 1060 can use any of the above information to determine the collision possibility. The distance information acquisition unit can be implemented by specially designed hardware, software modules or a combination thereof. The distance information acquisition unit can also be implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or a combination thereof.

[0224] The light detection system 1000 is connected to the vehicle information acquisition device 1310, and can acquire vehicle information such as vehicle speed, yaw rate, rudder angle, etc. The light detection system 1000 is also connected to the control electronic control unit (ECU) 1410 as a control device to output a control signal for generating a braking force on the vehicle based on the determination result of the collision determination unit 1060.

[0225] The light detection system 1000 is also connected to an alarm device 1420 that issues an alarm to the driver based on the determination result of the collision determination unit 1060. For example, if the possibility of collision is high as a result of the determination of the collision determination unit 1060, the control ECU 1410 performs vehicle control to avoid collision by applying the brake, releasing the accelerator, or controlling the engine output to mitigate damage. The alarm device 1420 issues an alarm by generating an alarm such as a sound, displaying an alarm message on a screen of a car navigation system or the like, or generating vibrations in a seat belt or a steering wheel.

[0226] In this exemplary embodiment, the surroundings of the vehicle (e.g., the front or rear) are imaged by the light detection system 1000. Fig.19B , the light detection system is shown when the front of the vehicle is imaged. The control to prevent collision with other vehicles is described above, but the present exemplary embodiment can also be applied to controlling autonomous driving by following another vehicle or controlling autonomous driving by preventing the vehicle from deviating from the lane. In addition, the light detection system 1000 can be applied not only to vehicles such as local vehicles, but also to moving bodies (mobile devices) such as ships, airplanes, or industrial robots. In addition to moving bodies, the light detection system 1000 can also be applied to equipment that widely uses object recognition such as intelligent transport systems (ITS).

[0227] While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the present disclosure is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A device comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; as well as A pixel unit having a plurality of pixels, each of the plurality of pixels comprising an avalanche diode, the plurality of pixels being arranged on a semiconductor substrate, Among them, avalanche diodes include: an avalanche amplification region including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the first semiconductor region being arranged in a first depth, and the second semiconductor region being arranged in a second depth greater than the first depth relative to the first surface; a charge generation region disposed at a third depth relative to the first surface that is greater than the second depth; and an isolation portion that isolates each of a plurality of pixels arranged in the pixel unit, and Wherein, in a plan view, the area of ​​the region where the first semiconductor region and the second semiconductor region overlap each other is smaller than the area of ​​the charge generation region, In a plan view, an area of ​​a region where the first semiconductor region and the second semiconductor region overlap each other is smaller than an area of ​​the second semiconductor region, and Among them, the charges generated in the charge generation region are collected in the avalanche amplification region.

2. The device according to claim 1, in, The impurity concentration of the first semiconductor region is 6.0 × 10 18 [atms / cm 3 ] above, and The impurity concentration of the second semiconductor region is 1.0 × 10 17 [atms / cm 3 ]the following.

3. The device according to claim 1, in, The charge generation region is a third semiconductor region of the first conductivity type having an impurity concentration lower than that of the first semiconductor region.

4. The device according to claim 1, in, For charges of the first conductivity type, the potential height of the third semiconductor region is lower at a shallow position relative to the first surface than at a deep position relative to the first surface.

5. The device according to claim 3, in, In the third semiconductor region, for charges of the first conductivity type, a potential height of a region farther from the isolation portion in a direction parallel to the first surface is lower than a potential height of a region closer to the isolation portion.

6. The device according to claim 3, in, The second conductivity type sixth semiconductor region is arranged in a position deeper than a position where the third semiconductor region is arranged with respect to the first surface.

7. The device according to claim 6, The isolation part includes: A fourth semiconductor region of the second conductivity type, arranged on one side of the first surface, the impurity concentration of the fourth semiconductor region being higher than the impurity concentration of the second semiconductor region; A fifth semiconductor region of the second conductivity type is arranged in a position deeper than the position where the fourth semiconductor region is arranged relative to the first surface, the impurity concentration of the fifth semiconductor region being higher than the impurity concentration of the second semiconductor region and lower than the impurity concentration of the fourth semiconductor region; and a seventh semiconductor region of the second conductivity type arranged in a position at the same depth as a position where the second semiconductor region is arranged, The second semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the sixth semiconductor region and the seventh semiconductor region are electrically connected.

8. The device according to claim 1, in, The isolation portion includes a dielectric isolation portion, and a contact plug is connected to the second surface.

9. The device according to claim 1, in, The first conductivity type is N type, and the second conductivity type is P type.

10. The apparatus according to claim 1, further comprising a different semiconductor substrate different from the semiconductor substrate, in, a control unit configured to control a potential supplied to the first semiconductor region is arranged on the different semiconductor substrate, wherein the semiconductor substrate and the different semiconductor substrate are stacked, and The first semiconductor region is electrically connected to the control unit via a wire.

11. The device according to claim 1, further comprising a microlens, in, The microlens is arranged so that an optical axis of the microlens overlaps with the second semiconductor region.

12. A light detection system comprising the device according to claim 1, comprising: a wavelength conversion unit configured to convert light in a first wavelength range into light in a second wavelength range different from the first wavelength range; Light of a second wavelength range is emitted from the wavelength conversion unit and enters the device; as well as A signal processing unit is configured to perform a combination process of a plurality of images obtained from a plurality of digital signals corresponding to the second wavelength range and held in the device.

13. A light detection system comprising the device according to claim 1, comprising: a light emitting unit configured to emit light to be detected by the device; as well as A distance calculation unit is configured to calculate a distance using a digital signal corresponding to the light detected by the device and held in the device.

14. A mobile object, comprising: The device according to claim 1; a distance calculation unit configured to acquire distance information indicating a distance to a target object based on a signal from the device; as well as The control unit is configured to control the moving object based on the distance information.

15. A light detection system, comprising the device according to claim 1, the light detection system comprising: A signal processing unit is configured to execute to process the signal from the device.

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