Three-dimensional funnel-shaped spin-transfer torque MRAM cell with non-uniform thickness in each layer

Abstract

The present disclosure relates to a three-dimensional funnel-shaped spin-transfer torque (STT) magnetoresistive random access memory (MRAM) cell in which each layer has a non-uniform thickness. A method for providing a funnel-shaped spin-transfer torque (STT) magnetoresistive random access memory (MRAM) device having a dual magnetic tunnel junction is provided. The method includes providing a metal pillar at a connection to a semiconductor device. The method includes providing a first reference layer on the metal pillar and on a portion of a first interlayer dielectric adjacent to the metal pillar. The method includes providing a first tunnel barrier on the first reference layer and providing a free layer on the first tunnel barrier layer. The method includes providing a second tunnel barrier on the free layer and a second reference layer on the second tunnel barrier in a semiconductor structure having the funnel-shaped spin-transfer torque (STT) MRAM device.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductor memory device technology, and more particularly to magnetoresistive random access memory devices. Background Art

[0002] Magnetoresistive random access memory (MRAM), based on the integration of silicon-based complementary oxide semiconductor (CMOS) and magnetic tunnel junction (MTJ) technology, is currently a promising non-volatile memory technology that has many advantages over other commercial memory types including SRAM, DRAM, flash memory, etc. in terms of write / read speed, power consumption and lifespan. Conventional MRAM devices include a magnetic tunnel junction (MTJ) structure having magnetic layers separated by an intermediate non-magnetic tunnel barrier layer. Digital information can be stored in the memory element and can be represented by the direction of the magnetization vector. In response to the current applied to the MTJ, the magnetic memory element exhibits different resistance values ​​and allows the MRAM device to provide the information stored in the magnetic memory element. Typically, MRAM devices can be manufactured using field effect transistors (FETs) that can access the MRAM device.

[0003] Recent developments in MRAM technology utilize spin transfer torque (STT) in the formation of MRAM devices. STT MRAM devices are formed with a perpendicular MTJ that manipulates the spin of electrons with a polarization current to change the magnetic state of the MTJ's free layer in order to write bits into the memory array. STT MRAM devices utilize spin transfer switching, whereby spin-aligned or polarized electrons in one layer generate torque when flowing onto a second layer, switching the spins in the second layer. Summary of the Invention

[0004] Embodiments of the present invention provide a structure for a funnel-shaped spin-transfer torque (STT) magnetoresistive random access memory (MRAM) device having a single or double magnetic tunnel junction. The semiconductor structure includes a metal pillar at a connection to the semiconductor device. The semiconductor structure includes a first reference layer on the metal pillar wall and on a portion of a first interlayer dielectric adjacent to the metal pillar. The semiconductor structure includes a first tunnel barrier on the first reference layer and a free layer on the first tunnel barrier layer. In addition, the semiconductor structure includes a second tunnel barrier on the free layer and a second reference layer on the second tunnel barrier.

[0005] Embodiments of the present invention provide a method for forming a magnetoresistive random access memory (MRAM) device. The method includes depositing a free layer on an interlayer dielectric layer and on a metal pillar. The metal pillar has angled sides and is located above a contact to a semiconductor device. The method includes depositing a tunnel barrier layer on the free layer. The method includes depositing a reference layer on the tunnel barrier layer. Furthermore, the method includes removing the free layer, the tunnel barrier layer, a horizontal portion of the reference layer, and a top portion of the interlayer dielectric adjacent to the metal pillar, and forming a contact over the remaining portion of the reference layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects, features and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0007] Figure 1 is a cross-sectional view of a pillar for forming a funnel-shaped spin-transfer torque MRAM device according to an embodiment of the present invention.

[0008] Figure 2 is a cross-sectional view of the semiconductor structure after forming a free layer on the pillars according to an embodiment of the present invention.

[0009] Figure 3 is a cross-sectional view of the semiconductor structure after a barrier layer is formed on the free layer according to an embodiment of the present invention.

[0010] Figure 4 is a cross-sectional view of the semiconductor structure after depositing a reference layer on the barrier layer and passivating the reference layer according to an embodiment of the present invention.

[0011] Figure 5 is a cross-sectional view of a semiconductor structure after depositing a top contact layer in accordance with an embodiment of the present invention.

[0012] Figure 6 is a cross-sectional view of the semiconductor structure after etching the top contact layer to form a bit line according to an embodiment of the present invention.

[0013] Figure 7 is a cross-sectional view of a semiconductor structure after depositing an ILD material layer and after performing chemical mechanical polishing (CMP) in accordance with an embodiment of the present invention.

[0014] Figure 8 is a cross-sectional view of a semiconductor structure of a second funnel-shaped STT MRAM device after depositing all layers required to form a DMTJ according to an embodiment of the present invention.

[0015] Figure 9is a cross-sectional view of a semiconductor structure of a second funnel-shaped STTMRAM device having a DMTJ after forming a top contact according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Embodiments of the present invention recognize that there are many technical challenges with conventional structures and methods for forming spin transfer torque (SST) magnetoresistive random access memory (MRAM) devices with perpendicular magnetic anisotropy (PMA). Embodiments of the present invention recognize that conventional STT MRAM with PMA has low switching efficiency due to the difficulty in achieving both high PMA and low damping simultaneously. High PMA materials typically include heavy metal oxides, where heavy metal oxides have high damping due to their strong spin-orbit coupling, while low damping materials do not provide a strong enough PMA to work with barrier layers such as MgO layers. A second approach to achieving high PMA by increasing the number of MgO / ferromagnetic interfaces also does not work because the spin transfer torque transferred by the reference layer only acts on the first ferromagnetic layer and is not large enough to switch the entire composite free layer with additional MgO / ferromagnetic interfaces.

[0017] Embodiments of the present invention recognize that conventional STT MRAM with PMA exhibits reduced PMA in both the free layer and the reference layer of the MTJ as the size of the STT MRAM device decreases. At very small STT MRAM device sizes, both the free layer and the reference layer are unstable. The instability of the reference layer can cause write errors at deeper WER floor levels. The unstable free layer can cause retention errors. Embodiments of the present invention recognize that in conventional STT MRAM with PMA, these instabilities are stronger in smaller STT MRAMs, and therefore, scaling STT MRAMs with very small complementary metal oxide semiconductor (CMOS) based devices or transistors will be challenging and / or limiting.

[0018] Embodiments of the present invention recognize that conventional STT MRAM with PMA may also require a very complex reference layer structure. Embodiments of the present invention recognize that conventional STT MRAM with PMA typically utilizes a synthetic antiferromagnet (SAF) with multiple layers of magnetic material to minimize the local magnetic field from the reference layer acting on the free layer. Depositing multiple layers of material to form the reference layer and the synthetic antiferromagnetic layer complicates the manufacturing process, thereby increasing cost and reducing yield. Furthermore, to ensure good PMA and stability, the reference layer becomes very thick.

[0019] Embodiments of the present invention recognize that conventional STT MRAM with PMA has difficulty achieving both a high magnetoresistance ratio (MR) and fast STT switching. High MR materials that provide good ability to read data typically have high magnetic moments that limit STT switching speeds. Therefore, embodiments of the present invention recognize that conventional STT MRAM with PMA will have difficulty providing a fast switching device that also provides effective read capability when using low MR materials to increase switching speeds. Ideally, a material with high magnetic saturation and low thickness (e.g., in the range of 5 to 20 angstroms) can provide faster switching speeds with good read capability.

[0020] Embodiments of the present invention recognize that for a given size of CMOS transistor current, conventional STT MRAM with PMA is closely related to the MTJ area of ​​the MRAM device, or more specifically, closely related to the resistance in ohms per square micron of the MTJ area. Embodiments of the present invention recognize that conventional STT MRAM with PMA is limited by the size and associated current of the CMOS transistors because smaller MTJs require thinner tunnel barrier layers to match the smaller current of the CMOS transistors. Embodiments of the present invention recognize that tunnel barrier optimization and or thickness is limited by the size of the CMOS select transistors.

[0021] Embodiments of the present invention recognize that conventional STT MRAM with PMA is typically limited to forming memory cells with a free layer above a reference layer. Embodiments of the present invention recognize that forming a stable reference layer above a tunnel barrier layer composed of MgO is challenging, especially when the reference layer is a SAF having multiple layers of magnetic material. For this reason, in most conventional STT MRAM with PMA, the free layer is typically located above the reference layer. However, embodiments of the present invention recognize that a reference layer located above the tunnel barrier layer provides better electrical matching with the n-type CMOS transistor and provides a smoother tunnel barrier layer with better device magnetics and better switching efficiency.

[0022] Embodiments of the present invention recognize that the most efficient MRAM design for conventional STT MRAM with PMA may be a dual MTJ (DMTJ) design, which includes two tunnel barrier layers and two reference layers and a free layer, wherein the first reference layer and the first tunnel barrier layer have a free layer above them and below the second reference layer and the tunnel barrier. In conventional STT MRAM with PMA, forming many magnetic layers in the various reference layers that require SAF becomes extremely difficult.

[0023] Embodiments of the present invention provide a new MRAM geometry for an STT MRAM device and a method for forming the new STT MRAM device using a funnel-shaped semiconductor structure. Embodiments of the present invention use a highly uniform deposition process. In physical vapor deposition or ion beam deposition, a highly parallel beam spans the surface of a semiconductor substrate above the wafer surface, where the semiconductor substrate surface is a three-dimensional surface including a metal pillar structure. Due to the three-dimensional nature of the semiconductor substrate surface, the use of physical vapor deposition or ion beam deposition results in non-uniform thickness within each layer. The method of forming a funnel-shaped STT MRAM device produces variable thickness within each layer of a magnetic tunnel junction (MTJ) structure. A funnel-shaped STT MRAM with an MTJ has ferromagnetic layers separated by an intermediate non-magnetic tunnel barrier layer. The funnel-shaped STT MRAM device includes an MTJ in which the material thickness in each of the MTJ layers on the side of the funnel above the metal pillar is different from the material thickness of each layer in the MTJ on a surface parallel to the semiconductor substrate or wafer surface. Embodiments of the present invention using the new funnel-shaped STT MRAM device can provide different thicknesses for each layer in the MTJ, and additionally provide different thicknesses within each layer of the MTJ.

[0024] Embodiments of the present invention using a novel funnel-shaped SST MRAM structure and methods of forming the funnel-shaped MRAM structure provide a funnel-shaped STT MRAM device that is capable of providing efficient, high switching speeds while overcoming or improving each of the challenges associated with conventional STT MRAM technology discussed above. The non-uniform thickness within each of the MTJ layers is caused by the use of a deposition bevel angle for the layers in the MTJ. For the various layers in the MTJ stack, the deposition bevel angle varies depending on the layer in the MTJ stack being deposited. Embodiments of the present invention provide a funnel-shaped STT MRAM device that can be formed directly on a connection or contact to a CMOS device or transistor.

[0025] Embodiments of the present invention using a novel funnel-shaped STT MRAM device can have a vortex state in the funnel-shaped STT MRAM device structure using a specific ratio of the funnel tube radius to the funnel tube height and appropriate thicknesses for each of the magnetic layers in the MTJ. The vortex state is a closed magnetic flux structure in which the local magnetization vector is curved in the plane of the funnel tube and parallel to the top and bottom sides of the funnel tube. The vortex state of the funnel-shaped STT MRAM structure is energetically stable and further provides adequate retention over a wide temperature range. By using a closed flux vortex state in the funnel-shaped STT MRAM device, the use of short nanofunnels in the funnel-shaped STT MRAM device allows the spin transfer torque to overcome only the exchange force to form a dynamic domain wall that can reverse the bit. In this case, good bit retention will be maintained in very small or ultrasmall funnel-shaped STT MRAM devices in the one to five nanometer range, limited only by superparamagnetism or spin quantum tunneling.

[0026] Due to the presence of vortex states in funnel-shaped STT MRAM devices, embodiments of the present invention do not require PMA materials with heavy metals or multipolar MgO / ferromagnetic interfaces. 25 Fe 75 or Fe 50 Ni 50 The invention relates to a new funnel-shaped STT MRAM device formed by using low-damping magnetic materials such as ferrite and quartz crystals. The use of low-damping magnetic materials in funnel-shaped STT MRAM devices allows for high switching efficiency and speed. In addition, the closed path structure that forms a vortex state provides good magnetic retention in the funnel-shaped STT MRAM device structure at small and extremely small memory cells. In this way, an embodiment of the present invention provides a funnel-shaped STT MRAM device in which a low magnetic moment material is stacked with a CoFeB (CBF) material having various compositions as a free layer to obtain fast switching and good MR signals without the need for PMA or PMA materials. Embodiments of the present invention allow the use of a funnel-shaped STT MRAM device with good exchange or high magnetization while maintaining a low local magnetic field at the edge of the funnel-shaped tube.

[0027] Embodiments of the present invention provide a funnel-shaped STT MRAM device with vortex states in both the free layer and the reference layer. The free layer tube is relatively short and has an exchange length that is greater than the size of the funnel-shaped STT MRAM device. Specifically, according to modeling, the aspect ratio of the funnel tube height to the funnel tube radius of the funnel-shaped STT MRAM device is less than approximately 1.81, so the local magnetization of the nanofunnel bends around the funnel. In this case, the funnel-shaped STT MRAM device with a vortex state has a closed magnetic path. The vortex state of the free layer and the reference layer minimizes the static magneto-coupling between the free layer and the reference layer, thereby simplifying the STT dynamic reversal of the free layer. In addition, the short nanofunnel with a thin free layer is energetically favorable for the generation and propagation of Neel walls along the perimeter of the funnel tube during STT switching. When the local magnetic direction bends along the nanotube wall, STT switching can be fast and efficient, and bit retention is excellent because spontaneous reversal of the entire vortex structure caused by thermal fluctuations is extremely unlikely or difficult.

[0028] Embodiments of the present invention provide a funnel-shaped STT MRAM device that provides both the ability to construct a funnel-shaped STT MRAM device with a free layer on top of a reference layer and the ability to construct an inverted STT MRAM device with a reference layer above or on top of the free layer. Embodiments of the present invention provide a funnel-shaped STT MRAM device with a dual MTJ (DMTJ) device structure that has two stable reference layers and a free layer with the highest possible retention for a given amount of magnetic volume. Additionally, embodiments of the present invention provide a method of forming an STT MRAM device with a non-SAF reference layer that can be thinner and easier to manufacture, and therefore has advantages over various conventional STT MRAM designs.

[0029] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing an integrated circuit (e.g., a semiconductor device). The present embodiment can be practiced in conjunction with integrated circuit manufacturing techniques for MRAM devices currently used in the art, and only includes many commonly practiced process steps necessary to understand the described embodiments. The accompanying drawings represent cross-sectional portions of the MRAM device after manufacture and are not drawn to scale, but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to employ the methods and structures of the present disclosure in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0030] References in the specification to "one embodiment," "another embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0031] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. The terms "overlying," "on top," "over," "on," "on top of," or "on top of" refer to a first element being present on a second element, wherein an intermediate element, such as an interface structure, may be present between the first and second elements. The term "directly contacting" refers to a first element being connected to a second element without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0032] In order not to obscure the presentation of the embodiments of the present invention, in the following detailed description, some processing steps, materials, or operations known in the art may be grouped together for presentation and for illustrative purposes, and may not be described in detail in some examples. In addition, for the sake of brevity and maintaining focus on the distinguishing features of the elements of the present invention, the descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other cases, some known processing steps or operations may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of various embodiments of the present invention. For the purposes of the present invention, the terms funnel-shaped STT MRAM device and funnel-shaped STT MRAM device are considered to be the same or interchangeable.

[0033] Figure 1 1 is a cross-sectional view of a metal pillar for forming a funnel-shaped or funnel-like STT MRAM device according to an embodiment of the present invention. Figure 1 As shown, it includes metal pillars located on a surface, such as a semiconductor wafer ( Figure 1 ) or a surface of a portion of a semiconductor structure over a portion of a semiconductor wafer, wherein the angle of the outer wall of the metal pillar relative to the horizontal surface is angle α, and the deposition angles θ1 and θ2 show the tilted deposition angles relative to a reference direction perpendicular or orthogonal to the horizontal surface, as shown in FIG. Figure 1As shown. In various embodiments, the angle α is in the range of 90 degrees to 45 degrees with respect to the horizontal surface of the semiconductor substrate or wafer (not shown) used to form the metal pillar. The metal pillar has a flat top funnel shape or a flattend cone shape. The deposition angles θ1 and θ2 are inclined deposition angles. The deposition angles θ1 and θ2 are measured relative to a direction perpendicular to the surface of the semiconductor substrate or wafer (or normal to the wafer surface). In various embodiments, the deposition angle θ1 is used to deposit a free layer and one or more reference layers on the metal pillar, while the deposition angle θ2 is used to deposit a tunnel barrier material. The semiconductor wafer (not shown) is placed on a reference Figure 1-9 The funnel-shaped STT MRAM device discussed is rotated during deposition of the various layers.

[0034] Figure 2 FIG. 2 is a cross-sectional view of a semiconductor structure 200 after a free layer 2 is formed on a metal pillar 10 according to an embodiment of the present invention. As shown in the figure, Figure 2 The present invention relates to a semiconductor device (not shown) in a semiconductor substrate or a semiconductor wafer (not shown). ...

[0035] In various embodiments, metal pillar 10 is formed directly above contact 9 and at an angle α to the top surface of ILD 8. As previously mentioned, angle α ranges from 90 degrees to 45 degrees. For example, unless otherwise specified, Figure 2-9 The typical angle α of the funnel-shaped STT MRAM structure depicted in FIG can be in the range of 80 degrees for the typical thickness discussed for each layer. Figure 2 As shown, the metal pillar 10 has a flat top that forms a funnel-like shape of the metal pillar 10, but the top of the metal pillar may also be rounded. In various embodiments, the typical height of the metal pillar 10 ranges from 4 nm to 40 nm, but is not limited to these heights.

[0036] In various embodiments, the free layer 2 is a magnetic material layer deposited at a deposition angle θ1, and the semiconductor substrate or wafer (not shown) containing the semiconductor structure 200 is rotated or spun about an axis perpendicular to the surface of the semiconductor wafer. Figure 1As discussed, the tilted deposition angle (i.e., deposition angle θ1) can typically be 70 to 80 degrees relative to a direction perpendicular to or measured relative to the surface of the semiconductor wafer, however, the deposition angle θ1 is not limited to these angles. In various embodiments, the rotation of the semiconductor substrate or wafer ensures that the material is uniformly deposited along the sides of the metal pillars 10. In various embodiments, the atomic flux is deposited on the top surfaces of the metal pillars 10 and the ILD 8 using, for example, physical vapor deposition (PVD) or ion beam deposition (IBD).

[0037] The oblique deposition of the free layer 2 using the deposition angle θ1 results in two different thicknesses of the deposited free layer 2 on the sides of the metal pillars 10 when compared to the thickness of the deposited free layer 2 on the horizontal surfaces of the semiconductor structure 200. In various embodiments, the free layer 2 is thicker on the sides of the metal pillars 10 and much thinner on the tops of the metal pillars 10 and the ILD 8. For example, with a deposition angle θ1 in the range of 70 to 80 degrees, the thickness of the free layer 2 on the sides of the metal pillars 10 is approximately 15 to 25 angstroms, while the thickness of the free layer 2 on the top surface of the ILD 8 and the top of the metal pillars 10 is in the range of 3 to 5 angstroms. With a deposition angle θ1 of 80 degrees, the thickness of the free layer 2 on the sides of the metal pillars 10 is approximately five times the thickness of the free layer 2 on the horizontal surfaces above the semiconductor wafer surface (not shown) (e.g., on the tops of the metal pillars 10 and on the exposed horizontal surfaces of the ILD 8). In other examples using different angles α of the metal pillars 10 or different deposition parameters, the thickness of the free layer 2 can range from 10 to 50 angstroms on the sides of the metal pillars 10. Due to the angled deposition of the free layer 2, the portion of the free layer 2 located on the surface of the ILD 8 and on top of the pillars 10 is substantially non-conductive due to the very thin layer of material deposited on the horizontal surface. As a result, little or no current flows in the horizontal portion of the free layer 2. Additionally, the very thin horizontal portion of the free layer 2 has substantially little to no magnetization and, therefore, resembles a non-ferromagnetic layer. Consequently, the thin horizontal portion of the free layer 2 does not interfere with the magnetic properties of the thicker portion of the free layer 2 located on the angled sidewalls of the pillars 10.

[0038] The free layer 2 can be made of various magnetic materials with different compositions and thicknesses. For example, the free layer 2 can have one or more compositions of cobalt, iron, and boron (CFB) with a thickness ranging from 10 to 50 angstroms. In another example, the free layer 2 can be Co for low damping. 25 Fe 75and a double layer of CFB for high MR to provide fast switching of funnel-shaped STT MRAM devices. In other examples, the free layer 2 can be CoX or FeX, where X is a light metal such as Li, Be, Mg, Al or any transition metal. In another example, a Heusler alloy such as CoFeAl or NiMnSb and a double layer of ultra-thin CFB for high MR can be used as a low damping material. In yet another example, the free layer 2 can be a double layer of a soft magnetic material such as permalloy (i.e., nickel-iron magnetic alloy) and CFB to avoid domain wall formation. The free layer 2 is not limited to these materials.

[0039] Figure 3 FIG. 3 is a cross-sectional view of a semiconductor structure 300 after a tunnel barrier 3 is formed on the free layer 2 according to an embodiment of the present invention. As shown in the figure, Figure 3 The structure of the free layer 2 includes an ILD 8, a contact 9, a metal pillar 10, a free layer 2, and a tunnel barrier 3. As the free layer 2 and all subsequent MTJ material layers are deposited, the semiconductor substrate or wafer is rotated during deposition. In various embodiments, a deposition angle θ2 is used to deposit the tunnel barrier 3. For example, the tilted deposition angle θ2 can be in the range of 10 to 15 degrees, resulting in a low thickness of the tunnel barrier 3 (approximately 10 angstroms) on the sides of the metal pillar 10, and a thickness of approximately 16 to 40 angstroms on the top of the metal pillar 10 and on top of the ILD 8 (assuming an angle α of 80 degrees). In other examples using different deposition parameters, the thickness of the tunnel barrier 3 on the angled sides of the free layer 2 above the sides of the metal pillar 10 can be in the range of 8 to 20 angstroms (depending on the various materials used as the tunnel barrier). The uneven material thickness deposition of the tunnel barrier 3 results in an extremely thick layer of tunnel barrier 3 on the horizontal surface of the free layer 2 above the ILD 8, and a thick deposition of the tunnel barrier 3 on the free layer 2 above the top or horizontal portion of the metal pillar 10. These thick portions of the tunnel barrier 3 can be considered substantially non-conductive. Current cannot flow through these thick horizontal portions of the tunnel barrier 3, or will be negligible or close to zero. A thinner layer of tunnel barrier 3, approximately 8-20 angstroms thick, can be present on the free layer 2 above the sides of the metal pillar 10, allowing electrons to tunnel through these regions. The portion of the tunnel barrier 3 on the sidewalls of the metal pillar 10 is thin enough to allow electrons to tunnel, and the horizontal portion of the tunnel barrier 3 is thick enough to prevent electrons from tunneling.

[0040] In various embodiments, the tunnel barrier 3 is composed of MgO. In some embodiments, the tunnel barrier 3 is composed of TiO2, CsO x 、BaO x 、SrO x, ZrO2, HfO2, Al2O3, MgAlO, or any combination or compound of these materials that can provide a good tunnel barrier, but the tunnel barrier 3 is not limited to these materials, where x can be any number of oxygen atoms that form a compound material for a good tunnel barrier.

[0041] Figure 4 FIG4 is a cross-sectional view of semiconductor structure 400 after depositing reference layer 4 over tunnel barrier 3 and passivating reference layer 4 according to an embodiment of the present invention. Reference layer 4 is deposited over tunnel barrier 3 using a deposition angle θ1. For example, when using a deposition angle θ1 of 80 degrees, the thickness of the deposited layer on tunnel barrier 3 above the sides of metal pillar 10 ranges from 25 to 35 angstroms, while the thickness of the deposited reference layer 4 on the horizontal surfaces of tunnel barrier 3 (e.g., above ILD 8 and above the top of metal pillar 10) ranges from 3 to 6 angstroms. In other examples, when using different deposition angles, the thickness of reference layer 4 over tunnel barrier 3 above the angled sides of metal pillar 10 can range from 20 to 100 angstroms. Due to the different thicknesses of reference layer 4 on the angled sides of the metal pillar and the horizontal surfaces of semiconductor structure 400, reference layer 4 on tunnel barrier 3 above ILD 8 is substantially non-conductive due to the extremely thin layer of reference layer 4 on the horizontal surfaces (e.g., little to no current flows through it).

[0042] In various embodiments, the reference layer 4 is composed of a CFB. In some embodiments, the reference layer 4 is composed of one or more bilayers of a high-damping material (e.g., a heavy metal) and a CFB to improve the stability of the reference layer 4 during STT switching. In other embodiments, the reference layer 4 is composed of one or more bilayers of an antiferromagnetic layer and a CFB to pin the CFB. In one embodiment, the reference layer 4 is composed of a bilayer of a SAF layer and a CFB layer to minimize stray dynamic fields from the reference layer 4 that may act on the free layer 2 during STT switching.

[0043] In the MTJ stack of a funnel-shaped STT MRAM device, the reference layer 4 can be twice as thick as the free layer 2 or thicker to ensure stability during STT switching. In another embodiment of the MTJ stack, the reference layer 4 is stacked with an antiferromagnetic (AFM) layer to achieve good STT switching. In yet another embodiment of the MTJ stack, the reference layer 4 is stacked with a high-damping layer such as Ta, W, Ir, and Pt.

[0044] In an alternative embodiment, the reference layer 4 is deposited directly on the metal pillar 10. In this embodiment, the tunnel barrier 3 can be deposited directly on the reference layer 4 using the deposition angles previously discussed, and the free layer 2 can be deposited on the tunnel barrier 3 (e.g., deposition angle θ1 for the reference layer 4 and the free layer 2, and deposition angle θ2 for the tunnel barrier 3). When the deposition of each of the layers of the MTJ stack (e.g., the reference layer 4, the tunnel barrier 3, and the free layer 2) is completed, the MTJ stack forms an inverted funnel-shaped STT MRAM device. The MTJ stack used to form an inverse STT MRAM device can have the free layer 2 above the tunnel barrier 3 and the tunnel barrier 3 above the reference layer 4, with the reference layer 4 deposited directly on the metal pillar 10.

[0045] In various embodiments, when the reference layer 4 in the horizontal plane above the ILD 8 is thicker than 5 angstroms and when forming a later Figure 8-9 When the DMTJ of the funnel-shaped STT MRAM device is discussed, a highly parallel oxygen ion beam is used to cause passivation of the reference layer 4. When the thickness of the reference layer 4 in the horizontal portion above the ILD 8 is greater than 5 angstroms, the highly parallel oxygen ion beam can be directed to the top surface of the semiconductor structure 400. Figure 4 As shown, the oxygen ion beam is perpendicular to the horizontal wafer surface. The thickness of the passivation layer in the reference layer 4 varies depending on the location of the reference layer 4. Passivation or oxidation of the reference layer reduces the conductivity of the reference layer 4. The passivated portion of the reference layer 4 becomes resistive.

[0046] In the horizontal portion of reference layer 4, passivation can be performed completely through the thickness of reference layer 4. For example, as depicted in the left-hand breakout portion of the horizontal portion of reference layer 4 above ILD 8, the horizontal portion of reference layer 4 above ILD 8 is completely passivated and will have a very high resistance. The complete passivation of the horizontal portion of reference layer 4 limits the electrical conductance of the horizontal portion of reference layer 4 and causes the horizontal portion to behave similarly to a non-ferromagnetic material. The energy of the oxygen ion beam can be adjusted, for example, between 50 eV and 800 eV, to achieve a desired passivation penetration depth. For example, when the horizontal portion of reference layer 4 is approximately 5 angstroms, the energy of the oxygen ion beam can be adjusted to achieve a passivation thickness of 5 angstroms in the horizontal portion of reference layer 4.

[0047] In semiconductor structure 400, when the thickness of reference layer 4 above the angled side of metal pillar 10 is about 25 to 35 angstroms, the thickness of the passivation of reference layer 4 above the side of metal pillar 10 is very thin, for example, in the range of angstroms. The penetration depth of the passivation on the angled or inclined side of metal pillar 10 is affected by angle α (i.e., the angle of the side of metal pillar 10) and the energy of the oxygen ion beam. An example of the thickness of the passivation of reference layer 4 above the side of metal pillar 10 is shown in the right open figure of reference layer 4 above the side of metal pillar 10.

[0048] Figure 5 is a cross-sectional view of semiconductor structure 500 after top contact 66 deposition according to an embodiment of the present invention. For example, a metal layer for top contact 66 can be deposited over semiconductor structure 500. In some embodiments, the top contact 66 material layer is selectively deposited. For example, a known semiconductor process is used to selectively deposit the top contact 66 layer to form top contact 66 (e.g., to form one or more bit lines). Top contact 66 can be made of any contact metal used in MRAM or CMOS devices.

[0049] Figure 6 6 is a cross-sectional view of a semiconductor structure 600 after forming a top contact 66 according to an embodiment of the present invention. Conventional photolithography and etching processes can be used to selectively pattern and etch the top contact 66 to form the top contact 66. In various embodiments, the top contact 66 can be formed above the reference layer 4. The top contact 66 is above the magnetic layer in the MTJ in the funnel-shaped STT MRAM device. The top contact 66 etching can terminate at the bottom surface of the metal pillar 10 or extend below the bottom surface of the metal pillar 10. In various embodiments, the etching of the top contact 66 continues into the top portion of the ILD 8 adjacent to the metal pillar 10. If the horizontal portion of the MTJ (e.g., the reference layer 4, the tunnel barrier 3, and the free layer 2) is exposed, the horizontal portion of the MTJ can be passivated by exposure to oxygen plasma. In various embodiments, the top contact 66 acts as a bit line.

[0050] Figure 7FIG2 is a cross-sectional view of a semiconductor structure 700 after depositing layers of an ILD 70 and after performing chemical mechanical polishing (CMP) according to an embodiment of the present invention. In various embodiments, an ILD 70 is deposited over the semiconductor structure 700, and CMP is performed until it contacts the top contact 66 to remove a top portion of the ILD 70. In some cases, the CMP may remove a top portion of the top contact 66. The semiconductor structure 700 depicts one embodiment of a funnel-shaped STT MRAM. In various embodiments, the semiconductor structure 700 depicts a funnel-shaped STT MRAM having a single MTJ stack comprised of a free layer 2, a tunnel barrier 3, and a reference layer 4, wherein the free layer 2 is on a metal pillar 10. In various embodiments, the MTJ stack is covered by the top contact 66. In various embodiments, the top surface of the semiconductor structure 700 is exposed for other semiconductor processes, such as etching or deposition processes, to form additional connections, semiconductor devices, or interconnect layers on the semiconductor structure 700. Additional metal, dielectric, or other material layers may be deposited on the semiconductor structure 700 to complete the formation of one or more semiconductor chips.

[0051] As previously discussed, the semiconductor structure 700 forms a funnel-shaped STT MRAM device that provides a stable or closed vortex state in the funnel-shaped STT MRAM device. For the reasons previously discussed, a stable or closed vortex state in a funnel-shaped STT MRAM is desirable. Figure 1-7 Using the methods and structures described above, a funnel-shaped STT MRAM device can be formed with a variety of structures to match a specific transistor resistance. For example, a target resistance of 10 kohm for a funnel-shaped STT MRAM device matching the resistance of a specific CMOS transistor can be achieved for various device geometries. By varying the tunnel barrier properties, such as resistance per area, due to different tunnel barrier geometries and / or materials, the target resistance can be achieved by varying the height-to-diameter ratio of the funnel-shaped STT MRAM device. For example, a tunnel barrier with 20 ohms per square micron, an average funnel radius of 20 nm, and a funnel height of 16 nm provides a very stable vortex state, as does a tunnel barrier with 5 ohms per square micron and a funnel height of 4 nm. This example illustrates that for a wide range of resistance per area of ​​the tunnel barrier 3 (e.g., 5-20 ohms per square micron), the target resistance of the funnel-shaped STT MRAM device can be achieved by varying the height of the funnel-shaped STT MRAM device (i.e., adjusting the nanofunnel height).

[0052] Figure 8 FIG. 8 is a cross-sectional view of a semiconductor structure 800 of a second funnel-shaped or funnel-shaped STT MRAM device having a DMTJ according to an embodiment of the present invention. Figure 1-7 The method discussed in is to deposit the layers in the DMTJ on the metal pillar 10 .

[0053] In various embodiments, a reference layer 81 is deposited on the metal pillar 10. The deposition of the reference layer 81 may be performed using a deposition angle θ1. For example, as previously described, a deposition angle in the range of 80 degrees may provide a thicker deposition of the reference layer 81 (i.e., the first reference layer in the DMTJ) on the angled side surfaces of the metal pillar 10. In some embodiments, the thickness of the reference layer 81 deposited on the sidewalls of the metal pillar 10 is twice as thick or thicker than the portion of the reference layer 81 deposited on horizontal surfaces above the semiconductor wafer surface (e.g., on the flat top of the metal pillar 10 and on the exposed horizontal surface or horizontal portion of the ILD 8). The material and material thickness used for the reference layer 81 may be different from those described with respect to FIG. Figure 4 The materials discussed with reference to layer 4 are the same or similar, but are not limited to these materials or material thicknesses.

[0054] Tunnel barrier 83 may be deposited over reference layer 81. Tunnel barrier 83 is a first tunnel barrier layer that may be composed of MgO, although not limited to this material. Tunnel barrier 83 may be deposited at a deposition angle θ2 to provide a thicker layer on horizontal surfaces of semiconductor structure 800 than on angled surfaces above metal pillars 10.

[0055] A free layer 85 is deposited on the tunnel barrier 83 using a deposition angle θ1 that provides a thicker layer of the free layer 85 above the angled sides of the metal pillars 10 and a much thinner layer of the free layer 85 on the horizontal surfaces of the tunnel barrier 83. In various embodiments, the free layer 85 is a synthetic antiferromagnet (SAF) composed of three layers. Each of the three layers in the free layer 85 is deposited at a deposition angle θ1. The free layer 85 can be made of a first free layer material (e.g., about Figure 2 The two parts of the SAF free layer can be made of materials such as Co, x Fe y B z / Co and Co / Co x Fe y B z The magnetic double layer is made of a magnetic double layer to make a SAF with strong antiferromagnetic coupling. The non-magnetic spacer needs to provide antiferromagnetic Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling between the first and second parts of the free layer 2. Common non-magnetic spacer materials for the middle layer of the free layer 85 can be Ru and Ir. In one embodiment, the structure of the free layer 85 (for example, the structure of the SAF for the free layer 85) can be Cox Fe y B z / Co / Ir / Co / Co x1 Fe y1 B z1 or Co x Fe y B z / Co / Ru / Co / Co x1 Fe y1 B z1 , where x, y, and z represent the number of atoms, and where x1, y1, and z1 represent different numbers of atoms, however, the free layer 85 is not limited to these materials.

[0056] In some embodiments, when the thickness of the horizontal portion of the free layer 85 is greater than 5 angstroms, the free layer 85 may be passivated using an oxygen ion beam process. The passivation may be performed to minimize the conduction of the horizontal portion of the free layer 85. Figure 4 The passivation process is described in detail. For example, the passivation of the free layer 85 can be performed using a highly parallel oxygen ion beam. The passivation can be performed after depositing the first layer of the free layer 85 (e.g., the first free layer of the SAF) or after depositing the second portion of the free layer 85 or the non-magnetic layer.

[0057] Tunnel barrier 87 may be a second tunnel barrier layer. In various embodiments, tunnel barrier 87 is formed of a different material than tunnel barrier 83 and has a different thickness than tunnel barrier 83. For example, tunnel barrier 83 may be formed of MgO, while tunnel barrier 87 may be formed of Mg2AlO4 or another oxide other than MgO. In the horizontal portion of reference layer 85, a typical thickness of tunnel barrier 87 (e.g., where deposition angle θ2 is a 15-degree deposition angle) may be 16 to 40 angstroms.

[0058] A typical thickness of the tunnel barrier 87 on the reference layer 85 above the angled side of the metal pillar 10 (e.g., angle θ2 = 15 degrees) can be 8 to 20 angstroms. By depositing a different material for the tunnel barrier 87 than the tunnel barrier 83 but with a different thickness than the tunnel barrier 83, optimization of the spin torque generated by the DMTJ and the MR signal from the DMTJ can occur simultaneously (e.g., both the MR signal and the spin torque can be maximized simultaneously).

[0059] In various embodiments, a reference layer 89 is deposited over the tunnel barrier 87 using a deposition angle θ2. Depositing the reference layer 89 using the deposition angle θ2 provides a thicker layer of the reference layer 89 on the tunnel barrier 87 over the angled sides of the metal pillar 10, and a thinner deposition of the reference layer 89 on the horizontal surface of the tunnel barrier 87. In some embodiments, the layer of the reference layer 89 deposited on the tunnel barrier 87 over the sidewalls of the metal pillar 10 is two to six times thicker than the portion of the reference layer 89 deposited on the horizontal surface of the tunnel barrier 87 (e.g., over the flat top of the metal pillar 10 and on the tunnel barrier 87 over the semiconductor wafer surface). As previously described, in this manner, the thin horizontal portion of the reference layer 89 is substantially non-conductive or magnetically inactive. In the case where the thickness of the horizontal portion of the second reference layer 89 is greater than 5 angstroms (e.g., is conductive), Figure 4 The passivation step described in can be used to minimize conduction in the horizontal portions of reference layer 89.

[0060] In various embodiments, reference layer 89 is composed of a different material and has a different thickness than reference layer 81. Modifying the material and thickness of reference layer 89 above the sides of metal pillar 10 (i.e., on the angled sides of tunnel barrier 87) based on the material and thickness of reference layer 81 allows optimization of the magnetic stability of reference layer 89. Furthermore, varying the material and thickness of reference layer 89 relative to reference layer 81 provides optimal conditions for setting the magnetization directions of reference layer 89 and reference layer 81. For example, when reference layer 81 is a 30 angstrom thick CFB layer on the angled surface of tunnel barrier 83 (i.e., above the angled sides of metal pillar 10), reference layer 89 can be 50 angstroms thick on the angled sides of tunnel barrier 87. In this case, by cooling the structure in a weak external magnetic field perpendicular to the wafer surface, an antiparallel configuration of vortices can be achieved in the two reference layers. The thickness of reference layer 89 on the angled surface of tunnel barrier 87 can range from 10 to 50 angstroms, but is not limited to these thicknesses. Some examples of materials for reference layer 89 include CFB, permalloy, CoFe, and combinations of these materials stacked with heavy metals to increase dumping. The selection of the specific material and material thickness for reference layer 89 can be optimized in various ways. For example, the specific material and material thickness for reference layer 89 can be selected to achieve one or more of a maximum MR signal, maximum device switching efficiency, to provide good bit stability at elevated temperatures (e.g., in automotive applications), or to ensure good stability of the reference layer.

[0061] Figure 9is a cross-sectional view of semiconductor structure 900 after completion of top contact 66 according to an embodiment of the present invention. The processes of depositing the top contact, etching the top contact 66, depositing ILD 70, and planarizing the top surface of semiconductor structure 900 using CMP have been previously described with reference to FIG. Figure 5-7 Described. Figure 9 In the embodiment, a top contact 66 can be formed around the reference layer 89 using known semiconductor processes for metal contact formation. For example, a metal layer can be deposited, patterned, and etched to form the top contact 66. In various embodiments, the top contact 66 is formed from Figure 9 The etching process of the top contact 66 can end at a level below the bottom surface of the metal pillar 10. In this case, the horizontal portion of the DMTJ (e.g., the reference layer 81, the tunnel barrier 83, the free layer 85, the tunnel barrier 87, and the reference layer 89) that is not adjacent to the metal pillar 10 can be removed. Using known semiconductor processes, a second layer of interlayer dielectric material (i.e., ILD 70) can be deposited over the top surface of the semiconductor structure 900. The ILD 70 can surround the top contact 66, be located on the exposed side of the reference layer 89 of the DMTJ, and be located on the exposed portion of the ILD 9. The ILD 70 is planarized by CMP until the top surface of the top contact 66 is reached, as previously described with respect to Figure 7 The top contact 66 may be used as a bit line in a funnel-shaped STT MRAM device having a DMTJ.

[0062] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure of a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device having a dual magnetic tunnel junction, the semiconductor structure comprising: metal pillars at the connections to the semiconductor device; a first reference layer on the metal pillar and on a portion of the first interlayer dielectric adjacent to the metal pillar; a first tunnel barrier on the first reference layer; a free layer on the first tunnel barrier layer; a second tunnel barrier on the free layer; as well as a second reference layer on the second tunnel barrier, wherein the second reference layer, the free layer, and the first portion of the first reference layer on the sidewalls of the metal pillar are thicker than the second reference layer, the free layer, and the second portion of the first reference layer on a horizontal surface above the surface of the semiconductor wafer and above the flat top of the metal pillar.

2. The semiconductor structure of claim 1, wherein the free layer is a synthetic antiferromagnet. 3 . The semiconductor structure according to claim 2 , wherein the free layer is composed of a first free layer, a nonmagnetic spacer, and a second free layer.

4. The semiconductor structure of claim 1 , wherein the second reference layer, the free layer, and the first portion of the first reference layer on the sidewalls of the metal pillar are twice as thick or thicker than the second portion of the second reference layer, the free layer, and the first reference layer on the horizontal surface above the semiconductor wafer surface and above the flat top of the metal pillar.

5. The semiconductor structure of claim 1 , wherein the second reference layer, the free layer, and the second portion of the first reference layer deposited on the horizontal surface above the semiconductor wafer surface and on the horizontal surface above the flat top of the metal pillar are non-conductive and non-ferromagnetic.

6. The semiconductor structure of claim 1 , wherein a thickness of one or more horizontal portions of the first tunnel barrier and a thickness of one or more horizontal portions of the second tunnel barrier are thicker than a portion of the first tunnel barrier and a portion of the second tunnel barrier deposited on a sidewall of the metal pillar. 7 . The semiconductor structure of claim 1 , wherein the first reference layer, the first tunnel barrier, the free layer, the second tunnel barrier, and the second reference layer form a double magnetic tunnel junction in the funnel-shaped spin-transfer torque MRAM device.

8. The semiconductor structure according to claim 1, further comprising: A contact metal is provided over the second reference layer, wherein a second interlayer dielectric surrounds the contact metal on the second reference layer, the second tunnel barrier, the free layer, the first tunnel barrier, an exposed side of the first reference layer, and on an exposed portion of the first interlayer dielectric.

9. The semiconductor structure of claim 8, wherein the contact metal over the second reference layer serves as a bit line.

10. A semiconductor structure having a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device, the structure comprising: metal pillars at the connections to the semiconductor device; a free layer on the metal post and on a portion of the first interlayer dielectric adjacent to the metal post; a tunnel barrier on the free layer; as well as a reference layer on the tunnel barrier layer, wherein a first portion of the reference layer on the sidewalls of the metal pillar and a first portion of the free layer above the sidewalls of the metal pillar are thicker than one or more portions of the free layer and a second portion of the reference layer on a horizontal surface above a surface of the semiconductor wafer and above a flat top of the metal pillar.

11. The semiconductor structure of claim 10, wherein the free layer is composed of one of the materials in the group consisting of: cobalt iron boron, a bilayer of cobalt iron boron and cobalt iron, a light metal, a bilayer of cobalt iron boron and a Heusler alloy, or a bilayer of cobalt iron boron and a soft magnetic material. 12 . The semiconductor structure of claim 11 , wherein the free layer is composed of one of a double layer of cobalt iron boron and cobalt iron aluminum, a double layer of cobalt iron boron and nickel manganese antimony, or a double layer of cobalt iron boron and permalloy.

13. The semiconductor structure of claim 10 , wherein the thickness of the free layer on the sidewalls of the metal pillars is five times the thickness of the free layer on the horizontal surface above the semiconductor wafer surface and on the horizontal surface above the flat tops of the metal pillars.

14. A method for forming a funnel-shaped spin transfer torque (SST) magnetoresistive random access memory (MRAM) device, the method comprising: depositing a free layer on a metal pillar and on an interlayer dielectric layer, wherein the metal pillar above a contact to a semiconductor device has angled sides; depositing a tunnel barrier layer on the free layer; depositing a reference layer on the tunnel barrier layer; removing the reference layer, the tunnel barrier layer, a horizontal portion of the free layer, and a top portion of the interlayer dielectric adjacent to the metal post; as well as A contact is formed over a remaining portion of the reference layer, wherein a first portion of the reference layer on a sidewall of the metal pillar and a first portion of the free layer above the sidewall of the metal pillar are thicker than one or more portions of the free layer and a second portion of the reference layer on a horizontal surface above a surface of the semiconductor wafer and above a flat top of the metal pillar.

15. The method of claim 14, wherein the free layer and the reference layer are deposited at a first oblique deposition angle, wherein the first oblique deposition angle is in a range of 70 to 80 degrees relative to a reference direction perpendicular to a surface of the semiconductor wafer when the semiconductor wafer is rotated.

16. The method of claim 15 , wherein depositing the free layer and the reference layer is performed using the same deposition angle, which provides a thin portion of the free layer and a thin portion of the reference layer above a horizontal surface of the interlayer dielectric adjacent to the metal pillar and above a top surface of the semiconductor wafer, and wherein the thin portion of the free layer and the thin portion of the reference layer are non-conductive.

17. The method of claim 14, wherein the tunnel barrier layer is deposited at a second oblique deposition angle, wherein the second oblique deposition angle for the tunnel barrier layer is in the range of 10 to 15 degrees measured relative to a reference direction perpendicular to the surface of the semiconductor wafer, and wherein the semiconductor wafer is rotated during the tunnel barrier layer deposition.

18. The method of claim 17, wherein the tunnel barrier layer is deposited at a first oblique deposition angle, wherein a first portion of the tunnel barrier on the sidewall of the metal pillar is thin enough to allow electron tunneling, and one or more horizontal portions of the tunnel barrier are thick enough to prevent electron tunneling.

19. A system for forming a funnel-shaped spin transfer torque (SST) magnetoresistive random access memory (MRAM) device, comprising modules respectively configured to perform the steps of the method according to any one of claims 14 to 18.

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