Level shifter including dummy circuit and method of manufacturing the same

Abstract

The present invention provides a level shifter including dummy circuits and a manufacturing method thereof. The present disclosure provides a technique for a level shifter that allows selection of a single-stage level shifter or a two-stage level shifter by a simple change in wiring. In the case where a single-stage level shifter is selected, some circuits can remain as dummy circuits.

Description

Technical Field

[0001] This disclosure relates to a level converter. Background Technology

[0002] Various electrical devices, such as displays, may include level converters for converting voltage signals from one voltage level to a desired voltage level.

[0003] A level converter can convert a low-voltage input signal into a high-voltage output signal, or vice versa.

[0004] Level converters can take various forms, and these forms are primarily determined by the operating environment of the electrical devices using the level converters. Based on an understanding of these environments, level converter designers tailor their level converters to suit different operating conditions.

[0005] With the diversification of electrical installations and their widespread application in recent years, diverse demands have arisen for the design of level converters. However, this diversity can increase the workload for designers and lead to higher manufacturing costs. Summary of the Invention

[0006] One aspect of this disclosure provides a level shifter technique that is easy to modify in design. Another aspect of this disclosure provides a technique for manufacturing level shifters that allows selection of a single-stage or two-stage level shifter simply by changing the wiring.

[0007] In one aspect, this disclosure provides a level shifter, comprising: a level shifter circuit including a first transistor and a second transistor, the first transistor being turned on and off by an input voltage to generate a voltage having a waveform inversely opposite to the input voltage at an inverting node, and the second transistor being turned on and off by an inverted voltage having a waveform inversely opposite to the input voltage to generate a voltage having the same waveform as the input voltage at an output node; and a dummy circuit including a first dummy transistor and a second dummy transistor, the gate terminal and source terminal of the first dummy transistor being short-circuited by a first short circuit, and the gate terminal and source terminal of the second dummy transistor being short-circuited by a second short circuit, wherein the dummy circuit operates as a two-stage level shifter circuit when the first and second short circuits are removed.

[0008] When the dummy circuit operates as the two-stage level converter circuit, the output voltage can be determined using the voltage at the drain terminal of the second dummy transistor, and the inverted output voltage can be determined using the voltage at the drain terminal of the first dummy transistor.

[0009] The first transistor and the first dummy transistor can be different types of transistors, and the second transistor and the second dummy transistor can be different types of transistors.

[0010] In another aspect, this disclosure provides a level shifter, comprising: a first path circuit in which a first transistor and a third transistor are connected in series between a high drive voltage and a low drive voltage; a second path circuit in which a second transistor and a fourth transistor are connected in series between the high drive voltage and the low drive voltage; a third path circuit in which a first dummy transistor and a third dummy transistor are connected in series between the high drive voltage and the low drive voltage; and a fourth path circuit in which a second dummy transistor and a fourth dummy transistor are connected in series between the high drive voltage and the low drive voltage, wherein an input voltage is supplied to the gate terminal of the first transistor, an inverted voltage having a waveform opposite to the input voltage is supplied to the gate terminal of the second transistor, the drain terminal of the first transistor is electrically connected to an output node, the drain terminal of the second transistor is electrically connected to an inverting node, the output node is electrically connected to the gate terminal of the fourth transistor, and the inverting node is electrically connected to the gate terminal of the third transistor.

[0011] The drain terminal of the first dummy transistor can be electrically connected to the gate terminal of the fourth dummy transistor, and the drain terminal of the second dummy transistor can be electrically connected to the gate terminal of the third dummy transistor.

[0012] In another aspect, this disclosure provides a method for manufacturing a level shifter, the method comprising: placing a transistor mask; forming a first transistor, a second transistor, a first dummy transistor, and a second dummy transistor in accordance with the transistor mask; placing a metal mask; and using the metal mask to mount wiring in such a manner that: the first transistor is turned on and off using an input voltage to generate a voltage having a waveform inversely to the input voltage at an inverting node; the second transistor is turned on and off using an inverting voltage having a waveform inversely to the input voltage to generate a voltage having a waveform identical to the input voltage at an output node; the gate terminal and source terminal of the first dummy transistor are short-circuited; and the gate terminal and source terminal of the second dummy transistor are short-circuited.

[0013] The manufacturing method may further include forming a passivation layer after wiring is installed, and exposing the output node and the inverting node through the passivation layer.

[0014] The first dummy transistor and the second dummy transistor can form a two-stage level converter circuit by changing the metal mask.

[0015] When forming the transistor, a first dummy limiting transistor for limiting the amount of current flowing to the first dummy transistor and a second dummy limiting transistor for limiting the amount of current flowing to the second dummy transistor can also be formed. When mounting and wiring, the wiring can be mounted in such a way that the gate terminal and source terminal of the first dummy limiting transistor and the gate terminal and source terminal of the second dummy limiting transistor are short-circuited.

[0016] Another exemplary embodiment of this disclosure provides a level shifter, comprising: a level shifter circuit including a first transistor and a second transistor, the first transistor being turned on and off using an input voltage to generate a voltage having a waveform inversely phase to the input voltage at an inverting node, and the second transistor being turned on and off using an inverted voltage having a waveform inversely phase to the input voltage to generate a voltage having a waveform identical to the input voltage at an output node; and a dummy circuit including transistors configured as a two-stage level shifter circuit, the transistors including a first dummy transistor and a second dummy transistor with their gate terminals and source terminals shorted.

[0017] As described above, according to embodiments of this disclosure, the design of the level converter can be changed more easily, and a single-stage or two-stage level converter can be selected simply by changing the wiring in the manufacturing process. Attached Figure Description

[0018] Figure 1 This is the circuit diagram of a single-stage level converter.

[0019] Figure 2 This is the circuit diagram of a two-level level converter.

[0020] Figure 3 It is a circuit diagram of a level converter that includes a dummy circuit.

[0021] Figure 4 It is a flowchart of a method for manufacturing a level converter that includes a dummy circuit.

[0022] Figure 5 This is a diagram showing the pattern used to form a transistor.

[0023] Figure 6A This is a diagram showing the metal layer pattern used to form a two-stage level converter.

[0024] Figure 6B This is a diagram showing the metal layer pattern used to form a single-stage level converter. Detailed Implementation

[0025] Figure 1 This is the circuit diagram of a single-stage level converter.

[0026] refer to Figure 1 The level converter 100 may include a first path circuit PT1 and a second path circuit PT2 formed between a first high drive voltage VDD1 and a first low drive voltage VSS1.

[0027] The first high drive voltage VDD1 can be electrically connected to one side of the first path circuit PT1, and the first low drive voltage VSS1 can be electrically connected to the other side, and current can flow from the first high drive voltage VDD1 to the first low drive voltage VSS1 via the first path circuit PT1.

[0028] The first path circuit PT1 may include a first transistor TR1, a third transistor TR3, and a fifth transistor TR5. Furthermore, the first transistor TR1, the third transistor TR3, and the fifth transistor TR5 may be connected in series with each other.

[0029] Although for ease of explanation, Figure 1 The first transistor TR1 is shown as an N-type transistor, and the third transistor TR3 and the fifth transistor TR5 are shown as P-type transistors, but this disclosure is not limited thereto.

[0030] The input voltage VI can be supplied to the gate terminal of the first transistor TR1. Furthermore, the first transistor TR1 can be turned on and off according to the voltage level of the input voltage VI.

[0031] The source terminal of the first transistor TR1 can be connected to a first low drive voltage VSS1, and its drain terminal can be connected to the inverting node NDOB. Using this structure, when a high-level input voltage VI is supplied to the gate terminal of the first transistor TR1, a low-level inverted output voltage VOB can be generated at the inverting node NDOB.

[0032] The gate terminal of the third transistor TR3 can be connected to the output node NDO. Furthermore, the source terminal of the third transistor TR3 can be electrically connected to the first high drive voltage VDD1, and its drain terminal can be connected to the inverting node NDOB. As described below, an output voltage VO with the same waveform as the input voltage VI can be generated at the output node NDO. The third transistor TR3 can be turned on and off using the output voltage VO. With this structure, a high-voltage inverted output voltage VOB can be generated at the inverting node NDOB when a low-voltage input voltage VI is supplied.

[0033] The fifth transistor TR5 can limit the amount of current flowing to the first path circuit PT1.

[0034] The gate terminal of the fifth transistor TR5 can be supplied with a first bias voltage VBIA1. In addition, the source terminal of the fifth transistor TR5 can be connected to a first high drive voltage VDD1, and its drain terminal can be connected to the source terminal of the third transistor TR3.

[0035] The first high drive voltage VDD1 can be electrically connected to one side of the second path circuit PT2, and the first low drive voltage VSS1 can be electrically connected to the other side, and current can flow from the first high drive voltage VDD1 to the first low drive voltage VSS1 via the second path circuit PT2.

[0036] The second path circuit PT2 may include a second transistor TR2, a fourth transistor TR4, and a sixth transistor TR6. Furthermore, the second transistor TR2, the fourth transistor TR4, and the sixth transistor TR6 may be connected in series with each other.

[0037] Although for ease of explanation, Figure 1 The second transistor TR2 is shown as an N-type transistor, and the fourth transistor TR4 and the sixth transistor TR6 are shown as P-type transistors, but this disclosure is not limited thereto.

[0038] An inverting voltage VIB can be supplied to the gate terminal of the second transistor TR2. Furthermore, the second transistor TR2 can be turned on and off according to the voltage level of the inverting voltage VIB.

[0039] The source terminal of the second transistor TR2 can be connected to the first low drive voltage VSS1, and its drain terminal can be connected to the output node NDO. Using this structure, when a high-level inverted voltage VIB is supplied to the gate terminal of the second transistor TR2, a low-level output voltage VO can be generated at the output node NDO. Because the inverted voltage VIB has a waveform that is inversely phase to the input voltage VI, the output voltage VO can have the same waveform as the input voltage VI.

[0040] The gate terminal of the fourth transistor TR4 can be connected to the inverting node NDOB. Furthermore, the source terminal of the fourth transistor TR4 can be electrically connected to the first high drive voltage VDD1, and its drain terminal can be connected to the output node NDO.

[0041] As described above, an inverted output voltage VOB with the same waveform as the inverted voltage VIB can be generated at the inverting node NDOB. The fourth transistor TR4 can be turned on and off using the inverted output voltage VOB. With this structure, a high-voltage inverted output voltage VOB can be generated at the output node NDO when a low-voltage inverted voltage VIB is supplied.

[0042] The sixth transistor TR6 can limit the amount of current flowing to the second path circuit PT2.

[0043] The gate terminal of the sixth transistor TR6 can be supplied with a first bias voltage VBIA1.

[0044] Furthermore, the source terminal of the sixth transistor TR6 can be connected to the first high drive voltage VDD1, and its drain terminal can be connected to the source terminal of the fourth transistor TR4.

[0045] Figure 2 This is the circuit diagram of a two-level level converter.

[0046] refer to Figure 2 The level converter 200 may include a single-stage circuit 210 and a two-stage circuit 220.

[0047] The single-stage circuit 210 may include a first path circuit PT1 and a second path circuit PT2. The single-stage circuit 210 may have the same characteristics as the reference circuit. Figure 1 The explained single-stage level converter (see Figure 1 The circuit configuration is the same as that of the 100th stage. Therefore, a detailed description of the single-stage circuit 210 will be omitted.

[0048] Figure 1 Depicted single-stage level converter (see) Figure 1 The difference between the 100) and the single-stage circuit 210 is that the second high drive voltage VDD2 is supplied as a high drive voltage, the second low drive voltage VSS2 is supplied as a low drive voltage, and the second bias voltage VBIA2 is supplied to the fifth transistor TR5 and the sixth transistor TR6.

[0049] In addition, single-stage circuit 210 and Figure 1 Depicted single-stage level converter (see) Figure 1 Another difference between 100 and 210 is that the output of the single-stage circuit 210 is connected to the input of the two-stage circuit 220. To illustrate this difference, Figure 1 The single-stage level converter depicted in (see) Figure 1 The output node of (100) is called the first output node NDO1, and its inverted node is called the first inverted node NDOB1.

[0050] The two-stage circuit 210 may include a third-path circuit PT3 and a fourth-path circuit PT4.

[0051] The second high drive voltage VDD2 can be electrically connected to one side of the third path circuit PT3, and the second low drive voltage VSS2 can be electrically connected to the other side, and current can flow from the second high drive voltage VDD2 to the second low drive voltage VSS2 via the third path circuit PT3.

[0052] The third path circuit PT3 may include a seventh transistor TR7, a ninth transistor TR9, and an eleventh transistor TR11. Furthermore, the seventh transistor TR7, the ninth transistor TR9, and the eleventh transistor TR11 may be connected in series with each other.

[0053] Although for ease of explanation, Figure 2 The seventh transistor TR7 is shown as a P-type transistor, and the ninth transistor TR9 and the eleventh transistor TR11 are shown as N-type transistors, but this disclosure is not limited thereto.

[0054] The gate terminal of the seventh transistor TR7 can be connected to the first output node NDO1 of the single-stage circuit 210. Furthermore, the seventh transistor TR7 can be turned on and off according to the voltage level at the first output node NDO1.

[0055] The source terminal of the seventh transistor TR7 can be connected to the second high drive voltage VDD2, and its drain terminal can be connected to the second inverting node NDOB2. Using this structure, when a low-level input voltage VI is supplied to the gate terminal of the seventh transistor TR7, a high-level inverted output voltage VOB can be generated at the second inverting node NDOB2.

[0056] The gate terminal of the ninth transistor TR9 can be connected to the second output node NDO2. Furthermore, the source terminal of the ninth transistor TR9 can be electrically connected to the second low drive voltage VSS2, and its drain terminal can be connected to the second inverting node NDOB2. As described below, an output voltage VO with the same waveform as the input voltage VI can be generated at the second output node NDO2. The ninth transistor TR9 can be turned on and off using the output voltage VO. With this structure, when a high-voltage input voltage VI is supplied, a low-voltage inverted output voltage VOB can be generated at the second inverting node NDOB2.

[0057] The eleventh transistor, TR11, can limit the amount of current flowing to the third path circuit, PT3.

[0058] The gate terminal of the eleventh transistor TR11 can be supplied with a third bias voltage VBIA3. In addition, the source terminal of the eleventh transistor TR11 can be connected to a second low drive voltage VSS2, and its drain terminal can be connected to the source terminal of the ninth transistor TR9.

[0059] The second high drive voltage VDD2 can be electrically connected to one side of the fourth path circuit PT4, and the second low drive voltage VSS2 can be electrically connected to the other side, and current can flow from the second high drive voltage VDD2 to the second low drive voltage VSS2 via the fourth path circuit PT4.

[0060] The fourth path circuit PT4 may include an eighth transistor TR8, a tenth transistor TR10, and a twelfth transistor TR12. Furthermore, the eighth transistor TR8, the tenth transistor TR10, and the twelfth transistor TR12 may be connected in series with each other.

[0061] Although for ease of explanation, Figure 2 The eighth transistor TR8 is shown as a P-type transistor, and the tenth transistor TR10 and the twelfth transistor TR12 are shown as N-type transistors, but this disclosure is not limited thereto.

[0062] The gate terminal of the eighth transistor TR8 can be connected to the first inverting node NDOB1 of the single-stage circuit 210. Furthermore, the eighth transistor TR8 can be turned on and off according to the voltage level at the first inverting node NDOB1.

[0063] The source terminal of the eighth transistor TR8 can be connected to the second high drive voltage VDD2, and its drain terminal can be connected to the second output node NDO2. Using this structure, a high-level output voltage VO can be generated at the second output node NDO2 when a low-level input voltage VI is supplied to the gate terminal of the eighth transistor TR8.

[0064] The gate terminal of the tenth transistor TR10 can be connected to the second inverting node NDOB2. Furthermore, the source terminal of the tenth transistor TR10 can be electrically connected to the second low drive voltage VSS2, and its drain terminal can be connected to the second output node NDO2.

[0065] As described above, an inverted output voltage VOB with the same waveform as the inverted voltage VIB can be generated at the second inverting node NDOB2. The tenth transistor TR10 can be turned on and off using the inverted output voltage VOB. With this structure, a low-voltage inverted output voltage VOB can be generated at the second output node NDO2 when a high-voltage inverted voltage VIB is supplied.

[0066] The twelfth transistor TR12 can limit the amount of current flowing to the fourth path circuit PT4.

[0067] The gate terminal of the twelfth transistor TR12 can be supplied with a third bias voltage VBIA3.

[0068] Furthermore, the source terminal of the twelfth transistor TR12 can be connected to the second low drive voltage VSS2, and its drain terminal can be connected to the source terminal of the tenth transistor TR10.

[0069] Figure 3 It is a circuit diagram of a level converter that includes a dummy circuit.

[0070] refer to Figure 3 The level converter 300 may include a level converter circuit 310 and a dummy circuit 320.

[0071] The level shifter circuit 310 may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 is turned on and off using the input voltage VI to generate a voltage with a waveform opposite to the input voltage VI at the inverting node NDOB. The second transistor TR2 is turned on and off using an inverting voltage VIB with a waveform opposite to the input voltage VI to generate a voltage with the same waveform as the input voltage VI at the output node NDO.

[0072] The level converter circuit 310 can have the same characteristics as... Figure 1 Depicted level converter (see) Figure 1 (100) Same circuit configuration.

[0073] Therefore, a detailed description of the level converter circuit 310 will be omitted.

[0074] The dummy circuit 320 may include a first dummy transistor DTR1 and a second dummy transistor DTR2. The gate and source terminals of the first dummy transistor DTR1 are short-circuited by a first shorting line LN1, and the gate and source terminals of the second dummy transistor DTR2 are short-circuited by a second shorting line LN2. Furthermore, when the first shorting line LN1 and the second shorting line LN2 are removed, the dummy circuit 320 can function as a two-stage level shifter circuit. Figure 2 (A two-stage circuit) is operated.

[0075] The virtual circuit 320 may include the third path circuit PT3 and the fourth path circuit PT4.

[0076] The third path circuit PT3 may include a first dummy transistor DTR1, a third dummy transistor DTR3, and a fifth dummy transistor DTR5, which are connected in series between the first high drive voltage VDD1 and the first low drive voltage VSS1.

[0077] In addition, the fourth path circuit PT4 may include a second dummy transistor DTR2, a fourth dummy transistor DTR4, and a sixth dummy transistor DTR6 arranged in series between the first high drive voltage VDD1 and the first low drive voltage VSS1.

[0078] The drain terminal of the first dummy transistor DTR1 can be electrically connected to the gate terminal of the fourth dummy transistor DTR4, and the drain terminal of the second dummy transistor DTR2 can be electrically connected to the gate terminal of the third dummy transistor DTR3.

[0079] Furthermore, the fifth dummy transistor DTR5 can be configured to limit the amount of current flowing to the first dummy transistor DTR1 and the third dummy transistor DTR3.

[0080] Furthermore, the sixth dummy transistor DTR6 can be configured to limit the amount of current flowing to the second dummy transistor DTR2 and the fourth dummy transistor DTR4.

[0081] The dummy circuit 320 may include and Figure 2 The depicted two-stage circuit (see Figure 2 The transistors are the same as those in 220, but there may be wiring differences between the dummy circuit 320 and the two-stage circuit 220.

[0082] exist Figure 2 and Figure 3 In the comparison, the first dummy transistor DTR1 can correspond to the seventh transistor TR7, the second dummy transistor DTR2 can correspond to the eighth transistor TR8, the third dummy transistor DTR3 can correspond to the ninth transistor TR9, the fourth dummy transistor DTR4 can correspond to the tenth transistor TR10, the fifth dummy transistor DTR5 can correspond to the eleventh transistor TR11, and the sixth dummy transistor DTR6 can correspond to the twelfth transistor TR12.

[0083] When the level converter 300 operates as a single-stage level converter, the dummy circuit 320 can be wired in a manner that prevents current from flowing into it. For example, the gate and source terminals of the first dummy transistor DTR1 can be shorted by the first shorting line LN1. Furthermore, the gate and source terminals of the second dummy transistor DTR2 can be shorted by the second shorting line LN2. Additionally, the gate and source terminals of the fifth dummy transistor DTR5 and the sixth dummy transistor DTR6 can be shorted by the third shorting line LN3.

[0084] The design of level converter 300 can be modified into a two-stage level converter. To modify the design of level converter 300 into a two-stage level converter, the following steps are required: Figure 2 The wiring has been changed as shown.

[0085] For example, when the dummy circuit 320 operates as a two-stage level converter circuit, the output node NDO of the level converter circuit 310 can be electrically connected to the gate terminal of the first dummy transistor DTR1, and its inverting node NDOB can be electrically connected to the gate terminal of the second dummy transistor DTR2.

[0086] In addition, the first shortest route LN1, the second shortest route LN2, and the third shortest route LN3 can be removed.

[0087] Figure 4 It is a flowchart of a method for manufacturing a level converter that includes a dummy circuit.

[0088] refer to Figure 4 It can perform wafer processing (S400) for providing a substrate to a level converter.

[0089] Next, a transistor mask can be placed (S402), and a transistor can be formed in accordance with the transistor mask (S404). In this case, the transistor mask may include multiple masks, and some components of the transistor can be formed in accordance with each mask.

[0090] Next, a metal mask can be placed (S406), and a metal layer can be formed in accordance with the metal mask (S408).

[0091] The metal layer can include wiring. Manufacturers or designers can form wiring in different ways by changing the metal mask. Furthermore, manufacturers or designers can manufacture single-stage or two-stage level shifters by using two types of metal masks.

[0092] In manufacturing a single-stage level converter, in the metal layer formation step S408, wiring can be installed as follows: a first transistor is turned on and off using the input voltage to generate a voltage with a waveform opposite to the input voltage at the inverting node; a second transistor is turned on and off using an inverted voltage with a waveform opposite to the input voltage to generate a voltage with the same waveform as the input voltage at the output node; the gate terminal and source terminal of the first dummy transistor are short-circuited; and the gate terminal and source terminal of the second dummy transistor are short-circuited.

[0093] In addition, the wiring can be installed in a manner that short-circuits the gate and source terminals of the fifth dummy transistor and the gate and source terminals of the sixth dummy transistor.

[0094] A passivation layer can be formed on the metal layer to isolate the metal layer (S410). Furthermore, the output node and the inverting node can be exposed through the passivation layer.

[0095] Figure 5 This is a diagram showing the pattern used to form a transistor. Figure 6A This is a diagram showing the metal layer pattern used to form a two-stage level converter. Figure 6B This is a diagram showing the metal layer pattern used to form a single-stage level converter.

[0096] refer to Figure 5 , Figure 6A and Figure 6B It can form such as Figure 5The transistors TR1 to TR6 and DTR1 to DTR6 are shown for both single-stage and two-stage level converters.

[0097] Subsequently, in the case of forming a two-stage level converter, the manufacturer can have, for example... Figure 6A The metal layer pattern shown is used to create a level converter that can be a two-stage level converter.

[0098] When forming as Figure 5 In the case where transistors TR1 to TR6 and DTR1 to DTR6 form a single-stage level shifter, the manufacturer can form such a... Figure 6B The metal layer pattern shown. A level shifter manufactured in this way can be a single-stage level shifter.

[0099] As described above, according to embodiments of this disclosure, the design of the level converter can be changed more easily, and a single-stage or two-stage level converter can be selected simply by changing the wiring in the manufacturing process.

[0100] Cross-reference to related applications

[0101] This application claims priority to Korean Patent Application 10-2020-0178855, filed on December 18, 2020, which is incorporated herein by reference for all purposes as fully set forth herein.

Claims

1. A level converter, comprising: In the first path circuit, a first transistor and a third transistor are connected in series between a high driving voltage and a low driving voltage. A second path circuit, in which a second transistor and a fourth transistor are connected in series between the high driving voltage and the low driving voltage; A third path circuit, in which a seventh transistor and a ninth transistor are connected in series between the high driving voltage and the low driving voltage. as well as A fourth path circuit, in which an eighth transistor and a tenth transistor are connected in series between the high drive voltage and the low drive voltage. An input voltage is supplied to the gate terminal of the first transistor, and an inverted voltage having a waveform opposite to the input voltage is supplied to the gate terminal of the second transistor. The drain terminal of the first transistor is electrically connected to an inverting node, the drain terminal of the second transistor is electrically connected to an output node, the output node is electrically connected to the gate terminal of the third transistor, and the inverting node is electrically connected to the gate terminal of the fourth transistor. The gate terminal and source terminal of the seventh transistor are short-circuited by a first short circuit, and the gate terminal and source terminal of the eighth transistor are short-circuited by a second short circuit.

2. The level converter according to claim 1, wherein, The first path circuit further includes a fifth transistor for limiting the amount of current flowing to the first transistor and the third transistor, and the second path circuit further includes a sixth transistor for limiting the amount of current flowing to the second transistor and the fourth transistor.

3. The level converter according to claim 1, wherein, The drain terminal of the seventh transistor is electrically connected to the gate terminal of the tenth transistor, and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the ninth transistor.

4. The level converter according to claim 3, wherein, The third path circuit further includes an eleventh transistor for limiting the amount of current flowing to the seventh and ninth transistors, and the fourth path circuit further includes a twelfth transistor for limiting the amount of current flowing to the eighth and tenth transistors.

5. The level converter according to claim 4, wherein, The gate and source terminals of the eleventh and twelfth transistors are short-circuited.

6. A method of manufacturing a level converter, the method comprising: Place the transistor mask; The first transistor, the second transistor, the seventh transistor, and the eighth transistor are formed in accordance with the transistor mask; Place the metal mask; as well as The wiring is mounted using the metal mask in the following manner: the first transistor is turned on and off according to the input voltage to generate a voltage at the inverting node having a waveform opposite to the waveform of the input voltage; the second transistor is turned on and off according to an inverted voltage having a waveform opposite to the waveform of the input voltage to generate a voltage at the output node having a waveform identical to the waveform of the input voltage; the gate terminal and source terminal of the seventh transistor are short-circuited; And the gate terminal and source terminal of the eighth transistor are short-circuited.

7. The method according to claim 6, further comprising: After the wiring is installed, a passivation layer is formed, and the output node and the inverting node are exposed through the passivation layer.

8. The method according to claim 6, wherein, The seventh and eighth transistors form a two-stage level shifter circuit based on the change of the metal mask.

9. The method according to claim 6, wherein, When forming the transistor, an eleventh transistor for limiting the amount of current flowing to the seventh transistor and a twelfth transistor for limiting the amount of current flowing to the eighth transistor are also formed, and during mounting and wiring, the gate terminals and source terminals of the eleventh transistor and the gate terminals and source terminals of the twelfth transistor are short-circuited.

10. A level converter, comprising: A level shifter circuit includes a first transistor and a second transistor, the first transistor being turned on and off according to an input voltage to generate a voltage at an inverting node having a waveform opposite to the waveform of the input voltage, and the second transistor being turned on and off according to an inverting voltage having a waveform opposite to the waveform of the input voltage to generate a voltage at an output node having a waveform identical to the waveform of the input voltage. as well as A dummy circuit comprising transistors arranged in the form of a two-stage level shifter circuit, wherein the gate terminals and source terminals of the seventh and eighth transistors are short-circuited.

11. The level converter according to claim 10, wherein, When the dummy circuit operates as the two-stage level converter circuit, the output node is electrically connected to the gate terminal of the seventh transistor, and the inverting node is electrically connected to the gate terminal of the eighth transistor.

12. The level converter according to claim 11, wherein, When the dummy circuit operates as the two-stage level converter circuit, the output voltage is determined based on the voltage at the drain terminal of the eighth transistor, and the inverted output voltage is determined based on the voltage at the drain terminal of the seventh transistor.

13. The level converter according to claim 10, wherein, The dummy circuit also includes an eleventh transistor for limiting the current flowing to the seventh transistor and a twelfth transistor for limiting the current flowing to the eighth transistor.

14. The level converter according to claim 13, wherein, The gate and source terminals of the eleventh transistor and the gate and source terminals of the twelfth transistor are short-circuited by a third short circuit.

15. The level converter according to claim 10, wherein, The first transistor and the seventh transistor are transistors of different types, and the second transistor and the eighth transistor are transistors of different types.

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