Matrix processor generating input delay adjustments for a SAR search to calibrate time phase mismatches of a multi-channel interleaved ADC

Abstract

An N-channel alternating analog-to-digital converter (ADC) with variable delays added to the input sampling clock of each ADC. During calibration, these variable delays are programmed by a successive approximation register (SAR) to minimize time phase mismatch between channels. Within each channel, the ADC output is filtered, and a product derivative correlator generates a product derivative factor of the correlation between two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlator into a matrix and multiplies this matrix by a correlation matrix. The correlation matrix is ​​a constant generated by an N×N shift matrix. The matrix processor outputs a sign bit vector. Each bit in the sign bit vector determines when to set or clear a test SAR bit to adjust the variable delay of the channel. Sampling clock and time phase mismatch can be reduced to one LSB across all N channels.

Description

[0001] Related applications

[0002] This invention is a continuation in part (CIP) of U.S. Serial No. 17455471, filed on November 18, 2021, entitled “Calibration of TimingSkews in a Multi-Channel Interleaved Analog-to-Digital Converter (ADC) by Auto-Correlation of Muxed-Together Channels in Binary Output Tree”. Technical Field

[0003] This invention relates to analog-to-digital converters (ADCs), and more particularly, to the calibration of alternating ADCs. Background Technology

[0004] Analog-to-digital converters (ADCs) are widely used to convert analog signals into digital values. Multi-bit ADCs have high resolution, and their accuracy can be improved through calibration. Higher sampling rates can be achieved by alternating between two ADCs, with each ADC operating at half the sampling rate.

[0005] Figure 1 An alternating ADC of the prior art is illustrated. ADC 10 and ADC 12 are interleaved, wherein ADC 10 samples the analog input AIN when the clock CLK closes switch 20, and ADC 12 samples the analog input AIN when the inverting clock CLKB closes switch 22. When CLK is high, multiplexer (MUX) 18 selects digital output Y1 from ADC 10 while ADC 10 has sufficient time to sample, hold, and convert AIN to a digital value. When CLK is low, the digital output DOUT to MUX 18 is Y2. Therefore, each of ADCs 10 and 12 can operate at half the data rate of the final output DOUT.

[0006] Figure 2This is a graph illustrating the analog sampling and clock skew. AIN is sampled into ADC 10 to generate Y1[K-1] and Y1[K] on the falling edge of CLK, while AIN is sampled into ADC 12 to generate Y2[K-1] and Y2[K] on the falling edge of CLKB, where K is the sample or time-index number. The sampling time or period of AIN is Ts. Ideally, there is no clock skew in CLK, and all samples are spaced Ts apart. However, CLK may not have a pulse width that is exactly 50% of the period 2*Ts, thus introducing sampling pulse-width mismatch and nonlinearity. The sampling of channel Y2 may be delayed by Ts+ΔT / 2 relative to the sampling of channel Y1, while the sampling of channel Y1 may be delayed by Ts-ΔT / 2 relative to the sampling of channel Y2. Ideally, ΔT = 0, and there is no mismatch in sampling. However, in practice, ΔT is finite. It is desirable to reduce ΔT to an acceptable minimum for more than two channels.

[0007] ADCs 10 and 12 and switches 20 and 22 may not be perfectly matched, thus introducing a finite bandwidth mismatch in the two channels Y1 and Y2. Therefore, both sampling-pulse mismatch and ADC component mismatch can lead to nonlinearity.

[0008] Figure 3 This is a graph showing the clutter in the spectrum of a conventional alternating ADC. Sampling pulse-width mismatch and component mismatch can introduce nonlinearity or errors, resulting in clutter 302. This clutter may appear at integer multiples of Fs / N, such as K*Fs / N±F, where K is an integer, Fs is the sampling frequency (period Ts = 1 / Fs), and N is the number of alternating channels. This clutter is undesirable because it can limit the dynamic range of a high-speed ADC and is proportional to the amplitude and frequency of the analog input signal.

[0009] What is needed is a highly alternating ADC with at least three ADC channels alternating together to operate at higher sampling rates. Preferably, a variable, programmable delay is introduced to each channel input to correct for time phase mismatches caused by sampling pulse-width, clock, and component mismatches in these three or more alternating channels. A calibration method is needed to test various values ​​of these delays in order to program them to minimize bias in these channels. Fast foreground and background calibration methods are needed to adjust for gradual temperature deviations. Attached Figure Description

[0010] Figure 1 An alternative ADC of the prior art is shown.

[0011] Figure 2 It is a graph of analog sampling and clock skew.

[0012] Figure 3 This is a graph showing the clutter in the spectrum of an existing alternating ADC.

[0013] Figure 4 It is a block diagram of a 4-channel alternating ADC with a product derivative correlator and a matrix processor for calibrating programmable input delays.

[0014] Figure 5 This is a diagram of a SAR delay element with binary weighted capacitance.

[0015] Figure 6 It is a block diagram of a 3-channel alternating ADC with details of a product derivative correlator used to drive the matrix processor to calibrate the programmable input delay.

[0016] Figures 7A-7B This is a flowchart of foreground calibration for N alternating ADC channels.

[0017] Figure 8 It is an alternating ADC that calibrates the channel input delay through a product derivative correlator and matrix processing, reducing noise in the spectrum.

[0018] Figure 9 The back-end processor that triggers the background calibration of the alternating ADC is shown.

[0019] Figures 10A-10B A flowchart of the background calibration process is shown.

[0020] Figure 11 An alternating ADC with a non-binary number of channels is shown, calibrated with a product derivative correlator and a matrix processor.

[0021] Figure 12 This illustrates a channel-alternating ADC with a non-binary odd number of channels calibrated using a product derivative correlator and a matrix processor.

[0022] Figure 13 A model of an alternating ADC is shown. Detailed Implementation

[0023] This invention relates to improvements in alternating ADC calibration. The following description is provided to enable those skilled in the art to make and use the invention as presented in the context of a particular application and its requirements. Various modifications to the preferred embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the invention is not intended to be limited to the specific embodiments shown and described, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

[0024] Figure 4 This is a block diagram of a 4-channel alternating ADC with a product derivative correlator and a matrix processor for calibrating programmable input delays. The analog input AIN is buffered by analog buffer 30 and sampled into ADCs 10, 12, 13, and 14 via switches 20, 22, 23, and 24, which generate digital values ​​D1, D2, D3, and D4, respectively. A multiplexer (MUX) 64 alternately selects D1, D2, D3, and D4 to generate the final data output DOUT. The final MUX 64 operates at clock TSX4, which has a frequency four times that of the sampling clock TS1.

[0025] Sampling clocks TS1, TS2, TS3, and TS4 can be four-phase clocks, all operating at the same frequency but with phase shifts of 0, 90, 180, and 270 degrees. Sampling clocks TS1, TS2, TS3, and TS4 are delayed by a variable amount to generate clocks T1, T2, T3, and T4. These clocks T1, T2, T3, and T4 control switches 20, 22, 23, and 24, respectively. These switches sample the AIN onto ADCs 10, 12, 13, and 14, which generate channel digital outputs D1, D2, D3, and D4 with phases of 0, 90, 180, and 270 degrees. During calibration, these variable delays are programmed using digital values ​​stored in the Successive Approximation Register (SAR), which control the enabling and disabling of the binary weighted capacitive delay elements. The calibration uses a successive approximation method, which first tests the larger most significant bit (MSB) capacitance, then tests the smaller capacitances in sequence, until the least significant bit (LSB) capacitance is tested.

[0026] SAR delay element 40 delays sampling clock TS1 to generate T1 for switch 20, while SAR delay elements 42, 43, and 44 delay sampling clocks TS2, TS3, and TS4 to generate T2, T3, and T4 for switches 22, 23, and 24, respectively. By adjusting the delay values ​​programmed into SAR delay elements 40, 42, 43, and 44, the time phase mismatch between channels D1, D2, D3, and D4 can be compensated and matched within the delay of one LSB capacitor in SAR delay elements 40, 42, 43, and 44.

[0027] Finite Impulse Response (FIR) filter 17 filters the digital outputs D1, D2, D3, and D4 from ADCs 10, 12, 13, and 14 to generate filtered digital values ​​Y1, Y2, Y3, and Y4. FIR filter 17 can also function as a low-pass or band-pass filter for calibration.

[0028] The product derivative correlator 52 receives the filtered digital values ​​Y1, Y2, Y3, and Y4, and generates product derivative factors F1, F2, F3, and F4. The product derivative factor F2 is a function of the filtered digital value Y2 of the current channel and the values ​​of adjacent channels Y1 and Y3. Generally, the product derivative factor F(X) of channel X has inputs Y(X), Y(X-1), and Y(X+1), where X-1 and X+1 are modulo N, where N is the number of alternating channels. Each product derivative correlator 52 generates the correlation factor of the current channel relative to two adjacent channels. The product derivative correlator 52 can be a midpoint correlator, for example... Figure 6 The logic circuit example described.

[0029] Matrix processor 50 receives product derivative factors F1, F2, F3, and F4 from product derivative correlator 52, forms a matrix from F1, F2, F3, and F4, and multiplies this matrix by the correlation matrix to generate the sign bit. The correlation matrix is ​​a constant matrix, fixed relative to a fixed number of channels N.

[0030] During calibration, the delay in SAR delay element 40 is fixed and serves as a timing reference for the other N-1 channels. Therefore, the sign bit of channel 1 is not generated by matrix processor 50.

[0031] For a constant or slowly shifting analog input AIN, all channels should generate the same filtered digital values ​​Y1, Y2, Y3, and Y4. Differences in these values ​​across channels indicate bias or time difference.

[0032] The product derivative factors F1, F2, F3, and F4 each indicate the digital value or time difference between a channel and its two adjacent channels. These time differences are combined with all other time differences by the matrix processor 50 to generate a sign bit. The sign bit indicates which channels have larger delays and which channels have smaller delays.

[0033] The calibrator 55 uses these sign bits during successive approximation sequences to determine when to maintain the test bit set in the SAR delay elements 42, 43, 44 and when to reset the test bit when a smaller bit position is tested in succession.

[0034] Figure 5 This is a diagram of a SAR delay element with binary weighted capacitors. The SAR delay element 40 has an input inverter 92 for inverting the input sampling clock TS1 to drive the delay node D and an output inverter 94 for driving the local sampling clock T1 of channel 1.

[0035] A series of binary weighted capacitors 110, 108, 106, 104, ... 102 have capacitance values ​​or weights that are 64, 32, 16, 8, 4, 2, and 1 times the minimum capacitance value C of capacitor C1 102, respectively. One terminal of each of the binary weighted capacitors 110, 108, 106, 104, ... 102 is connected to delay node D between inverters 92 and 94, while the other terminal is connected to ground via enable transistors 120, 118, 116, 114, ... 112. Bits in SAR register 130 drive the gates of enable transistors 120, 118, 116, 114, ... 112. When a bit in SAR register 130 is high, the enable transistors are turned on, thereby grounding the lower terminal of the capacitor, enabling and increasing the capacitance, and delaying delay node D.

[0036] For example, the value 1010000 written to SAR register 130 enables transistors 120 and 116 and capacitors 110 and 106, thereby increasing the capacitance on delay node D by 64C+16C or 80C. MSB capacitor 110 increases the delay by 64C, while capacitor 106 increases the delay by 16C. Other SAR delay elements 42, 43, and 44 operate in a similar manner, and each can be programmed to control with different SAR delay values.

[0037] Figure 6 This is a block diagram of a 3-channel alternating ADC with details of a product derivative correlator used to drive the matrix processor to calibrate the programmable input delay. In this simplified 3-channel ADC, there are only three ADCs 10, 12, 13, three sampling switches 20, 22, 23, three SAR delay elements 40, 42, 43, and three inputs D1, D2, D3 to the MUX64, which operates at clock TSX3.

[0038] Three FIR filters 17 generate filtered digital values ​​Y1, Y2, and Y3. These filtered digital values ​​are input to the product derivative correlators 52-1, 52-2, and 52-3 of channels 1, 2, and 3, respectively. These product derivative correlators 52-1, 52-2, and 52-3 generate product derivative factors F1, F2, and F3, respectively.

[0039] The product derivative correlator 52-2 of channel 2 has Y2, which is delayed by sample delay 11 before being input to multiplier 142. In multiplier 142, this is multiplied by the sum from adder 140, i.e., Y3 delayed by sample delay 148 minus Y1 delayed by sample delay 146. Then, averager (AVE) 54 calculates the average of M simulated input samples to generate the product derivative factor F2. The product derivative correlator 52-2 generates the following function:

[0040] F2=Average{Y2[n-1]*(Y3[n-1]-Y1[n-1])}

[0041] Where n is the sample number from 1 to N, and the mean is the average of the N samples. F2 is the average correlation between the current channel Y2 and its neighboring channels Y1 and Y3. F2 is the product derivative correlation factor.

[0042] Generally, for any channel X in an N-channel alternating ADC, the following holds:

[0043] F(X)=Average{Y(X)[n-1]*(Y(X+1)[n-1]-Y(X-1)[n-1])}

[0044] Wherein, X+1 and X-1 perform modulo N to make channel 1 have Y(X-1) = Y(N) = Y3 input to delayed sample 146, and sample delay 146 is delayed by 2 samples (Z) in product derivative correlator 52-1. -2 The last channel 3 has a direct input of Y(X+1) = Y(1) = Y1 to adder 140, thus bypassing the sample delay 148 in the product derivative correlator 52-3. When the model is wrapped, the sample number also increases or decreases by 1.

[0045] The first channel (X=1) product derivative correlator 52-1 is generated:

[0046] F(1)=Average{Y(1)[n-1]*(Y(2)[n-1]-Y(N)[n-2])}

[0047] Because X-1 modulus N wraps back to N, the last channel.

[0048] The last channel (X=N) product derivative correlator 52-3 is generated:

[0049] F(N)=Average{Y(N)[n-1]*(Y(1)[n]-Y(N-1)[n-1])}

[0050] Because X+1 modulo N is wound forward to channel 1.

[0051] Combine and arrange the product derivative factors F1, F2, F3, and F4 into matrix F:

[0052]

[0053] The correlation matrix is ​​based on a shift matrix C, which is a square N×N matrix with N rows and N columns.

[0054]

[0055] The correlation matrix is ​​the transpose of C. T Divide by the transpose of C T The product of C and:

[0056]

[0057] Alternative sites may include (C) T The inverse matrix INV of *C) multiplied by C T .

[0058] Matrix processor 50 generates the sign bits for channels 2 to N by multiplying matrix F by the correlation matrix:

[0059]

[0060] Since the shift matrix C is a constant that depends only on N, the adjacent channel correlation obtained by the product derivative factors [F1, F2, F3, ... FN] is a variable. This variable is multiplied by a constant to generate the sign bit. The sign bits sign(2), sign(3), ... sign(N) form a one-dimensional matrix or vector, and they can be transposed from a vertical 1×N matrix to a horizontal N×1 matrix for easier processing or data storage.

[0061] At the start of calibration, SAR delay element 40 is set with a fixed delay value such as a midpoint value of 10000...0, while SAR delay elements 42 and 43 have bits that are set and cleared by calibrator 55 during the SAR process. When the sign bit sign(2) generated by matrix processor 50 is high, calibrator 55 sets the bit in SAR delay element 42 high, but when the sign bit sign(2) is low, calibrator 55 clears the bit in SAR delay element 42 low. Similarly, when the sign bit sign(3) generated by matrix processor 50 is high, calibrator 55 sets the bit in SAR delay element 43 high, but when the sign bit sign(3) is low, calibrator 55 clears the bit in SAR delay element 43 low.

[0062] Figures 7A-7B This is a flowchart of foreground calibration for N alternating ADC channels. This process can be used during the initial calibration. Figure 4 4-way alternating ADC Figure 6 3-way alternating ADC Figure 11 6-way alternating ADC Figure 12 A 7-way alternating ADC, or any arbitrary N-way alternating ADC, where N is an integer of at least 3.

[0063] Clear all bits in all SAR delay elements 40, 42, 43, and 44 to initialize SAR(J) for any channel J (step 202). Set the SAR delay element 40SAR(1) of the first channel to the midpoint value 1000…0 (step 204). The first channel acts as a fixed timing reference for its correlation with the other channels, so SAR(1) remains fixed for the remainder of the foreground calibration. Bits in the SAR(J) of the other channels are set high or cleared during calibration.

[0064] Set the current bit position Q in SAR delay elements 42, 43, and 44 (SAR(J)) to the MSB of the variable delay or variable capacitance (CAP) (step 206). Set the MSB bit Q = MSB in the SAR (J = 2..N) of each of the remaining N-1 channels to high (step 208).

[0065] exist Figure 7B In step 210, the product derivative correlator 52 generates product derivative factors F1, F2, F3, F4, ... FN, each of which is the average correlation with adjacent channels over M samples (step 210). The matrix processor 50 arranges the product derivative factors F1, F2, F3, F4, ... FN into matrix F and multiplies it by the correlation matrix C. T / (C T *C)(Step 212). The result from matrix processor 50 is a symbol vector sign(2...N). This symbol vector has one sign bit for each of channels 2 to N. Each sign bit indicates the sign of the associated delay difference of that channel relative to the first channel.

[0066] When the sign bit of channel X is 1 (step 214), the calibrator 55 keeps the SAR(Q) of that channel high. The added delay in SAR delay elements 42, 43, and 44 is not large enough. SAR(Q) is the bit corresponding to bit position Q in SAR delay elements 42, 43, and 44.

[0067] When the sign bit of channel X is 0 (step 216), the calibrator 55 clears the SAR(Q) of that channel to 0. The added delay in the SAR delay elements 42, 43, and 44 is too large.

[0068] If Q has not yet reached the LSB (step 222), Q is decremented (step 224), and the next valid bit Q in the SAR delay elements 42, 43, 44 is set (step 218). Next, in step 210, the product derivative correlator 52 uses the new delay values ​​in the SAR delay elements 42, 43, 44 set by the calibrator 55 in step 218 to generate new values ​​for the product derivative factors F1, F2, F3, F4, ... Fn. The matrix processor 50 generates a new sign bit (step 212), and the calibrator 55 clears any bits with a zero sign bit (step 216).

[0069] In steps 210-224, the process is repeated for adjacent smaller Q bit positions and smaller additional capacitances until Q reaches the LSB (step 222), at which point the calibration ends.

[0070] Figure 8 It is an alternating ADC with channel input delay calibrated by a product derivative correlator and matrix processing, resulting in a reduced clutter spectrum curve. (By...) Figures 7A-7B Calibration process adjustments such as Figure 4 The programmable delays in the SAR delay elements 40, 42, 43, and 44 of the alternating ADC shown compensate for sampling pulse-width mismatch and component mismatch that introduce nonlinearity or error. This calibration reduces the amplitude of clutter 302. This clutter still appears at integer multiples of Fs / N, K*Fs / N ± Fin, where Fs is the sampling frequency (period Ts = 1 / Fs) and N is the number of channels alternating together. However, compared to... Figure 3 Compared to the existing clutter 302, the amplitude of clutter 303 is reduced.

[0071] Figure 9 The back-end processor that triggers background calibration of the alternating ADC is shown. Such as... Figures 7A-7B The foreground calibration shown can be triggered upon power-on, initialization, or reset. This foreground calibration uses a product derivative correlator and a matrix processor, along with calibrator 55, to perform a successive approximation search, thereby loading a delay value into the SAR delay register 744 in the alternating ADC 730 to compensate for time phase mismatch in the ADC channels of the alternating ADC 730.

[0072] Temperature and voltage conditions can drift over time. Switches, delays, the ADC, and other components, along with their errors, can be temperature and voltage-dependent. The circuitry in the alternating ADC 730 is sensitive to temperature and voltage. Over time, changes in temperature and supply voltage can cause an increase in time phase mismatch in the alternating ADC 730 when the system heats up or the environment changes. As conditions drift, it may be necessary to update the calibration delay to compensate for this drift. Background calibration can be periodically triggered to compensate for these drifts.

[0073] The downstream device 732 may be a baseband modem, a digital signal processor (DSP), a field-programmable array (FPGA), or other device using the digital output DOUT from the alternating ADC 730. The downstream device 732 may include logic for detecting when temperature, voltage, or other conditions change and triggering the alternating ADC 730 to perform background calibration. The downstream device 732 may have a timer and trigger background calibration after a certain time period (such as hourly or daily). The downstream device 732 may detect idle time or time when the analog input AIN has a suitable signal strength and frequency for calibration. Pattern generation logic integrated with the alternating ADC 730 may also be enabled to generate an analog input AIN signal suitable for calibration.

[0074] Figures 10A-10B This is a flowchart of the background calibration process. After the foreground calibration is completed, the background calibration is performed, and the calibrated delay is loaded into all SAR delay elements 40, 42, 43, 44, ... SAR(J) and reused (step 252).

[0075] The product derivative correlator 52 generates product derivative factors F1, F2, F3, F4, ... FN, which are the average correlations of M samples with respect to adjacent channels (step 260). The matrix processor 50 arranges the product derivative factors F1, F2, F3, F4, ... FN into a matrix F and multiplies it by the correlation matrix C. T / (C T *C)(Step 262). The result from matrix processor 50 is a sign vector sign(2...N). This sign vector has one sign bit for each of channels 2 to N.

[0076] When the sign bit of channel X is 1 (step 254), the calibrator 55 adds one LSB to the delay value in the SAR delay elements 42, 43, and 44 of channel X. The added delay in the SAR delay elements 42, 43, and 44 is not large enough.

[0077] When the sign bit of channel X is 0 (step 256), the calibrator 55 subtracts one LSB from the SAR delay value SAR(X) of that channel. The added delay in the SAR delay elements 42, 43, and 44 is too large.

[0078] exist Figure 10B In step 258, the sign vector sign(2..N) is stored as the old sign vector old_sign(2..N). The product derivative correlator 52 generates product derivative factors F1, F2, F3, F4, ..., FN again, which are the average correlations relative to adjacent channels over M samples (step 270). The matrix processor 50 arranges the product derivative factors F1, F2, F3, F4, ..., FN into matrix F again and multiplies it by the correlation matrix C. T / (C T *C)(Step 272). The result from matrix processor 50 is a new symbol vector sign(2...N).

[0079] When the sign bit of channel X changes such that sign(X) is not equal to old_sign(X) (step 274), the LSB added in step 254 or subtracted in step 256 is removed by means such as subtracting or adding an LSB, or by reloading the previous value in SAR(X) before the last loop. When the sign bit changes, the toggle indicator of channel X is incremented.

[0080] If the flip limit has not been reached (step 276), another loop begins. When the sign bit of channel X is 1 and the old sign bit old_sign(X) is also 1 (step 264), the calibrator 55 adds one LSB to the delay value in the SAR delay elements 42, 43, 44 of channel X.

[0081] When the sign bit of channel X is 0 and the old sign bit old_sign(X) is also 0 (step 266), the calibrator 55 subtracts one LSB from the SAR delay value SAR(X) of that channel. Then, steps 258, 270, 272, and 274 are repeated.

[0082] The background calibration process ends when the flip limit is reached (step 276). The flip limit can be defined as each channel having been flipped in every FL cycle of the last few FL cycles, or it may require that most channels have been flipped in every FL cycle of the last few FL cycles, or some other endpoint condition. For example, FL could be 20. When the endpoint is reached, each cycle iteration sequentially adds and removes LSBs in the SAR of each channel, indicating that a steady state has been reached and further iterations will not lead to better bias matching. The flip limit FL can be set to a value as small as 1 or larger for better robustness.

[0083] Foreground calibration is performed using the MSB when a larger delay change is needed to converge to the calibration result more quickly. However, background calibration is performed using the LSB because the expected drift is not large, so a slower adjustment is preferable for background calibration.

[0084] Figure 11 A non-binary number of channels of an ADC is illustrated, which is coupled and calibrated using product derivative correlators and a matrix processor. While a binary number of channels is very efficient, a non-binary number of ADC channels N may also exist. For example, there may be N = 6 ADC channels, which generate filtered outputs Y1, Y2, Y3, ... Y6 from FIR filter 17. Switches 20-26 sample analog inputs to ADCs 10-16, which are filtered by FIR filter 17 and drive six product derivative correlators 52. The six product derivative correlators 52 generate product derivative factors F1, F2, F3, F4, F5, F5, F6, which form a matrix. This matrix is ​​multiplied by the correlation matrix in matrix processor 50 to generate a sign bit vector sign(2..6) used to control calibrator 55 to adjust the delay values ​​in SAR delay element 40.

[0085] For N = 6 channels, F is:

[0086]

[0087] The correlation matrix is ​​C T / (C T *C), where C is:

[0088]

[0089] It can be replaced with other non-binary even values ​​of N as needed and the system can be adjusted.

[0090] Figure 12A non-binary odd number of ADCs is shown, coordinated and calibrated using product derivative correlators and a matrix processor. In this alternative, there are an odd number of ADC channels, N = 7, which generate filtered outputs Y1, Y2, Y3, ... Y7. Switches 20-27 sample the analog inputs into ADCs 10-16, 19, which are filtered by FIR filter 17 and drive seven product derivative correlators 52.

[0091] Seven product derivative correlators 52 generate product derivative factors F1, F2, F3, F4, F5, F6, and F7, which form a matrix. This matrix is ​​multiplied by the correlation matrix in the matrix processor 50 to generate a sign bit vector sign(2..7) used to control the calibrator 55 to adjust the delay values ​​in the SAR delay element 40.

[0092] For N = 7 channels, F is:

[0093]

[0094] The correlation matrix is ​​C T / (C T *C), where C is:

[0095]

[0096] It can be replaced with other odd non-binary values ​​of N as needed and the system can be adjusted.

[0097] Mathematical derivation of matrix formula

[0098] The following shows the mathematical derivation of the formula for generating symbol bit vectors for use in SAR routine decisions, implemented by the product derivative correlator 52 and the matrix processor 50.

[0099] The autocorrelation function is defined as:

[0100] R = E[Yi[n]Yj[n]]

[0101] Here, ΔT i This indicates that channel i is mismatched in time phase relative to the reference channel. If ΔT1, ΔT2, ΔT3, and ΔT4 are all smaller than Ts, then the first-order Taylor series can be approximated as:

[0102]

[0103] For 4 channels, we can summarize the following product derivative vector:

[0104]

[0105] The matrix C of the time phase mismatch error is summarized as follows:

[0106]

[0107] Therefore, everything is related to this equation:

[0108]

[0109] To solve this equation, we need to fix a time phase mismatch error to zero by removing the first column of C:

[0110]

[0111] Without losing generality, the vector ΔT can be analyzed as:

[0112]

[0113] The sign values ​​of the above equations provide the calibration direction for the convergent minimum vector ΔT:

[0114]

[0115] Since the derivative of autocorrelation has a fixed polarity over the Nyquist bandwidth, we can simply simplify the calibration equation to:

[0116]

[0117] Theoretical model of alternating ADC

[0118] Figure 13 The model of an alternating ADC is shown. The analog input X(S) is sampled by a first sampler 152 according to a function H1(S), and a first multiplier 158 multiplies it with a first delay 156D1(T) to generate X, which is input to the first ADC 154. S1 (S). In the second channel, the analog input X(S) is also sampled by the second sampler 162 according to the function H2(S), and the second multiplier 168 multiplies it with the second delay 166D2(T) to generate X, which is input to the second ADC 164. S2 (S). The digital outputs of the first ADC 154 and the second ADC 164 are multiplexed together by the MUX50 to generate the output Y(S).

[0119] The following equations and discussions are presented as theoretical background and are not intended to limit the invention or its claims, but are provided for inspiration.

[0120] Assuming it is a single-pole sampling system, the sampled analog signals (odd) and (even) are given by the following equation:

[0121]

[0122]

[0123] Therefore, the digital output Y(s) is given by the following formula:

[0124]

[0125] Ideally, if H1(s) = H2(s) = H(s) and ΔT = 0, then:

[0126]

[0127] Odd-numbered image copies from H2(s) are well canceled out by H1(s), in other words, the bandwidth of X(s) can be twice as expected due to the ping-pong sampling system. However, if ΔT≠0, then in reality there exists an error image (i.e., an uncorrected odd-numbered image copy) since H1(s)≠H2(s).

[0128] Here, we propose to approximate the error caused by finite bandwidth mismatch and time phase mismatch as follows:

[0129]

[0130] Where m is an odd number.

[0131] This provides the foundational analysis for the impact of "dynamic error" in the ADC system proposed in this application. Our goal is to evaluate the frequency response of E(s), which, in essence, can be summarized as:

[0132]

[0133] Therefore, the equivalent frequency response of the two sampling systems converges as follows:

[0134] E(s) = H′1(s) - H′2(s)

[0135] Considering the case with mismatched ping-pong sampling, the following equation holds:

[0136]

[0137]

[0138] Where Δt represents the time phase mismatch of channel 2 relative to channel 1, and Δω represents the finite bandwidth mismatch of channel 2 relative to channel 1.

[0139] Equivalently, it becomes:

[0140]

[0141] as well as

[0142]

[0143] Here, we exclude the effect of gain mismatch on H1′(s) and H2′(s) because if the cross-product term is negligible compared to the basic term, it is independent of the input frequency.

[0144] Consider the "dynamic error" E(s), that is:

[0145] E(s) = H′1(s) - H′2(s)

[0146] Equivalently, ignoring the cross-product term, it becomes:

[0147]

[0148]

[0149] E bw (s) and E sk (s) Explain the effects of finite bandwidth mismatch and time phase mismatch respectively.

[0150] Obviously, if Δω = 0 and ΔT = 0, then the dynamic errors caused by finite bandwidth mismatch and time phase mismatch are both zero.

[0151] However, dynamic error always exists, and therefore calibration is required to achieve the target performance. Therefore, the time derivative of the dynamic error is meaningful in our case. Consider the following:

[0152]

[0153]

[0154] By returning to the time domain using the inverse Laplace transform, we obtain:

[0155]

[0156]

[0157] From the above equation, Y(s) = Y ideal (s)·H(s)=X(s)·H(s) (that is, the filtered analog input signal).

[0158] Since H(s) is the desired response of the common loop filter in the ping-pong channel, the above equation is also equivalent to:

[0159]

[0160]

[0161] Note that, depending on the input signal frequency, the effect of H(s) introduces a finite gain error and phase shift, which does not result in an odd number of image copies, but will cause a mismatch on the two sampling systems.

[0162] In the time domain, the previous equation converges linearly as follows:

[0163] y(t)=y ideal (t)+e(t)=x(t)+e bw (t)+e sk (t)

[0164] Consider the absolute dynamic error signal e(t),

[0165]

[0166] For example, if ΔT = + / - 1ps, τ SAMP =1 / (2*π*5G)=32ps, and Δω / ω o If the error is 1%, then the first-order error term is limited to + / - 1.064 ps (in today's multi-GS / s ADCs).

[0167] From the above equations, ΔT and Δω / ω o Both are slightly related to signal / clock / component mismatches that can be reduced through proper layout and physical component size design, while τ SAMP These are circuit design parameters (PVT var.).

[0168] To mitigate the impact of dynamic errors, a wider sampling bandwidth (lower τ) can be designed. SAMP This reduces linearity performance (alternating excitation), thus fundamentally balancing noise, power, and other circuit design physical constraints.

[0169] From the above equation, it can be summarized as the Taylor series expansion error signal:

[0170]

[0171] Consider a single-carrier signal x(t) = Asin(ωt), where the odd and even time derivatives are given by the following equation:

[0172]

[0173] The error signal is proportional to the amplitude A and frequency of the signal.

[0174] Error signals appear at 90°C, 180°C, 270°C, etc. (i.e., integers * Fs / 2 ± Fin) -> noise. The sampling pulse and finite bandwidth mismatch both manifest as pulse width difference errors in the channel. Therefore, it is possible to eliminate this by adjusting the sampling pulse widths before the sampler via a variable delay element to align their effective sampling pulse widths.

[0175] Alternative embodiments

[0176] The inventors have also envisioned several other embodiments. For example, the clock can be derived from another clock and thus synchronized. The clock can be buffered, enabled, and limited by logic. Analog input signals can be buffered in various ways and with buffer arrangements or buffer trees. Although an initial clearing of all bits in all SARs is described, SAR bits can initially be all cleared to a high state instead of a low state. Active-low can be used instead of active-high.

[0177] All matrices can be rotated, transposed, or otherwise manipulated so that columns become rows and rows become columns. Therefore, the terms row and column are interchangeable.

[0178] The binary weighted capacitors 110, 108, 106, 104, ... 102 can be connected to a power supply or some other voltage, instead of ground. These capacitors can be enabled by p-channel or n-channel transistors, and the bits stored in the SAR delay element 40 can be active-high or active-low. These bits can be encoded in various ways and need to be decoded by a decoder in the SAR delay element 40. Although binary weighted capacitors 110, 108, 106, 104, ... 102 are shown, these capacitors can have other weight sequences, such as 1C, 1C, 2C, 5C, 11C, 15C, etc., and the successive approximation register (SAR) programming can be adjusted for these non-binary weight sequences. Instead of having binary weighted capacitors 110, 108, 106, 104, ... 102, the SAR delay element 40 can use other weighted delay elements, such as resistors, transistors, or buffers of various sizes or weights. Although a binary weighted capacitor is described, it can be replaced with other weighting methods, such as decimal weighting, prime number weighting, linear weighting, or octal weighting. The digital delay value in SAR can be in these other digital systems, such as octal numbers instead of binary numbers. Other types of delay elements can be used, such as parallel current sources, resistors, or various combinations thereof, as well as parallel, serial, or combined network arrangements. Values ​​can be shifted, transformed, or manipulated in various ways.

[0179] Although a product derivative correlator 52 is shown for a specific midpoint correlation, it can be replaced with other correlation functions, and the product derivative correlator 52 can be adjusted to perform these alternative correlation functions. Inversion and padding can be added at various locations. Switches 20, 22, 23, and 24 can be simple transistor switches, pass-through transistors, transmission gates, or other types of switches. Sample delays 11, 146, and 148 can be implemented as latches or other memory elements, or as delay implementations with combinational logic including NAND, NOR, XOR, and XNOR gates. Instead of using capacitors as delay elements, MOSFETs, FinFETs, or other devices (p-channel or n-channel) driven to power or ground can be used as delay elements.

[0180] Although the SAR delay element 40 of the first channel is described in step 204 as being initialized to a midpoint value of 1000..0, different channels can be initialized, or the initial value can be another value, such as 0100..0, 0010..0, etc. Any channel can serve as a fixed reference clock, and the delay of this fixed reference clock can be any value.

[0181] The matrix processor 50 may use a digital signal processor (DSP) or other processor that is efficient when performing matrix operations. The product derivative correlator 52 may be implemented in hardware and calibrated at high speed in parallel. Various combinations of hardware, firmware, and software may be used for the calibrator 55 and the embodiments described above.

[0182] The FIR filter 17 can act as a low-pass or band-pass filter for calibration, provided the polarity of its correlated derivative is known. FIR filtering helps constrain the polarity of its correlated derivative to a well-defined value or specification for calibrating an alternating ADC over a known frequency range. Because the correlated derivative is frequency-dependent, FIR filtering prevents any potential convergence problems during calibration.

[0183] For very fast logic systems that do not require pipelined timing, sample delays of 11, 146, and 148 can all reduce the delay by one sample cycle. Alternatively, for very fast pipelined systems with slow logic delays, these sample delays can increase the delay by one or more samples.

[0184] Although some operations are described in parallel for faster processing, serial operation is also possible. When executed serially, a single instance of the product derivative correlator 52 can be used in the hardware, rather than multiple separate instances of the product derivative correlator 52. Although a set of N product derivative correlators 52 is shown, the product derivative correlator 52 can be reused or operated in various serial and parallel arrangements.

[0185] The process steps can be executed serially, or some steps can be executed in parallel. Various sequences can be adjusted or modified. Higher-level operations can be executed using software or firmware, such as SAR testing and decision logic, while lower-level functions can be executed in hardware, such as using a product derivative correlator 52 to generate product derivative factors F1, F2, F3, and F4. Some or all calibration routines can be replaced by integrated circuits (ICs) or hardware on another chip (such as programmable logic, FPGAs, or other logic gates). Various combinations of hardware, software, firmware, etc., are possible replacements.

[0186] As an alternative, the product derivative correlator can operate on more than three inputs. The analog input buffers can be rearranged so that one analog input buffer drives four or two ADCs, or there can be a tree structure with multiple levels of analog input buffers.

[0187] For foreground and background calibration, the number of samples M used for averaging may differ, and even for different capacitor bit positions; for example, more samples may be used for the more sensitive LSB, while fewer samples may be used for the MSB. M may also differ due to other reasons, such as varying voltage or temperature conditions.

[0188] The analog input signal AIN is not necessarily a sine wave; it can be other forms of AC signal, such as a triangular wave, superimposed sine waves of different frequencies, or any wireless baseband signal. These signals can be used as input signals for calibration when the polarity of the relevant derivative can be determined.

[0189] The product derivative factors F1, F2, F3, and F4 can be averaged by setting the trigger for the current state and when the sign bit is 1 and clearing the trigger when the sign bit is 0.

[0190] A flip limit (FL) can be used to end background calibration when the sign bit is flipped more than FL times with increasing LSB. Alternatively, background calibration can end on the first sign bit flip.

[0191] The number of channels N can be binary, non-binary, even, or odd. Although a 4-channel alternating configuration is shown in detail, it can be replaced by an 8-channel, 7-channel, 6-channel, 16-channel, 32-channel, or N-channel alternating ADC. The alternation order of the channels can be varied. The alternation pattern may be nested or may be a long loop in stage 1.

[0192] Additional components, such as resistors, capacitors, inductors, and transistors, can be added at various nodes, and parasitic components may also exist. Enabling and disabling the circuit can be achieved using additional transistors or other methods. For isolation, pass-gate transistors or transmission gates can be added. Inverters or additional buffers can be added. Capacitors can be connected in parallel to create a larger capacitance that has the same edge or perimeter effect across several capacitor sizes. Switches can be n-channel transistors, p-channel transistors, or transmission gates with parallel n-channel and p-channel transistors, or more complex circuits (passive or active, amplifying or non-amplifying).

[0193] The number of bits in an ADC can be adjusted. For example, a 15-bit ADC can be used, or an 8-bit, 6-bit, 22-bit, or 18-bit ADC can be used. Different bit numbers can be used for different precisions, and the number of bits can be fixed or variable.

[0194] The background section of this invention may include background information about the problems or circumstances surrounding the invention, rather than describing prior art. Therefore, the inclusion of material in the background section does not imply that the applicant acknowledges prior art.

[0195] Any methods or processes described herein are implemented by machines or computers and are intended to be performed by machines, computers, or other devices, not by humans alone without the assistance of such machines. Tangible results may include reports or machine-generated displays on display devices such as computer monitors, projection devices, audio generating devices, and related media devices, and may include hard-copy printouts also generated by machines. Computer control of other machines is another tangible result.

[0196] Any advantages and benefits described may not apply to all embodiments of the invention. When the word "component" is recited in a claim element, the applicant intends that the claim element to be incorporated into paragraph 6 of 35 USC Sect. Typically, one or more words precede the word "component." These one or more words preceding the word "component" are intended to facilitate reference to the claim element rather than to convey structural limitations. Such component-plus-function claims are intended to cover not only the structure described herein for performing the function and its structural equivalents, but also equivalent structures. For example, although nails and screws have different structures, they are equivalent structures because they both perform the function of fastening. Claims that do not use the word "component" are not intended to be incorporated into paragraph 6 of 35 USC Sect. Signals are typically electronic signals, but can also be optical signals, such as those carried via fiber optic lines.

[0197] The above description of embodiments of the invention has been presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description, but by the appended claims.

Claims

1. A matrix-calibrated alternating analog-to-digital converter (ADC), comprising: There are N channels, where N is an integer of at least 4, and each of the N channels includes: An ADC used to convert a sampled analog input into a digital output having a digital value representing the sampled analog input; An analog switch that responds to a delayed clock for sampling analog inputs; During calibration, the successive approximation register (SAR) is programmed with a delay value; A variable delay element having a variable delay controlled by the delay value stored in the SAR, the variable delay element delaying the input sampling clock by the variable delay in order to generate the delayed clock for the analog switch; A product derivative correlator for correlating the digital output of a channel with the digital outputs of adjacent channels among the plurality of channels to generate the product derivative factors of the channels; and A matrix processor is configured to receive the product derivative factor of each of the N channels and to multiply the plurality of the product derivative factors with the correlation matrix to generate a symbol vector having correlation symbols of N-1 channels of the N channels; Specifically, the SAR is programmed with a delay value to compensate for time phase mismatch in the N channels using a successive approximation calibration procedure, which examines the relevant symbols in the symbol vector to determine when to accept or reject the test bit in the SAR of a certain channel corresponding to the relevant symbol in the symbol vector.

2. The matrix-calibrated alternating ADC as described in claim 1, wherein, The product derivative correlator for the current channel includes: The first sample delay is achieved by delaying the digital output of the current channel by one pulse of the sample clock to generate a sample with the first delay. The second sample delay is achieved by delaying the digital output of the first adjacent channel of the current channel by one pulse of the sample clock to generate a second delayed sample. The third sample delay is achieved by delaying the digital output of the second adjacent channel of the current channel by one pulse of the sample clock to generate a sample with the third delay. The first adjacent channel and the second adjacent channel are located in the N channels; A first adder subtracts a sample from the first delayed sample from the second delayed sample to generate a first sum; and A first multiplier multiplies the first sample and the sample with the first delay to generate a first product, the first product being the product derivative factor for the channel of a given sample.

3. The matrix-calibrated alternating ADC as described in claim 2, wherein, The product derivative correlator further includes: An averaging generator is used to average the first product among M samples of the simulated input, and to generate the product derivative factor as the average product derivative factor. Where M is an integer.

4. The matrix-calibrated alternating ADC as described in claim 3, wherein, The product derivative correlator in each channel further includes: A finite impulse response (FIR) filter is used to filter the digital output from the ADC, wherein the digital output is a filtered digital output.

5. The matrix-calibrated alternating ADC as described in claim 4, wherein, N is a non-binary number.

6. The matrix-calibrated alternating ADC as described in claim 4, wherein N is an odd number.

7. The matrix-calibrated alternating ADC of claim 4, further comprising: Successive approximation calibrator; The successive approximation calibrator has the following characteristics for each relevant symbol in the symbol vector: (a) When there is a corresponding related symbol with a value of 1 in the symbol vector of the channel, add a test bit to the SAR of the channel; (b) When there is a corresponding related symbol with a value of 0 in the symbol vector of the channel, the test bit is subtracted from the SAR of the channel; And, for the next bit position in the SAR, repeating from (a), Therefore, the relevant symbols in the symbol vector are used to add or subtract consecutive bit positions in the SAR.

8. The matrix-calibrated alternating ADC as described in claim 7, wherein, The successive approximation calibrator sets the SAR of the reference channel in the plurality of channels to a fixed value; The successive approximation calibrator does not adjust the fixed value in the SAR of the reference channel, but adjusts the SAR of the remaining N-1 channels out of the N channels.

9. The matrix-calibrated alternating ADC of claim 4, wherein the digital output from the ADC is at least 6 bits.

10. The matrix-calibrated alternating ADC as described in claim 2, wherein, The variable delay element includes multiple binary weighted capacitors, each of which is enabled by a bit in the SAR.

11. A calibration matrix method for reducing time-phase mismatch in a channel of an alternating analog-to-digital converter (ADC), the method comprising: Clear all bits in all successive approximation registers (SARs) used to set the variable input delay from the analog input to the alternating ADCs, each ADC samples the analog input and generates the ADC digital output; Set the bit in the SAR of the reference channel to the midpoint value; Each channel has a SAR, an ADC, and an input delay element with a variable input delay set by the SAR; (a) For each channel: The ADC digital outputs from the current channel, the previous adjacent channel, and the next adjacent channel are input to a product derivative correlator, which generates a sampled product derivative factor for quantifying the correlation between the ADC digital output of the current channel and the ADC digital outputs of the previous and next adjacent channels. The product derivative factor of the current channel is generated by averaging the sampling results of multiple samples of the simulated input. Arrange the product derivative factors of all channels into a factor matrix; The factor matrix is ​​multiplied by the correlation matrix to generate a sign vector with sign bits corresponding to the channels; Set the current bit position to the position of the most significant bit (MSB) of level 1 in the SAR; For all channels other than the reference channel: (b) When the symbol bit in the symbol vector corresponding to the selected channel is 1, a test bit is set at the current bit position in the SAR of the selected channel to adjust the variable input delay; (c) When the symbol bit in the symbol vector corresponding to the selected channel is 0, clear the test bit at the current bit position in the SAR of the selected channel to adjust the variable input delay; Decrease the bit position from the current bit position and repeat step (a) until the current bit position is the least significant bit (LSB) in the SAR; The calibration ends when all product derivative correlators have been used to adjust the settings in the SAR to adjust the variable input delay, thereby minimizing the time phase mismatch in all channels.

12. The calibration matrix method of claim 11, further comprising: Activating the background calibration process to adjust the settings in the SAR previously calibrated, the background calibration process includes: (a) For each channel: The ADC digital outputs from the current channel, the previous adjacent channel, and the next adjacent channel are input to a product derivative correlator, which generates a product derivative factor sampling result for quantifying the correlation between the ADC digital output of the current channel and the ADC digital outputs of the previous and next adjacent channels. The product derivative factor of the current channel is generated by averaging the sampling results of the product derivative factor of the multiple samples of the simulated input. Arrange the product derivative factors of all channels into a factor matrix; The factor matrix is ​​multiplied by the correlation matrix to generate a sign vector with sign bits corresponding to the channels; Set the current bit position to the position of the most significant bit (MSB) of level 1 in the SAR; For all channels other than the reference channel: (b) When the symbol bit in the symbol vector corresponding to the selected channel is 1 and the symbol bit from the previous iteration is 1, add an LSB test bit at the least significant bit (LSB) bit position in the SAR of the selected channel to adjust the variable input delay. (c) When the symbol bit in the symbol vector corresponding to the selected channel is 0 and the symbol bit was 0 for the previous iteration, the LSB test bit is subtracted at the LSB bit position in the SAR of the selected channel to adjust the variable input delay; Repeat step (a) until the endpoint is reached.

13. The calibration matrix method as described in claim 11, wherein, All product derivative correlators in the same stage are calibrated in parallel.

14. The calibration matrix method as described in claim 11, wherein, A multi-stage product derivative correlator for serial processing is implemented by reusing a single product derivative correlator hardware.

15. A calibration matrix alternating analog-to-digital converter (ADC), comprising: There are N channels, where N is an integer of at least 3, and each channel includes: An ADC with analog input for sampling and digital output; A sampling switch between the analog input and the sampled analog input, the sampling switch being responsive to a delayed clock; The successive approximation register (SAR) is used to store the delay settings; A delay element for generating a variable delay between an input clock and the delayed clock, wherein the variable delay is determined by the delay setting in the SAR; A filter used to generate a filtered channel output from the digital output of the ADC; A product derivative correlator for receiving the filtered channel output of a certain channel and the filtered channel output from an adjacent channel, the product derivative correlator generating a product derivative factor indicating the correlation between the channel and the adjacent channel; A matrix processor receives a plurality of product derivative factors from the product derivative correlators of the N channels and generates a sign bit vector by multiplying the plurality of product derivative factors with a correlation matrix; and A calibrator that uses each symbol bit in the symbol bit vector to determine when to add a test bit to the SAR in a certain channel and when to remove the test bit from the SAR in the channel, wherein each symbol bit in the symbol bit vector is used to add or remove a test bit to the SAR in different channels of the N channels.

16. The calibration matrix alternating ADC as described in claim 15, wherein, The matrix processor forms a product derivative factor matrix with N rows and 1 column from the multiple product derivative factors from the N channels, wherein the correlation matrix has N-1 rows and N columns, and the sign bit vector has N-1 sign bits.

17. The calibration matrix alternating ADC as described in claim 16, wherein, The correlation matrix is ​​generated from a shift matrix having N rows and N-1 columns, wherein the correlation matrix is ​​the transpose of the shift matrix divided by the product of the transpose of the shift matrix and the shift matrix.

18. The calibration matrix alternating ADC as described in claim 15, wherein, The adjacent channel includes two adjacent channels, wherein the product derivative correlator generates the product derivative factor indicating the correlation between the channel and the two adjacent channels.

19. The calibration matrix alternating ADC as described in claim 15, wherein, The product derivative correlator further includes: An averager is used to average the sample product derivative factors from the product derivative correlator for M simulated input samples, thereby generating the product derivative factors output to the matrix processor, where M is an integer.

20. The calibration matrix alternating ADC as described in claim 15, wherein, The calibrator further includes: A tester is configured to set test bits in the SAR for all channels of the symbol bit having a value of 1 in the symbol bit vector, clear the test bits in the SAR for all channels of the symbol bit having a value of 0 in the symbol bit vector, and repeat the above operations for adjacent bit positions in the SAR. Therefore, the sign bit of each channel is used to add or subtract consecutive bits in the SAR.

Images