Storage device and method of operating a storage device

Abstract

The present disclosure relates to methods, systems, and apparatuses for alleviating bandwidth bottlenecks during embedded operations. Based on the disclosed techniques, an exemplary storage device includes: a memory device configured to store matrix data; a memory controller coupled to the memory device and configured to receive non-zero data and indices of the non-zero data from a host and generate vector data based on the non-zero data and the indices; and an arithmetic component coupled to the memory device and the memory controller and configured to perform a multiplication operation between the matrix data and the vector data.

Description

[0001] Cross - reference to related applications

[0002] This patent document claims the priority and benefit of a Korean patent application filed on Dec. 22, 2020, with application number 10 - 2020 - 0181089, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a storage device and a method of operating the storage device. Background Art

[0004] A storage device is a device configured to store data under the control of a host device such as a computer, a smart phone, etc. The storage device may include a memory device configured to store data and a memory controller configured to control the memory device. The memory device may be classified as a volatile memory device or a non - volatile memory device.

[0005] A volatile memory device may be a memory device configured to store data only during power supply and to erase the stored data when the power supply is interrupted. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] A non - volatile memory device is a memory device configured such that data is not erased even when the power supply is interrupted. Examples of non - volatile memory devices include read - only memory (ROM), programmable memory (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] Embodiments of the disclosed technology relate to a storage device and a method of operating the storage device, which can also reduce bandwidth bottlenecks during embedded operations and other features and benefits.

[0008] In an embodiment for implementing the disclosed technology, a storage device may include: a memory device configured to store matrix data; a memory controller coupled to the memory device, configured to receive non - zero data and an index of the non - zero data from a host, and generate vector data based on the non - zero data and the index; and an arithmetic component coupled to the memory device and the memory controller, configured to perform a multiplication operation between the matrix data and the vector data.

[0009] Embodiments of the present disclosure may provide a method for operating a storage device. The method may include storing matrix data, receiving non-zero data and an index of the non-zero data from a host, generating vector data based on the non-zero data and the index, and performing a multiplication operation between the matrix data and the vector data.

[0010] Embodiments of the present disclosure may provide a storage device. The storage device may include: a memory device configured to store an embedding table including a plurality of embedding vectors; a memory controller coupled to the memory device and configured to receive non-zero data included in a first one-hot vector corresponding to target data and an index of the non-zero data from a host, and generate a second one-hot vector based on the non-zero data and the index; and an operation component coupled to the memory device and the memory controller and configured to calculate an embedding vector of the target data based on the embedding table and the second one-hot vector. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating an exemplary computing system according to an embodiment of the presently disclosed technology.

[0012] Figure 2 is a diagram illustrating an exemplary embedded operation according to an embodiment of the presently disclosed technology.

[0013] Figure 3 is a diagram illustrating an exemplary one-hot vector according to an embodiment of the presently disclosed technology.

[0014] Figure 4 is a diagram illustrating an exemplary storage device according to an embodiment of the presently disclosed technology.

[0015] Figure 5 is a diagram illustrating an example of transmitting non-zero data and an index according to an embodiment of the presently disclosed technology.

[0016] Figure 6 is a diagram illustrating an example of generating vector data according to an embodiment of the presently disclosed technology.

[0017] Figure 7 is a flowchart illustrating an exemplary method for operating a storage device according to an embodiment of the presently disclosed technology.

[0018] Figure 8 is a diagram illustrating according to an embodiment of the presently disclosed technology Figure 1 illustrating an exemplary component of the memory controller shown. DETAILED DESCRIPTION

[0019] Figure 1is a diagram showing an exemplary computing system according to an embodiment of the presently disclosed technology. As shown, the computing system 10 includes a storage device 50 and a host 400.

[0020] In some embodiments, the storage device 50 includes a memory device 100, a memory controller 200 configured to control the operation of the memory device 100, and an arithmetic component 300. The storage device 50 may be a device configured to store data under the control of a host 400 such as: a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game controller, a TV, a tablet PC, or an in-vehicle infotainment system, etc.

[0021] In some embodiments, the storage device 50 is fabricated as any one of various types of storage devices according to a host interface which is a method of communicating with the host 400. For example, the storage device 50 may be configured as any one of various types of storage devices such as: a solid state drive (SSD), a multimedia card (MMC), an eMMC, a reduced-size MMC (RS-MMC), or a multimedia card in the form of a micro MMC, a secure digital (SD) card, a mini SD, or a micro SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a storage device in the form of a Personal Computer Memory Card International Association (PCMCIA) card, a storage device in the form of a Peripheral Component Interconnect (PCI) card, a storage device in the form of a high-speed PCI (PCI-E) card, a compact flash (CF) card, a smart media card, a memory stick, etc.

[0022] In some embodiments, the storage device 50 may be fabricated as any one of various types of package forms. For example, the storage device 50 may be fabricated as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and / or a wafer level stack package (WSP), etc.

[0023] Continuing Figure 1 the description, the storage device 50 includes a memory device 100 and a memory controller 200, and the memory controller 200 is configured to control the operation of the memory device 100. In an example, the storage device 50 is a device configured to store data under the control of a host 400 such as: a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system, etc.

[0024] In some embodiments, the memory device 100 stores data and is operated and controlled by the memory controller 200.

[0025] In some embodiments, the memory device 100 may include a memory cell array ( Figure 1 not shown in FIG. Figure 1 ), which includes a plurality of memory cells configured to store data. Each of the memory cells may be configured as a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC). The SLC is configured to store a single data bit, the MLC is configured to store two data bits, the TLC is configured to store three data bits, and the QLC is capable of storing four data bits.

[0026] In some embodiments, the memory cell array includes a plurality of memory blocks. In an example, each of the memory blocks includes a plurality of memory cells. In another example, a single memory block includes a plurality of pages. In these embodiments, a page may be a unit in which data is stored in the memory device 100 or a unit for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0027] In some embodiments, the memory device 100 is a volatile memory device. For example, the memory device 100 may be a dynamic random access memory (DRAM), SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc.

[0028] In some embodiments, the memory device 100 is a non-volatile memory device. For example, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM), etc.

[0029] In some embodiments, the memory device 100 is configured to receive a command CMD and an address ADDR from the memory controller 200, and is configured to access a region selected by the address in the memory cell array. The memory device 100 may perform an operation specified by the command CMD on the region selected by the address ADDR. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 programs data into the region selected by the address ADDR. During the read operation, the memory device 100 reads data from the region selected by the address ADDR. During the erase operation, the memory device 100 erases the data stored in the region selected by the address ADDR.

[0030] In some embodiments, the memory controller 200 may control all operations of the storage device 50. In other embodiments, when power is applied to the storage device 50, the memory controller 200 may run firmware FW.

[0031] In some embodiments, the memory controller 200 receives data and a logical block address (LBA) from the host 400, and converts the logical block address into a physical block address (PBA), which indicates the address of the memory cells in the memory device 100 where the data is to be stored. In this patent document, the logical block address (LBA) and the "logical address" may be used interchangeably as having the same meaning, and the physical block address (PBA) and the "physical address" may be used interchangeably as having the same meaning.

[0032] In some embodiments, the memory controller 200 controls the memory device 100 to perform programming operations, read operations, erase operations, etc. in response to a request from the host 400. During the programming operation, the memory controller 200 provides a write command, a physical block address, and data to the memory device 100. During the read operation, the memory controller 200 provides a read command and a physical block address to the memory device 100. During the erase operation, the memory controller 200 provides an erase command and a physical block address to the memory device 100.

[0033] In some embodiments, the memory controller 200 controls two or more memory devices 100. In this case, the memory controller 200 controls the two or more memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be a method in which the operations of two or more memory devices 100 are controlled to overlap.

[0034] Continuing Figure 1 the description, the arithmetic component 300 may perform arithmetic operations such as addition, multiplication, etc. For example, the arithmetic component 300 may include a calculation unit for performing arithmetic operations.

[0035] As Figure 1 shown, the memory controller 200 and the computing component 300 are separate and distinct devices from each other, but are not limited thereto. For example, the computing component 300 may be implemented as a component of the memory controller 200.

[0036] In some embodiments, the host 400 communicates with the storage device 50 using at least one of various communication methods such as: Universal Serial Bus (USB), Serial ATA (SATA), Serial SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Low-Rank DIMM (LRDIMM), etc.

[0037] In some embodiments, the computing system 10 is configured to provide a recommendation system. For example, the recommendation system may recommend items (e.g., movies, music, news, books, products, etc.) that a user may be interested in based on information about the user. In some embodiments, the computing system 10 uses a deep learning-based recommendation model to provide the recommendation system. Herein, the recommendation model may be a learning model trained using multiple training data sets. For example, the deep learning-based recommendation model includes multiple neural networks and uses multiple training data sets to train the multiple neural networks. Each of the neural networks includes multiple layers. For example, a neural network may include an input layer, one or more hidden layers, and an output layer. A neural network including multiple hidden layers is referred to as a "deep neural network", and training a deep neural network is referred to as "deep learning". Hereinafter, training a neural network may be understood as training the parameters of the neural network, and a trained neural network may be understood as a neural network to which the trained parameters have been applied.

[0038] In some embodiments, the recommendation system of the computing system 10 is controlled by the host 400. For example, the host 400 includes a host processor and a host memory. The host processor may be a general-purpose processor such as a Central Processing Unit (CPU), an Accelerated Processing Unit (APU), a Digital Signal Processor (DSP), etc., a graphics processor such as a Graphics Processing Unit (GPU) or a Vision Processing Unit (VPU), an artificial intelligence (AI) processor such as a Neural Processing Unit (NPU). The host memory may store an operating system or an application program for providing the recommendation system.

[0039] In some embodiments, a deep learning-based recommendation system may cause bandwidth issues due to performing memory-intensive embedded operations and may cause host memory capacity shortages due to the need for a large amount of service data. Therefore, the computing system 10 may use the storage device 50 to perform embedding to achieve efficient embedding.

[0040] In some embodiments, the host 400 controls the storage device 50 to obtain an embedding vector of target data. For example, the host 400 requests an embedding vector from the storage device 50, thereby obtaining a corresponding embedding vector from the storage device 50. Using the provided embedding vector, the host 400 performs various operations for outputting a recommendation result based on a preset algorithm.

[0041] In some embodiments, the memory device 100 stores an embedding table including a plurality of embedding vectors.

[0042] In some embodiments, the memory controller 200 receives non-zero data and an index of the non-zero data from the host 400. Here, the non-zero data is data having a non-zero value among the values of vector elements in a one-hot vector corresponding to target data. The index indicates the position of the vector element in the one-hot vector. For example, the index i indicates the i-th vector element. The index of the non-zero data may be the index of the vector element having the non-zero data. Then, the memory controller 200 generates vector data based on the non-zero data and the index. For example, the generated vector data is a one-hot vector of target data.

[0043] In some embodiments, the arithmetic component 300 calculates an embedding vector of target data based on the embedding table and the vector data generated by the memory controller 200. For example, the arithmetic component 300 calculates the embedding vector through a multiplication operation between the embedding table and the vector data. Then, the memory controller 200 provides the calculated embedding vector to the host 400.

[0044] Figure 2 is a diagram showing an exemplary embedded operation according to an embodiment of the currently disclosed technology.

[0045] As Figure 2 shown, the embedded operation can be performed as an operation between a one-hot vector and an embedding table. Here, the one-hot vector is a vector in which one of a plurality of vector elements has a non-zero value and the remaining vector elements have zero values. A description of the one-hot vector will be further clarified with reference to Figure 3 below.

[0046] In some embodiments, the embedding table includes vector information obtained through embedding learning using multiple training data sets. In some embodiments, the embedding table includes multiple embedding vectors representing multiple pieces of data in the form of n-dimensional vectors. For example, the rows of the embedding table can be the embedding vectors of multiple pieces of data. Therefore, the number of rows of the embedding table can be determined based on the number of pieces of data. In addition, the number of columns of the embedding table can be set based on the dimension in which the embedding vectors are intended to be used. In this example, the dimension of the embedding vectors can be lower than the dimension of one-hot vectors.

[0047] In some embodiments, the multiple pieces of data are categorical data that can be classified into categories. For example, the multiple pieces of data can be items recommended by the computing system 10 and can be digitized in the form of vectors having similarities among the multiple pieces of data through an embedding operation. The vector information digitized in the form of vectors can be referred to as embedding vectors.

[0048] For example, the embedding vector of a specific piece of data is calculated through an operation between the one-hot vector of the specific piece of data and the embedding vector. Here, the one-hot vector of the specific piece of data is configured such that only the vector element corresponding to the index assigned to the specific piece of data has a non-zero value and the remaining vector elements have zero values. Therefore, through the operation between the one-hot vector of the specific piece of data and the embedding vector, the embedding vector of the specific piece of data can be determined from the multiple embedding vectors included in the embedding table.

[0049] Although, as in the above example, the embedding operation is described as an operation between the first-placed one-hot vector and the second-placed embedding table, it is not limited thereto. For example, the embedding operation can be performed through an operation between the first-placed embedding table and the second-placed one-hot vector. In the latter case, the one-hot vector can take the form of a column vector instead of a row vector, and the columns of the embedding table can be the embedding vectors of multiple pieces of data. In this case, the number of columns of the embedding table can be based on the number of pieces of data, and the number of rows of the embedding table can be based on the dimension in which the embedding vectors are intended to be used.

[0050] Figure 3 is a diagram showing an exemplary one-hot vector according to an embodiment of the currently disclosed technology.

[0051] As Figure 3 shown, it is assumed that index 1 is assigned to data a, index 2 is assigned to data b, and index 4 is assigned to data c. It is also assumed that the indices of the vector elements included in the one-hot vector increase sequentially.

[0052] In some embodiments, the dimension of the one-hot vector can be based on the number of pieces of data to be represented using the one-hot vector. For example, when there are z pieces of data, the one-hot vector of each of the multiple pieces of data can be a z-dimensional vector.

[0053] In some embodiments, the positions of the non-zero values in the one-hot vector can be based on the index assigned to the data. For example, for the one-hot vector of data a, the value of the vector element corresponding to index 1 can be a non-zero value. Similarly, for the one-hot vector of data b, the value of the vector element corresponding to index 2 can be a non-zero value, and for the one-hot vector of data c, the value of the vector element corresponding to index 4 can be a non-zero value. In other words, the index of the non-zero value included in the one-hot vector can be the index assigned to the data represented by the corresponding one-hot vector.

[0054] In the above example of the recommendation system, the host 400 provides a one-hot vector to the storage device 50 to perform an embedding operation. However, as the number of data items represented by the embedding vector increases, the size of the one-hot vector also increases, resulting in a bandwidth bottleneck problem.

[0055] Embodiments of the presently disclosed technology describe determining an embedding vector based on index identification information of target data provided from the host 400, thereby solving the bandwidth bottleneck problem.

[0056] Figure 4 is a diagram showing an exemplary storage device according to an embodiment of the presently disclosed technology.

[0057] As Figure 4 shown, the storage device 50 includes a memory device 100, a memory controller 200, and an arithmetic component 300. In the example, the memory device 100, the memory controller 200, and the arithmetic component 300 can be Figure 1 the memory device 100, the memory controller 200, and the arithmetic component 300 shown.

[0058] In some embodiments, the memory device 100 stores matrix data, which can be data in matrix form. For example, the matrix data can be an embedding table including multiple embedding vectors representing multiple data items in the form of n-dimensional vectors.

[0059] In some embodiments, the memory device 100 stores the matrix data in multiple memory regions. For example, the memory region can be a memory cell, a page, a storage block, a plane, a die, etc. The memory controller 200 can transmit data (e.g., matrix data) to the host 400 and receive data (e.g., matrix data) from the host 400.

[0060] In some embodiments, the memory controller 200 receives non-zero data and an index of the non-zero data from the host 400. Here, the non-zero data indicates a value that is not zero among other zero-valued vector elements included in the one-hot vector corresponding to the target data. The index of the non-zero data indicates the index of the vector element having a non-zero value in the one-hot vector. For example, when the memory controller 200 requests an embedding vector of target data, the host 400 provides the non-zero data and the index of the non-zero data to the memory controller 200.

[0061] In some embodiments, the memory controller 200 generates vector data based on the non-zero data and the index of the non-zero data. Here, the vector data may be a one-hot vector in which the vector element corresponding to the index has a non-zero value and the remaining vector elements have zero values. For example, the memory controller 200 may generate vector data such that among the multiple vector elements of the vector data, the value of the vector element corresponding to the index includes the non-zero data and the values of the remaining vector elements other than the vector element corresponding to the index include zero-valued data.

[0062] In some embodiments, the arithmetic component 300 performs a multiplication operation between matrix data and vector data. For example, the memory controller 200 may read the matrix data from the memory device 100 and provide the matrix data and the vector data to the arithmetic component 300.

[0063] In some embodiments, the arithmetic component 300 performs an embedding operation using the matrix data and the vector data. Specifically, the arithmetic component 300 performs the embedding operation using the embedding table read from the memory device 100 and the one-hot vector generated by the memory controller 200.

[0064] In some embodiments, the arithmetic component 300 calculates any one of the multiple embedding vectors through a multiplication operation between the matrix data and the vector data. The calculated embedding vector is the embedding vector corresponding to the target data.

[0065] In some embodiments, the memory controller 200 provides the embedding vector of the target data to the host 400 in response to a request from the host 400.

[0066] This advantageously enables embodiments of the presently disclosed technology to provide the embedding vector to the host 400 based on the non-zero data and the index provided by the host 400, thereby reducing the bandwidth bottleneck problem.

[0067] Figure 5 It is a diagram showing an example of transmitting non-zero data and an index according to an embodiment of the presently disclosed technology.

[0068] As shown in the figure, it is assumed that the one-hot vector corresponding to the target data is configured such that the i-th vector element includes non-zero data.

[0069] In some embodiments, non-zero data indicates a non-zero value among the values of vector elements included in a one-hot vector corresponding to target data. For example, the non-zero data may be "1". The index of the non-zero data (index i) indicates the index of the vector element in the one-hot vector that has the non-zero data.

[0070] In some embodiments, in response to a request for an embedded vector of target data, the host 400 provides the non-zero data and the index i that is the index of the non-zero data to the memory controller 200.

[0071] Although the non-zero data is described as "1" in the above example, it is not limited thereto, and in other embodiments, the non-zero data may include any non-zero value.

[0072] Figure 6 is a diagram showing an example of generating vector data according to an embodiment of the presently disclosed technology.

[0073] As shown in the figure, the memory controller 200 generates vector data based on the non-zero data and the index of the non-zero data (index i). Here, the vector data may be a one-hot vector.

[0074] For example, the vector data may include a plurality of vector elements. In some embodiments, among the plurality of vector elements of the vector data, the value of the vector element corresponding to the index may include non-zero data. For example, the memory controller 200 may set the value of the i-th vector element corresponding to the index i to be the non-zero data "1". The values of the remaining vector elements of the vector data include zero-valued data. For example, the memory controller 200 may set the values of the remaining vector elements other than the i-th vector element to be the zero-valued data "0". Thus, using the non-zero data and the index i, the memory controller 200 can generate a one-hot vector in which the value of the i-th vector element is "1" and the values of the remaining vector elements are "0" as the vector data.

[0075] Therefore, embodiments of the presently disclosed technology generate a one-hot vector using non-zero data and its index, and transmit the one-hot vector to solve the bandwidth bottleneck problem.

[0076] Figure 7 is a flowchart showing an exemplary method of operating a storage device according to an embodiment of the presently disclosed technology.

[0077] Figure 7 The method shown may be performed by, for example Figure 1 or Figure 4 the storage device 50 shown.

[0078] As Figure 7As shown, in step S701, the storage device 50 may store matrix data. In the example, the matrix data may be an embedding table including a plurality of embedding vectors.

[0079] In step S703, the storage device 50 receives non-zero data and an index of the non-zero data from the host 400.

[0080] In step S705, the storage device 50 generates vector data based on the non-zero data and its index.

[0081] In the example, the vector data may be a one-hot vector.

[0082] In another example, the storage device 50 generates vector data such that among the multiple vector elements of the vector data, the value of the vector element corresponding to the index includes the non-zero data and the values of the remaining vector elements other than the vector element corresponding to the index include zero-valued data.

[0083] In step S707, the storage device 50 performs a multiplication operation between the matrix data and the vector data.

[0084] In the example, the storage device 50 performs an embedding operation using the matrix data and the vector data.

[0085] In another example, the storage device 50 calculates any one of the multiple embedding vectors included in the embedding table through the multiplication operation between the matrix data and the vector data.

[0086] In step S709, the storage device 50 provides any one of the embedding vectors to the host 400.

[0087] Figure 8 is a diagram showing Figure 1 an exemplary component of the memory controller shown.

[0088] Referring to Figure 1 and Figure 8 the memory controller 200 includes a processor 240, a RAM 250, an error correction circuit 260, a ROM 270, a host interface 280, and a memory interface 290.

[0089] The processor 240 controls all operations of the memory controller 200. The RAM 250 can be used as a buffer memory, a cache memory, an arithmetic memory, etc. of the memory controller 200.

[0090] The error correction circuit 260 performs error correction. The error correction circuit 260 performs ECC encoding based on data to be written to the memory device through the memory interface 290. The ECC-encoded data can be transferred to the memory device through the memory interface 290. Then, the error correction circuit 260 performs ECC decoding on the data received from the memory device through the memory interface 290. For example, the error correction circuit 260 can be included in the memory interface 290 as a component of the memory interface 290.

[0091] The ROM 270 stores various information required for the operation of the memory controller 200 in the form of firmware.

[0092] In an example, the memory controller 200 communicates with an external device (e.g., the host 400, an application processor, etc.) through the host interface 280.

[0093] In another example, the memory controller 200 communicates with the memory device 100 through the memory interface 290. The memory controller 200 can transmit commands, addresses, control signals, etc. to the memory device 100 through the memory interface 290 and receive data from the memory device 100.

[0094] The presently disclosed technology describes a storage device capable of reducing bandwidth bottlenecks during embedded operations and a method of operating the storage device.

[0095] Although this patent document contains many details, these details should not be construed as limitations on the scope of any invention or what may be claimed, but rather as descriptions of specific features of particular embodiments of a particular invention. Certain features described in the context of different embodiments in this patent document can also be implemented in a single embodiment in combination. Conversely, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although the above features may be described as acting in certain combinations and even initially claimed as such, one or more features of the combination can in some cases be removed from the claimed combination, and the claimed combination can be directed to a sub-combination or a variation of the sub-combination.

[0096] Similarly, although operations are described in a particular order in the drawings, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed to achieve the desired result. Additionally, the separation of various system components in the embodiments described in this patent document should not be construed as required in all embodiments.

[0097] Only some embodiments and examples are described, and other embodiments, enhancements, and variations can be obtained based on what is described and shown in this patent document.

Claims

1. A storage device, comprising: A non-volatile memory device that stores matrix data including a plurality of embedding vectors; and at least one processor coupled to the non-volatile memory device, the at least one processor: receives from a host a request for an embedding vector among a plurality of embedding vectors, non-zero data included in a target vector associated with the embedding vector, and an index of the non-zero data, where the index is information identifying a vector element having a non-zero value among a plurality of vector elements included in the target vector; generates the target vector such that at least one vector element identified by the index includes the non-zero data, and the remaining vector elements among the plurality of vector elements include zero data; and generates the embedding vector based on the matrix data and the target vector.

2. The storage device according to claim 1, wherein the target vector includes a one - hot vector.

3. The storage device according to claim 2, wherein the plurality of embedding vectors includes information corresponding to multiple data formatted as n - dimensional vectors.

4. The storage device according to claim 2, wherein the at least one processor performs an embedding operation using the matrix data and the target vector.

5. The storage device according to claim 4, wherein the at least one processor calculates the embedding vector based on a multiplication operation between the matrix data and the target vector.

6. The storage device according to claim 5, wherein the at least one processor provides the embedding vector to the host.

7. A method of operating a storage device, comprising: Stores matrix data including a plurality of embedding vectors; Receives from a host a request for an embedding vector among a plurality of embedding vectors, non-zero data included in a target vector associated with the embedding vector, and an index of the non-zero data, where the index is information identifying a vector element having a non-zero value among a plurality of vector elements included in the target vector; Generates the target vector by at least one processor such that at least one vector element identified by the index includes the non-zero data, and the remaining vector elements among the plurality of vector elements include zero data; and Generates the embedding vector by the at least one processor based on the matrix data and the target vector.

8. The method according to claim 7, wherein the target vector includes a one - hot vector.

9. The method according to claim 8, wherein the plurality of embedding vectors includes information corresponding to multiple data formatted as n - dimensional vectors.

10. The method according to claim 8, wherein generating the embedding vector includes performing an embedding operation using the matrix data and the target vector.

11. The method according to claim 10, wherein generating the embedding vector includes calculating the embedding vector based on a multiplication operation between the matrix data and the target vector.

12. The method according to claim 11, further comprising: Provides the embedding vector to the host.

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