Method for implementing VPTAT multiplier in high-precision thermal sensor

Abstract

The present disclosure relates to a method for implementing a VPTAT multiplier in a high-precision thermal sensor. A temperature sensing circuit and a switched capacitor circuit selectively sample ΔVbe and Vbe voltages and provide the sampled voltages to the input of an integrator. A quantization circuit quantizes the output of the integrator to generate a bit stream. When the latest bit of the bit stream is a logic zero, the operation includes sampling and integrating ΔVbe a first given number of times to generate a voltage proportional to the absolute temperature. When the latest bit of the bit stream is a logic one, the operation includes sampling and integrating Vbe a second given number of times to generate a voltage complementary to the absolute temperature. A low-pass filter and a decimator filter and decimate the bit stream generated by the quantization circuit to generate a signal indicating the temperature of a chip in which the temperature sensing circuit is integrated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 129,244, filed on December 22, 2020, the contents of which are incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present application relates to the field of temperature sensing circuits, and more particularly to temperature sensing circuits that utilize a sigma-delta-based analog-to-digital converter to generate a high-precision temperature value, from which the temperature of an integrated circuit chip in which the temperature sensing circuit is placed can be determined. Sigma-delta-based analog-to-digital converters scale input voltages in the time domain, thereby resolving mismatch issues. Background Art

[0004] Systems on a chip (SOCs) are used in mobile devices such as smartphones and tablets, as well as in many embedded systems. Some current SOCs are capable of temperature-aware task scheduling and temperature-dependent self-calibration to help reduce power consumption. To achieve this functionality, such SOCs include an on-chip temperature sensor integrated with the other components of the SOC.

[0005] A voltage proportional to absolute temperature, Vptat, can be generated as the difference between the base-emitter junction voltages of two bipolar junction transistors biased at different current densities. Mathematically, this can be expressed as: Vptat = ΔVbe = Vbe1 - Vbe2. This voltage proportional to absolute temperature, Vptat, is relatively error-free in its generation because the errors in Vbe1 and Vbe2 due to the lack of ideal transistor performance cancel each other out.

[0006] The relationship between Vptat and temperature can be expressed mathematically as Where T is the temperature in Kelvin, k is the Boltzmann constant, q is the magnitude of the electron charge, and p is the ratio of the current densities of the bipolar junction transistors used to generate Vptat. The analog-to-digital converter (ADC) digitizes Vptat relative to a temperature-independent reference voltage Vref and thus outputs a ratio μ, which can be calculated as This ratio can be scaled appropriately to produce a digital temperature reading in the desired units, for example:

[0007] temperature Where A and B are constants.

[0008] In order to achieve temperature independence of the reference voltage Vref, the reference voltage Vref is usually generated as the sum of a voltage proportional to the absolute temperature Vptat and a voltage complementary to the absolute temperature Vctat, such as Figure 1 Visible in.

[0009] A voltage Vctat complementary to absolute temperature is generated as a base-emitter junction voltage Vbe of the bipolar junction transistor.

[0010] An example thermal sensor incorporating these principles is disclosed in U.S. patent application No. 17 / 136,240, filed on December 29, 2020, entitled “CONTROLLED CURVATURE CORRECTION IN HIGHACCURACY THERMAL SENSOR,” (claiming priority to provisional patent application No. 62 / 968,539, filed on January 31, 2020), the contents of which are incorporated by reference in their entirety.

[0011] The example thermal sensor includes a switched capacitor sigma-delta modulated analog-to-digital converter (ADC) that samples an input voltage (Vptat, as described above) and converts it into a digital bit stream by employing a loop filter based on an SC integrator module. The output of the loop filter is processed by a quantizer to produce a bit stream. This bit stream is used to apply appropriate feedback to complete the negative feedback loop. Specifically, in the input sampling circuit of the sigma-delta modulated ADC, a reference voltage (Vref, as described above) is sampled based on the previously generated bit stream and subtracted from the sampled input voltage Vptat. This complete loop encodes the bit stream in the time domain so that an appropriate digital decimation filter can generate a digital code corresponding to a representation of the ratio of the input voltage Vptat to the reference voltage Vref from the bit stream.

[0012] In more detail, the input sampling circuit of the sigma-delta modulation ADC is used to sample the input voltage Vptat based on the base-emitter junction voltages of two bipolar junction transistors biased with different current densities, and generate a reference voltage Vref by sampling Vptat and Vctat (the base-emitter junction voltage Vbe of the bipolar junction transistors).

[0013] To scale Vptat and Vctat, appropriately proportioned sampling capacitors are used to sample these voltages separately. Specifically, Vptat (note that Vptat = ΔVbe = Vbe1 - Vbe2) is sampled across α sampling capacitors as a voltage αΔVbe, while Vctat (note that Vctat = Vbe) is sampled across a single sampling capacitor as a voltage Vbe. As described above, the detected temperature is based on the ratio To generate, when substituting Vptat = αΔVbe and Vref = Vptat + Vctat = αΔVbe + Vbe, the ratio is equal to Thus, it can be appreciated that errors in the alpha capacitors, for example due to mismatches in capacitance values ​​of different ones of the alpha capacitors, can lead to errors in the ratio μ, which in turn lead to errors in the detected temperature.

[0014] To avoid this, dynamic element matching can be used on the sampling capacitors. However, dynamic element matching can be hardware and power intensive, involving, for example, digital logic circuits, level shifters, switches, bus routing, etc.

[0015] Therefore, there is a need to further develop techniques for scaling the Vptat voltage in thermal sensors with high accuracy. Summary of the Invention

[0016] The temperature sensor circuit generates: a first base-emitter junction voltage (Vbe1) of a first bipolar junction transistor biased with a first current density (I); a second base-emitter junction voltage (Vbe2) of a second bipolar junction transistor, the base and collector of the second bipolar junction transistor being coupled to the base and collector of the first bipolar junction transistor, the second bipolar junction transistor being biased with a second current density (pI); and a third base-emitter junction voltage (Vbe) of a third bipolar junction transistor, the third bipolar junction transistor being biased with a calibrated current and having a nonlinear curvature that exists with temperature.

[0017] A switched capacitor sigma-delta modulation (SDM) analog-to-digital converter (ADC) samples its input voltage and converts it into a digital bit stream (1s and 0s) by employing a loop filter based on a switched capacitor integrator block. The order of the loop filter depends on the number of integrators used. The output of the loop filter is then processed by a quantizer to produce a bit stream. This bit stream is used to apply appropriate feedback to complete the negative feedback loop. In the input sampling circuit of the first integrator, a reference voltage is sampled and subtracted from the sampled input voltage, depending on the previously generated bit of the bit stream. This complete loop encodes the bit stream in the time domain so that an appropriate digital decimation filter can generate a digital code corresponding to an accurate representation of the ratio of the input voltage to the reference voltage from the bit stream.

[0018] In the thermal sensor disclosed herein, the input sampling circuit of the SDM-based ADC can be used to sample (and subsequently integrate) an input voltage proportional to absolute temperature (Vptat) based on Vbe1 and Vbe2. The SDM input sampling circuit can also generate a temperature-independent reference voltage (Vref) by sampling (and subsequently integrating) Vptat and Vctat.

[0019] Using the sigma-delta modulation principle, Vptat is sampled as an input voltage and then a sampled reference voltage associated with the bit stream is subtracted. Therefore, the sampled voltage can be Vptat or (Vptat-Vref), depending on whether the bit of the previously generated bit stream is 0 or 1. This sampled voltage can be integrated and further processed in the loop filter and quantizer to generate a bit stream. The bit stream generated by the quantizer is used to appropriately operate the switches of the switched capacitor circuit to achieve sampling and integration of Vptat and Vref in a manner that produces a sigma-delta encoded bit stream, which, after filtering and decimation over a given time window, represents a digital code that can be appropriately scaled to produce a digital temperature read in the desired units.

[0020] In one non-limiting example, when Vptat is sampled, sampling and integration are performed α times, and when Vref is sampled, sampling and integration are performed once, thereby providing a scaling of Vptat by α. In another non-limiting example, when Vptat is sampled, sampling and integration are performed p times, and when Vref is sampled, sampling and integration are performed q times, thereby providing a scaling of Vptat by α=p / q.

[0021] Thus, as will be appreciated by those skilled in the art, disclosed herein are techniques for scaling Vptat in the time domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a diagram showing that a temperature-independent reference voltage (Vref) is generated by adding a voltage (Vptat) proportional to absolute temperature and a voltage (Vctat) complementary to absolute temperature in a related art temperature sensor.

[0023] Figure 2 is a detailed schematic diagram of an on-chip temperature sensor utilizing a sigma-delta analog-to-digital converter according to the present disclosure.

[0024] Figure 3 It shows Figure 2 The on-chip temperature sensor switches during the sampling and integration phases to generate a Figures 4A to 4D The timing diagram of the control signals for the timing of the operating states is shown.

[0025] Figure 4A Shown Figure 2 A design that operates in the sampling phase when the previous output bit of the generated bit stream is a logic 0.

[0026] Figure 4B Shown Figure 2 A design that operates in the integration phase when the previous output bit of the generated bit stream is a logic 0.

[0027] Figure 4C Shown Figure 2 A design that operates in the sampling phase when the previous output bit of the generated bit stream is a logic 1.

[0028] Figure 4D Shown Figure 2 A design that operates in the integration phase when the previous output bit of the generated bit stream is a logic 1.

[0029] Figure 5 It shows the Figure 2 The on-chip temperature sensor switches during the sampling and integration phases to generate a Figures 4A to 4D A timing diagram of an alternative scheme of the timing control signals for the operating states is shown.

[0030] Figure 6 is a detailed schematic diagram of another design of an on-chip temperature sensor using a sigma-delta analog-to-digital converter in accordance with the present disclosure.

[0031] Figure 7A Shown Figure 6 A design that operates in the sampling phase when the previous output bit of the generated bit stream is a logic 0.

[0032] Figure 7B Shown Figure 6 A design that operates in the integration phase when the previous output bit of the generated bit stream is a logic 0.

[0033] Figure 7C Shown Figure 6 A design that operates in the sampling phase when the previous output bit of the generated bit stream is a logic 1.

[0034] Figure 7D Shown Figure 6 A design that operates in the integration phase when the previous output bit of the generated bit stream is a logic 1. DETAILED DESCRIPTION

[0035] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but rather to the widest scope consistent with the principles and features disclosed or suggested herein. It should be noted that in the following description, unless otherwise stated, any resistor or resistance described is a discrete device, not just an electrical lead between two points. Therefore, any resistor or resistance described that is coupled between two points has a greater resistance than the lead between the two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitance described is a discrete device, not a parasitic device. In addition, unless otherwise stated, any inductor or inductance described is a discrete device, not a parasitic device.

[0036] Now refer to Figure 2 The structure of the temperature sensor circuit 5 is described in detail, and then referring to FIG. Figure 3 and Figures 4A to 4D The operation of the temperature sensor circuit 5 is described.

[0037] A. Structure of Temperature Sensor Circuit

[0038] Temperature sensor circuit 5 is arranged to include a sigma-delta modulated analog-to-digital converter (ADC). Temperature sensor circuit 5 includes an analog voltage generation circuit 10; a switched capacitor input sampling circuit 20 having an input for receiving a voltage generated by analog voltage generation circuit 10 and differential signal outputs coupled to the non-inverting and inverting terminals of a first integrator 40. First integrator 40 has a differential signal output coupled to the differential signal input of a second integrator 50, which in turn has a differential signal output coupled to the differential signal input of a quantization circuit 60. Quantization circuit 60 generates a bit stream that is fed to a control signal generator 70 and a low-pass filtering and decimation circuit 65. Control signal generator 70 generates control signals Φ1, Φ2, Φ3, and Φ4 in response to the logic states of the bits of the bit stream, wherein the control signals control the switch actuation of the respective switches of switched capacitor input sampling circuit 20. The low-pass filtering and decimation circuit 65 generates an output code from the bit stream, which can be used to calculate the temperature of the integrated circuit chip in which the temperature sensor circuit 5 is integrated in desired units.

[0039] In detail, analog voltage generation circuit 10 includes bipolar junction PNP transistors QP1 and QP2, whose collectors and bases are connected to ground. The emitter of QP2 is connected to current source 11 to receive current I, and the emitter of QP1 is connected to current source 12 to receive current pI (i.e., the magnitude of current pI is equal to the magnitude of current I, scaled by a factor p). Voltage Vbe1, the voltage across the base-emitter junction of transistor QP1, is generated at the emitter of transistor QP1. Similarly, voltage Vbe2, the voltage across the base-emitter junction of transistor QP2, is generated at the emitter of transistor QP2.

[0040] Analog voltage generation circuit 10 also includes a PNP transistor QP3, whose collector and base are connected to ground, and whose emitter is connected to current source 13 to receive calibration current Ical. Voltage Vbe, the voltage across the base-emitter junction of transistor QP3, is generated at the emitter of transistor QP3. Voltage Vbe is complementary to absolute temperature and, therefore, can be referred to as Vctat.

[0041] The switched capacitor input sampling circuit 20 includes a switch S1 (closed when the control signal Φ3 is logic high and open otherwise) that selectively connects the voltage Vbe1 to the first node of a switch S2 (closed when the control signal Φ1 is logic high and open otherwise). The first node of the capacitor Cs1 is connected to the second node of the switch S2. The switch S3 (closed when the control signal Φ2 is logic high and open otherwise) selectively connects the second node of the capacitor Cs1 to the non-inverting terminal of the first integrator 41. The switch S4 (closed when the control signal Φ4 is logic high and open otherwise) selectively connects the first node of the switch S2 to the common-mode voltage Vcm. The switch S5 (closed when the control signal Φ2 is logic high and open otherwise) selectively connects the first node of the capacitor Cs1 to the common-mode voltage Vcm, and the switch S6 (closed when the control signal Φ1 is logic high and open otherwise) selectively connects the second node of the capacitor Cs1 to the common-mode voltage Vcm.

[0042] The switched capacitor input sampling circuit 20 further includes a switch S7 (closed when the control signal Φ3 is high, otherwise open) that selectively connects the voltage Vbe2 to the first node of a switch S8 (closed when the control signal Φ1 is high, otherwise open). The first node of capacitor Cs2 is connected to the second node of switch S8. Switch S9 (closed when the control signal Φ2 is high, otherwise open) selectively connects the second node of capacitor Cs2 to the inverting terminal of the first integrator 41. Switch S10 (closed when the control signal Φ4 is high, otherwise open) selectively connects the first node of switch S8 to the common-mode voltage Vcm. Switch S11 (closed when the control signal Φ2 is high, otherwise open) selectively connects the first node of capacitor Cs2 to the common-mode voltage Vcm. Switch S12 (closed when the control signal Φ1 is high, otherwise open) selectively connects the second node of capacitor Cs2 to the common-mode voltage Vcm.

[0043] The switched capacitor input sampling circuit 20 further includes a switch S13 (closed when the control signal Φ4 is logic high, otherwise open) that selectively connects the ground voltage to the first node of a switch S14 (closed when the control signal Φ1 is logic high, otherwise open). The second node of switch S14 is connected to the first node of capacitor Cs3. Switch S15 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the second node of capacitor Cs3 to the non-inverting input of the first integrator 41. Switch S16 (closed when the control signal Φ3 is logic high, otherwise open) selectively connects the first node of switch S14 to the common-mode voltage Vcm. Switch S17 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the first node of capacitor Cs3 to the common-mode voltage Vcm, and switch S18 (closed when the control signal Φ1 is logic high, otherwise open) selectively connects the second node of capacitor Cs3 to the common-mode voltage Vcm.

[0044] Furthermore, switch S19 (closed when control signal Φ4 is logic high and open otherwise) selectively connects voltage Vbe to the first node of switch S20 (closed when control signal Φ1 is logic high and open otherwise). The second node of switch S20 is connected to the first node of capacitor Cs4. Switch S21 (closed when control signal Φ2 is logic high and open otherwise) selectively connects the second node of capacitor Cs4 to the inverting terminal of first integrator 41. Switch S22 (closed when control signal Φ3 is logic high and open otherwise) selectively connects the first node of switch S20 to common-mode voltage Vcm. Switch S23 (closed when control signal Φ2 is logic high and open otherwise) selectively connects the first node of capacitor Cs4 to common-mode voltage Vcm. Switch S24 (closed when control signal Φ1 is logic high and open otherwise) selectively connects the second node of capacitor Cs4 to common-mode voltage Vcm.

[0045] Capacitors Cs1 , Cs2 , Cs3 , and Cs4 may be matched and have equal capacitance values.

[0046] Integrator 40 is comprised of a fully differential amplifier 41 having a first integrating capacitor Ci1 connected between its non-inverting input and its non-inverting output, and a second integrating capacitor Ci2 connected between its inverting input and its inverting output. A second integrator 50 has differential inputs coupled to the non-inverting and inverting outputs of amplifier 41, and a differential output coupled to the differential inputs of a quantization circuit 60. Quantization circuit 60 has inputs coupled to a low-pass filtering and decimation circuit 65 and a control signal generator 70 (providing a bit stream). As described above, low-pass filtering and decimation circuit 65 provides an output digital code that is used to determine the temperature of the chip in which temperature sensor circuit 5 is integrated. Furthermore, as also described above, control signal generator 70 generates new control signals Φ1, Φ2, Φ3, Φ4 based on the most recently received bit of the bit stream.

[0047] B. Functional Operation of Temperature Sensor Circuit

[0048] First, the theory behind the operation of the temperature sensor circuit 5 is described.

[0049] The voltage generated by transistors QP1 and QP2, circuit 20, and the operation of first integrator 40, which is equal to (Vbe1-Vbe2), is proportional to absolute temperature and may be referred to as Vptat or ΔVbe. As will be explained below, by repeatedly sampling and integrating ΔVbe a number of times, ΔVbe may be scaled in the time domain by a factor of α to effectively produce a voltage αΔVbe. The voltage Vbe generated by transistor QP3 is complementary to absolute temperature and may be referred to as Vctat.

[0050] By adding the voltage Vbe to the voltage ΔVbe, a reference voltage Vref that is independent of temperature can be generated.

[0051] The goal of the temperature sensor circuit 5 is to generate a digital code that, obtained over a given time window, represents α*ΔVbe sampled relative to Vref, or in other words, it is the ratio μ=α*ΔVbe / Vref, which can be used in the formula Temperature=A*μ+B, where A and B are constants chosen so that the temperature is expressed in the desired units, such as degrees Celsius.

[0052] To achieve this, the sigma-delta modulation analog-to-digital converter is required to sample the voltage ΔVbe α times when the most recently generated bit stream value (produced by the quantization circuit 60) is a logic zero, and the sigma-delta modulation analog-to-digital converter is required to sample the voltage ΔVbe-Vref once when the most recently generated bit stream value is a logic one. It should be noted that mathematically, Vref = ΔVbe + Vbe, so sampling -Vbe is equivalent to sampling ΔVbe-Vref.

[0053] Now, refer to Figures 4A to 4D as well as Figure 3 The timing diagram of FIGURE 7 details the operation of the temperature sensor circuit. Upon receiving each pulse of the clock signal CLK, the control signal generator 70 generates new values ​​for the control signals Φ1, Φ2, Φ3, and Φ4 based on the logic value of the most recently received bit of the bit stream generated by the quantization circuit 60. The control signals Φ1, Φ2, Φ3, and Φ4 are generated so as to implement a sampling phase when the clock signal CLK is logic high and an integration phase when the clock signal CLK is logic low.

[0054] like Figure 4A Shown is the case where the most recently generated bit of the bit stream received by the control signal generator 70 is a logic one. In this case, Figure 3 As shown, when the clock signal CLK transitions to logic high at time t1 and the bit stream is at logic one, the control signal generator 70 causes the control signals Φ1 and Φ3 to transition to logic high and remain at logic high until the clock signal CLK transitions to logic low, while maintaining the control signals Φ2 and Φ4 at logic low, thereby starting the sampling phase.

[0055] The sampling phase Figure 4A , it can be seen that: switches S1, S2, and S6 are closed to sample the voltage Vbe1 referenced to the common-mode voltage Vcm across capacitor Cs1, thereby charging capacitor Cs1 to Vbe1-Vcm; and switches S7, S8, and S12 are closed to sample the voltage Vbe2 referenced to the common-mode voltage Vcm across capacitor Cs2, thereby charging capacitor Cs2 to Vbe2-Vcm. In addition, to maintain a consistent capacitive load on the first integrator 40 during the sampling and integration phases: switches S14, S16, and S18 are closed to sample the common-mode voltage Vcm referenced to itself across capacitor Cs3, thereby maintaining capacitor Cs3 at 0V; and switches S20, S22, and S24 are closed to sample the common-mode voltage Vcm referenced to itself across capacitor Cs4, thereby maintaining capacitor Cs4 at 0V.

[0056] When the clock signal CLK changes to logic low, as Figure 3As shown, the control signal generator 70 then causes the control signals Φ1 and Φ3 to transition to logic low, causes the control signal Φ2 to transition to logic high, and maintains the control signal Φ4 at logic low, thereby starting the integration phase. Figure 4B , in which it can be seen that switches S3 and S5 are closed to add the voltage Vcm to the voltage Vbe1-Vcm stored across capacitor Cs1, so that the voltage Vbe1 is applied to the non-inverting terminal of the integrator 41. And switches S9 and S11 are closed to add the voltage Vcm to the voltage Vbe2-Vcm stored across capacitor Cs2, so that the voltage Vbe2 is applied to the inverting terminal of the integrator 41.

[0057] Furthermore, to keep the capacitive loading on integrator 41 consistent during the sampling and integration phases: switches S15 and S17 are closed to add Vcm to the 0V stored across capacitor Cs3, thereby applying Vcm to the non-inverting terminal of integrator 41; and switches S21 and S23 are closed to add Vcm to the 0V stored across capacitor Cs4, thereby applying Vcm to the inverting terminal of integrator 41.

[0058] The voltages applied to the non-inverting terminal of integrator 41 are added to obtain voltage Vbe1+Vcm, while the voltages applied to the inverting terminal of integrator 40 are added to obtain voltage Vbe2+Vcm. Assuming that integrator 40 has unity gain, the integration result performed by integrator 40 is therefore voltage Vbe1-Vbe2.

[0059] It should be noted that Figure 3 As shown, when the bit stream is at 0, the sampling phase ( Figure 4A ) and the integration phase ( Figure 4B ) are repeated α times each. Therefore, α(Vbe1-Vbe2) is ultimately integrated when the bit stream is at 0, and the second integrator 50 further integrates the voltage α(Vbe1-Vbe2), which is then quantized by the quantization circuit 60 to generate the next bit of the bit stream. The next bit of the bit stream will be used by the control signal generator 70 to generate new values ​​for the control signals Φ1, Φ2, Φ3, and Φ4. Furthermore, the bit stream passes through the circuit 65, which performs low-pass filtering and decimation to produce an output digital code (where the ratio of 1s to 0s over a given time window represents the desired output μ, which can be used to calculate the temperature of the chip in which the temperature sensor circuit 5 is integrated).

[0060] Now assume that the next bit generated by quantization circuit 60 at time t2 is a logic 1. In this case, Figure 3As shown, when the clock signal CLK transitions to logic high and the bit stream is at logic zero, the control signal generator 70 causes the control signals Φ1 and Φ4 to transition to logic high and maintain logic high until the clock signal CLK transitions to logic low, while keeping the control signals Φ2 and Φ3 at logic low, thereby starting the sampling phase. Figure 4C , in which it can be seen that: switches S13, S14 and S18 are closed to sample the ground referenced to the common-mode voltage Vcm across capacitor Cs3, thereby charging capacitor Cs3 to the voltage GND-Vcm; and switches S19, S20 and S21 are closed to sample the voltage Vbe referenced to the common-mode voltage Vcm across capacitor Cs4, thereby charging capacitor Cs4 to the voltage Vbe-Vcm.

[0061] Furthermore, to keep the capacitive load on the first integrator 40 consistent during the sampling and integration phases: switches S2, S4, and S6 are closed to connect both sides of capacitor Cs1 to the common-mode voltage Vcm, thereby maintaining capacitor Cs1 at 0V; and switches S8, S10, and S12 are closed to connect both sides of capacitor Cs2 to the common-mode voltage Vcm, thereby maintaining capacitor Cs2 at 0V.

[0062] When the clock signal CLK changes to logic low, as Figure 3 As shown, the control signal generator 70 then causes the control signals Φ1 and Φ4 to transition to logic low, causes the control signal Φ2 to transition to logic high, and maintains the control signal Φ3 at logic low, thereby starting the integration phase. Figure 4D , in which it can be seen that: switches S2 and S15 are closed to add the voltage Vcm to the voltage GND-Vcm stored across the capacitor Cs3, thereby applying GND to the non-inverting terminal of the integrator 41; and switches S23 and S21 are closed to add the voltage Vcm to the voltage Vbe-Vcm stored across the capacitor Cs4, thereby applying Vbe to the inverting terminal of the integrator 41.

[0063] In addition, in order to keep the capacitive loading on the integrator 41 consistent during the sampling and integration phases: switches S2 and S5 are closed to add Vcm to the 0V stored across capacitor Cs1, thereby applying the voltage Vcm to the non-inverting terminal of the integrator 41; and switches S9 and S11 are closed to add Vcm to the 0V stored across capacitor Cs2, thereby applying the voltage Vcm to the inverting terminal of the integrator 41.

[0064] The voltages applied to the non-inverting terminal of the integrator 41 are added to obtain the voltage GND, while the voltages applied to the inverting terminal of the integrator 41 are added to obtain the voltage Vbe. Assuming that the integrator 41 has unity gain, the integration result performed by the integrator 41 is therefore the voltage -Vbe.

[0065] As mentioned above, when the bit stream is 0, the voltage -Vbe needs to be sampled, as shown above, which is determined by Figure 4D The integration result performed by the integrator 41 in .

[0066] Therefore, it can be seen that when the bit stream is 0, the integrator 41 integrates the voltage -Vbe as required. Figure 3 As shown, the sampling phase ( Figure 4C ) and the integration phase ( Figure 4D ) is performed once when the bit stream is at 0, so -Vbe is ultimately integrated when the bit stream is at 0, and a second integrator 50 performs a further integration of the voltage -Vbe, which is then quantized by a quantization circuit 60 to generate the next bit of the bit stream. The next bit of the bit stream will be used by a control signal generator 70 to generate new values ​​for the control signals Φ1, Φ2, Φ3, and Φ4. In addition, the bit stream passes through a low-pass filtering and decimation circuit 65, which performs low-pass filtering and decimation to produce an output digital code (where the ratio of 1s to 0s over a given time window represents the desired output μ, which can be used to calculate the temperature of the chip in which the temperature sensor circuit 5 is integrated).

[0067] Therefore, this design of temperature sensor 5 not only eliminates the need for digital component matching hardware, but also achieves ΔVbe scaling using a single capacitor rather than multiple capacitors. In other words, scaling ΔVbe by α is accomplished in the time domain, rather than in hardware by sampling Vbe1 and Vbe2 using the α capacitor. This eliminates mismatch errors because only a single capacitor is used for Vbe1 and Vbe2. Furthermore, this also offers the benefit of reduced wiring, which not only reduces space consumption but also reduces parasitic capacitance.

[0068] C. Alternative Configuration

[0069] In the above description, sampling and integration are described as being performed α times when the bit stream is 0 and once when the bit stream is 1 to provide an integral of α(Vbe1-Vbe2). However, as an alternative, sampling and integration may be performed p times when the bit stream is 0 and q times when the bit stream is 1 to thereby provide an integral of α(Vbe1-Vbe2), where α=p / q, as Figure 6 It should be noted that p and q are integers and thus allow for fractional scaling of ΔVbe. In some cases, p can be greater than q.

[0070] In view of the above description of the operation of the temperature sensor circuit 5, it should be apparent that during operation, only one voltage is applied to the non-inverting terminal of the integrator 41 and the inverting terminal of the integrator 41 at a time. Therefore, the design of the switched capacitor input sampling circuit 20' can be simplified, as shown in FIG. Figure 6 The temperature sensor circuit 5' is shown.

[0071] Here, the switched capacitor input sampling circuit 20′ includes a switch S30 (closed when the control signal Φ4 is logic high and open otherwise) that selectively connects ground to the first node of a switch S31 (closed when the control signal Φ1 is logic high and open otherwise). The second node of switch S31 is connected to the first node of capacitor Cs5. Switch S32 (closed when the control signal Φ2 is logic high and open otherwise) selectively connects the second node of capacitor Cs5 to the non-inverting input of the first integrator 40. Switch S33 (closed when the control signal Φ3 is logic high and open otherwise) selectively connects the first node of switch S31 to Vbe. Switch S34 (closed when the control signal Φ2 is logic high and open otherwise) selectively connects the first node of capacitor Cs5 to the common-mode voltage Vcm, and switch S35 (closed when the control signal Φ1 is logic high and open otherwise) selectively connects the second node of capacitor Cs5 to the common-mode voltage Vcm.

[0072] Switch S36 (closed when control signal Φ4 is logic high, otherwise open) selectively connects voltage Vbe to the first node of switch S37 (closed when control signal Φ1 is logic high, otherwise open). The second node of switch S37 is connected to the first node of capacitor Cs6. Switch S38 (closed when control signal Φ2 is logic high, otherwise open) selectively connects the second node of capacitor Cs6 to the inverting terminal of first integrator 40. Switch S39 (closed when control signal Φ3 is logic high, otherwise open) selectively connects the first node of switch S37 to Vbe2. Switch S29 (closed when control signal Φ2 is logic high, otherwise open) selectively connects the first node of capacitor Cs6 to common-mode voltage Vcm. Switch S28 (closed when control signal Φ1 is logic high, otherwise open) selectively connects the second node of capacitor Cs6 to common-mode voltage Vcm.

[0073] Capacitors Cs5 and Cs6 may be matched and have equal capacitance values.

[0074] Figure 6 The operation of the temperature sensor circuit 5' is now referred to 7A to 7D To describe.

[0075] Upon receipt of each pulse of the clock signal CLK, the control signal generator 70 generates new values ​​for the control signals Φ1, Φ2, Φ3, and Φ4 based on the logic value of the most recently received bit of the bit stream generated by the quantization circuit 60. The control signals Φ1, Φ2, Φ3, and Φ4 are generated so as to implement a sampling phase when the clock signal CLK is logic high and an integration phase when the clock signal CLK is logic low.

[0076] When the most recently generated bit of the bit stream received by the control signal generator 70 is a logic one, when the clock signal CLK transitions to a logic high at time t1, the control signal generator 70 causes the control signals Φ1 and Φ3 to transition to a logic high and maintain the logic high until the clock signal CLK transitions to a logic low, while keeping the control signals Φ2 and Φ4 at a logic low, thereby starting the sampling phase.

[0077] The sampling phase Figure 7A , in which it can be seen that: switches S31, S33 and S35 are closed to sample Vbe1 with reference to the common-mode voltage Vcm across capacitor Cs5, thereby charging capacitor Cs5 to a voltage of Vbe1-Vcm; and switches S37, S39 and S28 are closed to sample Vbe2 with reference to the common-mode voltage Vcm across capacitor Cs6, thereby charging capacitor Cs6 to a voltage of Vbe2-Vcm.

[0078] When the clock signal CLK then transitions to logic low, the control signal generator 70 then transitions the control signals Φ1 and Φ3 to logic low, transitions the control signal Φ2 to logic high, and maintains the control signal Φ4 at logic low, thereby starting the integration phase. Figure 7B , in which it can be seen that: switches S32 and S34 are closed to add the voltage Vcm to the voltage Vbe1-Vcm stored across capacitor Cs5, thereby applying Vbe1 to the non-inverting terminal of integrator 41; and switches S38 and S29 are closed to add the voltage Vcm to the voltage Vbe2-Vcm stored across capacitor C64, thereby applying Vbe2 to the inverting terminal of integrator 41.

[0079] The voltages applied to the non-inverting terminal of the integrator 41 are added to obtain voltage Vbe1, while the voltages applied to the inverting terminal of the integrator 41 are added to obtain voltage Vbe2. Assuming that the integrator 41 has unity gain, the integration result performed by the integrator 41 is therefore voltage Vbe1-Vbe2.

[0080] When the bit stream is at 0, the sampling phase ( Figure 7A ) and the integration phase ( Figure 7B) are repeated p times. Therefore, p(Vbe1-Vbe2) is finally integrated when the bit stream is at 0, and the second integrator 50 performs a further integration of the voltage p(Vbe1-Vbe2), which is then quantized by the quantization circuit 60 to generate the next bit of the bit stream. The next bit of the bit stream will be used by the control signal generator 70 to generate new values ​​of the control signals Φ1, Φ2, Φ3 and Φ4. In addition, the bit stream passes through the circuit 65, which performs low-pass filtering and decimation to produce an output digital code (where the ratio of 1s to 0s over a given time window represents the desired output μ, which can be used to calculate the temperature of the chip integrated with the temperature sensor circuit 5).

[0081] Now assume that the next bit generated by the quantization circuit 60 at time t2 is a logic 1. In this case, when the clock signal CLK transitions to logic high and the bit stream is at logic zero, the control signal generator 70 causes the control signals Φ1 and Φ4 to transition to logic high and remain at logic high until the clock signal CLK transitions to logic low, while keeping the control signals Φ2 and Φ3 at logic low, thereby starting the sampling phase. The sampling phase is Figure 7C , in which it can be seen that: switches S30, S31 and S35 are closed to sample the ground referenced to the common-mode voltage Vcm across capacitor Cs5, thereby charging capacitor Cs5 to the voltage GND-Vcm; and switches S36, S37 and S28 are closed to sample the voltage Vbe referenced to the common-mode voltage Vcm across capacitor Cs6, thereby charging capacitor Cs6 to the voltage Vbe-Vcm.

[0082] When the clock signal CLK then transitions to logic low, the control signal generator 70 then transitions the control signals Φ1 and Φ4 to logic low, transitions the control signal Φ2 to logic high, and maintains the control signal Φ3 at logic low, thereby starting the integration phase. Figure 7D , in which it can be seen that: switches S32 and S34 are closed to add the voltage Vcm to the voltage GND-Vcm stored across capacitor Cs5, thereby applying GND to the non-inverting terminal of the integrator 41; and switches S38 and S29 are closed to add the voltage Vcm to the voltage Vbe-Vcm stored across capacitor Cs6, thereby applying Vbe to the inverting terminal of the integrator 41.

[0083] The voltages applied to the non-inverting terminal of the integrator 41 are added to obtain the voltage GND, while the voltages applied to the inverting terminal of the integrator 41 are added to obtain the voltage Vbe. Assuming that the integrator 41 has unity gain, the integration result performed by the integrator 41 is therefore the voltage -Vbe.

[0084] When the bit stream is at 0, the sampling phase ( Figure 7C ) and the integration phase ( Figure 7D ) are repeated q times each. Thus, q(-Vbe) is ultimately integrated when the bit stream is at 0, and a second integrator 50 performs a further integration of the voltage q(-Vbe), which is then quantized by a quantization circuit 60 to generate the next bit of the bit stream. The next bit of the bit stream is used by a control signal generator 70 to generate new values ​​for the control signals Φ1, Φ2, Φ3, and Φ4. Furthermore, the bit stream passes through a circuit 65, which performs low-pass filtering and decimation to produce an output digital code (where the ratio of 1s to 0s over a given time window represents the desired output μ, which can be used to calculate the temperature of the chip in which the temperature sensor circuit 5 is integrated).

[0085] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments can be conceived without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A temperature sensing circuit comprising: A voltage generating circuit system comprising: a first bipolar junction transistor and a second bipolar junction transistor having coupled collectors and bases and biased at different current densities; and a third bipolar junction transistor, the collector of the third bipolar junction transistor being coupled to the base of the third bipolar junction transistor, the third bipolar junction transistor being biased by a calibration current; Integrator; a switched capacitor circuit configured to selectively sample a voltage generated by the voltage generating circuitry and provide the sampled voltage to an input of the integrator; a quantization circuit configured to quantize the output of the integrator to generate a bit stream; wherein the switched capacitor circuit cooperates with the integrator under control of the bit stream to: When a latest bit of the bit stream is logic zero, causing a difference between a base-emitter voltage of the first bipolar junction transistor and a base-emitter voltage of the second bipolar junction transistor to be sampled and integrated a first given number of times to thereby generate a voltage proportional to absolute temperature; and When the latest bit of the bit stream is a logic one, causing the base-emitter voltage of the third bipolar junction transistor to be sampled and integrated a second given number of times to thereby generate a voltage complementary to absolute temperature; and A low-pass filter and a decimator are configured to filter and decimate the bit stream generated by the quantization circuit to generate a signal indicating the chip temperature, and the temperature sensing circuit is placed in the chip.

2. The temperature sensing circuit of claim 1 , wherein the switched capacitor circuit comprises: a first capacitor, configured to sample and hold a base-emitter voltage of the first bipolar junction transistor; as well as The second capacitor is used to sample and hold the base-emitter voltage of the second bipolar junction transistor.

3. The temperature sensing circuit of claim 2 , wherein the switched capacitor circuit further comprises: A third capacitor is used to sample and hold the ground; as well as The fourth capacitor is used to sample and hold the base-emitter voltage of the third bipolar junction transistor.

4. The temperature sensing circuit of claim 3 , wherein the switched capacitor circuit further comprises: a first switch having a first node, the first node of the first switch being coupled to a base-emitter voltage of the first bipolar junction transistor, wherein the first switch operates in response to a third control signal; a second switch having a first node and a second node, the first node of the second switch being coupled to the second node of the first switch and the second node of the second switch being coupled to the first node of the first capacitor, wherein the second switch operates in response to a first control signal; a third switch having a first node and a second node, the first node of the third switch being coupled to the second node of the first capacitor and the second node of the third switch being coupled to the non-inverting input of the integrator, wherein the third switch operates in response to a second control signal; a fourth switch having a first node and a second node, the first node of the fourth switch being coupled to the second node of the first switch and the second node of the fourth switch being coupled to a common mode voltage, wherein the fourth switch operates in response to a fourth control signal; a fifth switch having a first node and a second node, the first node of the fifth switch being coupled to the first node of the first capacitor, the second node of the fifth switch being coupled to the common-mode voltage, wherein the fifth switch operates in response to the second control signal; as well as A sixth switch has a first node and a second node, the first node of the sixth switch is coupled to the second node of the first capacitor, the second node of the sixth switch is coupled to the common mode voltage, wherein the sixth switch operates in response to the first control signal.

5. The temperature sensing circuit of claim 4 , wherein the switched capacitor circuit further comprises: a seventh switch having a first node, the first node of the seventh switch coupled to a base-emitter voltage of the second bipolar junction transistor, wherein the seventh switch operates in response to the third control signal; an eighth switch having a first node and a second node, the first node of the eighth switch being coupled to the second node of the seventh switch, the second node of the eighth switch being coupled to the first node of the second capacitor, wherein the eighth switch operates in response to the first control signal; a ninth switch having a first node and a second node, the first node of the ninth switch being coupled to the second node of the second capacitor, the second node of the ninth switch being coupled to the inverting input of the integrator, wherein the ninth switch operates in response to the second control signal; a tenth switch having a first node and a second node, the first node of the tenth switch being coupled to the second node of the seventh switch, the second node of the tenth switch being coupled to the common-mode voltage, wherein the tenth switch operates in response to the fourth control signal; an eleventh switch having a first node and a second node, the first node of the eleventh switch being coupled to the first node of the second capacitor, the second node of the eleventh switch being coupled to the common mode voltage, wherein the eleventh switch operates in response to the second control signal; as well as A twelfth switch has a first node and a second node, the first node of the twelfth switch is coupled to the second node of the second capacitor, the second node of the twelfth switch is coupled to the common mode voltage, wherein the twelfth switch operates in response to the first control signal.

6. The temperature sensing circuit of claim 5 , wherein the switched capacitor circuit further comprises: a thirteenth switch having a first node, the first node of the thirteenth switch being coupled to ground, wherein the thirteenth switch operates in response to the fourth control signal; a fourteenth switch having a first node and a second node, the first node of the fourteenth switch being coupled to the second node of the thirteenth switch, the second node of the fourteenth switch being coupled to the first node of the third capacitor, wherein the fourteenth switch operates in response to the first control signal; a fifteenth switch having a first node and a second node, the first node of the fifteenth switch being coupled to the second node of the third capacitor, the second node of the fifteenth switch being coupled to the non-inverting input of the integrator, wherein the fifteenth switch operates in response to the second control signal; a sixteenth switch having a first node and a second node, the first node of the sixteenth switch being coupled to the second node of the thirteenth switch, the second node of the sixteenth switch being coupled to the common mode voltage, wherein the sixteenth switch operates in response to the third control signal; a seventeenth switch having a first node and a second node, the first node of the seventeenth switch being coupled to the first node of the third capacitor, the second node of the seventeenth switch being coupled to the common mode voltage, wherein the seventeenth switch operates in response to the second control signal; as well as An eighteenth switch has a first node and a second node, the first node of the eighteenth switch is coupled to the second node of the third capacitor, the second node of the eighteenth switch is coupled to the common mode voltage, wherein the eighteenth switch operates in response to the first control signal.

7. The temperature sensing circuit of claim 6 , wherein the switched capacitor circuit further comprises: a nineteenth switch having a first node, the first node of the nineteenth switch being coupled to a base-emitter voltage of the third bipolar junction transistor, wherein the nineteenth switch operates in response to the fourth control signal; a twentieth switch having a first node and a second node, the first node of the twentieth switch being coupled to the second node of the nineteenth switch, the second node of the twentieth switch being coupled to the first node of the fourth capacitor, wherein the twentieth switch operates in response to the first control signal; a twenty-first switch having a first node and a second node, the first node of the twenty-first switch being coupled to the second node of the fourth capacitor, the second node of the twenty-first switch being coupled to the inverting input of the integrator, wherein the twenty-first switch operates in response to the second control signal; a twenty-second switch having a first node and a second node, the first node of the twenty-second switch being coupled to the second node of the nineteenth switch, the second node of the twenty-second switch being coupled to the common mode voltage, wherein the twenty-second switch operates in response to the third control signal; a twenty-third switch having a first node and a second node, the first node of the twenty-third switch being coupled to the first node of the second capacitor, the second node of the twenty-third switch being coupled to the common-mode voltage, wherein the twenty-third switch operates in response to the second control signal; as well as A twenty-fourth switch has a first node and a second node, the first node of the twenty-fourth switch is coupled to the second node of the second capacitor, the second node of the twenty-fourth switch is coupled to the common mode voltage, wherein the twenty-fourth switch operates in response to the first control signal.

8. The temperature sensing circuit according to claim 7 , further comprising a control signal generator, wherein when the latest bit of the bit stream is logic zero: During a sampling phase, asserting the first control signal and the third control signal while de-asserting the second control signal and the fourth control signal; and During the integration phase, the second control signal is asserted while the first control signal, the third control signal, and the fourth control signal are de-asserted.

9. The temperature sensing circuit according to claim 8, wherein the control signal generator is further configured to: when the latest bit of the bit stream is logic one: During a sampling phase, asserting the first control signal and the fourth control signal while de-asserting the second control signal and the third control signal; and During the integration phase, the second control signal is asserted while the first control signal, the third control signal, and the fourth control signal are de-asserted.

10. The temperature sensing circuit of claim 3, wherein the switched capacitor circuit further comprises: a first switching circuit configured to selectively connect the first capacitor between a base-emitter voltage of the first bipolar junction transistor and a non-inverting input of the integrator when the latest bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the most recent bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform integration, the first switching circuit selectively connects the first capacitor between a common mode voltage and a non-inverting input of the integrator; a second switching circuit configured to selectively connect the second capacitor between a base-emitter voltage of the second bipolar junction transistor and an inverting input of the integrator when the latest bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the most recent bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform integration, the second switching circuit selectively connects the second capacitor between the common mode voltage and an inverting input of the integrator; a third switching circuit configured to selectively connect the third capacitor between ground and a non-inverting input of the integrator when the latest bit of the bit stream is a logic one and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the latest bit of the bit stream is a logic one and the switched capacitor circuit cooperates with the integrator to perform integration, the third switching circuit selectively connects the third capacitor between the common mode voltage and a non-inverting input of the integrator; a fourth switching circuit configured to selectively connect the fourth capacitor between the base-emitter voltage of the third bipolar junction transistor and the inverting input of the integrator when the latest bit of the bit stream is a logic one and the switched capacitor circuit cooperates with the integrator to perform sampling; and When the latest bit of the bit stream is logic one and the switched capacitor circuit cooperates with the integrator to perform integration, the fourth switch circuit selectively connects the fourth capacitor between the common mode voltage and the inverting input of the integrator.

11. The temperature sensing circuit of claim 2, wherein the switched capacitor circuit further comprises: a first switching circuit configured to selectively connect the first capacitor between a base-emitter voltage of the first bipolar junction transistor and a non-inverting input of the integrator when the latest bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the most recent bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform integration, the first switching circuit selectively connects the first capacitor between a common mode voltage and a non-inverting input of the integrator; wherein when the latest bit of the bit stream is a logic one and the switched capacitor circuit cooperates with the integrator to perform sampling, the first switching circuit selectively connects the first capacitor between ground and a non-inverting input of the integrator; wherein when the most recent bit of the bit stream is a logic one and the switched capacitor circuit cooperates with the integrator to perform integration, the first switching circuit selectively connects the first capacitor between the common mode voltage and a non-inverting input of the integrator; a second switching circuit configured to selectively connect the second capacitor between a base-emitter voltage of the second bipolar junction transistor and an inverting input of the integrator when the latest bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the most recent bit of the bit stream is a logic zero and the switched capacitor circuit cooperates with the integrator to perform integration, the second switching circuit selectively connects the second capacitor between the common mode voltage and an inverting input of the integrator; wherein when the latest bit of the bit stream is a logic one and the switched capacitor circuit cooperates with the integrator to perform sampling, the second switching circuit selectively connects the second capacitor between the base-emitter voltage of the third bipolar junction transistor and the inverting input of the integrator; and When the latest bit of the bit stream is logic one and the switched capacitor circuit cooperates with the integrator to perform integration, the second switching circuit selectively connects the second capacitor between the common mode voltage and the inverting input of the integrator.

12. The temperature sensing circuit of claim 2 , wherein the switched capacitor circuit further comprises: a 30th switch having a first node, the first node of the 30th switch coupled to ground, wherein the 30th switch operates in response to a fourth control signal; a thirty-first switch having a first node and a second node, the first node of the thirty-first switch being coupled to the second node of the thirtieth switch, the second node of the thirty-first switch being coupled to the first node of the first capacitor, wherein the thirty-first switch operates in response to a first control signal; a thirty-second switch having a first node and a second node, the first node of the thirty-second switch being coupled to the second node of the first capacitor, the second node of the thirty-second switch being coupled to the non-inverting input of the integrator, wherein the thirty-second switch operates in response to a second control signal; a thirty-third switch having a first node and a second node, the first node of the thirty-third switch being coupled to the base-emitter voltage of the first bipolar junction transistor, the second node of the thirty-third switch being coupled to the second node of the thirtieth switch, wherein the thirty-third switch operates in response to a third control signal; a thirty-fourth switch having a first node and a second node, the first node of the thirty-fourth switch being coupled to the second node of the thirty-first switch, the second node of the thirty-fourth switch being coupled to a common mode voltage, wherein the thirty-fourth switch operates in response to a second control signal; a thirty-fifth switch having a first node and a second node, the first node of the thirty-fifth switch being coupled to the second node of the first capacitor, the second node of the thirty-fifth switch being coupled to the common-mode voltage, wherein the thirty-fifth switch operates in response to the first control signal; a thirty-sixth switch having a first node, the first node of the thirty-sixth switch being coupled to a base-emitter voltage of the third bipolar junction transistor, wherein the thirty-sixth switch operates in response to the fourth control signal; a thirty-seventh switch having a first node and a second node, the first node of the thirty-seventh switch being coupled to the second node of the thirty-sixth switch, the second node of the thirty-seventh switch being coupled to the first node of the second capacitor, wherein the thirty-seventh switch operates in response to a first control signal; a thirty-eighth switch having a first node and a second node, the first node of the thirty-eighth switch being coupled to the second node of the second capacitor, the second node of the thirty-eighth switch being coupled to the inverting input of the integrator, wherein the thirty-eighth switch operates in response to a second control signal; a thirty-ninth switch having a first node and a second node, the first node of the thirty-ninth switch being coupled to the base-emitter voltage of the second bipolar junction transistor, the second node of the thirty-ninth switch being coupled to the second node of the thirty-sixth switch, wherein the thirty-ninth switch operates in response to a third control signal; a twenty-ninth switch having a first node and a second node, the first node of the twenty-ninth switch being coupled to the second node of the thirty-seventh switch, the second node of the twenty-ninth switch being coupled to a common mode voltage, wherein the twenty-ninth switch operates in response to a second control signal; as well as A twenty-eighth switch has a first node and a second node, the first node of the twenty-eighth switch is coupled to the second node of the second capacitor, the second node of the twenty-eighth switch is coupled to the common mode voltage, wherein the twenty-eighth switch operates in response to the first control signal. 13 . The temperature sensing circuit according to claim 1 , wherein the first given number of times is an integer greater than 1; and wherein the second given number of times is one. 14 . The temperature sensing circuit of claim 1 , wherein the first given number is a first integer greater than 1; and wherein the second given number is a second integer greater than 1. 15 . The temperature sensing circuit according to claim 11 , wherein the second given number of times is smaller than the first given number of times.

16. A sensing circuit comprising: A voltage generating circuit system comprising: a first bipolar junction transistor and a second bipolar junction transistor having coupled collectors and bases and biased at different current densities; and a third bipolar junction transistor having a collector coupled to a base of the third bipolar junction transistor, the third bipolar junction transistor being biased by a calibration current and having a base-emitter voltage that is a voltage complementary to absolute temperature; Integrator; a switched capacitor circuit configured to: selectively sample a voltage generated by the voltage generation circuitry and provide the sampled voltage to an input of the integrator; a quantization circuit configured to: quantize the output of the integrator to generate a bit stream; wherein the switched capacitor circuit cooperates with the integrator under control of the bit stream to: When the latest bit of the bit stream is a first logic value, causing a difference between the base-emitter voltage of the first bipolar junction transistor and the base-emitter voltage of the second bipolar junction transistor to be sampled and integrated a first given number of times; and When the latest bit of the bit stream is a second logic value, causing the base-emitter voltage of the third bipolar junction transistor to be sampled and integrated a second given number of times; and The output circuit system is configured to generate an output signal by performing an operation on the bit stream. 17 . The sensing circuit of claim 16 , wherein the first given number of times is an integer greater than 1; and wherein the second given number of times is one. 18 . The sensing circuit of claim 16 , wherein the first given number is a first integer greater than 1; and wherein the second given number is a second integer greater than 1. The sensing circuit according to claim 18 , wherein the second given number of times is smaller than the first given number of times.

20. The sensing circuit of claim 16, wherein the switched capacitor circuit comprises: a first capacitor, configured to sample and hold a base-emitter voltage of the first bipolar junction transistor; a second capacitor, configured to sample and hold a base-emitter voltage of the second bipolar junction transistor; a first switching circuit configured to selectively connect the first capacitor between a base-emitter voltage of the first bipolar junction transistor and a non-inverting input of the integrator when the latest bit of the bit stream is the first logic value and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the latest bit of the bit stream is the first logic value and the switched capacitor circuit cooperates with the integrator to perform integration, the first switching circuit selectively connects the first capacitor between a common mode voltage and a non-inverting input of the integrator; as well as a second switching circuit configured to selectively connect the second capacitor between the base-emitter voltage of the second bipolar junction transistor and the inverting input of the integrator when the latest bit of the bit stream is the first logic value and the switched capacitor circuit cooperates with the integrator to perform sampling; When the latest bit of the bit stream is the first logic value and the switched capacitor circuit cooperates with the integrator to perform integration, the second switching circuit selectively connects the second capacitor between the common mode voltage and the inverting input of the integrator.

21. The sensing circuit of claim 16, wherein the switched capacitor circuit comprises: a first capacitor, configured to sample and hold a base-emitter voltage of the first bipolar junction transistor; a second capacitor, configured to sample and hold a base-emitter voltage of the second bipolar junction transistor; a first switching circuit configured to selectively connect the first capacitor between ground and a non-inverting input of the integrator when the latest bit of the bit stream is the second logic value and the switched capacitor circuit cooperates with the integrator to perform sampling; wherein when the latest bit of the bit stream is the second logic value and the switched capacitor circuit cooperates with the integrator to perform integration, the first switching circuit selectively connects the first capacitor between a common mode voltage and a non-inverting input of the integrator; as well as a second switching circuit configured to selectively connect the second capacitor between the base-emitter voltage of the third bipolar junction transistor and the inverting input of the integrator when the latest bit of the bit stream is the second logic value and the switched capacitor circuit cooperates with the integrator to perform sampling; When the latest bit of the bit stream is the second logic value and the switched capacitor circuit cooperates with an integrator to perform integration, the second switching circuit selectively connects the second capacitor between the common mode voltage and the inverting input of the integrator.

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