Accelerated arithmetic device, method, integrated circuit chip, computing device and board

Abstract

The present disclosure relates to an acceleration operation device, method, integrated circuit chip, computing device and board, wherein the computing device can be included in a combined processing device which can further include a general-purpose interconnection interface and other processing devices. The computing device interacts with the other processing devices to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected to the computing device and the other processing devices respectively for data of the computing device and the other processing devices. The scheme of the present disclosure can be widely applied in data caching.

Description

Technical Field

[0001] This disclosure generally relates to the field of computing devices. More specifically, this disclosure relates to accelerated computing devices, methods, integrated circuit chips, computing devices, and circuit boards. Background Technology

[0002] Currently, computing devices are developing rapidly, leading to increasingly complex algorithms and ever-increasing computational demands. Consequently, the number of integrated computing units is also growing. To accelerate computation, many processor architectures employ fractal computing, as they organize simple basic computing units in a specific way to achieve parallel computing and thus speed up computation.

[0003] However, with increasingly higher demands for computational speed, this fractal computing still cannot meet the requirements. Therefore, how to obtain a device that can further accelerate computation has become a problem that needs to be solved in the existing technology. Summary of the Invention

[0004] In order to at least partially solve the technical problems mentioned in the background art, the present disclosure provides an accelerated computing device and method thereof, an integrated circuit chip including the accelerated computing device, a computing device and a board.

[0005] In one aspect, this disclosure provides an accelerated computing device, wherein the accelerated computing device includes: a data cache unit including a plurality of storage blocks for storing data; the data cache unit stores data in storage blocks pointed to by at least one set of write pointers; the data cache unit outputs data from read-read spaces pointed to by a plurality of sets of read pointers; wherein each of the at least one set of write pointers includes write pointers in at least two dimensions, and each of the plurality of sets of read pointers includes read pointers in at least two dimensions.

[0006] In another aspect, this disclosure provides an accelerated computing method implemented using an accelerated computing device, wherein the accelerated computing method includes: using the data buffer unit of the adder computing device to provide computing data to at least one of the plurality of computing units according to a received data read instruction; and using the at least one computing unit to perform operations on the received computing data according to the respective received computing instructions.

[0007] In another aspect, this disclosure provides an integrated circuit chip that includes the aforementioned accelerated computing device. In yet another embodiment, the accelerated computing device of this disclosure can constitute a standalone integrated circuit chip.

[0008] In another aspect, this disclosure provides a computing device that includes the aforementioned accelerated computing device or the aforementioned integrated circuit chip.

[0009] In another aspect, this disclosure provides a board that includes the aforementioned computing device.

[0010] By utilizing the accelerated computing device, corresponding caching method, integrated circuit chip, computing device, and board disclosed herein, the computing speed can be comprehensively improved by organizing multiple computing units into an accelerated architecture. Furthermore, the accelerated computing device of this disclosure can implement arbitrary grouped operations under a single instruction. Therefore, the accelerated computing device of this disclosure has higher computing power and can be widely applied in various accelerated computing applications. Attached Figure Description

[0011] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0012] Figure 1 This is a schematic block diagram illustrating an accelerated computing device according to an embodiment of the present disclosure;

[0013] Figure 2 This is a schematic block diagram illustrating an accelerated computing device according to another embodiment of the present disclosure;

[0014] Figure 3 This is a schematic block diagram illustrating an accelerated computing device according to yet another embodiment of the present disclosure;

[0015] Figure 4 This is a schematic block diagram illustrating a data cache of a first data cache module according to an embodiment of the present disclosure;

[0016] Figure 5 This is a schematic block diagram illustrating a data cache of a first data cache module according to another embodiment of the present disclosure;

[0017] Figure 6 This is a flowchart illustrating an accelerated computing method according to an embodiment of the present disclosure;

[0018] Figure 7 This is a flowchart illustrating a method for accelerating computation according to another embodiment of the present disclosure;

[0019] Figure 8 This is a flowchart illustrating a method for accelerating computation according to yet another embodiment of the present disclosure;

[0020] Figure 9 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

[0021] Figure 10This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation

[0022] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0023] The technical solution disclosed herein provides an accelerated computing device, method, integrated circuit chip, computing device, and board as a whole. Unlike existing accelerated computing devices, this disclosure provides an architecture for an accelerated computing device composed of multiple computing units, thereby improving computing speed. In particular, the accelerated computing device of this disclosure can implement arbitrary grouped operations under a single instruction. Therefore, the accelerated computing device of this disclosure has the characteristic of higher computing power.

[0024] Figure 1 This is a schematic block diagram illustrating an accelerated computing device 100 according to one embodiment of the present disclosure. Figure 1 As shown, the accelerated computing device 100 may include a data cache unit 101 and a plurality of computing units 102. The data cache unit 101 may be used to provide computing data to at least one computing unit 102 among the plurality of computing units according to a received data read instruction. The at least one computing unit 102 may be used to perform operations on the received computing data according to its respective received computing instructions.

[0025] According to an embodiment of this disclosure, in the accelerated computing device 100, the data cache unit 101 can receive a data read instruction and output the cached computing data to the computing unit 102 that needs the data according to the instruction. The computing unit 102 that needs the computing data can then perform calculations on the computing data according to the received computing instructions.

[0026] The data cache unit 101 can perform multiple reads and writes, and can be a one-dimensional or multi-dimensional data cache unit. Therefore, the data cache unit 101 can provide computation data to multiple arithmetic units 102 according to a single data read instruction, meaning that multiple arithmetic units 102 can share the computation data. Thus, the data cache unit 101 can improve the data read and write speed.

[0027] The aforementioned computational data may include: external data input from outside the accelerated computing device; and local data stored inside the accelerated computing device.

[0028] In this embodiment, the data cache unit 101 stores external data and local data, and the processing unit 102 can perform calculations on the external data and local data. Each calculation involves both external and local data. Furthermore, one of the two data items involved in the calculation is stored internally in the accelerated processing device, while the other is input externally. This avoids both data items being input externally, thereby improving data transmission speed.

[0029] Reference Figure 2 , Figure 2 This is a schematic block diagram illustrating an accelerated computing device 200 according to another embodiment of the present disclosure. Figure 2 The accelerated computing device 200 shown is Figure 1 The only difference between the shown accelerated computing device 100 and the one shown is that the accelerated computing device 200 may also include a random access memory 201. The random access memory 201 can be used to store and output the local data according to random access memory instructions.

[0030] According to embodiments of this disclosure, random access memory (RAM) 201 is located within the accelerated computing device 200 and stores the aforementioned local data. Furthermore, the RAM 201 can receive RAM instructions, through which local data can be read and written.

[0031] According to embodiments of the present disclosure, the data cache unit 101 can store at least one external data and at least one local data from random access memory according to a received data write instruction.

[0032] In this embodiment, the data cache unit 101 can receive a data write instruction, through which data can be written to the data cache unit 101. Specifically, external data from outside the accelerated computing device and local data from the random access memory 201 can be stored in the data cache unit 101. As described above, the data cache unit 101 can perform multiple reads and multiple writes, thus improving the speed of writing external data and local data to the data cache unit.

[0033] Furthermore, the data write instruction may include a first sub-write instruction and a second sub-write instruction, and the data cache unit 101 may include: a first data cache module, which is used to store at least one external data according to a received first sub-write instruction; and a second data cache module, which is used to store at least one local data from the random access memory 201 according to a received second sub-write instruction.

[0034] In this embodiment, the data cache unit 101 may include two data cache modules: a first data cache module and a second data cache module. The first data cache module can receive a first sub-write instruction in a write instruction, through which external data from outside the accelerated computing device 200 can be written to the first data cache module. Furthermore, the second data cache module can receive a second sub-write instruction in a write instruction, through which local data from the random access memory 201 can be written to the second data cache module. Both the first and second data cache modules can perform multiple reads and multiple writes, thereby improving the speed of writing external and local data.

[0035] On the other hand, the above combination Figure 1 The data read instruction may include a first sub-read instruction and a second sub-read instruction. The first data cache module can be used to output external data to at least one of the multiple operation units 102 according to a received first sub-read instruction. The second data cache module can be used to output local data to at least one of the multiple operation units 102 according to a received second sub-read instruction.

[0036] In this embodiment, the first data cache module can receive a first sub-read instruction in the read instruction. Through this instruction, multiple external data can be read from the first data cache module and these data can be transferred to the corresponding multiple processing units 102. Furthermore, the second data cache module can receive a second sub-read instruction in the read instruction. Through this instruction, multiple local data can be read from the second data cache module and these data can be transferred to the corresponding processing unit 102. As described above, both the first and second data cache modules can perform multiple reads and multiple writes, thereby improving the reading speed of both external and local data.

[0037] After the arithmetic unit completes the calculation, the arithmetic unit outputs the obtained calculation result to the bus or the random access memory.

[0038] In this embodiment, after completing the calculation, each arithmetic unit can output the calculation result to the bus for storage in an external storage unit or for use by an external device. Additionally, after completing the calculation, each arithmetic unit can output the calculation result to random access memory.

[0039] When it is necessary to return the calculation result to the random access memory 201, the random access memory 201 can be used to store the calculation result according to the random access memory instructions and use the calculation result as local data.

[0040] In this embodiment, the random access memory 201 can receive random access memory instructions, and through these instructions, data that needs to be returned to the random access memory 201 can be stored as local data so that the computing unit 102 of the accelerated computing device of this disclosure can use the computing results for further computing in subsequent computing.

[0041] Furthermore, the aforementioned first data caching module can be a one-dimensional data caching module or a multi-dimensional data caching module. Similarly, the aforementioned second data caching module can also be a one-dimensional data caching module or a multi-dimensional data caching module.

[0042] In this embodiment, both the first and second data cache modules can be one-dimensional or multi-dimensional data cache modules, and both have read-write functionality. Thus, the first and second data cache modules have strong applicability and very fast read / write speeds.

[0043] Reference Figure 3 , Figure 3 This is a schematic block diagram illustrating an accelerated computing device 300 according to yet another embodiment of the present disclosure. Figure 3 The accelerated computing device 300 shown is Figure 2 The difference between the accelerated computing device 200 shown is that the accelerated computing device 300 may further include a control cache unit 301. This control cache unit 301 can be used to receive external instructions and, based on the external instructions, parse the data read instructions and data write instructions for the data cache unit, the random access memory instructions for the random access memory, and the computing instructions for the computing unit.

[0044] According to embodiments of this disclosure, the control cache unit 301 may include a data instruction cache module, a memory instruction cache module, and an arithmetic instruction cache module. The data instruction cache module can receive external instructions and parse them into data read and write instructions for the data cache unit 101. The memory instruction cache module can receive external instructions and parse them into random access memory (RAM) instructions for the random access memory (RAM) 201. The arithmetic instruction cache module can receive external instructions and parse them into arithmetic instructions for the arithmetic unit 102.

[0045] As described above, the first data cache module and the second data cache module can be either a one-dimensional data cache module or a multi-dimensional data cache module with multiple read and write capabilities. Since the first data cache module and the second data cache module have the same structure and working principle, the first data cache module will be used as an example for detailed description below.

[0046] When the first data cache module is a one-dimensional data cache module, it may include a data cache, which may include multiple storage rows for storing the aforementioned external data (hereinafter referred to as data). The data cache can store data in storage rows pointed to by at least one write pointer. Furthermore, the data cache can output data from storage rows pointed to by multiple read pointers.

[0047] According to this embodiment, the data buffer has multiple storage rows, and data is written and read from these storage rows. One or more write pointers can write data to their respective storage rows, and multiple read pointers can read data from their respective storage rows. It should be noted that the write pointers and read pointers can operate independently.

[0048] Specifically, you can refer to Figure 4 , Figure 4 This is a schematic diagram illustrating a data cache 1011 of a first data cache module according to an embodiment of the present disclosure. Figure 4 As shown, the data buffer 1011 has multiple storage rows for storing data. Two write pointers W0 and W1 can write data to the storage row they point to, and two read pointers R0 and R1 can read data from the storage row they point to. It should be noted that... Figure 4 The two write pointers and two read pointers shown are merely illustrative examples, and this disclosure is not limited thereto.

[0049] To allow for more flexible reading and writing of data, multiple write pointers can each point to a different storage line; multiple read pointers can each point to a single storage line.

[0050] In this embodiment, when the at least one write pointer is multiple write pointers, each write pointer points to a different storage row, so that data can be written to different storage rows simultaneously, and the problem of data loss caused by repeatedly writing different data to the same storage row under one instruction is avoided. Multiple read pointers can each point to a different storage row, meaning that each read pointer can point to a different storage row, or at least two read pointers can point to the same storage row, so that at least two read pointers can read data from the same storage row, thereby achieving data sharing. Figure 4 The data buffer 1011 shown has two write pointers W0 and W1 pointing to different memory rows, and two read pointers R0 and R1 pointing to different memory rows. Of course, the two read pointers R0 and R1 can also point to the same memory row.

[0051] When writing data to a storage line in the data buffer, it should be noted that when the storage line pointed to by the write pointer is empty, the data buffer 1011 can store data in the storage line; when the storage line pointed to by the write pointer contains data, the data buffer 1011 can wait for the data in the storage line to be cleared.

[0052] In this embodiment, when writing data to the data buffer 1011, unused or still needed data should be avoided from being overwritten. Data in the data buffer 1011 is cleared once it has been used. Therefore, for example, refer to... Figure 4 If the storage line pointed to by the write pointers W0 and / or W1 is empty, data can be written to that storage line; if data exists in that storage line, it means that the data has not been used up or has not been cleared yet, so it is necessary to wait for the data in that storage line to be cleared before writing the data to that storage line.

[0053] When reading data from a storage row in the data buffer 1011, it should be noted that when the storage row pointed to by the read pointer is empty or has not been written, the data buffer 1011 waits for the storage row to be written; when the storage row pointed to by the read pointer has been written, the data buffer 1011 outputs the data of the storage row according to the number of reads indicated by the read control signal corresponding to the read pointer, and clears the data of the storage row after the number of reads is completed.

[0054] In this embodiment, when reading data from the data cache, it should be ensured that the data in the stored row is completely present. For example, refer to... Figure 2 If the storage row pointed to by read pointers R0 and / or R1 does not contain data or is being written to, the system must wait until the data is completely written to the storage row before reading from it. If the storage row contains complete data, it can be read, and the data in the storage row will be cleared after the read is complete. It should be noted that the same read pointer, such as read pointers R0 or R1, can read data from the same storage row multiple times according to the read control signal, thus reusing the same data. Therefore, the data in the storage row is cleared after the number of reads indicated by the read control signal has been completed.

[0055] Therefore, the data buffer 1011 may include a counting module. The data buffer 1011 can determine whether the read operation has been completed by counting the data in the counting module.

[0056] In this embodiment, to determine whether the read count is complete, the data buffer 1011 may include a counting module. This counting module can count the number of reads indicated by the read control signal. When the count is complete, the read count is considered complete.

[0057] In addition, when at least two read pointers point to the same storage row, the counting module counts the number of reads indicated by the read control signals corresponding to each of the at least two read pointers, and the data in the storage row is cleared after all the read counts are completed.

[0058] In this embodiment, for example, refer to Figure 2 When read pointers R0 and R1 need to read data from the same storage line, the counting module can count the number of reads indicated by the read control signal corresponding to each read pointer R0 and R1. Once the counting module has completed counting the number of reads indicated by each read control signal, the data in that storage line can be cleared.

[0059] In order to read or write data in any storage line in the data buffer, the write pointer determines the storage line it points to based on the step size indicated by the corresponding write control signal; the read pointer determines the storage line it points to based on the step size indicated by the corresponding read control signal.

[0060] In this embodiment, when the data buffer initially starts working, the write pointer and read pointer can be initialized to point to the starting position of the data buffer (e.g., the position of the first storage line). Subsequently, the write pointer and read pointer can determine the storage line they point to based on the step size indicated by the corresponding write control signal and read control signal. That is, the write pointer and read pointer can determine the storage line they need to point to based on the storage line they point to and the step size indicated by the current write control signal and read control signal.

[0061] The step size can be set according to the number of storage rows to ensure that the write pointer and read pointer can point to any storage row according to the write control signal and read control signal. For example, the step size can be set from 0 to n-1, where n represents the number of storage rows in the data storage unit.

[0062] For example, if the number of storage rows in the data cache unit is 100, and the write pointer and read pointer originally pointed to the 5th storage row, then if the row step is 8, the storage row they will point to will be the 13th storage row. Furthermore, when the step is 0, it means the storage row pointed to by the write pointer and read pointer remains unchanged, i.e., it still points to the original storage row. When the step is n-1, it means the storage row that the write pointer and read pointer will point to is the preceding storage row of the original storage row. For example, if the number of storage rows in the data cache is 100, and the write pointer and read pointer originally pointed to the 5th storage row, then if the step is 99, the storage row they will point to will be the 4th storage row. Therefore, for each step, the counting of storage rows in the data cache cycles from the first storage row to the last storage row; that is, when the index of the original storage row plus the step is greater than the index of the last storage row, the counting continues from the first storage row to the last storage row.

[0063] As can be seen from the above, there can be multiple write pointers and read pointers; however, the data buffer 1011 may include at least one data input port and at least one data output port.

[0064] In one embodiment, the data buffer 1011 may include multiple data input ports and multiple data output ports. The data buffer 1011 can store data in parallel through the multiple data input ports according to a write control signal; the data buffer 1011 can output data in parallel through the multiple data output ports according to a read control signal.

[0065] In this embodiment, the data buffer 1011 may have multiple data input ports and multiple data output ports. Therefore, the number of data input ports may correspond to the number of write pointers, and the number of data output ports may correspond to the number of read pointers. Thus, write pointers can write data in parallel through the data input ports, and read pointers can read data in parallel through the data output ports.

[0066] In another embodiment, the data buffer 1011 may include a data input port and a data output port. The data buffer 1011 can serially store data through a data input port according to a write control signal; the data buffer 1011 can serially output data through a data output port according to a read control signal.

[0067] In this embodiment, the data buffer 1011 may have only one data input port and one data output port. Therefore, multiple write pointers share one data input port, and multiple read pointers share one data output port. Thus, data can be serially passed through the data input port and written into the respective memory rows pointed to by the multiple write pointers, and data can be read from the respective memory rows pointed to by the multiple read pointers and output serially through the data output port.

[0068] Of course, the number of data input ports and data output ports may not correspond to the number of write pointers and read pointers, and may not be a single port. In this case, when the number of data input ports is less than the number of write pointers, some write pointers can share a single data input port, while others can use their own dedicated data input port. Similarly, when the number of data output ports is less than the number of read pointers, some read pointers can share a single data output port, while others can use their own dedicated data output port. Thus, a combination of serial and parallel methods can be used to store and output data through the data input and data output ports.

[0069] In addition, the first data cache module may also include an instruction cache. The instruction cache can be used to receive instructions from outside the first data cache module, and parse at least one write control signal and multiple read control signals according to the instructions, wherein each write control signal includes a write pointer and each read control signal includes a read pointer.

[0070] In this embodiment, the instructions in the instruction buffer can control the reading and writing of data in the data buffer 1011. Specifically, the instruction buffer can receive instructions from outside the first data buffer module and parse the external instructions to obtain at least one write control signal and multiple read control signals for the data buffer 1011. Each write control signal includes a write pointer, and each read control signal includes a read pointer. Furthermore, each write control signal also includes the aforementioned step size, and each read control signal also includes the aforementioned step size and the number of reads.

[0071] Furthermore, instructions from outside the first data cache module may include the above combination Figure 2 The description includes a first sub-write instruction (hereinafter referred to as a write instruction) and a first sub-read instruction (hereinafter referred to as a read instruction). The instruction buffer includes at least one write instruction buffer and multiple read instruction buffers. Each write instruction buffer is used to receive and store the write instruction and parse a write control signal according to each write instruction. Each read instruction buffer is used to receive and store the read instruction and parse a read control signal according to each read instruction.

[0072] Specifically, both the write instruction buffer and the read instruction buffer can be FIFO (First-In, First-Out) buffers. The write instruction buffer receives and stores write instructions, and the read instruction buffer receives and stores read instructions. The number of write instruction buffers corresponds to the number of write pointers, and the number of read instruction buffers corresponds to the number of read pointers. Each write instruction buffer can parse the write control signal from the top-ranked write instruction according to the FIFO principle, and each read instruction buffer can parse the read control signal from the top-ranked read instruction according to the FIFO principle. Write and read instructions include wait instructions. When the number of memory lines to be read or written is less than the number of write and read instruction buffers, the control signals parsed by some write instruction buffers and / or some read instruction buffers are wait signals, and no operation is performed.

[0073] When the first data caching module is a multi-dimensional data caching module, it may include a data cache, which may include multiple storage blocks for storing the aforementioned external data (hereinafter referred to as data). The data cache stores data in storage blocks pointed to by at least one set of write pointers. Furthermore, the data cache outputs data from read-read spaces pointed to by multiple sets of read pointers. Each of the at least one set of write pointers includes write pointers in at least two dimensions, and each of the multiple sets of read pointers includes read pointers in at least two dimensions.

[0074] In an embodiment where the first data cache module is a two-dimensional data cache module, the data cache can have multiple storage rows, each storage row including multiple storage blocks, and all storage blocks in the data storage unit have the same storage space. Thus, these storage blocks can form a storage array. Therefore, the data cache can constitute a two-dimensional data cache. Consequently, each write pointer group can each include write pointers in two dimensions, and each read pointer group can each include read pointers in two dimensions.

[0075] Furthermore, for this data buffer, data writing is performed on storage blocks, meaning data can be written to any storage block; therefore, the storage block is the basic unit of writing. Data reading, on the other hand, is performed on the space to be read (a storage space of arbitrary size within a storage row), meaning data of arbitrary bit width can be read from any storage row. In other words, the space to be read can be located within a single storage block, can be a single storage block, or can be a storage space larger than a single storage block; therefore, 1 bit is the basic unit of reading.

[0076] Therefore, one or more write pointer groups can write data to the memory blocks they point to, and multiple read pointer groups can read data from the memory spaces they point to. Each write pointer group includes two write pointers, and each read pointer group includes two read pointers. It should be noted that write pointer groups and read pointer groups can operate independently.

[0077] In an embodiment where the first data cache module is a three-dimensional data cache module, the data cache may include multiple storage slices, and each storage slice may include multiple storage rows, while each storage row may include multiple storage blocks. In this case, the data cache can constitute a three-dimensional cache. Therefore, each write pointer group may each include write pointers in three dimensions, and each read pointer group may each include read pointers in three dimensions.

[0078] Similarly, the higher the dimension of the data cache, that is, the more storage layers there are, the larger the dimension of the pointer group.

[0079] The following will describe in detail the case where the first data cache module is a two-dimensional data cache module.

[0080] When at least one write pointer group each includes write pointers in two dimensions and multiple read pointer groups each include read pointers in two dimensions, at least one write pointer group may each include a row write pointer and a column write pointer, the row write pointer and the column write pointer can jointly determine the memory block to which it points; multiple read pointer groups may each include a row read pointer and a column read pointer, the row read pointer and the column read pointer can jointly determine the start position of the read space to which it points, and the read control signal corresponding to the read pointer group indicates the bit width of the space to be read.

[0081] Specifically, you can refer to Figure 5 , Figure 5 This is a schematic diagram illustrating a data cache 1012 of a first data cache module according to another embodiment of the present disclosure. Figure 5 The example shown is an N×4 storage matrix for the data cache 1012, where N is the number of storage rows. Furthermore, Figure 5 Two sets of write pointers are shown. One set includes a row write pointer Wr0 and a column write pointer Wc0, while the other set includes a row write pointer Wr1 and a column write pointer Wc1. The row write pointers Wr0 and Wr1 point to the row containing the data to be written, and the column write pointers Wc0 and Wc1 point to the column containing the data to be written. Therefore, the row write pointers Wr0 and Wr1 and the column write pointers Wc0 and Wc1 in each set can collectively determine the specific memory block they point to.

[0082] Furthermore, the data buffer 1012 can also be viewed as an N×M storage matrix, where N is the number of storage rows and M is the number of storage bits (bit width) in each storage row. Figure 5 Two sets of read pointers are also shown: one set includes a row read pointer Rr0 and a column read pointer Rc0, and the other set includes a row read pointer Rr1 and a column read pointer Rc1. In each set, the row read pointers Rr0 and Rr1 point to the row containing the data to be read, and the column read pointers Rc0 and Rc1 point to the column containing the starting storage bit of the data to be read. Therefore, the row read pointers Rr0 and Rr1 and the column read pointers Rc0 and Rc1 in each set can jointly determine the starting position of the read space. Furthermore, the read control signal corresponding to the read pointer set can indicate the bit width of the read space, thereby determining the bit width of the data to be read.

[0083] It should be noted that Figure 5 The two write pointer groups and the two read pointer groups are shown only by way of example, and this disclosure is not limited thereto.

[0084] To enable more flexible reading and writing of data, multiple write pointer groups can each point to different storage blocks; the multiple read pointer groups can each point to a space to be read.

[0085] In this embodiment, when there are multiple write pointer groups, each write pointer group points to a different memory block. This allows for simultaneous writing of data to different memory blocks and avoids data loss caused by repeatedly writing different data to the same memory block under a single instruction. Multiple read pointer groups can each point to a different space to be read, meaning each read pointer group can point to a different space, or at least two read pointer groups can point to the same space. This allows at least two read pointer groups to read data from the same space, thus achieving data sharing. Figure 5 The data storage 1012 shown has two write pointer groups pointing to different memory blocks and two read pointer groups pointing to different spaces to be read. Of course, the two read pointer groups can also point to the same space to be read.

[0086] When writing data to a storage block in the data buffer, it should be noted that when the storage block pointed to by the write pointer group is empty, the data buffer 1012 can store data in the storage block; when the storage block pointed to by the write pointer group contains data, the data buffer 1012 can wait for the data in the storage block to be cleared.

[0087] In this embodiment, when writing data to the data cache 1012, unused or still needed data should be avoided from being overwritten. In the data cache 1012, data in a storage block that has been used up will be cleared. Therefore, for example, refer to... Figure 5 If the memory block pointed to by the write pointer group is empty, data can be written to that memory block; if data exists in that memory block, it means that the data has not been used up or has not been cleared yet, so it is necessary to wait for the data in that memory block to be cleared before writing the data to that memory block.

[0088] When reading data from the data buffer, it should be noted that when the space to be read pointed to by the read pointer is empty or has not been written, the data buffer 1012 waits for the space to be read to be written; when the space to be read pointed to by the read pointer group has been written, the data buffer 1012 outputs the data of the space to be read according to the number of reads indicated by the read control signal corresponding to the read pointer group.

[0089] In this embodiment, when reading data from the data buffer, it should be ensured that the data in the space to be read is completely present. For example, refer to... Figure 5If the space pointed to by the read pointer group does not contain data or is being written, the system must wait until the data is completely written into the space before reading it. If the space contains complete data, it can be read. It should be noted that the same read pointer group can read data from the same space multiple times based on the read control signal to reuse the same data. It should also be noted that when data in a memory block is no longer accessed in subsequent reads (i.e., no longer used), the data in that memory block should be cleared.

[0090] Furthermore, the data buffer 1012 may include a counting module. The data buffer 1012 can determine whether the read operation has been completed by counting the data from the counting module.

[0091] In this embodiment, to determine whether the read count is complete, the data buffer 1012 may include a counting module. This counting module can count the number of reads indicated by the read control signal. When the count is complete, the read count is considered complete.

[0092] In addition, when at least two read pointer groups point to the same space to be read, the counting module counts the number of reads indicated by the read control signals corresponding to each of the at least two read pointer groups.

[0093] In this embodiment, for example, refer to Figure 5 When the read pointer groups need to read data from the same read space, the counting module can count the number of reads indicated by the read control signal corresponding to each read pointer group.

[0094] In order to write data to any storage block in the data cache and to read data from any read space in the data cache, the write pointer group determines the storage block to be pointed to based on the row step and column step indicated by the corresponding write control signal; the read pointer group determines the read start position to be pointed to based on the row step and column step indicated by the corresponding read control signal.

[0095] In this embodiment, when the data buffer initially starts working, the write pointer group and the read pointer group can be initialized to point to the starting position of the data buffer (e.g., the position of the first storage bit in the first storage block of the first row and first column). Subsequently, the write pointer group and the read pointer group can determine the storage block to be pointed to and the space to be read based on the step size indicated by the corresponding write control signal and read control signal. That is, the write pointer group and the read pointer group can determine the storage block to be pointed to and the space to be read based on the storage block to be pointed to and the step size indicated by the current write control signal and read control signal.

[0096] The range of the row step size for the row write pointer and the column step size for the column write pointer can be set according to the number of rows and columns of the storage matrix formed by the storage blocks. This ensures that the row write pointer and the column write pointer can point to any row and column according to the write control signal, thus jointly identifying any storage block. For example, the range of the row step size can be set to 0 to n-1, and the range of the column step size can be set to 0 to m-1, where n represents the number of rows in the storage matrix formed by the storage blocks, and m represents the number of columns in the storage matrix formed by the storage blocks.

[0097] For example, if the number of storage rows in the data cache unit is 100, and the row write pointer originally pointed to the 5th storage row, if the row step size is 8, then the storage row it will point to will be the 13th storage row. Furthermore, when the row step size is 0, it means the storage row pointed to by the row write pointer remains unchanged, i.e., it still points to the original storage row. When the row step size is n-1, it means the storage row the row write pointer will point to is the adjacent storage row above the original storage row. For example, if the number of storage rows in the data cache is 100, and the row write pointer originally pointed to the 5th storage row, if the row step size is 99, then the storage row it will point to will be the 4th storage row. Therefore, for each row step size, the counting of storage rows in the data cache cycles from the first storage row to the last storage row. That is, when the index of the originally pointed-to storage row plus the row step size is greater than the index of the last storage row, the counting continues from the first storage row to the last storage row.

[0098] For example, if the number of storage columns in a data cache unit is 100, and the column write pointer originally pointed to column 5, then if the column step size is 8, the column it will point to will be column 13. Furthermore, when the column step size is 0, it means the column the column write pointer points to remains unchanged, i.e., it still points to the original column. When the column step size is n-1, it means the column the column write pointer will point to is the adjacent column above the original column. For example, if the number of storage columns in the data cache is 100, and the column write pointer originally pointed to column 5, then if the step size is 99, the column it will point to will be column 4. In other words, for each column step size, the counting of storage columns in the data cache cycles from the first column to the last column; that is, when the index of the originally pointed-to column plus the column step size is greater than the index of the last column, the counting continues from the first column to the last column.

[0099] The range of the row step size for the row read pointer and the column step size for the column read pointer can be set according to the number of rows and columns of the storage matrix formed by the storage bits. This ensures that the row read pointer and the column read pointer can point to any row and column according to the read control signal, thus jointly determining any space to be read. For example, the range of the row step size can be set to 0 to n-1, and the range of the column step size can be set to 0 to m-1, where n represents the number of rows in the storage matrix formed by the storage bits, and m represents the number of columns in the storage matrix formed by the storage bits. The specific description is similar to the description of the row write pointer and the column write pointer above, and will not be repeated here.

[0100] As can be seen from the above, there can be multiple write pointer groups and read pointer groups; however, the data buffer 1012 may include at least one data input port and at least one data output port.

[0101] In one embodiment, the data buffer 1012 may include multiple data input ports and multiple data output ports. The data buffer 1012 can store data in parallel through the multiple data input ports according to a write control signal; the data buffer 1012 can output data in parallel through the multiple data output ports according to a read control signal.

[0102] In this embodiment, the data buffer 1012 may have multiple data input ports and multiple data output ports. Therefore, the number of data input ports may correspond to the number of write pointer groups, and the number of data output ports may correspond to the number of read pointer groups. Thus, write pointer groups can write data in parallel through the data input ports, and read pointer groups can read data in parallel through the data output ports.

[0103] In another embodiment, the data buffer 1012 may include a data input port and a data output port. The data buffer 1012 may serially store data through a data input port according to a write control signal, and the data buffer 1012 may serially output data through a data output port according to a read control signal.

[0104] In this embodiment, the data buffer 1012 may have only one data input port and one data output port. Therefore, multiple write pointer groups share one data input port, and multiple read pointer groups share one data output port. Thus, data can be serially passed through the data input port and written into the memory blocks pointed to by the multiple write pointer groups, and data can be read from the read space pointed to by the multiple read pointer groups and output serially through the data output port.

[0105] Of course, the number of data input ports and data output ports may not correspond to the number of write pointer groups and may not be a single group. In this case, when the number of data input ports is less than the number of write pointer groups, some write pointer groups can share a single data input port, while others can each use a separate data input port. Similarly, when the number of data output ports is less than the number of read pointer groups, some read pointer groups can share a single data output port, while others can each use a separate data output port. Thus, a combination of serial and parallel methods can be used to store and output data through the data input and data output ports.

[0106] In addition, the first data cache module may also include an instruction cache. The instruction cache can be used to receive instructions from outside the first data cache module, and parse at least one write control signal and multiple read control signals according to the instructions, wherein each write control signal includes a write pointer group and each read control signal includes a read pointer group.

[0107] In this embodiment, the instructions in the instruction buffer can control the reading and writing of data in the data buffer 1011. Specifically, the instruction buffer can receive instructions from outside the first data buffer module and parse the external instructions to obtain at least one write control signal and multiple read control signals for the data buffer 1011. Each write control signal includes a write pointer group, and each read control signal includes a read pointer group. Furthermore, each write control signal also includes the aforementioned step size, and each read control signal also includes the aforementioned step size and the number of reads.

[0108] Furthermore, instructions from outside the first data cache module may include the above combination Figure 2 The description includes a first sub-write instruction (hereinafter referred to as a write instruction) and a first sub-read instruction (hereinafter referred to as a read instruction). The instruction buffer includes at least one write instruction buffer and multiple read instruction buffers. Each write instruction buffer is used to receive and store the write instruction and parse a write control signal according to each write instruction. Each read instruction buffer is used to receive and store the read instruction and parse a read control signal according to each read instruction.

[0109] Specifically, both the write instruction buffer and the read instruction buffer can be FIFO (First-In, First-Out) buffers. The write instruction buffer receives and stores write instructions, and the read instruction buffer receives and stores read instructions. The number of write instruction buffers corresponds to the number of write pointer groups, and the number of read instruction buffers corresponds to the number of read pointer groups. Each write instruction buffer can parse the write control signal from the top-ranked write instruction according to the FIFO principle, and each read instruction buffer can parse the read control signal from the top-ranked read instruction according to the FIFO principle. Write and read instructions include wait instructions. When the number of memory lines to be read or written is less than the number of write and read instruction buffers, the control signals parsed by some write instruction buffers and / or some read instruction buffers are wait signals, and no operation is performed.

[0110] To accommodate larger-scale and more complex calculations, the aforementioned accelerated computing devices can be used to form an accelerated computing system. Therefore, this disclosure can also provide an accelerated computing system that may include multiple or more combinations of... Figures 1 to 5 The described acceleration computing device.

[0111] The multiple accelerated computing devices in this acceleration system can be used in conjunction with other devices or systems. These other devices or systems can be integrated into the aforementioned accelerated computing system or operate independently of it. For example, the accelerated computing system may include a main processing circuit, and the multiple accelerated computing devices can serve as slave processing circuits, with the main processing circuit controlling the accelerated computing devices to perform computational operations. The main processing circuit and the multiple slave processing circuits can be arranged in an H-shaped structure, a tree structure, or an array structure; no specific limitation is made here.

[0112] The main processing circuit can distribute input data or instructions to at least one of multiple slave processing circuits. Each slave processing circuit can perform operations on its received input data and its locally stored data according to the received instructions. The input data can be neurons or weights; when the input data is a neuron, the local data is the weight; when the input data is a weight, the local data is a neuron.

[0113] In an optional embodiment, each piece of input data carries a corresponding data distribution mode, which can be a broadcast mode, a multicast mode, or a unicast mode. The main processing circuit can distribute the input data to multiple slave processing circuits according to the data distribution mode of the input data.

[0114] When the input data distribution mode is broadcast mode, the main processing circuit can send the input data to each of the multiple slave processing circuits, and the multiple slave processing circuits form a group.

[0115] When the input data distribution mode is multicast, multiple slave processing circuits can be divided into two or more groups, and each group can include a portion of the multiple slave processing circuits. The master processing circuit can send the input data to one of the groups of multiple slave processing circuits according to the input data distribution mode.

[0116] When the input data is distributed in unicast mode, the main processing circuit can send the input data to one of the plurality of slave processing circuits indicated by the multicast mode.

[0117] The accelerated computing system disclosed herein achieves rapid grouped computing by grouping multiple slave computing circuits and controlling the distribution of input data through a data distribution mode, thereby improving computing efficiency.

[0118] This disclosure also provides a method for accelerating computation using an accelerator. (See reference...) Figure 6 , Figure 6 This is a flowchart illustrating a method for accelerating computation according to an embodiment of the present disclosure. Figure 6 As shown, it can be understood that the accelerated computing device used in this accelerated computing method is the one mentioned above. Figures 1-5 The description of the accelerated computing device is detailed, and therefore the preceding description of the accelerated computing device and its internal components, functions and operations also applies to the description herein.

[0119] The accelerated computing method disclosed herein is applied to the aforementioned accelerated computing device. Therefore, the accelerated computing method includes the following steps S101-S102.

[0120] In step S101, the data buffer unit of the adder operation device provides operation data to at least one of the multiple operation units according to a received data read instruction.

[0121] In step S102, at least one arithmetic unit performs arithmetic operations on the received arithmetic data according to the arithmetic instructions it receives.

[0122] According to embodiments of this disclosure, the computational data includes: external data input from outside the accelerated computing device; and local data stored inside the accelerated computing device.

[0123] Reference Figure 7 , Figure 7 This is a flowchart illustrating a method for accelerating computation according to another embodiment of the present disclosure. For example... Figure 7 As shown, the accelerated computation method may include steps S201-S203.

[0124] In step S201, the random access memory of the accelerated computing device is used to store and output local data according to the random access memory instructions.

[0125] Based on the above Figure 6 In step S202, the data buffer unit of the adder operation device provides external data and local data to at least one of the multiple operation units according to a received data read instruction.

[0126] In step S203, at least one arithmetic unit performs arithmetic operations on the received external data and local data according to the arithmetic instructions received by each unit.

[0127] According to embodiments of this disclosure, a data caching unit is used to store at least one external data and at least one local data from random access memory according to a received data write instruction.

[0128] According to embodiments of this disclosure, the data write instruction includes a first sub-write instruction and a second sub-write instruction, and a first data cache module of the data cache unit stores at least one external data according to a received first sub-write instruction; and a second data cache module of the data cache unit stores at least one local data from the random access memory according to a received second sub-write instruction.

[0129] According to an embodiment of this disclosure, the data read instruction includes a first sub-read instruction and a second sub-read instruction. A first data cache module is used to output external data to at least one of the multiple arithmetic units based on a received first sub-read instruction; and a second data cache module is used to output local data to at least one of the multiple arithmetic units based on a received second sub-read instruction.

[0130] According to embodiments of this disclosure, the first data caching module is a one-dimensional data caching module or a multi-dimensional data caching module; the second data caching module is a one-dimensional data caching module or a multi-dimensional data caching module.

[0131] According to embodiments of this disclosure, the obtained calculation result is output to the bus or the random access memory using the arithmetic unit.

[0132] According to embodiments of this disclosure, the computation result is stored in random access memory according to random access memory instructions, and the computation result is used as local data.

[0133] Reference Figure 8 , Figure 8 This is a flowchart illustrating a method for accelerating computation according to yet another embodiment of the present disclosure. Figure 8 The accelerated calculation method shown is similar to Figure 7 The difference between the accelerated calculation methods shown is that... Figure 8 The accelerated computation method shown can be used in Figure 7 The accelerated computing method shown includes step S301 before step S201. In step S301, the control cache unit of the accelerated computing device receives external instructions and parses data read and write instructions for the data cache unit, random access memory instructions for the random access memory, and computing instructions for the computing unit based on the external instructions.

[0134] Figure 9 This is a structural diagram illustrating a combined processing apparatus 700 according to an embodiment of the present disclosure. As shown, the combined processing apparatus 700 includes a computing device 702, which may include the accelerated computing device of the present disclosure as described above in conjunction with the accompanying drawings. Additionally, the combined processing apparatus includes a general interconnect interface 704 and other processing devices 706. The computing device according to the present disclosure interacts with other processing devices to jointly complete user-specified operations.

[0135] According to the scheme of this disclosure, the other processing device may include one or more types of processors such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a neural network processor, and other general-purpose and / or special-purpose processors, and the number is not limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the computing device of this disclosure (which may be embodied as a machine learning computing device) and external data and control, performing tasks including but not limited to data transfer, and completing basic control such as starting and stopping the machine learning computing device; the other processing device may also cooperate with the machine learning computing device to jointly complete computing tasks.

[0136] According to the present disclosure, the universal interconnect interface can be used to transfer data and control commands between a computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnect interface and write it to on-chip storage. Furthermore, the computing device can obtain control commands from other processing devices via the universal interconnect interface and write them to on-chip control cache. Alternatively or optionally, the universal interconnect interface can also read data from the computing device's storage module and transmit it to other processing devices.

[0137] Optionally, the combined processing apparatus may further include a storage device 708, which may be connected to the computing device and the other processing device respectively. In one or more embodiments, the storage device may be used to store data from the computing device and the other processing device, particularly suitable for data that cannot be fully stored in the internal storage of the computing device or other processing device, requiring computation.

[0138] Depending on the application scenario, the combined processing device disclosed herein can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, video capture equipment, and video surveillance equipment. This effectively reduces the core area of ​​the control unit, increases processing speed, and lowers overall power consumption. In this case, the general-purpose interconnect interface of the combined processing device connects to certain components of the device. These components may include, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface.

[0139] In some embodiments, this disclosure also discloses a chip or integrated circuit chip that includes the aforementioned computing device, combined processing device, and accelerated computing device of this disclosure. In other embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip.

[0140] In some embodiments, this disclosure also discloses a circuit board that includes the above-described chip packaging structure. See also... Figure 10 The aforementioned exemplary board is provided. In addition to the chip 802, the board may also include other supporting components, including but not limited to: storage device 804, interface device 806, and controller 808.

[0141] The storage device is connected to the chip within the chip package structure via a bus and is used to store data. The storage device may include multiple sets of storage cells 810. Each set of storage cells is connected to the chip via a bus. It can be understood that each set of storage cells may be DDR SDRAM (“Double Data Rate SDRAM”).

[0142] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include four groups of memory cells. Each group of memory cells may include multiple DDR4 chips. In one embodiment, the chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.

[0143] In one embodiment, each group of memory cells may include multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the chip for controlling the data transfer and data storage of each memory cell.

[0144] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to realize data transmission between the chip and an external device 812 (e.g., a server or computer). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0145] The controller is electrically connected to the chip to monitor its status. Specifically, the chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller ("MCU"). The chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Thus, the chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the chip.

[0146] In some embodiments, this disclosure also discloses an electronic device or apparatus that includes the aforementioned circuit board. Depending on the application scenario, the electronic device or apparatus may include a data processing device, robot, computer, printer, scanner, tablet computer, smart terminal, mobile phone, dashcam, navigator, sensor, camera, server, cloud server, camera, camcorder, projector, watch, earphone, mobile storage, wearable device, vehicle, home appliance, and / or medical device. The vehicle includes airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs.

[0147] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0148] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0149] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the circuit division is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple circuits or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections between devices or circuits through some interfaces, and may be electrical, optical, acoustic, magnetic, or other forms.

[0150] The circuit described as a separate component may or may not be physically separate. The components shown as circuits may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0151] Furthermore, the functional circuits in the various embodiments of this disclosure can be integrated into one processing unit, or each circuit can exist physically separately, or two or more circuits can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0152] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, when the technical solution of this disclosure can be embodied in the form of a software product, the computer software product is stored in a storage device and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage device includes various media capable of storing program code, such as a USB flash drive, read-only memory ("ROM"), random access memory ("RAM"), portable hard drive, magnetic disk, or optical disk.

[0153] The foregoing can be better understood in accordance with the following terms:

[0154] Clause A1, an accelerated computing device, wherein the accelerated computing device includes a data cache unit and a plurality of computing units; the data cache unit is configured to provide computing data to at least one of the plurality of computing units according to a received data read instruction; the at least one computing unit is configured to perform operations on the received computing data according to its respective received computing instructions.

[0155] Clause A2, the accelerated computing device as described in Clause A1, wherein the computing data includes: external data input from outside the accelerated computing device; and local data stored inside the accelerated computing device.

[0156] Clause A3, the accelerated computing device according to Clause A2, wherein the accelerated computing device further includes: random access memory for storing and outputting the local data according to random access memory instructions.

[0157] Clause A4, the accelerated computing device according to Clause A3, wherein the data cache unit stores at least one of the external data and at least one of the local data from the random access memory according to a received data write instruction.

[0158] Clause A5, the accelerated computing apparatus according to Clause A4, wherein the data write instruction includes a first sub-write instruction and a second sub-write instruction, and the data cache unit includes: a first data cache module for storing the at least one external data according to a received first sub-write instruction; and a second data cache module for storing the at least one local data from the random access memory according to a received second sub-write instruction.

[0159] Clause A6, the accelerated computing device according to Clause A5, wherein the data read instruction includes a first sub-read instruction and a second sub-read instruction, the first data cache module is configured to output the external data to at least one of the plurality of computing units according to a received first sub-read instruction; the second data cache module is configured to output the local data to at least one of the plurality of computing units according to a received second sub-read instruction.

[0160] Clause A7, the accelerated computing device described in Clause A5 or A6, wherein the first data cache module is a one-dimensional data cache module or a multi-dimensional data cache module; and the second data cache module is a one-dimensional data cache module or a multi-dimensional data cache module.

[0161] Clause A8, an accelerated computing device according to any one of Clauses A3 to A6, wherein the computing unit outputs the obtained computing result to a bus or the random access memory.

[0162] Clause A9, the accelerated computing apparatus according to Clause A8, wherein the random access memory is used to store the computing results according to random access memory instructions and to treat the computing results as local data.

[0163] Clause A10, the accelerated computing device according to Clause A4, wherein the accelerated computing device further includes: a control cache unit, which is configured to receive external instructions and parse out the data read instructions and the data write instructions for the data cache unit, the random access memory instructions for the random access memory, and the computing instructions for the computing unit according to the external instructions.

[0164] Clause A11, an accelerated computing method implemented using an accelerated computing device, wherein the accelerated computing method includes: using the data buffer unit of the adder to provide computing data to at least one of the plurality of computing units according to a received data read instruction; and using the at least one computing unit to perform operations on the received computing data according to their respective received computing instructions.

[0165] Clause A12, an integrated circuit chip, including an accelerated computing device according to any one of Clauses A1-A10.

[0166] Clause A13, a computing device comprising an accelerated computing device according to any one of Clauses A1-A10 or an integrated circuit chip according to Clause A12.

[0167] Clause A14, a board including a computing device as described in Clause A13.

[0168] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0169] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0170] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0171] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0172] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. An accelerated computing device, wherein, The accelerated computing device includes a data cache unit and multiple computing units; The data cache unit is used to provide computation data to at least one of the plurality of computation units according to a received data read instruction; The at least one arithmetic unit is used to perform arithmetic operations on the received arithmetic data according to the arithmetic instructions received by each unit. The data cache unit stores at least one external data and at least one local data from random access memory according to a received data write instruction; The arithmetic unit outputs the obtained calculation result to the bus or the random access memory; the random access memory is used to store the calculation result according to the random access memory instructions, and to use the calculation result as local data.

2. The accelerated computing device according to claim 1, wherein, The computational data includes: External data input from outside the accelerated computing device; and The local data stored inside the accelerated computing device.

3. The accelerated computing device according to claim 2, wherein, The accelerated computing device also includes: The random access memory is used to store and output the local data according to random access memory instructions.

4. The accelerated computing device according to claim 3, wherein, The data write instruction includes a first sub-write instruction and a second sub-write instruction, and the data cache unit includes: A first data cache module is used to store the at least one external data according to a received first sub-write instruction; The second data cache module is used to store the at least one local data from the random access memory according to a received second sub-write instruction.

5. The accelerated computing device according to claim 4, wherein, The data read instruction includes a first sub-read instruction and a second sub-read instruction. The first data caching module is used to output the external data to at least one of the plurality of arithmetic units according to a received first sub-read instruction; The second data caching module is used to output the local data to at least one of the plurality of arithmetic units according to a received second sub-read instruction.

6. The accelerated computing device according to claim 4 or 5, wherein, The first data caching module is a one-dimensional data caching module or a multi-dimensional data caching module; The second data caching module is a one-dimensional data caching module or a multi-dimensional data caching module.

7. The accelerated computing device according to claim 3, wherein, The accelerated computing device also includes: A control cache unit is configured to receive external instructions and parse out the data read instructions and data write instructions for the data cache unit, the random access memory instructions for the random access memory, and the arithmetic instructions for the arithmetic unit based on the external instructions.

8. A method for accelerating computation using an accelerator, wherein, The accelerated computation method includes: The data cache unit of the accelerated computing device provides computing data to at least one of a plurality of computing units according to a received data read instruction; The at least one arithmetic unit performs arithmetic operations on the received arithmetic data according to the arithmetic instructions received by each unit. The data cache unit is used to store at least one external data and at least one local data from random access memory according to a received data write instruction; The computation unit outputs the obtained computation result to the bus or the random access memory; the random access memory stores the computation result according to the random access memory instructions, and the computation result is used as local data.

9. An integrated circuit chip, comprising an accelerated computing device according to any one of claims 1 to 7.

10. A computing device comprising an accelerated computing device according to any one of claims 1 to 7 or an integrated circuit chip according to claim 9.

11. A board comprising the computing device according to claim 10.

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