A method and device for eliminating false triggering of multi-core DSP interrupts

Abstract

The present invention provides a method and device for eliminating the mis-triggering of multi-core DSP interrupts. The method comprises: setting an interrupt label L corresponding to core n n , n=1,…,N‑1, N is the number of cores in the multi-core DSP; set L in the interrupt service routine of core 0 n =1, n=1,…,N-1; at the beginning of the interrupt service routine of core n, read L n If the value of L n =1, then L n Clear to zero and execute subsequent program code; if L n = 0, directly exit the interrupt program; n = 1, 2, ..., N-1. This invention effectively solves the problem of repeated false triggering of interrupts between cores in multi-core DSP embedded software. When a core generates repeated false triggering of interrupts, its interrupt service routine is immediately exited, and no false triggering occurs on subsequent cores. This allows the program in this core and other cores to run stably, ensuring the high reliability of the multi-core DSP embedded software system.

Description

Technical Field

[0001] The invention belongs to the technical field of computer interruption, and in particular relates to a method and main device for eliminating mis-triggering of multi-core DSP interruption. Background Art

[0002] Multi-core computers are increasingly being used. For example, the internal navigation computer board of a positioning, directional, and aiming system (hereinafter referred to as the aiming system) utilizes a multi-core DSP (TMS320C6674) with four cores: Core 0, Core 1, Core 2, and Core 3. Each core runs its own software program, and data and instruction exchanges between cores are typically handled through inter-core interrupts. The order of inter-core interrupts begins with Core 0: Core 0 triggers Core 1, which in turn triggers Core 2, which in turn triggers Core 3. Core 0 is triggered every 1ms by a timer interrupt, ensuring it will not experience repeated false triggering. However, subsequent cores (Cores 1, 2, and 3) may experience repeated false triggering of interrupts, leading to subsequent false triggering of other cores when responding to the inter-core interrupts. This can cause system software instability and, in severe cases, software crashes on some cores. Summary of the Invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a method and apparatus for eliminating false triggering of multi-core DSP interrupts.

[0004] In order to achieve the above objectives, the present invention adopts the following technical solutions.

[0005] In a first aspect, the present invention provides a method for eliminating false triggering of multi-core DSP interrupts, comprising:

[0006] Set the interrupt label L corresponding to core n n , n=1,…,N-1, N is the number of cores in the multi-core DSP;

[0007] Set L in the interrupt service routine of core 0 n =1, n=1,…,N-1;

[0008] At the beginning of the interrupt service routine of core n, read L n If the value of L n =1, then L n Clear to zero and execute subsequent program code; if L n =0, exit the interrupt program directly; n=1,2,…,N-1.

[0009] Furthermore, the interrupt of core 0 is triggered by a timer interrupt.

[0010] Furthermore, the core n interrupt is triggered by core (n-1) before exiting its interrupt service routine, n=1, ..., N-1.

[0011] Furthermore, the interruption label L n The setting method is: add the array Label[N-1] after the original data and command parameter area in the shared memory area of ​​the multi-core DSP, L n =Label[n-1], n=1,...,N-1.

[0012] Furthermore, the method further comprises: if L n =0, exit the interrupt program after sending a prompt message about repeated false triggering of core n, n=1,2,…,N-1.

[0013] Furthermore, N=4.

[0014] In a second aspect, the present invention provides a device for eliminating false triggering of multi-core DSP interrupts, comprising:

[0015] Label setting module, used to set the interrupt label L corresponding to core n n , n=1,…,N-1, N is the number of cores in the multi-core DSP;

[0016] Label assignment module, used to set L in the interrupt service routine of core 0 n =1, n=1,…,N-1;

[0017] The false trigger judgment module is used to read L at the beginning of the interrupt service routine of core n. n If the value of L n =1, then L n Clear to zero and execute subsequent program code; if L n =0, exit the interrupt program directly; n=1,2,…,N-1.

[0018] Furthermore, the core 0 interrupt is triggered by a timer interrupt.

[0019] Furthermore, the core n interrupt is triggered by core (n-1) before exiting its interrupt service routine, n=1, ..., N-1.

[0020] Furthermore, the interruption label L n The setting method is: add the array Label[N-1] after the original data and command parameter area in the shared memory area of ​​the multi-core DSP, L n =Label[n-1], n=1,...,N-1.

[0021] Furthermore, the method further comprises: if L n =0, exit the interrupt program after sending a prompt message about repeated false triggering of core n, n=1,2,…,N-1.

[0022] Furthermore, N=4.

[0023] Compared with the prior art, the present invention has the following beneficial effects.

[0024] The present invention sets an interruption label L corresponding to the core n. n , set L in the interrupt service routine of core 0 n =1, at the beginning of the interrupt service routine of core n, read L n If the value of L n =1, then L n Clear to zero and execute subsequent program code. If L n = 0, directly exit the interrupt program, realizing inter-core interrupts in a multi-core DSP. This invention effectively solves the problem of repeated false triggering of inter-core interrupts in multi-core DSP embedded software. When a core generates repeated false triggering of an interrupt, its interrupt service routine is immediately exited, and no false triggering occurs on subsequent cores. This enables the program of this core and other cores to run stably, ensuring the high reliability of the operation of the multi-core DSP embedded software system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention provides a flowchart of a method for eliminating false triggering of multi-core DSP interrupts.

[0026] Figure 2 Schematic diagram of the interrupt execution relationship between 4-core DSP cores.

[0027] Figure 3 The figure is a flowchart of the inter-core interrupt response process of a 4-core DSP.

[0028] Figure 4 The present invention is a block diagram of a device for eliminating false triggering of multi-core DSP interrupts according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the present invention more clear and understandable, the present invention is further described below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0030] Figure 1 This is a flow chart of a method for eliminating false triggering of multi-core DSP interrupts according to an embodiment of the present invention, comprising the following steps:

[0031] Step 101: Set the interrupt label L corresponding to core n n , n=1,…,N-1, N is the number of cores in the multi-core DSP;

[0032] Step 102, set L in the interrupt service routine of core 0 n =1, n=1,…,N-1;

[0033] Step 103, at the beginning of the interrupt service routine of core n, read L n If the value of L n =1, then L n Clear to zero and execute subsequent program code; if L n =0, exit the interrupt program directly; n=1,2,…,N-1.

[0034] This embodiment proposes a method for eliminating false interrupt triggering in a multi-core DSP. A multi-core DSP has multiple cores, each of which runs its own software program. The interaction of data and instructions between different cores is generally handled through inter-core interrupts. Inter-core interrupts are executed sequentially according to a set order. For example, an interrupt starts with core 0, core 0 triggers core 1, core 1 triggers core 2, and so on. Since core 0 is not triggered by other cores (for example, its interrupt can be triggered once every 1ms by a timer interrupt), the interrupt of core 0 generally does not experience repeated false triggering. However, subsequent interrupts from cores 1, 2, and so on may experience repeated false interrupt triggering, causing subsequent false triggering when other cores respond to the inter-core interrupt, making the system software unstable; in severe cases, it may cause the software of some cores to crash. Therefore, this embodiment proposes a method for resolving false interrupt triggering between cores in multi-core DSP embedded software. The method is applicable to the situation where the inter-core interrupt is repeatedly falsely triggered during the multi-core inter-core interrupt process.

[0035] In this embodiment, step 101 is mainly used to set the interrupt label. The purpose of setting the interrupt label is to determine whether the corresponding core interrupt has been triggered based on its different values ​​(such as 0 and 1), and on this basis, certain measures are taken to eliminate the impact of false triggering. This embodiment assumes that the total number of cores is N, N≥2; the N cores are called core 0, core 1, ..., core (N-1) in sequence; the execution order of the N core interrupts is core 0, core 1, ..., core (N-1), that is, the core 0 interrupt is triggered first, and the core 1 interrupt is triggered before exiting the interrupt service program. Core 1 then triggers the core 2 interrupt, and so on, until core (N-1) is triggered. Therefore, only the interrupt of core 0 is not triggered by the interrupts of other cores, so the interrupt of core 0 generally does not have the phenomenon of repeated false triggering. Therefore, this embodiment sets an interrupt label for each core except core 0 in the multi-core DSP, that is, a total of (N-1) labels are set. Without loss of generality, the interrupt label corresponding to core n is recorded as L n , where n=1,…,N-1.

[0036] In this embodiment, step 102 is mainly used to modify the interrupt service routine of core 0. As mentioned above, core 0 has special features compared with the other (N-1) cores. Therefore, the modification of the interrupt service routine of core 0 is also different from that of the other cores and needs to be performed separately. In this embodiment, the method for modifying the interrupt service routine of core 0 is to set the value of all interrupt labels to 1, that is, to set L n =1, n=1, ..., N-1. In this embodiment, an interrupt flag value of 1 indicates that the interrupt of the corresponding core has not been triggered, and an interrupt flag value of 0 indicates that the interrupt of the corresponding core has been triggered. Of course, 0 can also be used to indicate that the interrupt has not been triggered, and 1 can be used to indicate that the interrupt has been triggered. Other numbers other than 0 and 1 can also be used to distinguish.

[0037] In this embodiment, step 103 is mainly used to modify the interrupt service routines of other cores. The modification method of the interrupt service routines of core 1 to core (N-1) is the same, which is to read the value L of the interrupt label corresponding to the core at the beginning of the interrupt service routine. n , if L n The value of L is 1, indicating that the interrupt of the core has not been triggered (or responded to) before. n After clearing, execute the subsequent program code of the interrupt service program. Of course, you can also execute the subsequent program code of the interrupt service program first, and clear L before exiting the interrupt service program. n Cleared; if L n If the value of 0 indicates that the interrupt of the core has been triggered, the interrupt routine is directly exited. This can avoid repeated response to the interrupt service routine that was triggered by mistake.

[0038] This embodiment sets an interrupt tag, checks the value of the interrupt tag in the core interrupt service program, and determines whether it is a repeated false triggering of an inter-core interrupt based on whether the value is 0 or 1. If so, the interrupt service program is immediately exited (not executed). This allows the current core program and other core programs to run stably, ensures the high reliability of the multi-core DSP embedded software system, and effectively solves the problem of repeated false triggering of inter-core interrupts in the multi-core DSP embedded software.

[0039] As an optional embodiment, the core 0 interrupt is triggered by a timer interrupt.

[0040] This embodiment provides a technical solution for triggering the core 0 interrupt. As mentioned above, the core 0 interrupt is not triggered by other core interrupts. In this embodiment, the core 0 interrupt is triggered by a timer interrupt. An interrupt means that when some unexpected situation occurs during the operation of the computer and the host needs to intervene, the machine can automatically stop the running program and switch to the program to handle the new situation. After the processing is completed, it returns to the originally suspended program to continue running. Interrupts include external interrupts and internal interrupts. Timer interrupts are internal interrupts. Timer interrupts are interrupts requested by timer overflow. Many processors or single-chip microcomputers are equipped with timers. For example, the 51 single-chip microcomputer has two timers T0 and T1, which have timer 0 interrupt and timer 1 interrupt functions. Timers generally use a periodic interrupt method, that is, an interrupt is triggered every other cycle. The core 0 interrupt in this embodiment is triggered by the timer every 1 millisecond.

[0041] As an optional embodiment, the core n interrupt is triggered by core (n-1) before exiting its interrupt service routine, where n=1, ..., N-1.

[0042] This embodiment provides a method for triggering inter-core interrupts. In this embodiment, except for core 0, interrupts for all other cores are triggered before the interrupt service routine of the adjacent core exits. For example, the interrupt for core 1 is triggered before core 0 exits its interrupt service routine; the interrupt for core 3 is triggered before core 2 exits its interrupt service routine. This is achieved by adding a statement at the end of each core's interrupt service routine to trigger the interrupt for the next core. This exception applies to the last core, core (N-1).

[0043] As an optional embodiment, the interruption label L n The setting method is: add the array Label[N-1] after the original data and command parameter area in the shared memory area of ​​the multi-core DSP, L n =Label[n-1], n=1,...,N-1.

[0044] This embodiment provides a method for setting the interruption label L n A specific technical solution. This embodiment adds an array as an interrupt label after the original data and command parameter area in the shared memory area. As mentioned above, when the number of cores is N, (N-1) interrupt labels need to be set (core 0 does not need it), so the length of the array, that is, the number of elements in the array, should be (N-1), recorded as Label[N-1]. Label[0] is the first interrupt label L1, Label[1] is the second interrupt label L2, and so on. Label[N-2] is the (N-1)th interrupt label L N-1 .

[0045] As an optional embodiment, the method further includes: if L n=0, exit the interrupt program after sending a prompt message about repeated false triggering of core n, n=1,2,…,N-1.

[0046] This embodiment provides a technical solution for providing an alarm for repeated core triggering. In this embodiment, if the interrupt flag value is 0, indicating a repeated core triggering, an alarm message is sent to provide a prompt before exiting the interrupt service routine. Of course, this requires adding a statement to send the alarm message at the beginning of the corresponding interrupt service routine. Similarly, this embodiment covers all cores except core 0, namely, cores 1 to core (N-1).

[0047] As an optional embodiment, N=4.

[0048] This embodiment limits the total number of cores N. In this embodiment, N=4, that is, there are 4 cores in total, namely core 0, core 1, core 2, and core 3. Figure 2 A schematic diagram of the interrupt execution relationship between 4-core DSP cores is given; Figure 3 A schematic diagram of the 4-core DSP inter-core interrupt response process is given. Figure 3 The three interrupt labels in the array are Label[3].

[0049] Figure 4 This is a schematic diagram of a device for eliminating false triggering of multi-core DSP interrupts according to an embodiment of the present invention. The device includes:

[0050] The label setting module 11 is used to set the interrupt label L corresponding to the core n. n , n=1,…,N-1, N is the number of cores in the multi-core DSP;

[0051] Label assignment module 12, used to set L in the interrupt service routine of core 0 n =1, n=1,…,N-1;

[0052] The false trigger judgment module 13 is used to read L at the beginning of the interrupt service program of core n. n If the value of L n =1, then L n Clear to zero and execute subsequent program code; if L n =0, exit the interrupt program directly; n=1,2,…,N-1.

[0053] The device of this embodiment can be used to perform Figure 1 The technical solution of the method embodiment shown has similar implementation principles and technical effects, which will not be described in detail here. The same is true for the following embodiments, which will not be described in detail.

[0054] As an optional embodiment, the core 0 interrupt is triggered by a timer interrupt.

[0055] As an optional embodiment, the core n interrupt is triggered by core (n-1) before exiting its interrupt service routine, where n=1, ..., N-1.

[0056] As an optional embodiment, the interruption label L n The setting method is: add the array Label[N-1] after the original data and command parameter area in the shared memory area of ​​the multi-core DSP, L n =Label[n-1], n=1,...,N-1.

[0057] As an optional embodiment, the method further includes: if L n =0, exit the interrupt program after sending a prompt message about repeated false triggering of core n, n=1,2,…,N-1.

[0058] As an optional embodiment, N=4.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for eliminating false triggering of multi-core DSP interrupts, characterized in that: The following steps are involved: Set the interrupt label L corresponding to core n n , where the core n interrupt is triggered by the statement that triggers the next core interrupt added before core n-1 exits its interrupt service routine, n=1,…,N-1, N is the number of cores in the multi-core DSP; Set L in the interrupt service routine of core 0 n =1, n=1,…,N-1; At the beginning of the interrupt service routine of core n, read L n If the value of L n =1, indicating that the interrupt of core n has not been triggered or responded to before, then L n Clear to 0 and execute the subsequent program code of the interrupt service program; if L n =0, exit the interrupt program directly; n=1,2,…,N-1.

2. The method for eliminating false triggering of multi-core DSP interrupts according to claim 1, characterized in that: The interrupt of the core 0 is triggered by the timer interrupt.

3. The method for eliminating false triggering of multi-core DSP interrupts according to claim 2, characterized in that: The interrupt label L n The setting method is: add the array Label[N-1] after the original data and command parameter area in the shared memory area of ​​the multi-core DSP, L n =Label[n-1], n=1,…,N-1.

4. The method for eliminating false triggering of multi-core DSP interrupts according to claim 3, characterized in that: The method further comprises: if L n =0, exit the interrupt routine after sending a prompt message about repeated false triggering of core n, n=1,2,…,N-1.

5. The method for eliminating false triggering of multi-core DSP interrupts according to any one of claims 1 to 4, characterized in that: N=4。 6. A device for eliminating false triggering of multi-core DSP interrupts, characterized in that: include: Label setting module, used to set the interrupt label L corresponding to core n n , where the core n interrupt is triggered by the statement that triggers the next core interrupt added before core n-1 exits its interrupt service routine, n=1,…,N-1, N is the number of cores in the multi-core DSP; Label assignment module, used to set L in the interrupt service routine of core 0 n =1, n=1,…,N-1; The false trigger judgment module is used to read L at the beginning of the interrupt service routine of core n. n If the value of L n =1, indicating that the interrupt of core n has not been triggered or responded to before, then L n Clear to 0 and execute the subsequent program code of the interrupt service program; if L n =0, exit the interrupt program directly; n=1,2,…,N-1.

7. The device for eliminating false triggering of multi-core DSP interrupts according to claim 6, characterized in that: The core 0 interrupt is triggered by a timer interrupt.

8. The device for eliminating false triggering of multi-core DSP interrupts according to claim 7, characterized in that: The interrupt label L n The setting method is: add the array Label[N-1] after the original data and command parameter area in the shared memory area of ​​the multi-core DSP, L n =Label[n-1], n=1,…,N-1.

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