Wafer Bonding Identification and Its Forming Method, Wafer Bonding Method

Abstract

The present application provides a wafer bonding mark, a method for forming the same, and a wafer bonding method. The wafer bonding mark includes a main marking scale, which includes a plurality of main engraved lines evenly distributed and having a first interval dimension; a secondary marking scale, which is aligned with the starting point of the main marking scale and is distributed parallel to the main marking scale, and includes a plurality of secondary engraved lines evenly distributed and having a second interval dimension; the first interval dimension is greater than the second interval dimension and has a specific difference. The wafer bonding mark of the technical solution of the present application can be used as a bonding mark during bonding, and can also provide offset data to ensure bonding accuracy.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly to a wafer bonding mark, a method for forming the same, and a wafer bonding method. Background Art

[0002] With the development of semiconductor technology, 3D packaging technology has been increasingly widely used. 3D packaging technology refers to a packaging technology in which two or more chips are stacked and connected vertically in the same package without changing the planar size of the package. Since 3D packaging technology requires two or more wafers to be vertically stacked and connected, it is necessary to align and connect two or more wafers.

[0003] The bonding technology used to connect wafers utilizes the interatomic bonding force on the surfaces of two wafers with flat surfaces and the same or different materials, making a preliminary face-to-face bonding, and then through special treatment, the atoms on the surfaces of these two wafers react to generate covalent bonding, so that the bonding energy between the two planes reaches a certain strength. Currently, with the development of semiconductor manufacturing technology, the bonding technology is also facing more and more challenges, including how to ensure high bonding accuracy. Summary of the Invention

[0004] The technical problem to be solved by the present application is to provide a wafer bonding mark that can be used as a mark during wafer bonding and can also provide offset data to ensure bonding accuracy.

[0005] To solve the above technical problem, the present application provides a wafer bonding mark located on the bonding surface or non-bonding surface of a wafer to be bonded, including: a main marking scale, including a plurality of main engraved lines evenly distributed with a first interval size; a secondary marking scale, aligned with the starting point of the main marking scale and distributed parallel to the main marking scale, including a plurality of secondary engraved lines evenly distributed with a second interval size; the first interval size is greater than the second interval size and has a specific difference.

[0006] In an embodiment of the present application, the specific difference is 10 nm to 100 nm.

[0007] In an embodiment of the present application, the bonding surface includes a trimmed recessed portion, and the recessed portion is a region extending a specific width from the edge of the wafer to be bonded towards the geometric center of the wafer to be bonded.

[0008] In an embodiment of the present application, the specific width is 1 mm - 5 mm.

[0009] In an embodiment of the present application, the non-bonding surfaces on opposite sides of the recessed portion include at least a pair of main marking scales and secondary marking scales.

[0010] In the embodiments of the present application, the sum of the depths of the main engraved lines, the sub-engraved lines and the recessed part is less than the thickness of the wafer to be bonded.

[0011] In the embodiments of the present application, the depth of the recessed part is 100μm - 200μm, the depths of the main engraved line and the sub-engraved line are 0.003μm - 100μm, and the thickness of the wafer to be bonded does not exceed 800μm.

[0012] In the embodiments of the present application, the wafer to be bonded includes a first wafer and a second wafer, and the bonding surface of the first wafer or the second wafer includes a trimmed recessed part.

[0013] The technical solution of the present application also provides a method for forming a wafer bonding mark, including: providing a wafer to be bonded, the wafer to be bonded including a bonding surface and a non-bonding surface; etching the bonding surface or the non-bonding surface to form a main marking scale and a sub-marking scale; wherein, the main marking scale includes a plurality of main engraved lines evenly distributed and having a first interval dimension; the sub-marking scale, aligned with the starting point of the main marking scale and distributed parallel to the main marking scale, includes a plurality of sub-engraved lines evenly distributed and having a second interval dimension; the first interval dimension is greater than the second interval dimension and has a specific difference.

[0014] In the embodiments of the present application, the specific difference is 10nm - 100nm.

[0015] In the embodiments of the present application, before etching the bonding surface or the non-bonding surface, it further includes: trimming treatment, the trimming treatment includes etching a part of the wafer to be bonded on the side of the bonding surface to form a recessed part, wherein the recessed part is a region extending a specific width from the edge of the wafer to be bonded towards the geometric center of the wafer to be bonded.

[0016] In the embodiments of the present application, the specific width is 1mm - 5mm.

[0017] In the embodiments of the present application, the wafer to be bonded includes a first wafer and a second wafer, and trimming treatment is performed on the first wafer or the second wafer.

[0018] In the embodiments of the present application, a part of the wafer to be bonded on the side opposite to the recessed part is etched to form at least a pair of main marking scales and sub-marking scales.

[0019] In the embodiments of the present application, the method for forming the main marking scale and the sub-marking scale includes at least one of laser etching, cutting and photolithography.

[0020] In the embodiments of the present application, before or after forming the main engraved lines and the sub-engraved lines, the edge of the wafer to be bonded is etched to form at least one notch, and the notch penetrates the wafer to be bonded in the thickness direction.

[0021] The technical solution of this application also provides a wafer bonding method, including: providing a first wafer and a second wafer to be bonded; forming the above-mentioned wafer bonding mark on the non-bonding surfaces of the first wafer and the second wafer; aligning the wafer bonding marks of the first wafer and the second wafer to complete the bonding operation.

[0022] In the embodiment of this application, after completing the bonding operation, it further includes: selecting the wafer bonding mark of the first wafer or the second wafer as the reference mark, and the wafer bonding marks of the remaining wafers as the reading marks; reading the offset data of the reading mark relative to the reference mark to obtain the offset data of the bonding operation.

[0023] In the embodiment of this application, the method for reading the offset data includes: obtaining that the leftmost main scale line of the reading mark is aligned with the nth main scale line of the reference mark, or the leftmost main scale line of the reading mark is located between adjacent main scale lines of the reference mark, and the left main scale line of the adjacent main scale lines is the nth main scale line, where n is a natural number, and taking the result of n×the first interval size as the main scale reading of the reading mark; obtaining that the secondary scale line of the reading mark is closest to the mth main scale line of the reference mark, where m is a natural number, and taking the result of m×(the first interval size - the second interval size) as the secondary scale reading of the reading mark; adding the main scale reading and the secondary scale reading to obtain the offset data.

[0024] In the embodiment of this application, after obtaining the offset data, it further includes: determining that the offset data of the bonding operation is within a reasonable range; continuing to etch the bottom of the recess until the main scale line and the secondary scale line are etched completely.

[0025] The wafer bonding mark of the technical solution of this application can be located on the bonding surface or the non-bonding surface of the wafer to be bonded, and includes a main scale and a secondary scale. During bonding, the main scale and the secondary scale can be used as alignment marks; after bonding, the readings of the main scale and the secondary scale can be directly obtained, and adding the reading of the main scale and the reading of the secondary scale can obtain the offset data of this bonding operation.

[0026] By setting the main scale and the secondary scale, where the main scale has a first interval size and the secondary scale has a second interval size, making the first interval size greater than the second interval size and having a specific difference, due to the existence of the specific difference, the combination of the main scale and the secondary scale for measurement has higher precision.

[0027] Furthermore, making the main scale and the secondary scale located in the trimming area of the non-bonding surface of the wafer to be bonded can not only ensure that the bonding surface is not damaged, but also not occupy the effective area of the wafer to be bonded additionally.

[0028] The wafer bonding identification adopting the technical solution of the present application can make the bonding identifications of the wafers to be bonded the same, reducing the design workload. When the wafer bonding identification is located in the scribe line area, the wafer with the wafer bonding identification can be directly used as a normal wafer, avoiding the situation that once the "nested" mark is formed on the wafer to be bonded, the relative positions (above and below) between the wafer to be bonded and another wafer to be bonded are determined during bonding, and the wafer to be bonded with the "nested" mark can no longer be directly used as a normal wafer. Description of the Drawings

[0029] The following drawings detail the exemplary embodiments disclosed in the present application. The same reference numerals in the several views of the drawings represent similar structures. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0030] Figure 1 It is a schematic diagram of a method for wafer bonding alignment;

[0031] Figure 2 It is a schematic diagram of the structure of a "nested" mark;

[0032] Figure 3 It is a schematic diagram of the structure of wafer bonding alignment;

[0033] Figure 4 It is a schematic diagram of the structure of the wafer bonding identification according to the embodiment of the present application;

[0034] Figure 5 It is a schematic diagram of Structure I in the wafer bonding identification according to the embodiment of the present application;

[0035] Figure 6 It is a kind of offset result shown by the wafer bonding identification according to the embodiment of the present application;

[0036] Figure 7 It is a top view of the upper wafer to be bonded in the wafer to be bonded according to the embodiment of the present application;

[0037] Figure 8 It is along Figure 7 The cross-sectional view in the OO1 direction in

[0038] Figure 9 It is a schematic diagram of the structure after bonding the wafers to be bonded according to the embodiment of the present application;

[0039] Figure 10 It is a schematic diagram of the structure of the wafer bonding identification according to the embodiment of the present application;

[0040] Figure 11 This is a schematic structural diagram of the notch in the embodiment of the present application. Detailed implementation manners

[0041] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the illustrated embodiments, but has the broadest scope consistent with the claims.

[0042] Reference Figure 1 , a method for wafer bonding alignment is to etch notches on all wafers to be bonded. During bonding, only the notches need to be aligned. For example, the wafers to be bonded include wafer A and wafer B. First, notch A1 is etched on wafer A, and notch B1 is formed on wafer B. Then, with notch A1 as the reference object, notch B1 is aligned with notch A1, and wafer B is stacked on wafer A to complete the bonding of wafer A and wafer B. Generally, the bonding step at this stage can achieve relatively high precision. However, this is a rough alignment method. If the bonding step continues, due to the increase in the number of stacked wafers, the alignment precision will decrease. For example, when wafer C is bonded to the surface of wafer B, it is very likely that notch C1 cannot be completely aligned with notch B1, resulting in abnormal connection between wafer B and wafer C.

[0043] Another method for wafer bonding alignment is to use specific marks for alignment. Micron-level marks are prepared in the wafers through photolithography as alignment reference objects. Reference Figure 2 , the current marks can be called "nested" marks, that is, during wafer bonding, each wafer has a set of marks. For example, mark A2 is made in wafer A, and mark B2 is made in wafer B. The sizes or shapes of mark A2 and mark B2 are different. After bonding, the bonding offset is characterized by measuring the distance between the corresponding positions of mark A2 and mark B2. However, when making marks, they need to be "merged" with the photomask of a certain layer of the device structure pattern, and the marks are placed in the scribe line, which will affect the original test key design or layout. Moreover, different types of device wafers have different pattern layouts, so different designs or layouts need to be made for the marks. This bonding method also requires a mark matrix to be formed on the wafer, and air bubbles may be formed after bonding.

[0044] Reference Figure 3 , a mark A2 is formed in wafer A, and a mark B2 is formed on wafer B. Among them, mark A2 is a dielectric layer groove mark, and mark B2 is a metal layer mark. After the planarization process, the metal layer mark is not affected, while the dielectric layer groove mark will be weakened or even lose its marking significance. This is because the planarization process also uses a dielectric film, so the dielectric layer groove mark will be filled, resulting in a reduced contrast. Moreover, the mark A2 is prone to form bubbles during bonding. Coupled with the mark matrix on the wafer surface, a large number of bubbles will be generated after bonding, seriously affecting the bonding quality.

[0045] In view of this, the technical solution of this application makes a wafer bonding mark on the wafer to be bonded. The wafer bonding mark includes a main marking scale and a secondary marking scale. Among them, the main marking scale lines include several uniformly distributed main scale lines, and the secondary marking scale includes several secondary scale lines. The main scale lines and the secondary scale lines can not only serve as bonding marks, but also can serve as a scale to provide bonding offset data. In addition, the main scale lines and the secondary scale lines can be made in the "trim" area, so that the main scale lines and the secondary scale lines can be removed together during the trimming process without additionally occupying the effective area of the wafer. Moreover, the wafer bonding marks of the wafers to be bonded are all the same, reducing the design workload. The wafers with the main scale lines and the secondary scale lines made have high versatility and can also be used directly as ordinary wafers.

[0046] The following will describe in detail the wafer bonding marks of the technical solution of this application with reference to the accompanying drawings and specific embodiments.

[0047] Please refer to Figure 4 , the embodiment of this application provides a wafer bonding mark, which can play an alignment role during wafer bonding and can directly read the bonding offset data without measurement. The wafer bonding mark can be located on the bonding surface of the wafer to be bonded or on the non-bonding surface of the wafer to be bonded. The bonding surface refers to the contact surface when the wafer to be bonded is bonded, and the non-bonding surface refers to the surface on the opposite side of the wafer to be bonded from the bonding surface. For example, the wafer to be bonded includes a first wafer and a second wafer. In some embodiments, the wafer bonding marks of the first wafer and the second wafer are both located on the bonding surface. In some embodiments, the wafer bonding mark of the first wafer is located on the bonding surface, and the wafer bonding mark of the second wafer is located on the non-bonding surface. Or in some embodiments, the wafer bonding mark of the first wafer is located on the non-bonding surface, and the wafer bonding mark of the second wafer is located on the bonding surface. In the embodiment of this application, the wafer bonding marks 1 of the wafer O to be bonded are all located on the non-bonding surface, which can avoid damaging the bonding surface of the wafer to be bonded when making the wafer bonding mark.

[0048] Reference Figure 4and Figure 5 In the wafer bonding identification 1 of the embodiment of the present application, there are at least two most basic structures, namely Structure I and Structure II. Structure I will be introduced first below. The Structure I includes a main identification scale 100 and a secondary identification scale 200. The main identification scale 100 includes a plurality of main engraved lines 101 evenly distributed, and there is a first interval size d1 between adjacent main engraved lines 101. The secondary identification scale 200 includes a plurality of secondary engraved lines 201 evenly distributed, and there is a second interval size d2 between adjacent secondary engraved lines 201. In current measuring tools (such as a straight ruler, vernier caliper, etc.), the value of the smallest grid between two adjacent scales on the measuring tool is called the least count, which means the unit scale. Generally speaking, the smaller the least count, the higher the measurement precision. For the convenience of description, the embodiment of the present application also introduces the concept of least count, where the first interval size d1 represents the least count of the main identification scale 100, and the second interval size d2 represents the least count of the secondary identification scale 200. The starting points of the secondary identification scale 200 and the main identification scale 100 are aligned. That is to say, the first secondary engraved line 201 of the secondary identification scale 200 and the first main engraved line 101 of the main identification scale 100 are on the same straight line. It can also be considered that the first main engraved line 101 serves as the zero scale line (also called zero engraved line) of the main identification scale 100. Correspondingly, the first secondary engraved line 201 serves as the zero scale line (also called zero engraved line) of the secondary identification scale 200. The zero scale line of the main identification scale 100 and the zero scale line of the secondary identification scale 200 are on the same straight line. The function of the first main engraved line 101 on the main identification scale 100 and the function of the first secondary engraved line 201 on the secondary identification scale 200 are equivalent to the function of the line marked with "0" on the existing measuring tool.

[0049] Similar to the structure of a straight ruler or vernier caliper, the main identification scale 100 can be sequentially numbered in groups of 10 main engraved lines 101. The sequentially numbered numbers are the scales of the main identification scale 100, and the size of the scales is determined according to the least count and range of the main identification scale 100. The range of the main identification scale 100 refers to the distance between the first main engraved line 101 (zero scale line) and the last main engraved line 101. The range of the main identification scale 100 is designed according to actual needs. For example, the range of the main identification scale 100 can be 5μm, and its least count is 0.1μm. Another example is that the range of the main identification scale 100 is 1μm, and its least count is 0.02μm. Structure I shows a main identification scale 100 with a range of 5μm, which is sequentially numbered in groups of 10 main engraved lines 101. The sequentially numbered numbers are 1μm, 2μm, 3μm, 4μm, and 5μm from small to large, which can be analogized to the scale representation method on a common straight ruler.

[0050] The distance between the first secondary engraved line 201 (zero scale line) and the last secondary engraved line 201 of the secondary scale 200 (i.e., the range of the secondary scale 200) and the length represented by the first scale of the main scale 100 (such as Figure 4 the scale marked with "1" in the middle standard) Figure 4 The length represented by the scale marked with "1" in the middle standard is 1μm) has a specific difference (the specific difference is analogous to the specific difference between the main scale and the vernier scale in a vernier caliper), and the specific difference is designed according to actual requirements. Since there is a specific difference between the range of the secondary scale 200 and the length represented by the first scale value of the main scale 100, there is also a specific difference between the graduation value of the main scale 100 and the graduation value of the secondary scale 200. That is to say, there is a specific difference between the first interval size d1 and the second interval size d2, and the first interval size d1 is greater than the second interval size d2. The size of the specific difference is determined according to the actual situation. The smaller the specific difference, the higher the measurement accuracy. However, when the specific difference is too small, it is not easy to identify and read the value. Especially in the semiconductor manufacturing field, the wafer size itself is very small, so the offset size generated during bonding is even more negligible. Therefore, the specific difference needs to be controlled within a certain range to be able to better identify and read the value while still having a high accuracy. In the embodiments of the present application, the specific difference can be 10nm to 100nm. Here, the embodiments of the present application introduce the concept of "accuracy", and the difference between the first interval size d1 and the second interval size d2 is called the accuracy of the wafer bonding mark during measurement.

[0051] As Figure 5 shown, the first interval size d1 is 0.1μm, and the second interval size d2 is 0.09μm. Therefore, the accuracy of the wafer bonding mark in the embodiments of the present application during measurement is 0.01μm.

[0052] Referring to Figure 4 , the structure II of the wafer bonding mark is basically the same as the structure I, except that the main engraved line and the secondary engraved line in the structure I are made into a "cross" shape, which can play an alignment role. And according to the actual situation, one or both ends of the main engraved line and the secondary engraved line can be made into a "cross" shape, or all the main engraved lines and the secondary engraved lines can be made into a "cross" shape. The main engraved line and the secondary engraved line of the structure II are both in a linear structure, and this way can also play an alignment role, but there are not as many alignable positions as in the structure I. In the structure I and the structure II, the positions of the main scale and the secondary scale can be interchanged, as long as it is ensured that the main scale and the secondary scale are parallelly distributed and the starting points are aligned.

[0053] Referring to Figure 6, when taking readings, the reading method of a vernier caliper can be referred to. For example, two wafers are respectively formed with the wafer bonding identifier A and the wafer bonding identifier B of the embodiments of the present application, and the two wafers have been bonded. To determine the offset data of the wafer bonding identifier B relative to the wafer bonding identifier A, only by taking the main scale 100 on the wafer bonding identifier A as a reference, read the offset data of the main scale 110 and the secondary scale 210 on the wafer bonding identifier B. Taking the graduation value of the main scale 100 as 0.1 μm and the graduation value of the secondary scale 200 as 0.09 μm as an example to introduce the specific reading method: First, read the position of the zero scale line on the main scale 110 on the main scale 100. As Figure 6 shown, the zero scale line of the main scale 110 is aligned with the 3rd main engraved line of the main scale 100. Therefore, the reading of the main scale 110 is obtained, and its reading is 0.3 μm. Then, it is observed that the 3rd secondary engraved line on the secondary scale 210 is aligned with the main engraved line on the main scale 100. Therefore, the reading of the secondary scale 210 is obtained as 3×(0.1 - 0.09) = 0.03 μm. Finally, add the main scale reading and the secondary scale reading to obtain the offset data of 0.33 μm.

[0054] Figure 7 shows a top view of the wafer to be bonded located on the upper layer during bonding, Figure 8 shows a cross-sectional view cut along the Figure 7 OO1 direction in. In order to avoid damage defects to the wafer caused by the thinning process, the wafer will be trimmed before the thinning process, so that the bonding surface of the wafer to be bonded includes a recessed portion 300. Since Figure 7 is a top view from the non-bonding surface perspective, the recessed portion 300 cannot be seen. It can be understood that the recessed portion 300 is the ring between the dotted circle and the solid circle. Combining with Figure 8 can more clearly understand the shape and position of the recessed portion 300. The recessed portion 300 of the embodiments of the present application is a region extending a specific width W from the edge of the wafer to be bonded to the geometric center of the wafer to be bonded. The size of the recessed portion 300 is determined according to the size of the invalid area on the wafer to be bonded, and the wafer at the bottom of the recessed portion 300 also needs to be removed in the subsequent process, leaving only the effective area on the wafer to be bonded. The effective area on the wafer to be bonded described in the embodiments of the present application refers to the area where chips are produced. On the contrary, the invalid area on the wafer to be bonded refers to the area where chips are not produced. The size of the specific width W is relatively critical. If the specific width W is too small, too much of the remaining invalid area will result in an oversized wafer size. If the specific width W is too large, the effective area of the wafer will also be removed, which may cause the wafer to be unusable. In the embodiments of the present application, the specific width W can be controlled between 1 mm and 5 mm.

[0055] Continue to refer to Figure 8 , the wafer bonding mark of the embodiment of the present application is located on the non-bonding surface on the opposite side of the recess 300. On the one hand, the wafer bonding mark located on the non-bonding surface can avoid damage to the bonding surface during the production of the main scribe line and the sub-scribe line; on the other hand, the wafer bonding mark is located on the opposite side of the recess 300, without additionally occupying the effective area of the wafer to be bonded. And due to the existence of the recess 300, the wafer below the wafer bonding mark becomes thinner, increasing the light penetration ability, which is more conducive to the recognition and alignment during bonding.

[0056] The sum of the depth D1 of the main scribe line 101 and the depth D3 of the recess 300 needs to be less than the thickness T of the wafer to be bonded, and the sum of the depth D2 of the sub-scribe line 201 and the depth D3 of the recess 300 also needs to be less than the thickness T of the wafer to be bonded. This is because when D1+D3≥T or D2+D3≥T, it means that the scribe line penetrates the wafer. When other process operations are performed on the wafer, such as coating, cleaning, or depositing a thin film, the reagents or materials used will penetrate through the scribe line that penetrates the wafer to the back of the wafer, thereby contaminating the back of the wafer and even contaminating the equipment where the wafer is located. In the embodiment of the present application, the depth D3 of the recess 300 is between 100 μm and 200 μm, the depth D1 of the main scribe line and the depth D2 of the sub-scribe line are 0.003 μm - 100 μm, and the thickness T of the wafer to be bonded does not exceed 800 μm.

[0057] Refer to Figure 9 , in some embodiments, the wafer to be bonded includes a first wafer W1 and a second wafer W2, wherein the bonding surface of the first wafer W1 or the second wafer W2 includes a trimmed recess 300. Specifically, which wafer needs to be trimmed depends on which wafer needs to be thinned subsequently. In the embodiment of the present application, only the second wafer W2 is trimmed, so only the second wafer W2 has the recess 300.

[0058] Refer to Figure 10, the non-bonding surfaces on the opposite sides of the recessed portion 300 include at least a pair of main identification scales and sub-identification scales. For example, Figure a shows a schematic structural diagram when there is only one pair of main identification scales and sub-identification scales. The main identification scales and sub-identification scales can be located at any orientation of the wafer to be bonded, as long as the main identification scales and sub-identification scales are located on the opposite sides of the recessed portion 300, so as to remove the main identification scales and sub-identification scales in subsequent processes. Figure b shows a schematic structural diagram including two pairs of main identification scales and sub-identification scales located opposite to each other. In other embodiments, the two pairs of main identification scales and sub-identification scales can also be located adjacent to each other, and it is also necessary to ensure that the two pairs of main identification scales and sub-identification scales are located on the opposite sides of the recessed portion 300. Figure c shows a schematic structural diagram when there are three pairs of main identification scales and sub-identification scales, and Figure d shows a schematic structural diagram when there are four pairs of main identification scales and sub-identification scales. The more pairs of main identification scales and sub-identification scales there are, the higher the bonding accuracy and the more accurate the obtained offset data. Among them, in Figure d, there is a pair of main identification scales and sub-identification scales in four different directions. Therefore, its bonding accuracy is the highest and the obtained offset data is also the most accurate. The following will be described by taking four pairs of main identification scales and sub-identification scales as an example. In addition, there is no requirement for the relative positions of the main identification scales and the sub-identification scales, as long as the starting points of the main identification scales and the sub-identification scales are aligned.

[0059] Reference Figure 11 , at least one notch 400 is further formed on the edge of the wafer to be bonded, and the notch 400 penetrates the wafer to be bonded in the thickness direction. For example, Figures a' to d' respectively show schematic structural diagrams with one notch, two notches, three notches, and four notches, and each figure only shows one possible situation with the corresponding number of notches. In other embodiments, different structures can also be obtained by adjusting the positions of the wafer bonding identification and the notch. The notch 400 plays a role of pre-alignment during bonding. The notch 400 can assist in judging whether the general direction of the wafer to be bonded is aligned, and then precise alignment is performed through the wafer bonding identification. The size and shape of the notch 400 are not limited.

[0060] Correspondingly, the embodiment of the present application also provides a method for forming the wafer bonding identification, including:

[0061] Step S1: Provide a wafer to be bonded, and the wafer to be bonded includes a bonding surface and a non-bonding surface;

[0062] Step S2: Etch the bonding surface or the non-bonding surface to form main identification scales and sub-identification scales.

[0063] In some embodiments, before performing step S2, step S20: trimming treatment is also required.

[0064] Refer to Figure 8, the trimming process includes etching a part of the wafer to be bonded on the bonding surface side to form a recessed portion 300, where the recessed portion 300 is a region extending a specific width from the edge of the wafer to be bonded towards the geometric center of the wafer to be bonded. The region with the extended specific width only includes the invalid area of the wafer to be bonded and does not include the valid area. The specific width is 1 mm - 5 mm. The depth of the recessed portion 300 is 100 μm - 200 μm, so that the sum of the depths of the main scribing line and the secondary scribing line formed in the subsequent process and the depth of the recessed portion does not exceed the thickness of the wafer to be bonded. The trimming process can be achieved through conventional processes, such as physical polishing. The trimming process can not only avoid damage defects to the wafer caused by the thinning process, but also reduce the thickness of the wafer to be bonded, increase the light penetration ability, and is more conducive to recognition and alignment during bonding.

[0065] Not all wafers participating in the bonding operation need to be trimmed. Only the wafers that need to be thinned in the subsequent process are trimmed before the bonding operation. For example, the wafer to be bonded includes a first wafer and a second wafer, and the first wafer or the second wafer is trimmed.

[0066] In the embodiment of the present application, a main identification scale and a secondary identification scale are formed on the non-bonding surface to avoid damage to the bonding surface and affect the bonding effect. Further, a part of the wafer to be bonded on the opposite side of the recessed portion 300 is etched to form at least a pair of main identification scales and secondary identification scales. The method for forming the main identification scale and the secondary identification scale includes at least one of laser etching, cutting, and photolithography. In the embodiment of the present application, the main scribing line and the secondary scribing line are substantially grooves formed by etching. The reason for calling them the main "scribing line" and the secondary "scribing line" is that the grooves formed by etching in the embodiment of the present application are thin enough to be used as scale lines during measurement. For example, when using the photolithography process, a photoresist can be first formed on the non-bonding surface of the wafer to be bonded; then it is exposed and developed to form the patterns of the main identification scale and the secondary identification scale on the non-bonding surface; finally, the patterns of the main identification scale and the secondary identification scale are transferred to the non-bonding surface.

[0067] Combined Figure 4 and Figure 5 , the formed main identification scale 100 includes a plurality of main scribing lines 101 evenly distributed and having a first interval size d1. The formed secondary identification scale 200, aligned with the starting point of the main identification scale 100 and distributed parallel to the main identification scale 100, includes a plurality of secondary scribing lines 201 evenly distributed and having a second interval size d2. The first interval size d1 is greater than the second interval size d2, and there is a specific difference d1 - d2. In order to balance the measurement accuracy and the readability, the specific difference d1 - d2 can be 10 nm - 100 nm.

[0068] ReferenceFigure 8 , the main grooves, secondary grooves and recesses formed by etching need to meet the following conditions: the sum of the depth D1 of the main groove 101 and the depth D3 of the recess 300 needs to be less than the thickness T of the wafer to be bonded, and the sum of the depth D2 of the formed secondary groove 201 and the depth D3 of the recess 300 also needs to be less than the thickness T of the wafer to be bonded. In the embodiments of the present application, the depth D1 of the main groove 101 and the depth D2 of the secondary groove 102 are 0.003 μm - 100 μm, and the thickness T of the wafer to be bonded does not exceed 800 μm.

[0069] Before or after forming the main groove and the secondary groove, etch the edge of the wafer to be bonded to form at least one notch that penetrates the wafer to be bonded in the thickness direction. The notch can be formed by a dry etching process or a wet etching process. In other embodiments, the notch may not be formed.

[0070] The embodiments of the present application also provide a method for wafer bonding, including:

[0071] Step S1: Provide a first wafer and a second wafer to be bonded;

[0072] Step S2: Form the above-mentioned wafer bonding marks on the non-bonding surfaces of the first wafer and the second wafer;

[0073] Step S3: Align the wafer bonding marks of the first wafer and the second wafer to complete the bonding operation.

[0074] After completing the bonding operation, the following processes may also be included:

[0075] Step S4: Select the wafer bonding mark of the first wafer or the second wafer as the reference mark, and the wafer bonding marks of the remaining wafers as the reading marks;

[0076] Step S5: Read the offset data of the reading mark relative to the reference mark to obtain the offset data of the bonding operation.

[0077] The method for reading the offset data may include: obtaining that the leftmost main groove (i.e., the zero scale line) of the reading mark is aligned with the nth main groove of the reference mark, or the leftmost main groove (i.e., the zero scale line) of the reading mark is located between adjacent main grooves of the reference mark, and the left main groove of the adjacent main grooves is the nth main groove, where n is a natural number, and the result of n × the first interval size is used as the main scale reading of the reading mark; obtaining that the secondary groove of the reading mark is closest to the mth main groove of the reference mark, m is a natural number, and the result of m × (the first interval size - the second interval size) is used as the secondary scale reading of the reading mark; adding the main scale reading and the secondary scale reading to obtain the offset data.

[0078] After reading the offset data, it further includes: determining that the offset data of the bonding operation is within a reasonable range; continuing to etch the bottom of the recess until the main engraved line and the secondary engraved line are completely etched.

[0079] By forming the wafer bonding identifier of the embodiment of the present application on the bonding surface or the non-bonding surface of the wafer to be bonded, it can not only play a role in aligning the wafers during bonding, but also directly read the bonding offset data after bonding without additional measurement steps. Further, the wafer bonding identifier is located in the trimming area of the non-bonding surface of the wafer to be bonded, which will not damage the bonding surface and does not occupy the effective area of the wafer to be bonded.

[0080] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.

[0081] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0082] Similarly, it should be understood that when an element such as a layer, a region, or a substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprises", "comprising", "includes", or "including", when used in this application document, specify the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0083] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

Claims

1. A wafer bonding identification, characterized in that, The wafers to be bonded include a first wafer and a second wafer. The bonding surface of the first wafer or the second wafer includes a trimmed recess. The recess is an annular region extending from the edge of the wafers to be bonded towards the geometric center of the wafers to be bonded with a specific width. The wafer bonding mark is located on the non-bonding surface on the opposite side of the recess and includes: A main mark scale, including a number of main engraved lines evenly distributed with a first interval dimension; A secondary mark scale, aligned with the starting point of the main mark scale and distributed parallel to the main mark scale, including a number of secondary engraved lines evenly distributed with a second interval dimension; The first interval dimension is greater than the second interval dimension and has a specific difference.

2. The wafer bonding identification according to claim 1, wherein The specific difference is 10 nm to 100 nm.

3. The wafer bonding identification according to claim 1, characterized in that The specific width is 1 mm - 5 mm.

4. The wafer bonding identification according to claim 1, wherein The non-bonding surface on the opposite side of the recess includes at least a pair of the main mark scale and the secondary mark scale.

5. The wafer bonding identification according to claim 4, wherein The sum of the depths of the main engraved lines and the secondary engraved lines and the depth of the recess is less than the thickness of the wafers to be bonded.

6. The wafer bonding identification according to claim 5, characterized in that, The depth of the recess is 100 μm - 200 μm, the depths of the main engraved lines and the secondary engraved lines are 0.003 μm - 100 μm, and the thickness of the wafers to be bonded does not exceed 800 μm.

7. The wafer bonding identification according to claim 1, wherein At least one notch is further formed at the edge of the wafers to be bonded, and the notch penetrates the wafers to be bonded in the thickness direction.

8. A method for forming a wafer bonding identification, characterized in that, Including: Providing wafers to be bonded, which include a bonding surface and a non-bonding surface, and the wafers to be bonded include a first wafer and a second wafer; Performing trimming on the first wafer or the second wafer. The trimming includes etching a part of the wafers to be bonded on the bonding surface side to form a recess, where the recess is an annular region extending from the edge of the wafers to be bonded towards the geometric center of the wafers to be bonded with a specific width; Etching the non-bonding surface on the opposite side of the recess to form the wafer bonding mark including the main mark scale and the secondary mark scale; wherein, the main mark scale includes a number of main engraved lines evenly distributed with a first interval dimension; the secondary mark scale, aligned with the starting point of the main mark scale and distributed parallel to the main mark scale, includes a number of secondary engraved lines evenly distributed with a second interval dimension; the first interval dimension is greater than the second interval dimension and has a specific difference.

9. The method for forming a wafer bonding identification according to claim 8, wherein The specific difference is 10 nm to 100 nm.

10. The method for forming a wafer bonding identifier according to claim 8, wherein The specific width is 1 mm - 5 mm.

11. The method for forming a wafer bonding identification according to claim 8, wherein, Etching a part of the wafers to be bonded on the opposite side of the recess to form at least a pair of the main mark scale and the secondary mark scale.

12. The method for forming a wafer bonding identification according to claim 11, wherein, The method for forming the main mark scale and the secondary mark scale includes at least one of laser etching, cutting, and photolithography.

13. The method for forming a wafer bonding mark according to claim 8, wherein Before or after forming the main engraved lines and the secondary engraved lines, etching the edge of the wafers to be bonded to form at least one notch, and the notch penetrates the wafers to be bonded in the thickness direction.

14. A wafer bonding method, characterized in that, Including: Providing a first wafer and a second wafer to be bonded; Forming the wafer bonding mark according to any one of claims 1 to 7 on the non-bonding surfaces of the first wafer and the second wafer; Aligning the wafer bonding marks of the first wafer and the second wafer to complete the bonding operation.

15. The wafer bonding method according to claim 14, wherein After completing the bonding operation, further including: Select the wafer bonding identification of the first wafer or the second wafer as the reference identification, and the wafer bonding identifications of the remaining wafers as the reading identifications; Read the offset data of the reading identifications relative to the reference identification to obtain the offset data of the bonding operation.

16. The wafer bonding method according to claim 15, wherein, The method for reading the offset data includes: Obtain that the leftmost main scale line of the reading identification is aligned with the nth main scale line of the reference identification, or the leftmost main scale line of the reading identification is located between adjacent main scale lines of the reference identification, and the left main scale line of the adjacent main scale lines is the nth main scale line, where n is a natural number, and use the result of n×the first interval size as the main scale reading of the reading identification; Obtain that the secondary scale line of the reading identification is closest to the mth main scale line of the reference identification, m is a natural number, and use the result of m×(the first interval size - the second interval size) as the secondary scale reading of the reading identification; Add the main scale reading and the secondary scale reading to obtain the offset data.

17. The wafer bonding method according to claim 16, wherein After obtaining the offset data, it further includes: Determine that the offset data of the bonding operation is within a reasonable range; Continue to etch the bottom of the recess until the main scale line and the secondary scale line are etched completely.

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