Three-dimensional memory and preparation method and storage system thereof

Abstract

The present disclosure provides a three-dimensional memory and a preparation method and a storage system thereof, which relate to the field of semiconductor chips and are intended to reduce the misalignment error between array devices and peripheral devices and reduce the process difficulty. The preparation method of the three-dimensional memory includes: forming a stacked structure on the first side of the substrate; forming a partition groove that penetrates the stacked structure and extends into the substrate, and filling the partition groove with a sacrificial material; forming a plurality of conductive structures on the side of the stacked structure away from the substrate; providing a peripheral circuit, bonding the peripheral circuit to at least one of the plurality of conductive structures; removing at least part of the substrate to expose the sacrificial material; and removing the sacrificial material, and replacing the sacrificial layer with a first conductive layer through the partition groove. The preparation method provided by the present disclosure first bonds the peripheral circuit to the conductive structure, and then removes the sacrificial material to make the first conductive layer, thereby reducing the misalignment error between the peripheral circuit and the array device containing the conductive structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and a preparation method and a storage system thereof. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] In the process of forming 3D NAND, it is necessary to bond the array device on one substrate to the peripheral device on another substrate. However, misalignment errors are prone to occur between the bonded array device and the peripheral device. Summary of the invention

[0005] Embodiments of the present disclosure provide a three-dimensional memory, a preparation method thereof, and a storage system.

[0006] The embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a method for preparing a three-dimensional memory is provided, the method comprising: forming a stacked structure on a first side of a substrate, the stacked structure comprising alternating dielectric layers and sacrificial layers; forming a partition groove penetrating the stacked structure and extending into the substrate, and filling the partition groove with a sacrificial material; forming a plurality of conductive structures on a side of the stacked structure away from the substrate, at least some of the plurality of conductive structures extending into the stacked structure; providing a peripheral circuit, and bonding the peripheral circuit to at least one of the plurality of conductive structures; removing at least a portion of the substrate to expose the sacrificial material in the partition groove; removing the sacrificial material in the partition groove, and replacing the sacrificial layer with a first conductive layer through the partition groove, so that at least some of the plurality of conductive structures are electrically connected to the first conductive layer.

[0008] In some embodiments, the substrate includes a first substrate layer and a second substrate layer sequentially adjacent to the stacked structure; the second substrate layer has a different etching selectivity from the first substrate layer, and the partition groove extends into the first substrate layer; the step of removing at least a portion of the substrate to expose the sacrificial material in the gate partition groove includes: etching the first substrate layer to the second substrate layer to expose the sacrificial material in the gate partition groove.

[0009] In some embodiments, after the step of replacing the sacrificial layer with the first conductive layer, the step further includes: sequentially forming a first protective layer in the groove along a direction away from the inner wall of the groove, forming a first conductive portion on a side of the first insulating layer away from the first protective layer, and forming a second protective layer covering an end of the first conductive portion away from the peripheral circuit; removing the second substrate layer to expose the second protective layer; and forming a source layer covering the second protective layer.

[0010] In some embodiments, after the step of replacing the sacrificial layer with the first conductive layer, the step further includes: forming a first protective layer and a first insulating layer in the groove in sequence along a direction away from the inner wall of the groove, forming a first conductive portion on a side of the first insulating layer away from the first protective layer, and forming a second protective layer covering an end of the first conductive portion away from the peripheral circuit; removing the second substrate layer, the second protective layer, a portion of the first insulating layer and a portion of the first protective layer to expose the end of the first conductive portion away from the peripheral circuit; and forming a source layer covering an end of the first conductive portion away from the peripheral circuit.

[0011] In some embodiments, the substrate further comprises: a third substrate layer; the third substrate layer is located on a side of the second substrate layer away from the first substrate layer; the third substrate layer and the second substrate layer have different etching selectivities. After removing the second substrate layer, the step further comprises: removing at least a portion of the third substrate layer.

[0012] In some embodiments, the stacked structure includes a step area and a storage area; before the step of forming a partition groove that penetrates the stacked structure and extends into the substrate, it also includes: forming a channel hole that penetrates the stacked structure and extends into the third substrate layer in the storage area, and sequentially forming a storage function layer and a channel layer in the channel hole along a direction away from the inner wall of the channel hole to form a channel structure; forming a virtual channel hole that penetrates the stacked structure and extends into the first substrate layer in the step area, and filling the virtual channel hole with a dielectric material to form a virtual channel structure; wherein some of the multiple conductive structures are electrically connected to the channel layer.

[0013] In some embodiments, before the step of forming the stacked structure, it also includes: forming a first etch stop layer and a second etch stop layer in sequence on a side of the third substrate layer close to the stacked structure and in a direction away from the third substrate layer, the first etch stop layer and the second etch stop layer having different etching selectivities; the step of removing the second substrate layer and at least a portion of the third substrate layer includes: etching the second substrate layer and at least a portion of the third substrate layer to the first etch stop layer to expose a portion of the storage function layer extending into the third substrate layer; etching the first etch stop layer and the exposed portion of the storage function layer to the second etch stop layer to expose an end of the channel layer away from the peripheral circuit; wherein, after the source layer is formed, the source layer is electrically connected to an end of the channel layer away from the peripheral circuit.

[0014] In some embodiments, before the step of forming the source layer, the step further includes: performing ion doping on at least the exposed portion of the channel layer, wherein the type of ion doping is the same as the doping type of the source layer.

[0015] In some embodiments, before the step of filling the sacrificial material in the partition, it also includes: forming a third protective layer on at least a portion of the inner wall of the partition; wherein the third protective layer at least covers the surface of the third substrate layer exposed in the partition, the surface of the first substrate layer exposed in the partition, and the surface of the second etch stop layer exposed in the partition.

[0016] In some embodiments, after etching the second substrate layer and before etching at least a portion of the third substrate layer, it also includes: setting a mask plate covering the virtual channel structure to retain the portion of the third substrate layer covering the virtual channel structure after etching a portion of the third substrate layer.

[0017] In some embodiments, after the step of forming the source layer, it also includes: forming a dielectric layer on a side of the source layer away from the stacked structure; forming a second conductive portion in the dielectric layer, the second conductive portion being electrically connected to the source layer; forming a second conductive layer on a side of the dielectric layer away from the stacked structure, the second conductive layer being electrically connected to the second conductive portion.

[0018] In some embodiments, the multiple conductive structures also include a first conductive structure and a second conductive structure; the first conductive structure is electrically connected to the source layer, and the second conductive structure is electrically connected to the peripheral circuit; after etching the first substrate layer, the second substrate layer, the third substrate layer and the second etching stop layer, the ends of the first conductive structure and the second conductive structure are also exposed; the dielectric layer separates the source layer from the first conductive structure and the second conductive structure.

[0019] In some embodiments, during the process of forming the second conductive portion, a third conductive portion and a fourth conductive portion are also formed in the dielectric layer, the third conductive portion is electrically connected to the first conductive structure, and the fourth conductive portion is electrically connected to the peripheral circuit; the second conductive layer is also electrically connected to the third conductive portion.

[0020] In some embodiments, during the process of forming the second conductive layer, a fifth conductive portion is further formed on a side of the dielectric layer away from the stacked structure, and the fifth conductive portion is electrically connected to the fourth conductive portion.

[0021] On the other hand, a three-dimensional memory is provided, which includes a semiconductor layer, a stacked structure, a plurality of conductive structures, a peripheral circuit, and a separation structure.

[0022] In some embodiments, the stacked structure is located on one side of the semiconductor layer; the stacked structure includes dielectric layers and conductive layers alternately arranged. The multiple conductive structures are located on a side of the stacked structure away from the semiconductor layer, and at least some of the multiple conductive structures extend into the stacked structure. The peripheral circuit is bonded to at least one of the multiple conductive structures. The separation structure penetrates the stacked structure and extends into the semiconductor layer; the width of the separation structure at one end close to the semiconductor layer is smaller than the width of the separation structure at one end away from the semiconductor layer.

[0023] In some embodiments, the partition structure has an air gap therein.

[0024] In some embodiments, the air gap extends in a direction perpendicular to the semiconductor layer; and a width of a region of the air gap close to the semiconductor layer is smaller than a width of a region of the air gap far from the semiconductor layer.

[0025] On the other hand, a storage system is provided. The storage system includes a controller and the above three-dimensional memory, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory.

[0026] The method for preparing a three-dimensional memory provided by the above-mentioned embodiment of the present disclosure is that before removing the sacrificial material in the partition groove and replacing the sacrificial layer in the stacked structure with the first conductive layer, the peripheral circuit is first bonded to the multiple conductive structures on the substrate. Therefore, it can play a good supporting role for the multiple conductive structures on the substrate before bonding, so that the multiple conductive structures are not easily misaligned when bonding with the peripheral circuit, that is, the misalignment error when the peripheral circuit is bonded with the multiple conductive structures is improved. It can be understood that the multiple conductive structures here are part of the array device on the substrate, therefore, the misalignment error between the peripheral circuit and the array device formed later is improved.

[0027] On this basis, the subsequent step of removing the sacrificial material in the groove and replacing the sacrificial layer in the stacked structure with the first conductive layer is also helpful to reduce the stress generated before bonding, thereby improving the stability and reliability of the formed three-dimensional memory.

[0028] In addition, when forming the partition groove, it is only necessary to ensure that the lower end of the partition groove extends into a part of the substrate, and the sacrificial material in the partition groove can be exposed by removing at least a part of the substrate, so as to facilitate the subsequent use of the partition groove to replace the sacrificial layer in the stacked structure with the first conductive layer. It can be understood that here, the depths of the multiple partition grooves extending into the substrate can be consistent or inconsistent, and the partition grooves need to be opened from the back side and the sacrificial material in the partition grooves need to be removed later. Therefore, the preparation method of the three-dimensional memory provided by the embodiment of the present disclosure does not require high etching accuracy of the partition groove, which also helps to reduce process difficulty and save process costs.

[0029] The beneficial effects that can be achieved by the three-dimensional memory and the storage system provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the method for preparing the three-dimensional memory described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1A to Figure 1G is a flow chart of a method for preparing a three-dimensional memory according to some embodiments;

[0032] Figure 2A to Figure 2Q It is a longitudinal cross-sectional structural diagram corresponding to each step in the method for preparing a three-dimensional memory according to some embodiments;

[0033] Figure 3A is a top view of a three-dimensional memory according to some embodiments;

[0034] Figure 3B is a top view of another three-dimensional memory according to some embodiments;

[0035] Figure 4A to Figure 4D is a longitudinal cross-sectional structural diagram of a three-dimensional memory according to some embodiments;

[0036] Figure 5 is a block diagram of a storage system according to some embodiments;

[0037] Figure 6 is a block diagram of another storage system according to some embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0039] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0040] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0041] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0042] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0043] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0044] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate.

[0045] Figure 1A to Figure 1G A flow chart of a method for preparing a three-dimensional memory provided in some embodiments of the present disclosure; Figure 2A to Figure 2Q 1 is a longitudinal cross-sectional structural diagram corresponding to each step in the method for preparing a three-dimensional memory according to some embodiments. It should be understood that: Figure 1A to Figure 1G The steps shown are not exclusive, and other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different steps. Figure 1A to Figure 1G The following is performed in the order shown. Figure 1A to Figure 1G ,as well as Figure 2A to Figure 2Q The preparation methods of the three-dimensional memory in some embodiments are described.

[0046] Some embodiments of the present disclosure provide a method for preparing a three-dimensional memory, see Figure 1A , Figure 1A It is a flow chart of a method for preparing a three-dimensional memory, and the method includes steps S1 to S6.

[0047] S1 . Form a stacked structure 2 on a first side of a substrate 11 . The stacked structure 2 includes dielectric layers 21 and sacrificial layers 22 that are alternately arranged.

[0048] In step S1, see 2A, Figure 2A This is a longitudinal cross-sectional structural diagram of a three-dimensional memory after a stacked structure 2 is formed on a first side of a substrate 11. The stacked structure 2 is formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0049] In some examples, the thicknesses of the multiple dielectric layers 21 in the stacked structure 2 may be the same or different; the thicknesses of the multiple sacrificial layers 22 may be the same or different; and they may be specifically set according to process requirements. In addition, in the preparation process of the stacked structure 2, different numbers of stacked layers correspond to different stacking heights. For example, the number of stacked layers of the stacked structure 2 may be 8 layers, 32 layers, 64 layers, 128 layers, etc. The more layers of the stacked structure 2, the higher the integration, that is, the more storage units are subsequently formed. The number of stacked layers and the stacking height of the stacked structure 2 may be specifically designed according to actual storage requirements, and the present disclosure does not impose specific restrictions on this.

[0050] In some examples, the dielectric layer 21 and the sacrificial layer 22 have different etching selectivities, the sacrificial layer 22 can be removed in a subsequent process to form a sacrificial gap, and a conductive material can be filled in the sacrificial gap (i.e., the space where the sacrificial layer 22 is located) to form a first conductive layer, i.e., a word line. Exemplarily, the material of the dielectric layer 21 includes silicon oxide, and the material of the sacrificial layer 22 includes silicon nitride. The step of forming the first conductive layer will be described in detail in some later embodiments.

[0051] It can be understood that although some embodiments of the present disclosure adopt an implementation method in which the sacrificial layer 22 is subsequently replaced by a filled conductive material to form the first conductive layer 23, the implementation method of forming the first conductive layer 23 in the present disclosure is not limited to this. For example, it can also be achieved by directly forming overlapping dielectric layers 21 and first conductive layers 23.

[0052] In some embodiments, see Figure 2A, the substrate 11 includes a first substrate layer 11, a second substrate layer 12, and a third substrate layer 13, which are sequentially close to the stacked structure 2. That is, the third substrate layer 13 is close to the stacked structure 2, the second substrate layer 12 is located on a side of the third substrate layer 13 away from the stacked structure 2, and the first substrate layer 11 is located on a side of the second substrate layer away from the third substrate layer 13. The second substrate layer 12 has a different etching selectivity with the first substrate layer 11, and the second substrate layer 12 has a different etching selectivity with the third substrate layer 13.

[0053] Exemplarily, the material of the second substrate layer 12 is silicon oxide, and the materials of the first substrate layer 11 and the third substrate layer 13 are both polysilicon.

[0054] It should be noted that the materials of the second substrate layer 12 are different from those of the first substrate layer 11 and the third substrate layer 13, so that the second substrate layer 12 and the first substrate layer 11 and the third substrate layer 13 have different etching selectivities, thereby helping to control the process uniformity during the removal of the first substrate layer 11.

[0055] In some examples, the second substrate layer 12 and the third substrate layer 13 can be formed on the side of the first substrate layer 11 close to the stacked structure 2 using a thin film deposition process such as CVD, PVD or ALD, and are formed sequentially on the first substrate layer 11 along the direction in which the first substrate layer 11 is close to the stacked structure 2.

[0056] In some embodiments, see Figure 1B , Figure 1B The flowchart is a preparation method for forming a channel structure 3 and a dummy channel structure 3' in a stacked structure 2. The stacked structure 2 further includes a storage area A and a step area B, and the preparation method further includes steps S01-S02.

[0057] S01. A channel hole 31 is formed in the storage area A, penetrating the stacked structure 2 and extending into the third substrate layer 13, and a storage function layer 32 and a channel layer 33 are sequentially formed in the channel hole 31 in a direction away from the inner wall of the channel hole 31 to form a channel structure 3.

[0058] See also Figure 2B , Figure 2B This is a longitudinal cross-sectional structural diagram of the three-dimensional memory after forming a channel hole 31 in the stacked structure 2. In step S01, the channel hole 31 can be formed in the stacked structure 2 using, for example, a dry / wet etching process. The channel hole 31 can be perpendicular to the substrate 1 and extend in a direction close to the substrate 1 to extend into the third substrate layer 13.

[0059] See also Figure 2C , Figure 2C3 is a longitudinal cross-sectional structural diagram of a three-dimensional memory after forming a channel structure 3 in a stacked structure 2. A thin film deposition process such as CVD, PVD or ALD can be used to sequentially deposit a charge blocking layer 321, a charge trapping layer 322, a tunneling layer 323 and a channel layer 33 on the inner wall (including the bottom wall and the side wall) of the channel hole 31 in a direction away from the inner wall of the channel hole 31. Among them, the charge blocking layer 321, the charge trapping layer 322 and the tunneling layer 323 constitute a storage function layer 32. Exemplarily, the material of the charge blocking layer 321 is silicon oxide, the material of the charge trapping layer 322 is silicon nitride, and the material of the tunneling layer 323 is silicon oxide to form an "ONO" structure.

[0060] In some examples, the material of the channel layer 33 is polysilicon.

[0061] In the above steps, a thin film deposition process such as CVD, PVD or ALD may be used to fill a dielectric material, such as silicon oxide, in the channel hole 31 formed with the storage function layer 32 and the channel layer 33 to form a channel structure 3 having the channel layer 33, the storage function layer 32 and the filled dielectric material. Exemplarily, one or more air gaps may be formed during the filling process by controlling the channel filling process to relieve structural stress.

[0062] When the materials of the charge blocking layer 321, the charge trapping layer 322, the tunneling layer 323 and the channel layer 33 are silicon oxide, silicon nitride, silicon oxide and polysilicon respectively, and the filled dielectric material is silicon oxide, the formed channel structure 33 can be called an "ONOPO" structure.

[0063] For some examples, see Figure 2B and Figure 2C Before forming the storage function layer 32, an oxide layer 34 and a high dielectric constant dielectric layer 35 may be sequentially formed on the inner wall of the channel hole 31 in a direction away from the inner wall of the channel hole 31. Compared with the scheme of setting the high dielectric constant dielectric layer 35 in the sacrificial gap formed after removing the sacrificial layer 22, the scheme of forming the high dielectric constant dielectric layer 35 in the channel hole 31 can reduce the thickness of the total stacked structure 2, which is beneficial to reducing the load of etching the channel hole 31, etching the gate line gap and etching the contact hole. The scheme of forming the high dielectric constant dielectric layer 35 in the channel hole 31 can also expand the process window for etching the channel hole 31 and the process window for removing the back storage stack (such as ONO), and the oxide layer 34 plays a role in strengthening adhesion and isolation protection.

[0064] In some examples, the oxide layer 34 and the high dielectric constant dielectric layer 35 are formed by thin film deposition processes such as CVD, PVD or ALD. The dielectric constant of the high dielectric constant dielectric layer 35 is higher than the dielectric constant of silicon oxide, for example, the dielectric constant value k>4.2, and the material of the high dielectric constant dielectric layer 35 includes but is not limited to aluminum oxide. The material of the oxide layer 34 is but is not limited to silicon oxide.

[0065] It should be noted that in this example, Figure 2B and Figure 2C Two channel structures 3 are used as an example for illustration. In actual manufacturing, the number of channel structures 3 can be greater than two, that is, multiple channel structures 3 that penetrate the stacked structure 2 and extend into the third substrate layer 13 can be formed. The number and arrangement of the channel structures 3 can be prepared according to the actual storage requirements of the memory. After the above process, the area corresponding to the channel structure 3 formed on the substrate 1 and penetrating the stacked structure 2 can be called the storage area A of the array device (for example Figure 2D The storage area A shown in the figure can be used to implement the storage function of the three-dimensional memory.

[0066] See also Figure 2D , Figure 2D The longitudinal cross-sectional structure diagram of the three-dimensional memory after forming a step-like structure, a barrier layer BB covering the step-like structure, and an insulating layer 4 covering the barrier layer BB on the stacked structure 2. In some embodiments, the step-like structure is formed at the edge of the stacked structure 2, and the step-like structure can be formed by performing multiple "trim-etch" cycle processes on multiple dielectric layers 21 and multiple sacrificial layers 22 of the stacked structure 2.

[0067] On this basis, a barrier layer BB and an insulating layer 4 away from the substrate 1 can be sequentially formed on the step-like structure. The insulating cover layer 4 can be formed by forming a dielectric material on the step-like structure and covering the step-like structure. Exemplarily, the insulating layer 4 can extend toward the edge direction of the stacked structure 2 (for example, the direction close to the peripheral region C).

[0068] The method for forming the insulating layer 4 may be a thin film deposition process such as CVD, PVD or ALD. The material of the insulating layer 4 may be the same material as the dielectric layer 21, such as silicon oxide. Exemplarily, the surface of the insulating layer 4 away from the substrate 1 may be planarized by, for example, a chemical mechanical polishing (CMP) process.

[0069] After the above-mentioned process, the area corresponding to the step-shaped structure formed by the stacked structure 2 on the substrate 1 can be called the step area B of the array device, and the step area B can be the electrical connection area of ​​the word line (the first conductive layer 23). The area corresponding to the insulating layer 4 on the substrate 1 can be called the peripheral area C, and the peripheral area C can be used to form a peripheral contact structure (exemplarily, the fourth conductive part A3 hereinafter) and a source contact (exemplarily, the second conductive part A1 and / or the third conductive part A2 hereinafter) structure electrically connected to the peripheral circuit layer in the subsequent process. The steps of forming the fourth conductive part A3, the second conductive part A1 and / or the third conductive part A2 will be described in detail in some later embodiments.

[0070] S02 . Form a virtual channel hole in the step region B that penetrates the stacked structure 2 and extends into the first substrate layer 11 , and fill the virtual channel hole with a dielectric material to form a virtual channel structure 3 ′.

[0071] In this step, see Continue Figure 2D , Figure 2D The longitudinal cross-sectional structure of the three-dimensional memory after forming a virtual channel structure 3' in the stacked structure 2 is shown. It should be noted that the number of the virtual channel structures 3' can be multiple, and the present disclosure does not impose any specific restrictions on the number of virtual channel structures 3'. The depths of the multiple virtual channel structures 3' extending into the first substrate layer 11 can be the same or different. Figure 2D ,exist Figure 2D In the figure, it is illustrated by taking the example that the depths of the multiple dummy channel structures 3 ′ extending into the substrate 1 are the same.

[0072] In the step of forming the virtual channel structure 3', a thin film deposition process such as CVD, PVD or ALD can be used to fill the virtual channel hole with a dielectric material, such as silicon oxide, to form the virtual channel structure 3'. Exemplarily, by controlling the filling process, one or more air gaps can be formed during the filling process to reduce structural stress. In the embodiment of the present disclosure, the virtual channel structure 3' can be used to provide mechanical support without forming a storage function layer and a channel layer with a storage function.

[0073] It should be noted that, in this article, only the formation of the virtual channel structure 3′ and the channel structure 3 is taken as an example (the channel structure 3 is formed before the step of forming the step-like structure at the edge of the stacked structure 2, and the virtual channel structure 3′ is formed after the step of forming the step-like structure at the edge of the stacked structure 2). In some other embodiments, the virtual channel structure 3′ and the channel structure 3 can also be selected to be formed under the same process.

[0074] S2 , forming a trench 51 penetrating the stacked structure 2 and extending into the substrate 1 , and filling the trench 51 with a sacrificial material 50 .

[0075] In step S2, continue to refer to Figure 2D , Figure 2D The longitudinal cross-sectional structure of the three-dimensional memory after the sacrificial material 50 is filled in the partition 51 is shown. The partition 51 can be formed in the stacked structure 2 by, for example, a dry / wet etching process, and the partition 51 can be perpendicular to the substrate 1 and extend toward the substrate 1 to extend into the first substrate layer 11.

[0076] In some examples, it is defined that: the end of the partition 51 away from the substrate 1 is the first end, and the end of the partition 51 extending into the substrate 1 is the second end. Figure 2D , the width H1 of the opening at the first end of the partition 51 is greater than the width H2 of the opening at the second end of the partition 51. For example, the width of the partition 51 may gradually decrease from the first end to the second end. In this example, since the opening at the first end of the partition 51 is larger, it is easier to fill the partition 51 with the sacrificial material 50, so that the three-dimensional memory after filling with the sacrificial material 50 can have better support stability.

[0077] Here, it is understandable that Figure 2D to Figure 2Q This is only a schematic diagram, and therefore the width change of the partition groove 51 is not shown.

[0078] In some examples, the sacrificial material 50 includes, but is not limited to, polysilicon. Moreover, the sacrificial material 50 may be filled in the trench 51 using a thin film deposition process such as CVD, PVD, or ALD.

[0079] For some examples, see Figure 2D , a capping layer T is formed on the side of the stacked structure 2 away from the substrate 1 by a thin film deposition process such as CVD, PVD or ALD. The capping layer T can cover the end surface of the end of the partition 51 away from the substrate 1 and the end surface of the end of the virtual channel structure 3' away from the substrate 1, thereby playing a sealing and protective role for the virtual channel structure 3', and preventing the subsequent etching process from damaging the structure of the virtual channel structure 3'. Exemplarily, the capping layer T can be made of the same material (such as silicon oxide) as the insulating layer 4 and the dielectric layer 21.

[0080] S3 . Form a plurality of conductive structures 6 on a side of the stacked structure 2 away from the substrate 1 ; at least a portion of the plurality of conductive structures 6 extends into the stacked structure 2 .

[0081] In step S3, refer to Figure 2E , Figure 2E The longitudinal cross-sectional structure diagram of the three-dimensional memory after forming a plurality of conductive structures 6. The conductive structures 6 can realize electrical connection between the channel layer 33, the word line and the peripheral area C and the peripheral circuit 7.

[0082] In some embodiments, the plurality of conductive structures 6 include a first conductive structure 61 and a second conductive structure 62. Exemplarily, the first conductive structure 61 is a source conductive structure, and the second conductive structure 62 is a peripheral conductive structure. The first conductive structure 61 is used to be electrically connected to the source layer 8 formed subsequently, and the second conductive structure 62 is used to be electrically connected to the peripheral circuit 7. The first conductive structure 61 and the second conductive structure 62 may penetrate the insulating layer 4 in the peripheral region C and extend into the substrate 1. Exemplarily, the first conductive structure 61 and the second conductive structure 62 may vertically penetrate the insulating layer 4 in the peripheral region C and extend into the substrate 1. The depth to which the first conductive structure 61 extends into the substrate 1 may be the same as or different from the depth to which the channel structure 3 extends into the substrate 1. Similarly, the depth to which the second conductive structure 62 extends into the substrate 1 may be the same as or different from the depth to which the channel structure 3 extends into the substrate 1. Among them, the number and arrangement of the first conductive structure 61 and the second conductive structure 62 may be prepared according to the actual requirements of the three-dimensional memory, for example, they may be designed according to the signal transmission requirements of the three-dimensional memory, and the various embodiments of the present disclosure are not limited to this.

[0083] While manufacturing the first conductive structure 61 and the second conductive structure 62, illustratively, as Figure 2E As shown, a word line conductive structure 63 and a channel conductive structure 64 can also be fabricated simultaneously. The word line conductive structure 63 is electrically connected to the first conductive layer 23 formed subsequently, and the channel conductive structure 64 is electrically connected to the channel structure 3. Multiple word line conductive structures 63 extend into the stacked structure 2 and are electrically connected to the first conductive layer 23 described below.

[0084] It can be understood that, when the above-mentioned capping layer T is provided, Figure 2E As shown, the first conductive structure 61 , the second conductive structure 62 , the word line conductive structure 63 and the channel conductive structure 64 may also penetrate the capping layer T.

[0085] S4. Provide a peripheral circuit 7 , and bond the peripheral circuit 7 to at least one conductive structure 6 among the plurality of conductive structures 6 .

[0086] In step S4, if Figure 2F As shown, Figure 2F The longitudinal cross-sectional structure diagram of the three-dimensional memory after the peripheral circuit 7 is bonded to at least one conductive structure 6 of the plurality of conductive structures 6. In some examples, a substrate 71 for carrying the peripheral circuit 7 is further disposed on a side of the peripheral circuit 7 away from the conductive structure 6.

[0087] In some examples, the bonding method may be a hybrid bonding method, for example, the two are bonded via a relatively flat surface to achieve electrical connection.

[0088] The peripheral circuit 7 may be electrically connected to the first conductive structure 61 , the second conductive structure 62 , the word line conductive structure 63 and the channel conductive structure 64 .

[0089] It should be noted that the above-mentioned multiple conductive structures are part of the array device on the substrate 1, and the substrate 1 and the array device constitute another semiconductor structure that can be bonded to the above-mentioned peripheral circuit 7. In some examples, the above-mentioned array device may include: a stacked structure, and the aforementioned channel structure 3, a virtual channel structure 3', a plurality of conductive structures 6, and a separation structure 5 (such as Fig.2I As shown). Exemplarily, the stacked structure may be formed by replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23.

[0090] The peripheral circuit 7 is configured to control and sense the array device. The peripheral circuit 7 may include, for example, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any active (or passive) components of the circuit (e.g., transistors, diodes, resistors, capacitors, etc.).

[0091] The peripheral circuit 7 may include a plurality of transistors, all or part of which are formed in the substrate 71 (e.g., below the surface of the substrate 71 away from the peripheral circuit 7) and / or directly on the substrate 71. Similarly, shallow trench isolation and doped regions (e.g., source and drain regions of the transistors) may also be formed in the substrate 71.

[0092] It should be noted that the peripheral circuit 7 may also include any other circuit compatible with the advanced logic process. Exemplarily, the peripheral circuit 7 includes a logic circuit (e.g., a processor and a programmable logic device (PLD)), and / or a storage circuit (e.g., a static random access memory (SRAM)).

[0093] S5 , removing at least a portion of the substrate 1 to expose the sacrificial material 50 in the trench 51 .

[0094] For some examples, see Figure 2G , Figure 2G The longitudinal cross-sectional structure diagram of the three-dimensional memory after removing the first substrate layer 11. Step S5 includes: etching the first substrate layer 11 to the second substrate layer 12 to expose the sacrificial material 50 in the partition groove 51. The first substrate layer 11 is removed by dry / wet etching process, and after removing part of the substrate 1, the sacrificial material 50 in the partition groove 51 and the end of the dummy channel structure 3' away from the peripheral circuit 7 are exposed.

[0095] S6 , removing the sacrificial material 50 in the partition groove 51 , and replacing the sacrificial layer 22 with the first conductive layer 23 through the partition groove 51 , so that at least part of the plurality of conductive structures 6 (eg the above-mentioned word line conductive structure 63 ) is electrically connected to the first conductive layer 23 .

[0096] In this step, refer to Figure 2H , Figure 2H The cross-sectional structure diagram of the three-dimensional memory after removing the sacrificial material 50 in the partition groove 51. The sacrificial material 50 in the partition groove 51 is removed by dry / wet etching process, and then the sacrificial layer is removed through the partition groove 51 as a channel of the etchant to form a sacrificial gap, for example, all the sacrificial layers 22 in the stacked junction are removed by a wet etching process to form a plurality of sacrificial gaps.

[0097] In the step of forming the first conductive layer 23 in the sacrificial gap, a thin film deposition process such as CVD, PVD or ALD may be used to form the first conductive layer 23 in the sacrificial gap. The material of the first conductive layer 23 may be any one or a combination of conductive materials selected from tungsten, tungsten, cobalt, copper, aluminum, doped crystalline silicon or silicide.

[0098] In some examples, before the step of forming the first conductive layer 23 in the sacrificial gap, a gate barrier layer may be formed on the inner walls of the gate gap and the plurality of sacrificial gaps by using a thin film deposition process such as CVD, PVD or ALD. On this basis, illustratively, an adhesion layer is formed on the surface of the gate barrier layer located in the sacrificial gap by using a thin film deposition process such as CVD, PVD or ALD.

[0099] The material of the gate barrier layer may be a high dielectric constant material, such as aluminum oxide. The material of the bonding layer may be, for example, tantalum nitride, titanium nitride, etc. The bonding layer helps to increase the adhesion between the gate barrier layer and the first conductive layer 23 formed in the subsequent process.

[0100] Exemplarily, after the step of forming the gate barrier layer and the adhesive layer, the adhesive layer, the gate barrier layer and the first conductive layer 23 near the partition 51 may be removed by, for example, a wet etching process to form a groove in the narrow groove, but the implementation of the present disclosure is not limited thereto. In other embodiments, the filled first conductive layer 23 may be aligned with the inner wall of the partition 51 without forming a groove. So far, the gate barrier layer, the adhesive layer and the first conductive layer 23 are sequentially deposited on the inner wall of the sacrificial gap.

[0101] In summary, the preparation method of the three-dimensional memory provided by some embodiments of the present disclosure is that before removing the sacrificial material 50 in the partition groove 51 and replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23, the peripheral circuit 7 is first bonded to the multiple conductive structures 6 on the substrate 1. Therefore, before bonding, the multiple conductive structures 6 on the substrate 1 can play a good supporting role, so that the multiple conductive structures 6 are not easily misaligned when bonding with the peripheral circuit 7, that is, the misalignment error when the peripheral circuit 7 is bonded with the multiple conductive structures 6 is improved. It can be understood that the multiple conductive structures 6 here are part of the array device on the substrate 1, and therefore, the misalignment error between the peripheral circuit 7 and the array device further formed later is improved.

[0102] On this basis, the subsequent step of removing the sacrificial material 50 in the partition 51 and replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23 is also beneficial to reducing the stress generated before bonding, thereby improving the stability and reliability of the formed three-dimensional memory.

[0103] In addition, when forming the partition 51, it is only necessary to ensure that the lower end of the partition 51 extends into a portion of the substrate 1, and the sacrificial material 50 in the partition 51 can be exposed by removing at least a portion of the substrate 1, so that it is convenient to use the partition 51 to replace the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23. It can be understood that here, the depths of the multiple partitions 51 extending into the substrate 1 can be consistent or inconsistent, and the partition 51 needs to be opened from the back side and the sacrificial material 50 in the partition 51 needs to be removed. Therefore, the embodiment of the present disclosure provides a method for preparing a three-dimensional memory, which does not require high etching accuracy of the partition 51, thereby helping to reduce process difficulty and save process costs.

[0104] In some embodiments, see Figure 1C , Figure 1C The flowchart of the preparation method for forming the separation structure 5 and the source layer 8 is shown. After the step of replacing the sacrificial layer 22 with the first conductive layer 23, the method further includes steps S7 to S9.

[0105] S7. A first protective layer 52 and a first insulating layer 53 are sequentially formed in the partition groove 51 in a direction away from the inner wall of the partition groove 51, a first conductive portion 54 is formed on a side of the first insulating layer 53 away from the first protective layer 52, and a second protective layer 55 is formed to cover an end of the first conductive portion 54 away from the peripheral circuit 7.

[0106] See also Fig.2I , Fig.2IThe longitudinal cross-sectional structure diagram of the three-dimensional memory after forming the first protective layer 52, the first insulating layer 53, the first conductive part 54 and the second protective layer 55 in the partition 51. The first protective layer 52 and the first insulating layer 53 can be deposited on the inner wall (side wall and bottom wall) of the partition 51 in sequence by a thin film deposition process such as CVD, PVD or ALD, and the first conductive part 54 is formed in the inner cavity formed by the first insulating layer 53, and the second protective layer 55 is formed at one end of the first conductive part 54 away from the peripheral device 7 to form a separation structure 5. The first protective layer 52 can prevent the first conductive layer 23 from directly contacting the first conductive part 54; the first insulating layer 53 can further electrically isolate the first conductive layer 23 from the first conductive part 54; the second protective layer 55 can electrically isolate the source layer 8 to be formed later from the first conductive part 54 to meet the functional requirements of the three-dimensional memory.

[0107] In some examples, the material of the first protective layer 52 is silicon oxide, the material of the first insulating layer 53 is silicon nitride, the material of the first conductive portion 54 is polysilicon, silicon nitride, silicon oxide, etc., and the material of the second protective layer 55 is silicon oxide.

[0108] S8 . Remove the second substrate layer 12 and at least a portion of the third substrate layer 13 to expose the second protection layer 55 .

[0109] See also Figure 2J and Figure 2K , Figure 2J The longitudinal cross-sectional structure diagram of the three-dimensional memory after removing the second substrate layer 12 and the third substrate layer 13 is shown. Figure 2K The longitudinal cross-sectional structure diagram of the three-dimensional memory after removing the second substrate layer 12 and part of the third substrate layer 13. The second substrate layer 12 and at least part of the third substrate layer 13 can be removed by, for example, a dry / wet etching process. The above-mentioned removal of "at least part of the third substrate layer 13" means removing all or part of the third substrate layer 13.

[0110] For example, see Figure 2J , the third substrate layer 13 is completely removed. At this time, the portion of the dummy conductive structure 3' located in the third substrate 13 can also be basically completely removed.

[0111] In other examples, after etching the second substrate layer 12 and before etching the third substrate layer 13 , the method further includes: setting a mask covering the dummy channel structure 3 ′ so as to retain the portion of the third substrate layer 13 covering the dummy channel structure 3 ′ after etching the third substrate layer 13 .

[0112] See also Figure 2K , a portion of the third substrate layer 13 is retained, thereby strengthening the supporting effect on the dummy channel structure 3'.

[0113] S9 , forming a source layer 8 covering the second protection layer 55 .

[0114] In this step, refer to Figure 2L and Figure 2M , Figure 2L is a longitudinal cross-sectional structural diagram of a three-dimensional memory, in which the third substrate layer 13 is completely removed; Figure 2M : is a longitudinal cross-sectional structure diagram of another three-dimensional memory, in which the third substrate layer 13 covering the virtual channel structure 3' is retained, thereby strengthening the support function of the virtual channel structure 3'. The formed source layer 8 covers the exposed portion Q1 of the channel layer 33, so that the source layer 8 can be electrically contacted with the end of the channel layer 33 away from the peripheral circuit 7. Since the portion of the first conductive portion 54 located in the source layer 8 is covered by the second protective layer 55 and other protective layers, the first conductive portion 54 is electrically isolated from the source layer 8.

[0115] In this step, continue to Figure 2L and Figure 2M , a polysilicon layer may be deposited by a thin film deposition process to form a source layer 8. The source layer 8 may be in electrical contact with the exposed portion of the channel layer 33, thereby achieving electrical connection between the channel structure 3 and the source layer 8. For example, Figure 2L and Figure 2M As shown, the source layer 8 surrounds the channel layer 33 at the end of the channel structure 3, so that the source layer 8 and the channel layer 33 at the end of the channel structure 3 have a larger contact area, which is beneficial to increase the reliability of the contact connection and improve the performance of the three-dimensional memory after preparation.

[0116] In some embodiments of the present disclosure, the substrate 1 material at the bottom of the channel is directly removed to expose the bottom of the channel structure 3, so that the etching process can be conveniently performed from the bottom of the channel structure 3 to expose the channel layer 33, and then the electrical connection between the channel layer 33 and the source is realized by forming the source layer 8. In this way, it is avoided to drill holes at the bottom of the channel, and it is not necessary to perform multiple etchings through the slits to open the storage function layer 32 on the side wall of the channel structure 3, and the difficulty of process implementation is greatly reduced.

[0117] In some embodiments, see Figure 2L The source layer 8 also covers the exposed end of the virtual channel structure 3′ and the first protective layer 52 located on the outer wall of the first conductive part 54, the second protective layer 55 located at the end of the first conductive part 54 away from the peripheral circuit 7, and the third protective layer 56 located in the source layer 8 and on the outer wall of the first protective layer 52.

[0118] In some other embodiments, see Figure 1D , Figure 1DIt is a flow chart of another preparation method for forming the separation structure 5 in the partition groove 51 and forming the source layer 8. After step S7, the above steps S8 and S9 are not included, but steps S80 to S90 are included.

[0119] S80 , removing the second substrate layer 12 , at least a portion of the third substrate layer 13 , the second protection layer 55 , a portion of the first insulating layer 53 , and a portion of the first protection layer 52 to expose an end of the first conductive portion 54 away from the peripheral circuit 7 .

[0120] In this step, refer to Figure 2N and Fig.2O , Figure 2N The longitudinal cross-sectional structure diagram of a three-dimensional memory after removing the second protection layer 55 is shown. In this diagram, the third substrate layer 13 originally covering the end of the dummy channel structure 3' away from the peripheral circuit 7 is completely removed. Fig.2O This is a longitudinal cross-sectional structural diagram of another three-dimensional memory after the second protection layer 55 is removed. In this diagram, a portion of the third substrate layer 13 covering the end of the dummy channel structure 3' away from the peripheral circuit 7 is retained.

[0121] In some examples, the second substrate layer 12, at least a portion of the third substrate layer 13, the second protection layer 55, a portion of the first insulating layer 53, and a portion of the first protection layer 52 may be removed by, for example, a dry / wet etching process. Figure 2P , Figure 2P The longitudinal cross-sectional structure of a three-dimensional memory after forming the source layer 8 is shown in FIG. 1 , in which the third substrate layer 13 is completely removed. After removing the third substrate layer 13, an end of the first conductive portion 54 away from the peripheral circuit 7 is exposed, so that the first conductive portion 54 can be electrically connected to the source layer 8.

[0122] For some examples, see Figure 2N , the third substrate layer 13 is completely removed by dry / wet etching.

[0123] For some examples, see Fig.2O After etching the second substrate layer 12 and before etching the third substrate layer 13, it also includes: setting a mask plate covering the virtual channel structure 3′, so that after etching the third substrate layer 13, the third substrate layer 13 is retained to cover the portion of the virtual channel structure 3′ away from the end of the peripheral circuit 7, thereby strengthening the supporting effect on the virtual channel structure 3′.

[0124] S90 , forming a source layer 8 covering an end of the first conductive portion 54 away from the peripheral circuit 7 .

[0125] In this step, refer to Figure 2P and Figure 2QThe formed source layer 8 covers the exposed portion of the channel layer 33 and the end of the first conductive portion 54 away from the peripheral circuit 7, so that electrical contact can be achieved between the source layer 8 and the end of the channel layer 33 away from the peripheral circuit 7 and the end of the first conductive portion 54 away from the peripheral circuit 7. Figure 2Q This is a longitudinal cross-sectional structural diagram of another three-dimensional memory after the source layer 8 is formed. In this diagram, the portion of the third substrate layer 13 covering the virtual channel structure 3′ is retained, and one end of the first conductive portion 54 away from the peripheral circuit 7 is exposed, thereby facilitating electrical connection between the first conductive portion 54 and the formed source layer 8.

[0126] In this step, the method of forming the source layer 8 can refer to the above content and will not be repeated here.

[0127] In some embodiments, before the above step S9 (or step S90 ), the preparation method further includes: performing ion doping on at least the exposed portion of the channel layer 33 , wherein the type of ion doping is the same as the doping type of the source layer 8 .

[0128] In this step, continue to Figure 2K and Figure 2L When the source layer 8 is doped with an N-type ion dopant, at least the portion Q1 exposed to the channel layer 33 is doped with the N-type ion dopant; when the source layer 8 is doped with a P-type ion dopant, at least the portion Q1 exposed to the channel layer 33 is doped with the P-type ion dopant. Since the ion doping types of the two are the same, it is helpful to improve the conductivity between the source layer 8 and the channel layer 33.

[0129] In some embodiments, the same type of ion doping may also be performed on a portion Q2 of the channel layer 33 close to the exposed portion Q1 to improve conductive stability.

[0130] In some embodiments, see Figure 1E , Figure 1E The flowchart of the method for manufacturing a three-dimensional memory includes the steps of forming a first etch stop layer 91, a second etch stop layer 92, and exposing an end of the channel structure 3 away from the peripheral circuit 7. Before step S1, step S001 is also included.

[0131] S001. Form a first etch stop layer 91 and a second etch stop layer 92 on a side of the third substrate layer 13 close to the stacked structure 2 and in a direction away from the third substrate layer 13. The first etch stop layer 91 and the second etch stop layer 92 have different etching selectivities.

[0132] In this step, if Figure 2CAs shown, the first etch stop layer 91 is formed on the surface of the third substrate layer 13, and the second etch stop layer 92 is formed on the surface of the first etch stop layer 91 away from the third substrate layer 13. By adding the first etch stop layer 91 and the second etch stop layer 92, etching can be stopped at the first etch stop layer 91 or the second etch stop layer 92, which helps to control the process uniformity during the removal of the third substrate layer 13 and the first etch stop layer 91, thereby ensuring the uniformity of the channel layer 33 after removing part of the storage function layer 32 of the channel structure 3.

[0133] Exemplarily, the first etch stop layer 91 and the second etch stop layer 92 may be formed by at least one of thin film deposition processes such as CVD, PVD, ALD, etc. The first etch stop layer 91 may be prepared by silicon oxide. The second etch stop layer 92 may be prepared by polysilicon. It should be noted that the first etch stop layer 91 and the second etch stop layer 92 should be prepared by materials that achieve a predetermined etching selectivity with the subsequent material to be etched, and the first etch stop layer 91 and the second etch stop layer 92 should have different etching selectivities.

[0134] On this basis, in some implementations, continue to refer to Figure 1E In the above steps S8 and S80, the step of removing the second substrate layer 12 and at least a portion of the third substrate layer 13 includes steps S81 to S82.

[0135] S81 , etching the second substrate layer 12 and at least a portion of the third substrate layer 13 to the first etch stop layer 91 to expose a portion of the storage function layer 32 extending into the third substrate layer 13 .

[0136] See also Figure 2J , Figure 2K , Figure 2N and Fig.2O In this step, for example, a wet etching process may be used to remove the second substrate layer 12 and at least a portion of the third substrate layer 13, and the etching may be stopped at the first etch stop layer 91 by selecting a predetermined etchant.

[0137] The first etch stop layer 91 has the same or similar etching selectivity as the storage function layer 32. For example, the material of the first etch stop layer 91 is the same as the material of the charge blocking layer 321 of the storage function layer 32, that is, the first etch stop layer 91 has the same etching selectivity as the storage function layer 32.

[0138] When the material of the first etch stop layer 91 is the same as that of the charge blocking layer 321 of the storage function layer 32, for example, both are made of silicon oxide, when the third substrate layer 13 is removed by, for example, a wet etching process, the etching can also be stopped at the charge blocking layer 321, thereby exposing the portion of the storage function layer 32 of the channel structure 3 extending into the third substrate layer 13. By adding the first etch stop layer 91, it is helpful to control the process uniformity during the removal of the second substrate layer 12 and at least a portion of the third substrate layer 13.

[0139] S82 , etching the first etch stop layer 91 and the exposed portion of the storage function layer 32 to the second etch stop layer 92 to expose an end of the channel layer 33 away from the peripheral circuit 7 .

[0140] Continue reading Figure 2J , Figure 2K , Figure 2N and Fig.2O In this step, the first etch stop layer 91 may be removed by, for example, a wet etching process, and the etching may be stopped at the second etch stop layer 92 by selecting a predetermined etchant.

[0141] The second etch stop layer 92 has the same or similar etching selectivity as the channel layer 33. For example, the material of the second etch stop layer 92 is the same as the material of the channel layer 33, that is, the second etch stop layer 92 has the same etching selectivity as the channel layer 33.

[0142] When the material of the second etch stop layer 92 is the same as that of the channel layer 33 of the channel structure 3, for example, both are made of polysilicon, when the first etch stop layer 91 and the storage function layer 32 are removed by, for example, a wet etching process, the etching can also be stopped at the channel layer 33, thereby exposing the portion of the channel layer 33 of the channel structure 3 extending into the second substrate layer 12 and the third substrate layer 13. By adding the second etch stop layer 92, it is helpful to control the process uniformity during the removal of the first etch stop layer 91 and the storage function layer 32.

[0143] On this basis, illustratively, the portion of the storage function layer 32 of the channel structure 3 extending into the second etch stop layer 92 can be further removed by controlling the etching time, so that the channel layer 33 of the channel structure 3 has a larger exposed area.

[0144] In some embodiments, after etching the third substrate layer 13, a portion of the dummy channel structure 3' extending into the third substrate layer 13 is also exposed; during etching of the exposed portion of the first etch stop layer 91 and the storage function layer 32, at least the exposed portion of the dummy channel structure 3' is removed. Figure 2K , Figure 2M , Fig.2O and Figure 2QTaking the example that the exposed portion of the dummy channel structure 3 ′ is partially removed, it can be understood that in other examples, the exposed portion of the dummy channel structure 3 ′ may also be completely removed.

[0145] In some embodiments, see Figure 2J , Figure 2K , Figure 2N and Fig.2O After etching the third substrate layer 13 and the first etch stop layer 91, the portion of the first conductive structure 61 extending into both the third substrate layer 13 and the first etch stop layer 91 and the portion of the second conductive structure 62 extending into both the third substrate layer 13 and the first etch stop layer 91 are also exposed.

[0146] In some embodiments, see Figure 2J , Figure 2K , Figure 2N and Fig.2O After etching the third substrate layer 13 and the first etch stop layer 91 , the portion of the first conductive portion 54 extending into both the third substrate layer 13 and the first etch stop layer 91 is also exposed.

[0147] Exemplarily, the third substrate layer 13 and the first etch stop layer 91 can be removed by, for example, a wet etching process, and by selecting a predetermined etchant or controlling the etching time, the etching is stopped at the outer surface of the virtual channel structure 3′ extending to both the third substrate layer 13 and the first etch barrier layer, the outer surface of the first conductive structure 61 extending to both the third substrate layer 13 and the first etch stop layer 91, the outer surface of the second conductive structure 62 extending to both the third substrate layer 13 and the first etch stop layer 91, and the outer surface of the first conductive portion 54 extending to both the third substrate layer 13 and the first etch stop layer 91, so as to expose the end portions of the virtual channel structure 3′ extending to both the third substrate layer 13 and the first etch stop layer 91, the end portions of the first conductive structure 61 extending to both the third substrate layer 13 and the first etch stop layer 91, the end portions of the second conductive structure 62 extending to both the third substrate layer 13 and the first etch stop layer 91, and the end portions of the first conductive portion 54 extending to both the third substrate layer 13 and the first etch stop layer 91.

[0148] The cross-sectional structure of the three-dimensional memory after the process in step S82 is as follows: Figure 2J , Figure 2K , Figure 2N and Fig.2O shown. Figure 2J and Figure 2NThe three-dimensional memory formed in the present invention does not have the third substrate layer 13 and the first etch stop layer 91 described above, but still retains the second etch stop layer 92. The second etch stop layer 92 can also be used as a spacer between the stacked structure 2 and the source layer 8 formed in the subsequent process. And by controlling the thickness of the second etch stop layer 92, the distance between the first conductive layer 23 (word line) and the source layer 8 in the stacked structure 2 can be effectively controlled.

[0149] In some embodiments, see Figure 1F , Figure 1F The flowchart of the method for preparing a three-dimensional memory includes forming a third protection layer 56. Before step S2, the step of filling the sacrificial material 50 in the partition groove 51, the method further includes step S0001.

[0150] S0001 . Form a third protective layer 56 on at least a portion of the inner wall of the partition groove 51 .

[0151] The third protection layer 56 at least covers the surface of the third substrate layer 13 exposed in the trench 51 , the surface of the first substrate layer 11 exposed in the trench 51 , and the surface of the second etch stop layer 92 exposed in the trench 51 .

[0152] In this step, refer to Figure 2D to Figure 2F When the materials of the third substrate layer 13, the first substrate layer 11 and the second etch stop layer 92 are the same as the material of the sacrificial material 50, when the sacrificial material 50 in the partition groove 51 is removed by etching, the third protective layer 56 can well stop the etching at the third protective layer 56, thereby preventing the third substrate layer 13, the first substrate layer 11 and the second etch stop layer 92 from being etched.

[0153] It can be understood that the material of the third protective layer 56 is different from the third substrate layer 13, the first substrate layer 11, the second etch stop layer 92 and the sacrificial material 50. Exemplarily, the third substrate layer 13, the first substrate layer 11, the second etch stop layer 92 and the sacrificial material 50 are all made of polysilicon, and the material of the third protective layer 56 is silicon oxide.

[0154] After the partition groove 51 is formed, the third substrate layer 13, the first substrate layer 11 and the second etch stop layer 92 are back-etched through the partition groove 51, and grooves are generated on the side walls of the partition groove 51 at the third substrate layer 13, the first substrate layer 11 and the second etch stop layer 92. Then, at least one of the thin film deposition processes such as CVD, PVD, ALD, etc. is used to form a third protective layer 56. The inner wall of the third protective layer 56 is in the same plane as the inner wall of the partition groove 51, ensuring that the sacrificial material 50 can be well deposited on the side wall of the partition groove 51 later.

[0155] In some embodiments, see Figure 1G , Figure 1G The flowchart of the method for preparing a three-dimensional memory for forming the dielectric layer 101, the second conductive part A1 and the second conductive layer 102. The method for preparing the three-dimensional memory further includes the steps: S10 to S12

[0156] S10 , forming a dielectric layer 101 on a side of the source layer 8 away from the stacked structure 2 .

[0157] In this step, refer to Figure 2L , Figure 2M , Figure 2P and Figure 2Q , a high density plasma chemical vapor deposition process, for example, can be used to fill a dielectric material, such as silicon oxide, on the side of the source layer 8 away from the stacked structure 2 to form a dielectric layer 101. On this basis, illustratively, a CMP process can be used to planarize the surface of the dielectric layer 101 away from the stacked structure 2.

[0158] In some embodiments, see Figure 2L , Figure 2M , Figure 2P and Figure 2Q Before manufacturing the dielectric layer 101, a dry or wet etching process may be used to remove the portion of the source layer 8 corresponding to the first conductive structure 61, and to remove the portion of the source layer 8 corresponding to the second conductive structure 62. On this basis, illustratively, the portion of the second etch stop layer 92 corresponding to the first conductive structure 61, and the portion of the second etch stop layer 92 corresponding to the second conductive structure 62 may be removed by controlling the etching time.

[0159] S11 . Form a second conductive portion A1 in the dielectric layer 101 . The second conductive portion A1 is electrically connected to the source layer 8 .

[0160] In this step, refer to Figure 2L , Figure 2M , Figure 2P and Figure 2Q A dry or wet etching process may be used to remove the portion of the dielectric layer 101 corresponding to the source layer 8 (eg Figure 2L , Figure 2M , Figure 2P and Figure 2Q A portion of the dielectric layer 101 corresponding to the channel structure 3 is formed to form an opening area, and then a conductive material is deposited in the opening area to form a second conductive portion A1 electrically connected to the source layer 8.

[0161] On this basis, illustratively, a dry or wet etching process may be used to remove the portion of the dielectric layer 101 corresponding to the first conductive structure 61, and to remove the portion of the dielectric layer 101 corresponding to the second conductive structure 62. Thus, the end of the first conductive structure 61 and the end of the second conductive structure 62 may be exposed, and then a third conductive portion A2 electrically connected to the end of the first conductive structure 61 and a fourth conductive portion A3 electrically connected to the end of the second conductive structure 62 are formed in the dielectric layer 101, and the fourth conductive portion A3 is electrically connected to the peripheral circuit 7 through the second conductive structure 62.

[0162] Methods for forming the second conductive portion A1 , the third conductive portion A2 and the fourth conductive portion A3 include but are not limited to thin film deposition processes such as CVD, PVD, and ALD.

[0163] In some embodiments, Figure 2L , Figure 2M , Figure 2P and Figure 2Q As shown, the dielectric layer 101 separates the source layer 8 from the first conductive structure 61 and the second conductive structure 62, preventing the source layer 8 from being in direct electrical contact with any two of the first conductive structure 61 and the second conductive structure 62. Thus, the source layer 8 and the first conductive structure 61 and the second conductive structure 62 can be prevented from generating crosstalk when receiving and transmitting signals.

[0164] S12, forming a second conductive layer 102 on a side of the dielectric layer 101 away from the stacked structure 2, wherein the second conductive layer 102 is electrically connected to the second conductive portion A1.

[0165] In this step, a thin film deposition process such as CVD, PVD, ALD, etc. may be used to form a metal thin film, and then the metal thin film is patterned (such as exposed, developed, etc.) to form the second conductive layer 102. Figure 2L , Figure 2M , Figure 2P and Figure 2Q The second conductive layer 102 can be electrically connected to the second conductive portion A1 and the third conductive portion A2 at the same time, thereby realizing the transmission of the source signal.

[0166] In some embodiments, see Figure 2L , Figure 2M , Figure 2P and Figure 2Q In the process of forming the second conductive layer 102, a fifth conductive portion 102' is formed on the side of the dielectric layer 101 away from the stacked structure 2, and the fifth conductive portion 102' is electrically connected to the fourth conductive portion A3. The fifth conductive portion 102' is used to connect to an external circuit.

[0167] In some embodiments, the method for preparing a three-dimensional memory further includes: forming a barrier layer 103, see Figure 2L , Figure 2M , Figure 2P and Figure 2Q The blocking layer 103 blocks the fifth conductive portion 102 ′ and the second conductive layer 102 , so that signal interference is not likely to occur between the fifth conductive portion 102 ′ and the second conductive layer 102 .

[0168] In some embodiments, the present disclosure provides a three-dimensional memory, and the three-dimensional memory 10 provided in some embodiments of the present disclosure is prepared by using any of the preparation methods described above. The beneficial effects of using any of the preparation methods described above can be found in the above content and will not be repeated here.

[0169] Figure 3A and Figure 3B is a top view of a three-dimensional memory according to some embodiments, Figure 4A to Figure 4D is a longitudinal cross-sectional structural diagram of a three-dimensional memory according to some embodiments.

[0170] exist Figure 3A The three-dimensional memory 10 shown includes four three-dimensional memories located on a wafer, a step area B of a three-dimensional memory is located between two storage areas A, that is, the three-dimensional memory is in an intermediate drive form, and a cutting path V is provided between adjacent three-dimensional memories, and the cutting path V is used to subsequently cut and separate multiple three-dimensional memories; Figure 3B In the three-dimensional memory shown, the step area B of a three-dimensional memory is located on both sides of the storage area A, that is, the three-dimensional memory is a two-side drive type, and a cutting path V is also provided between adjacent three-dimensional memories.

[0171] Figure 4A to Figure 4D The longitudinal cross-sectional structure diagram of four types of three-dimensional memory prepared by the above-mentioned preparation method. Figure 4A to Figure 4D The three-dimensional memory 10 includes a semiconductor layer 200 , a stacked structure 201 , a plurality of conductive structures 6 , a peripheral circuit 7 and a separation structure 5 .

[0172] The stacked structure 201 is located on one side of the semiconductor layer 200; the stacked structure 201 includes dielectric layers 201a and conductive layers 201b that are alternately arranged. A plurality of conductive structures 6 are located on a side of the stacked structure 201 away from the semiconductor layer 200, and at least some of the plurality of conductive structures 6 extend into the stacked structure 201. The peripheral circuit 7 is bonded to at least one of the plurality of conductive structures 6. The separation structure 5 penetrates the stacked structure 201 and extends into the semiconductor layer 200. The width of the separation structure 5 at one end close to the semiconductor layer 200 is smaller than the width of the separation structure 5 at one end away from the semiconductor layer 200.

[0173] The three-dimensional memory device 10 adopts the manufacturing method described in any of the above embodiments. During the manufacturing process, before removing the sacrificial material 50 in the partition groove 51 and replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23, the peripheral circuit 7 is first bonded to the multiple conductive structures 6 on the substrate 1. Therefore, the multiple conductive structures 6 on the substrate can be well supported before bonding, so that the multiple conductive structures 6 are not easily misaligned when bonding with the peripheral circuit 7, that is, the misalignment error when the peripheral circuit 7 is bonded with the multiple conductive structures 6 is improved. It can be understood that the multiple conductive structures 6 here are part of the array device on the substrate 1, so the misalignment error between the peripheral circuit 7 and the array device formed later is improved. On this basis, by removing the sacrificial material 50 in the partition groove 51 later and replacing the sacrificial layer 22 in the stacked structure 2 with the first conductive layer 23, it is also beneficial to reduce the stress generated before bonding, thereby reducing the structural deformation when the peripheral circuit 7 and the conductive structure 6 are bonded, thereby improving the yield of the three-dimensional storage device product and the stability of the structure and performance of the three-dimensional storage device product, thereby helping to improve the service life of the three-dimensional storage device product.

[0174] On the other hand, since the width D1 of the separation structure 5 close to the semiconductor layer 200 is smaller than the width D2 of the separation structure 5 away from the semiconductor layer 200 , the support force of the separation structure 5 at the end with a larger width is increased.

[0175] In some embodiments, the width of the trenches 51 in the separation structure 5 gradually increases in a direction away from the semiconductor layer 200 .

[0176] The width of the partition groove 51 in the partition structure 5 gradually increases along one direction, thereby ensuring that the size of the partition groove 51 changes gently without sudden changes, thereby avoiding stress concentration at a certain position of the partition groove 51.

[0177] It should be noted that Figure 4A to Figure 4D It is only a schematic diagram, and does not clearly show the width difference of the separation structure 5 in the direction away from the semiconductor layer 200. It can be understood that the width difference of the separation structure 5 comes from the width difference of the formed separation groove 51, that is, the aforementioned separation groove 51 also has a width difference. Figure 2D to Figure 2Q It is only a schematic diagram, and does not clearly show the difference in width between the separation groove 51 and the separation structure 5 along the direction away from the semiconductor layer 200 .

[0178] In some embodiments, an air gap 202 is provided in the separation structure 5 .

[0179] Please continue reading Figure 4A to Figure 4DAn air gap 202 is provided in the partition structure 5 , and the stress in the partition structure 5 can be well released through the air gap 202 .

[0180] In some embodiments, the air gap 202 extends in a direction perpendicular to the semiconductor layer 200 , and a width of a region of the air gap 202 close to the semiconductor layer 200 is smaller than a width of a region of the air gap 202 far from the semiconductor layer 200 .

[0181] Please continue reading Figure 4A to Figure 4D The width of the air gap 202 is set in this way, so that the size of the air gap 202 can match the overall size of the separation structure 5, which is conducive to better stress release of the air gap 202 at different positions.

[0182] It should be noted that when forming the first conductive portion 54 in the separation structure 5, a deposition process such as CVD, PVD, ALD, etc. can be used. At this time, the first conductive portion 54 starts to grow from the side wall of the partition 51, so the side wall of the air gap 202 formed in the middle can have a concave-convex structure adapted to the inner wall of the partition 51. Figure 4A to Figure 4D It is only a schematic diagram, and the concave-convex structure on the side wall of the air gap 202 is not clearly shown.

[0183] For some examples, see Figure 4A to Figure 4D , along the direction away from the semiconductor layer 200, the width of the air gap 202 generally tends to gradually increase (that is, the concave-convex structure on the sidewall of the air gap 202 is not considered), that is, Figure 4A to Figure 4D The cross section of the air gap is roughly an isosceles triangle.

[0184] This arrangement allows the size of the air gap 202 to change gradually in a direction away from the semiconductor layer 200 without causing a sudden change, thereby releasing the structural stress more evenly.

[0185] Figure 5 is a block diagram of a storage system 100 according to some embodiments. Figure 6 FIG. 1 is a block diagram of another storage system 100 according to some embodiments. Figure 5 and Figure 6 Some embodiments of the present disclosure further provide a storage system 100. The storage system 100 includes a controller 20 and the three-dimensional memory 10 of some embodiments above, and the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data. The beneficial effects brought by the storage system 100 are the same as the beneficial effects brought by the three-dimensional memory 10 and the method for preparing the three-dimensional memory described in any of the above embodiments, and will not be repeated here.

[0186] The storage system 100 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 100 may be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0187] In some embodiments, see Figure 5 The storage system 100 includes a controller 20 and a three-dimensional memory 10, and the storage system 100 can be integrated into a memory card.

[0188] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0189] In other embodiments, see Figure 6 The storage system 100 includes a controller 20 and a plurality of three-dimensional memories 10 ( Figure 6 Taking four three-dimensional memories as an example, the storage system 100 is integrated into a solid state drive (SSD).

[0190] In the storage system 100, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0191] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0192] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 may also be configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0193] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10. For example, the controller 20 may communicate with an external device (eg, a host) through at least one of various interface protocols.

[0194] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0195] The above-mentioned controller can be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0196] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: include: forming a stacked structure on a first side of the substrate, the stacked structure comprising dielectric layers and sacrificial layers arranged alternately; forming a groove penetrating the stacked structure and extending into the substrate, and forming a third protective layer on at least a portion of the inner wall of the groove, wherein the third protective layer at least covers the surface of the substrate exposed in the groove; Filling the compartment with a sacrificial material; forming a plurality of conductive structures on a side of the stacked structure away from the substrate; at least part of the plurality of conductive structures extending into the stacked structure; providing a peripheral circuit, and bonding the peripheral circuit to at least one conductive structure of the plurality of conductive structures; removing at least a portion of the substrate to expose the sacrificial material in the trench; The sacrificial material in the partition groove is removed, and the sacrificial layer is replaced by a first conductive layer through the partition groove, so that at least part of the plurality of conductive structures is electrically connected to the first conductive layer.

2. The preparation method according to claim 1, characterized in that: The substrate comprises a first substrate layer and a second substrate layer which are adjacent to the stacked structure in sequence; the second substrate layer and the first substrate layer have different etching selectivities, and the partition groove extends into the first substrate layer; The step of removing at least a portion of the substrate to expose the sacrificial material in the trench comprises: The first substrate layer is etched to the second substrate layer to expose the sacrificial material in the isolation groove.

3. The preparation method according to claim 2, characterized in that: After the step of replacing the sacrificial layer with the first conductive layer, the method further includes: forming a first protective layer and a first insulating layer in the groove in sequence along a direction away from the inner wall of the groove; forming a first conductive portion on a side of the first insulating layer away from the first protective layer, and forming a second protective layer covering an end of the first conductive portion away from the peripheral circuit; removing the second substrate layer to expose the second protective layer; A source layer covering the second protection layer is formed.

4. The preparation method according to claim 2, characterized in that: After the step of replacing the sacrificial layer with the first conductive layer, the method further includes: forming a first protective layer and a first insulating layer in the groove in sequence along a direction away from the inner wall of the groove; forming a first conductive portion on a side of the first insulating layer away from the first protective layer, and forming a second protective layer covering an end of the first conductive portion away from the peripheral circuit; removing the second substrate layer, the second protection layer, a portion of the first insulating layer and a portion of the first protection layer to expose an end of the first conductive portion away from the peripheral circuit; A source layer is formed to cover an end of the first conductive portion away from the peripheral circuit.

5. The preparation method according to claim 3 or 4, characterized in that: The substrate further comprises: a third substrate layer; the third substrate layer is located on a side of the second substrate layer away from the first substrate layer; the third substrate layer and the second substrate layer have different etching selectivities; After removing the second substrate layer, the method further includes removing at least a portion of the third substrate layer.

6. The preparation method according to claim 5, characterized in that: The stacked structure includes a step area and a storage area; Before the step of forming a groove penetrating the stacked structure and extending into the substrate, the method further includes: Forming a channel hole in the storage area that penetrates the stacked structure and extends into the third substrate layer, and sequentially forming a storage function layer and a channel layer in the channel hole in a direction away from an inner wall of the channel hole to form a channel structure; forming a virtual channel hole in the step region that penetrates the stacked structure and extends into the first substrate layer, and filling the virtual channel hole with a dielectric material to form a virtual channel structure; Part of the plurality of conductive structures is electrically connected to the channel layer.

7. The preparation method according to claim 6, characterized in that: Before the step of forming the stacked structure, the method further comprises: forming a first etch stop layer and a second etch stop layer in sequence on a side of the third substrate layer close to the stacked structure and in a direction away from the third substrate layer, wherein the first etch stop layer and the second etch stop layer have different etching selectivities; The step of removing the second substrate layer and at least a portion of the third substrate layer comprises: Etching the second substrate layer and at least a portion of the third substrate layer to the first etch stop layer to expose a portion of the storage function layer extending into the third substrate layer; Etching the first etch stop layer and the exposed portion of the storage function layer to the second etch stop layer to expose an end of the channel layer away from the peripheral circuit; After the source layer is formed, the source layer is electrically connected to an end of the channel layer away from the peripheral circuit.

8. The preparation method according to claim 7, characterized in that: Before the step of forming the source layer, the method further comprises: At least the exposed portion of the channel layer is ion doped, and the type of the ion doping is the same as the doping type of the source layer.

9. The preparation method according to claim 7, characterized in that: The forming of a third protective layer on at least a portion of the inner wall of the partition groove comprises: The third protection layer is formed at least on a surface of the third substrate layer exposed in the trench, a surface of the first substrate layer exposed in the trench, and a surface of the second etch stop layer exposed in the trench.

10. The preparation method according to claim 6, characterized in that: After etching the second substrate layer and before etching at least a portion of the third substrate layer, the method further includes: A mask covering the dummy channel structure is provided so as to retain a portion of the third substrate layer covering the dummy channel structure after etching a portion of the third substrate layer.

11. The preparation method according to claim 5, characterized in that: After the step of forming the source layer, the method further comprises: forming a dielectric layer on a side of the source layer away from the stacked structure; forming a second conductive portion in the dielectric layer, the second conductive portion being electrically connected to the source layer; A second conductive layer is formed on a side of the dielectric layer away from the stacked structure, and the second conductive layer is electrically connected to the second conductive portion.

12. The preparation method according to claim 11, characterized in that: The plurality of conductive structures include a first conductive structure and a second conductive structure; The first conductive structure is electrically connected to the source layer, and the second conductive structure is electrically connected to the peripheral circuit; After etching the first substrate layer, the second substrate layer, the third substrate layer and the second etching stop layer, exposing one end of the first conductive structure and the second conductive structure away from the peripheral circuit; The dielectric layer separates the source layer from the first conductive structure and the second conductive structure.

13. The preparation method according to claim 12, characterized in that: In the process of forming the second conductive part, a third conductive part and a fourth conductive part are also formed in the dielectric layer, the third conductive part is electrically connected to the first conductive structure, and the fourth conductive part is electrically connected to the peripheral circuit; the second conductive layer is also electrically connected to the third conductive part.

14. The preparation method according to claim 13, characterized in that: During the process of forming the second conductive layer, a fifth conductive portion is further formed on a side of the dielectric layer away from the stacked structure, and the fifth conductive portion is electrically connected to the fourth conductive portion.

15. A three-dimensional memory, characterized in that: include: Semiconductor layer; A stacked structure located on one side of the semiconductor layer; the stacked structure comprises dielectric layers and conductive layers arranged alternately; A plurality of conductive structures are located on a side of the stack structure away from the semiconductor layer, and at least some of the plurality of conductive structures extend into the stack structure; a peripheral circuit bonded to at least one of the plurality of conductive structures; as well as, A separation structure, wherein the separation structure penetrates the stacked structure and extends into the semiconductor layer; a width of the separation structure at one end close to the semiconductor layer is smaller than a width of the separation structure at one end away from the semiconductor layer.

16. The three-dimensional memory according to claim 15, characterized in that: The partition structure has an air gap therein.

17. The three-dimensional memory according to claim 16, characterized in that: The air gap extends in a direction perpendicular to the semiconductor layer; and a width of a region of the air gap close to the semiconductor layer is smaller than a width of a region of the air gap far from the semiconductor layer.

18. A storage system, characterized in that: The device comprises a controller and the three-dimensional memory according to any one of claims 15 to 17, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory.

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