Voltage regulator and system

Abstract

This application provides a voltage regulator including a rise-conversion circuit, a fall-conversion circuit, and a transient response control circuit, and provides a regulated output voltage. The rise-conversion circuit couples a first node of the voltage regulator to a first constant reference potential when a first condition of the regulated output voltage occurs. The fall-conversion circuit couples the first node to a second constant reference potential when a second condition of the regulated output voltage occurs. The transient response control circuit disables the rise-conversion circuit and the fall-conversion circuit when the rate of change of the regulated output voltage exceeds a predetermined rate. The first node is one of the output node and the output switching node of the voltage regulator. This application also provides a system including the above-described voltage regulator. The technical solution provided by this application improves the transient response of the voltage regulator.

Description

[0001] CLAIM OF PRIORITY

[0002] This patent application claims priority to and incorporates by reference in its entirety the pending provisional Indian patent application entitled “Method to improve transient response of linear regulator” having application number 202141020188 filed on May 3, 2021, and the priority to and incorporates by reference in its entirety the U.S. patent application having application number 17 / 646,871 filed on January 4, 2022, both of which are incorporated by reference herein in their entirety. TECHNICAL FIELD

[0003] Embodiments of the present application generally relate to voltage regulators, and more specifically, to improving transient response of voltage regulators. BACKGROUND

[0004] Voltage regulators are commonly used to provide a constant voltage source for electronic circuits, as is well known in the relevant art. A voltage regulator receives an input voltage (e.g., from a power supply) and produces a regulated output voltage of constant amplitude for a given input voltage and range of load currents. The voltage regulator can be a linear regulator (e.g., low dropout linear regulator, LDO) or a switching regulator.

[0005] Each voltage regulator is characterized by its ability to respond to transient conditions in which the output voltage fluctuates from the desired constant amplitude. Such fluctuations are typically caused by changes in one or more of the input voltage and load current. A voltage regulator can be said to be in a transient state until the output voltage reaches the desired constant amplitude.

[0006] The response of a voltage regulator in such transient states can be referred to as transient response. Transient response is typically quantified in terms of the magnitude of the change from the desired constant amplitude and the time it takes for the output voltage to return to the desired constant amplitude.

[0007] Several aspects of the present application relate to improving transient response of voltage regulators. SUMMARY

[0008] Embodiments of the present application aim to provide a voltage regulator that is capable of improving transient response of the voltage regulator.

[0009] Some embodiments of the present application provide a voltage regulator for producing a regulated output voltage from an input voltage. The voltage regulator includes a rise conversion circuit for coupling a first node of the voltage regulator to a first constant reference potential when a first condition of the regulated output voltage occurs. The voltage regulator includes a transient response control circuit for disabling the rise conversion circuit when a rate of change of the regulated output voltage changes from negative to positive after the first condition occurs. The first node is one of an output node and an output steering node of the voltage regulator.

[0010] In some embodiments, the voltage regulator further comprises a falling transition circuit for coupling the first node to the second constant reference potential when a second condition of the regulated output voltage occurs. The transient response control circuit is further for disabling the falling transition circuit when the rate of change changes from a positive value to a negative value after the second condition occurs.

[0011] In some embodiments, the rate of change exceeds a predetermined rate. The first condition comprises the regulated output voltage undershooting to a level less than a first threshold voltage, and the second condition comprises the regulated output voltage overshooting to a level greater than a second threshold voltage.

[0012] In some embodiments, the transient response control circuit comprises a differentiator for receiving the regulated output voltage and generating a first output signal. The first output signal has a magnitude proportional to the rate of change of the regulated output voltage. The transient response control circuit comprises a first comparator for receiving the first output signal and a third threshold voltage and generating a first disable signal. The first disable signal is a comparison of the first output signal and the third threshold voltage. The transient response control circuit comprises a second comparator for receiving the first output signal and a fourth threshold voltage and generating a second disable signal. The second disable signal is a comparison of the first output signal and the fourth threshold voltage.

[0013] In some embodiments, the voltage regulator further comprises a resistive voltage dividing circuit. The resistive voltage dividing circuit is coupled between the output node and the second constant reference potential. The resistive voltage dividing circuit provides a feedback voltage at a feedback terminal, wherein the feedback voltage is a scaled down version of the regulated output voltage. The rising transition circuit comprises a third comparator for receiving a scaled down version of the first threshold voltage and the feedback voltage and generating a first signal. The first signal is a comparison of the scaled down version of the first threshold voltage and the feedback voltage. The first signal is used to drive a control terminal of a first transistor at a first magnitude. The rising transition circuit comprises the first transistor for receiving the first signal at the control terminal of the first transistor, wherein a first current terminal of the first transistor is coupled to the first node. The rising transition circuit further comprises a first switch coupled between the first constant reference potential and a second current terminal of the first transistor. The first switch is controlled to close or open by the first disable signal. The first transistor is turned on to couple the first node of the voltage regulator to the first constant reference potential when the feedback voltage is less than the scaled down version of the first threshold voltage. The first transistor is turned off when the feedback voltage is greater than the scaled down version of the first threshold voltage. The first disable signal opens the first switch to disable the rising transition circuit when the first output signal is greater than the third threshold voltage. The first disable signal closes the first switch when the first output signal is less than the third threshold voltage. The rising transition circuit is for generating a rising transition current having the first magnitude when enabled by the first signal.

[0014] In some embodiments, the falling conversion circuit includes a fourth comparator for receiving the scaled version of the second threshold voltage and the feedback voltage and generating a second signal. The second signal is a comparison result of the scaled version of the second threshold voltage and the feedback voltage. The second signal is used to drive the control terminal of a second transistor at a second amplitude. The falling conversion circuit includes the second transistor for receiving the second signal at the control terminal of the second transistor. The first current terminal of the second transistor is coupled to the first node. The falling conversion circuit includes a second switch coupled between the second constant reference potential and the second current terminal of the second transistor. The second switch is controlled to be closed or open by a second disable signal. When the feedback voltage is greater than the scaled version of the second threshold voltage, the second transistor is turned on to couple the first node of the voltage regulator to the second constant reference potential. When the feedback voltage is less than the scaled version of the second threshold voltage, the second transistor is turned off. When the first output signal is less than a fourth threshold voltage, the second disable signal opens the second switch to disable the falling conversion circuit. When the first output signal is greater than the fourth threshold voltage, the second disable signal closes the second switch. The falling conversion circuit is used to generate a falling conversion current having the second amplitude when enabled by the second signal.

[0015] In some embodiments, the transient response control circuit further includes a first circuit for reducing the drive of the control terminal of the first transistor to a value less than the first amplitude for a predetermined interval immediately following an overshoot of the regulated output voltage. The transient response control circuit further includes a second circuit for reducing the drive of the control terminal of the second transistor to a value less than the second amplitude for a predetermined interval immediately following an undershoot of the regulated output voltage.

[0016] In some embodiments, the first circuit includes a series combination of a first capacitor and a first current-controlled current source. A connection point of the first capacitor and the first current-controlled current source is coupled to the control terminal of the first transistor, wherein the first current-controlled current source is controlled by the falling conversion current. The second circuit includes a parallel combination of a second capacitor and a second current-controlled current source. The parallel combination is coupled between the control terminal of the second transistor and the second constant reference potential, wherein the second current-controlled current source is controlled by the rising conversion current.

[0017] In some embodiments, the voltage regulator is a linear regulator. The linear regulator includes a pass transistor having a first current terminal to receive an input voltage. The pass transistor has a second current terminal coupled to an output node of the linear regulator and to provide a regulated output voltage. The linear regulator includes an error amplifier having a first input terminal to receive a reference voltage and a second input terminal to receive a feedback voltage. The error amplifier is to generate an error signal representative of a difference between the reference voltage and the feedback voltage. A control terminal of the pass transistor is to receive the error signal. Wherein the first node is an output steering node of the linear regulator, and the output steering node is the control terminal of the pass transistor.

[0018] In some embodiments, the voltage regulator is a linear regulator. The linear regulator includes a pass transistor having a first current terminal to receive an input voltage. The pass transistor has a second current terminal coupled to an output node of the linear regulator and to provide a regulated output voltage. The linear regulator includes an error amplifier having a first input terminal to receive a reference voltage and a second input terminal to receive a feedback voltage. The error amplifier is to generate an error signal representative of a difference between the reference voltage and the feedback voltage. A control terminal of the pass transistor is to receive the error signal. Wherein the first node is an output node of the linear regulator.

[0019] Some embodiments of the application also provide a system including a power supply terminal coupled to a power supply and a power supply unit to receive power from the power supply terminal. The power supply unit includes a first voltage regulator to receive the power and to generate a first lower supply voltage. Wherein the first voltage regulator is as described above, and the first lower supply voltage is the regulated output voltage.

[0020] In some embodiments, the system further includes an antenna, a first duplexer coupled to the antenna, and a first transceiver. The first lower supply voltage is to power a noise sensitive block in the first transceiver. The first transceiver includes a transmitter portion and a receiver portion. The transmitter portion and the receiver portion are each coupled to the first duplexer. The first transceiver is to transmit communication signals to a wireless medium via the first duplexer and the antenna, and to receive communication signals from the wireless medium via the first duplexer and the antenna.

[0021] In some embodiments, the system is a base transceiver station (BTS) system. The BTS system further includes a combiner coupled to an antenna, a plurality of duplexers, and a plurality of transceivers. Each of the plurality of duplexers is coupled to the combiner. The plurality of duplexers includes a first duplexer. The plurality of transceivers includes a first transceiver. Each of the plurality of transceivers includes a transmitter portion and a receiver portion. One end of the transmitter portion and the receiver portion is coupled to a respective one of the plurality of duplexers, and the other end is coupled to a base station controller (BSC). Each of the plurality of transceivers is configured to transmit an information signal received from the BSC into a wireless medium via a respective one of the plurality of duplexers, the combiner, and the antenna, and to forward an information signal received from the wireless medium to the BSC via a respective one of the plurality of duplexers, the combiner, and the antenna. The power supply unit includes a plurality of direct current-direct current (DC-DC) converters configured to receive power from the power supply terminal and generate respective supply voltages. The plurality of DC-DC converters includes a first DC-DC converter configured to generate a first supply voltage. The first supply voltage is configured to power relatively noise-insensitive modules in the first transceiver. The first voltage regulator is configured to receive the first supply voltage from the first DC-DC converter to generate a first lower supply voltage. The plurality of voltage regulators is configured to receive a supply voltage from a respective one of the plurality of DC-DC converters and generate a respective lower supply voltage. The plurality of voltage regulators includes the first voltage regulator. The supply voltage generated by one or more of the DC-DC converters is configured to power relatively noise-insensitive modules in the plurality of transceivers, and the supply voltage generated by one or more of the voltage regulators is configured to power noise-sensitive modules in the plurality of transceivers. At least a second voltage regulator of the plurality of voltage regulators is implemented in the same manner as the first voltage regulator. BRIEF DESCRIPTION OF DRAWINGS

[0022] Example embodiments of the present application will be described with reference to the following figures.

[0023] Figure 1 A circuit diagram of an example device in which aspects of the present application can be implemented is shown.

[0024] Figure 2A And Figure 2B An alternative path for transient detection and correction in the prior art is shown.

[0025] Figure 3 Is a timing diagram illustrating the oscillatory nature of the transient response in the prior art.

[0026] Figure 4 Is a block diagram of a voltage regulator implemented in embodiments of the present application.

[0027] Figure 5A And Figure 5Bis a circuit diagram illustrating implementation details of a voltage regulator in an embodiment of the application.

[0028] Figure 6 is a timing diagram illustrating waveforms at various nodes of a voltage regulator in an embodiment of the application.

[0029] Figure 7A is a block diagram illustrating a technique to prevent the up-slew circuit and the down-slew circuit from triggering each other in an embodiment of the application.

[0030] Figure 7B is a block diagram illustrating a technique to prevent the up-slew circuit and the down-slew circuit from triggering each other in an embodiment of the application. Figure 7A is a circuit diagram illustrating implementation details of some of the blocks shown in

[0031] Figure 8 is a timing diagram illustrating waveforms at various nodes of a voltage regulator in an embodiment of the application.

[0032] Figure 9 is a block diagram of a system in an embodiment of the application, which can include devices implemented in accordance with aspects of the application.

[0033] In the drawings, like reference numerals are generally used to refer to same, similar, and / or corresponding elements throughout the drawing figures. The first occurrence of an element in a figure is indicated by the left-most digit in the corresponding reference numeral. DETAILED DESCRIPTION

[0034] 1. OVERVIEW

[0035] According to an aspect of the application, a voltage regulator includes an up-slew circuit and a transient response control circuit. The up-slew circuit is configured to couple a first node of the voltage regulator to a first constant reference potential when a first condition of a regulated output voltage occurs. The transient response control circuit is configured to disable the up-slew circuit when a rate of change of the regulated output voltage changes from a negative value to a positive value after the first condition occurs. The first node is one of an output node and an output steering node of the voltage regulator. The voltage regulator also includes a down-slew circuit configured to couple the first node to a second constant reference potential when a second condition of the regulated output voltage occurs. The transient response control circuit is configured to disable the down-slew circuit when the rate of change changes from a positive value to a negative value after the second condition occurs.

[0036] In one embodiment, the first condition includes the regulated output voltage undershooting to a level less than a first threshold voltage, and the second condition includes the regulated output voltage overshooting to a level greater than a second threshold voltage. The disabling of the up-slew circuit and the down-slew circuit by the transient response control circuit occurs only when the rate of change of the regulated output voltage exceeds a predetermined rate. Thus, the transient response of the voltage regulator is improved.

[0037] Several aspects of the application are described below with reference to examples for illustrative purposes. Practitioners, however, will recognize that the application can be practiced without one or more of the specific details or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the application. Further, the described features / aspects can be implemented in various combinations, as would be understood by one skilled in the art. The methods, processes, and systems described herein can be implemented in a computing system that includes various types of hardware components and / or software components that interact in various ways. One example of such a system is shown in FIG. 1. The system includes one or more server computers 102 and one or more client computers 104. These server and client computers can each include one or more processors 106, one or more storage devices 108, and one or more memories 110. These components can be interconnected in a system bus configuration, in a client-server configuration, or in any other suitable configuration. The components can also be interconnected in a distributed computing environment.

[0038] 2. Example device

[0039] Figure 1 A circuit diagram showing details of an example voltage regulator that can be extended in accordance with several aspects of the application. Figure 1 The specific components of the voltage regulator 100 are shown by way of example only. However, several aspects of the application can also be implemented in alternative embodiments as briefly described in the following sections. Moreover, the voltage regulator 100 is shown as a linear regulator. However, several aspects of the application are also applicable to switching regulators. Any modifications to the technology described herein for such other scenarios will be apparent to those skilled in the art upon reading the disclosure provided herein.

[0040] The voltage regulator 100 is shown as receiving an input voltage Vin 101 and providing an (regulated) output voltage Vout 111 at an output node of the voltage regulator 100. The voltage regulator 100 operates in steady state conditions when Vout 111 is substantially equal to a constant amplitude Vreg. The voltage regulator 100 is shown as containing an error amplifier 110, a pass transistor 120, a voltage divider circuit containing a resistor 130 and a resistor 140, and an output capacitor 150. The voltage regulator 100 can be implemented in part or in whole in an integrated circuit (IC) or in a discrete form. A DC source (not shown) provides Vin 101 to the voltage regulator 100. A load current Iload 160 represents the current drawn by a load (not shown) of the voltage regulator 100. In one embodiment, the voltage regulator 100 is implemented as a low-drop-out linear regulator (LDO).

[0041] Error amplifier 110 receives a reference voltage Vref 121 and a feedback voltage Vfb 131. Vref represents a stable reference direct current (DC) voltage generated in a known manner inside voltage regulator 100. Vfb 131 is a scaled-down version of output voltage Vout 111, determined by the ratio of resistors 130 and 140. Note here that output voltage Vout 111 (not Vfb) can be used as an input to error amplifier 110, with the Vref value changed accordingly. Error amplifier 110 is used to amplify the difference between Vref 121 and Vfb 131, and generate a control signal ndrv 112 until Vfb 131 equals Vref 121. Signal ndrv 112 is applied to the gate of pass transistor 120 (implemented here as an N-type metal oxide semiconductor (NMOS) power transistor), and controls the drain-source resistance of power NMOS 120 to keep Vout 111 at the desired amplitude Vreg.

[0042] The combination of error amplifier 110, pass transistor 120, and the voltage divider circuit forms a feedback loop. Changes in output voltage Vout are sensed by the feedback loop, which then adjusts the drain-source resistance of pass transistor 120 to keep output voltage Vout 111 substantially constant. The gate (control terminal) of pass transistor 120 can be referred to as the output turn-around node of voltage regulator 100. The drain terminal of pass transistor 120 is connected to input voltage Vin 101, and the source terminal of pass transistor 120 provides the regulated output voltage Vout 111.

[0043] As is well known in the relevant art, changes in Iload 160 (load transients) can cause Vout 111 to increase (overshoot) or decrease (undershoot) relative to Vreg. When Iload 160 increases from its current value, Vout 111 falls below Vreg. Error amplifier 110 detects the fall through Vfb 131 and increases voltage ndrv to bring Vout back to Vreg. A decrease in Iload 160 from its current value causes Vout 111 to rise above Vreg. Error amplifier 110 detects the rise through Vfb 131 and decreases voltage ndrv to bring Vout 111 back to Vreg. The larger the increase or decrease in Iload 160 from its current value, the larger the fall and rise in Vout 111, respectively.

[0044] However, several factors affect the speed at which the feedback loop corrects for any changes in Vout. Some of these factors include the closed-loop bandwidth of the feedback loop, the size of the capacitance of capacitor 150 (in addition to whether capacitor 150 is included at all), the amplitude of the rise / fall in Vout, etc. For example, when voltage regulator 100 is implemented as a low-dropout (LDO) voltage regulator, the feedback loop has a relatively low closed-loop bandwidth, and the rise / fall in Vout is relatively small. As a result, the feedback loop takes a relatively long time to correct for any changes in Vout. In contrast, when voltage regulator 100 is implemented as a switching voltage regulator, the feedback loop has a relatively high closed-loop bandwidth, and the rise / fall in Vout is relatively large. As a result, the feedback loop takes a relatively short time to correct for any changes in Vout. Figure 1LDO with NMOS power transistor 120 (to get good power supply rejection ratio (PSRR)) in the example of Figure 1, gate terminal ndrv 112 can need to be driven higher than Vin 101. Thus, error amplifier 110 is powered by a voltage Vcp 141 that is greater than Vin 101, which is generated by a charge pump (not shown) within voltage regulator 100. Typically, a charge pump has a limited output current capability.

[0045] Furthermore, there can be a strict Iq (quiescent current) specification that can limit the quiescent / bias current consumption of error amplifier 110. Thus, the bias current drawn by error amplifier 110 can need to be limited to a small value, e.g., 100 µA. Furthermore, the power NMOS needs to be large enough to support the high load current Iload. Thus, the gate-source (or gate-to-body / ground) capacitance of power NMOS 120 can be relatively high, e.g., on the order of 200 pF (10 -12 When a load transient occurs, this capacitance needs to be charged or discharged before power NMOS 120 can react to the ndrv change induced by the feedback loop.

[0046] The combination of the limited bias current in error amplifier 110 and the large gate capacitance of power NMOS 120 typically results in a slow response of the feedback loop to load transients. Thus, the change in Vout 111 due to a load transient can not be corrected fast enough, and this delay can be unacceptable in at least some environments.

[0047] Several features of the present application will be better understood and appreciated once reference is made to the following detailed description of the application and claims taken in conjunction with the accompanying drawings. Figure 2A and Figure 2B An example prior art is briefly described.

[0048] Figure 2A and Figure 2B The use of an extra path / feedback loop to handle load transients in prior / conventional technology is shown. Figure 2A An existing voltage regulator 200 is shown that additionally (relative to voltage regulator 100) contains a rising transition circuit 280 and a falling transition circuit 290. Components 210, 220, 230, 240, 250, and 260 correspond to components 110, 120, 130, 140, 150, and 160, respectively, in Figure 1 in Figure 1 for brevity.

[0049] The rising conversion circuit 280 is shown connected between a constant reference potential Vcrpl 251 and the node 212, while the falling conversion circuit 290 is shown connected between the node 212 and ground 270. The rising conversion circuit 280 is used to quickly pull up the node 212 to Vcrpl 251 when Vout 211 falls below Vreg or below a threshold voltage of Vreg. The falling conversion circuit 290 is used to quickly pull down the node 212 to ground 270 when Vout 211 exceeds Vreg or above a threshold voltage of Vreg.

[0050] Figure 2B The implementation details of the rising conversion circuit 280 and the falling conversion circuit 290 according to the prior art are shown. The rising conversion circuit 280 is shown to contain a comparator 265 and a PMOS (P-channel Metal Oxide Semiconductor) transistor 275. The comparator 265 is shown to receive the feedback voltage Vfb at the positive terminal and the threshold voltage Vthl at the negative terminal. When undershoot occurs, Vfb falls below Vthl, the comparator 265 generates a logic 0 on the path 234, causing the gate of the transistor 275 to be pulled down (to ground). As a result, the node 212 is pulled up to Vcrpl 251, thereby quickly charging the gate capacitance of the pass transistor 220. In turn, Vout is quickly corrected to Vreg by the rising conversion circuit 280. Vcrpl 251 represents a voltage generated internally within the voltage regulator 200, for example, by a charge pump different from the charge pump that generates Vcp 241.

[0051] The falling conversion circuit 290 is shown to contain a comparator 285 and an NMOS transistor 295. The comparator 285 is shown to receive the feedback voltage Vfb at the positive terminal and the threshold voltage Vth2281 at the negative terminal. When overshoot occurs, Vfb 231 exceeds Vth2281, the comparator 285 generates a logic 1 on the path 244, causing the gate of the transistor 295 to be pulled up (to the supply voltage of the comparator 285). As a result, the node 212 is pulled down to ground, thereby quickly discharging the gate capacitance of the pass transistor 220. In turn, Vout is quickly corrected to Vreg by the falling conversion circuit 290. Each of the comparator 265 and the comparator 285 can be powered by a power supply other than the power supply that provides Vcp, for example, a charge pump, and thus can be powered by Vcrpl itself.

[0052] In Figure 2BIn the present embodiment, Vthl 271 and Vth2 281 are slightly (e.g., 5mV) less than and greater than Vref, respectively, rather than equal to Vref. Thus, the up- conversion circuit and the down-conversion circuit operate only when the value of Vfb is outside the range of Vthl to Vth2, or correspondingly, when Vout is outside the corresponding voltage range (hereinafter referred to as the "output voltage window") determined by the values of resistor 130 and resistor 140. In one embodiment, the resistor values are such that the above-mentioned corresponding voltage range is + / - 50mV. The up-conversion circuit 280 operates only when Vfb is below Vthl, and the down-conversion circuit 290 operates only when Vfb is above Vth2. In other words, when the value of Vfb is within the range of Vthl to Vth2, the main feedback loop handles changes in Vout (relative to Vreg). However, in general, Vthl and Vth2 can be equal to Vref. Note that each of comparators 265 and 285 can employ a suitable amount of hysteresis.

[0053] It will be appreciated that the charge pump that generates Vcrpl (or the supply voltage for comparators 265 and 285, in general) is designed to be capable of providing a higher current than the current that generates Vcp. Thus, the secondary feedback loop that includes the up-conversion circuit and the down-conversion circuit is designed to handle load transients faster than the main loop of voltage regulator 200. Under steady state conditions (when Vout is substantially equal to Vreg, and there are no transients of sufficient magnitude), transistors 275 and 295 are off, and comparators 265 and 285 can consume minimal current. However, Figure 2A The faster (secondary) feedback loop of prior voltage regulators still suffers from some drawbacks. These drawbacks will be described below with reference to Figure 3 the following figures.

[0054] Figure 3 is a timing diagram (not to scale) that depicts the transient response that occurs when the undershoot condition occurs in the previous embodiment. Specifically, the waveforms of load current Iload and feedback voltage Vfb are shown. Although the transient response has been described using the undershoot condition, it will be appreciated that the corresponding situation can also be encountered in the case of an overshoot condition.

[0055] Voltage regulator 200 is in steady state condition (Vout is equal to Vreg, and equivalently, Vfb is equal to Vref) until time t31. Waveform 260 represents Iload, and depicts a step change from the current value Iload-1 to a higher value Iload-2 at time t31. As a result, the output voltage Vout begins to decrease from the desired constant amplitude Vreg. This is reflected by a decrease in Vfb from the value Vref.

[0056] At time t32, when Vfb falls below Vthl, the up-conversion circuit 280 (see Figure 2B ) starts to operate, node 212 is pulled up to Vcrpl, and the gate capacitance of power NMOS 220 starts to charge rapidly to Vcrpl. At a time between t32-t33 (not shown), the current through the power NMOS starts to increase in the direction of Iload-2, and the slope of Vfb becomes less steep (although Figure 3 not shown in FIG. 15).

[0057] At time t33, when Vfb reaches a valley 315 (Vfb-low), the current through the power NMOS 220 is equal to the load current Iload-2, and Vfb starts to move back to Vref and eventually can reach the desired regulation value Vref at time t34. Accordingly, Vout rises to Vreg at time t34.

[0058] However, the up-conversion circuit 280 can continue to operate after time t34 and pull up the gate 212 of power NMOS 220 to a value beyond the Vgs (gate-source voltage) value that is just needed to correct the undershoot. This can occur due to a combination of factors such as the correction speed of the up-conversion circuit and the delay in detecting the Vout value through Vfb in the secondary feedback loop. As a result, Vout becomes higher than Vreg, and Vfb becomes higher than Vref. Vfb can exceed the threshold value Vth2 at time t344 (between t34 and t44), and over-correct for the undershoot, resulting in an overshoot condition. The overshoot can cause Vfb to rise to a value Vos1 (overshoot amount). As a result of the overshoot, the down-conversion circuit 290 is triggered at time t344, although this triggering is not a direct result of Iload. As a result, Vfb falls below Vref at time t454, as shown in FIG. 16. This unintended overshoot correction by the down-conversion circuit 290 can in turn cause an undershoot condition at time t54. The undershoot can cause Vfb to continue to fall until it equals Vusl (undershoot amount) at time t54, from which point Vfb starts to rise back to Vref. As a result, Vout (and Vref) exhibits a sustained (non-decaying) oscillatory transient response, as shown in FIG. 17. Figure 3 Figure 3 In the illustration of FIG. 17, the effect of the primary feedback loop has been ignored. In general, it is noted here that the closed-loop response of the secondary feedback loop can cause Vout to exhibit either a sustained oscillation as shown in FIG. 17, or at least an oscillation that takes a long duration to die out. Figure 3 Figure 3

[0059] ​​​Accordingly, while the secondary feedback loop responds quickly to load transients, there is still a disadvantage of oscillatory transient response due to the secondary feedback loop. The voltage regulator implemented in accordance with aspects of the present application improves transient response by minimizing or completely eliminating the duration of oscillatory transient response (caused by potential overcorrection by the rise and fall transition circuits as described above) as described in detail below in connection with example embodiments.

[0060] 3. Transient response control circuit

[0061] According to one aspect of the present application, the voltage regulator includes, in addition to the rise and fall transition circuits, a transient response control circuit. The transient response control circuit operates to improve the transient response provided by the rise and fall transition circuits alone. In addition, the rise and fall transition circuits are modified accordingly to be controlled by the transient response control circuit. The transient response control circuit is used to disable the pull-up and pull-down paths provided by the modified rise and fall transition circuits, respectively, to minimize unintended overcorrection of Vout.

[0062] Figure 4 is a block diagram of a voltage regulator implemented in accordance with aspects of the present application in one embodiment. The voltage regulator 400 can be implemented in place of the voltage regulator 100 of Figure 1 The voltage regulator 400, which can be implemented in place of the voltage regulator 100 of Figure 1 for brevity, are not repeated here.

[0063] Referring to Figure 4 , the transient response control circuit 410 disables the rise transition circuit 420 by disabling signal 451 and the fall transition circuit 430 by disabling signal 471 at appropriate times after a dip or overshoot, respectively. Implementation details of the transient response control circuit 410 in embodiments of the present application are described below in connection with Figure 5A and Figure 5B It is noted here that Vfb is a scaled down version of Vout. Accordingly, any change in Vfb and any comparison of Vfb to a threshold voltage will translate to a corresponding change in Vout and the corresponding threshold voltage. Accordingly, Vfb and Vout can be used interchangeably under the corresponding assumption in describing the operation of the voltage regulator.

[0064] Figure 5Ais a circuit diagram illustrating implementation details of the transient response control circuit 410 in the embodiments of the present application. The transient response control circuit 410 is shown to include comparators 580 and 590, and a differential circuit 575 including a capacitor 550, an operational amplifier 560, and a resistor 570. The transient response control circuit 410 receives the feedback voltage Vfb 131 and generates the disable signal 451 and the disable signal 471. The common mode voltage Vcm 551 is an internally generated voltage used to keep Vdiff 544 at an intermediate level between the power supply and ground of the comparators 580 and 590, which can be Vcrp1 and 470, respectively. Vth3 and Vth4 are greater and less than Vcm in magnitude, respectively. In one embodiment, Vcm is equal to Vref, and Vth3 and Vth4 are equal to Vth2 and Vth1, respectively.

[0065] The differential circuit 575 generates the voltage Vdiff 544. The magnitude of the voltage Vdiff 544 is proportional to the rate of change of Vfb with respect to time, and depends on the values of the resistor 570 and the capacitor 550. As mentioned above, since Vfb is a scaled down version of Vout, Vdiff is also proportional to the rate of change of Vout. The output voltage Vdiff is connected to the comparators 580 and 590.

[0066] The comparator 580 receives the voltage Vdiff at the positive terminal, and the threshold voltage Vth3 521 at the negative terminal. When Vdiff is greater than Vth3 521, the comparator 580 generates a logic 1 on the path 451. When Vdiff is less than Vth3 521, the comparator 580 generates a logic 0 on the path 451.

[0067] The comparator 590 receives the voltage Vdiff at the negative terminal, and the threshold voltage Vth4 531 at the positive terminal. When Vdiff is less than Vth4 531, the comparator 590 generates a logic 0 on the path 471. When Vdiff is greater than Vth4 531, the comparator 590 generates a logic 1 on the path 471.

[0068] Each of the comparators 580 and 590 is powered by a power supply other than the one that provides Vcp1 141, e.g., a charge pump, and thus can be Vcrp1 441 itself. Reference is next made to Figure 5B The manner in which the transient response control circuit 410 operates to disable the rising conversion circuit 420 and the falling conversion circuit 430 at the appropriate times is described.

[0069] Figure 5B Details of the rising and falling conversion circuits according to the present application are shown. The components 510 and 530 of the rising conversion circuit 420 correspond to the components 510 and 530 of the falling conversion circuit 430, respectively. Figure 2BThe components 265, 275 of the up-conversion circuit 280, and for brevity, are not repeated here. In addition, the up-conversion circuit 420 includes a switch 515, and the opening or closing of the switch 515 is controlled by a signal 451. The components 520 and 540 of the down-conversion circuit 430 correspond to the components 285 and 295 of the down-conversion circuit 290, respectively, and for brevity, are not repeated here. In addition, the down-conversion circuit 430 includes a switch 525, and the opening or closing of the switch 525 is controlled by a signal 471.

[0070] The switch 515 is shown connected between the voltage Vcrp1441 and the source terminal of the PMOS transistor 530. The switch 525 is shown connected between the drain terminal of the NMOS transistor 540 and the ground 470.

[0071] When the rate of change of Vout / Vfb is less than a predetermined rate (determined by the values of the capacitor 550 and the resistor 570), Vdiff is equal to Vcm or a positive or negative pulse (relative to Vcm) whose magnitude does not exceed Vth3 and Vth4, respectively. Accordingly, the signal 451 and the signal 471 are at logic 0 and logic 1, respectively, so that the switches 515 and 525 remain closed. When the slope (rate of change) of Vout / Vfb exceeds the predetermined value, Vdiff is a positive or negative pulse (relative to Vcm) whose magnitude exceeds Vth3 or Vth4, respectively. Specifically, when Vout / Vfb changes from a negative value to a positive value at a rate greater than the predetermined value, Vdiff pulses above Vth3 for a corresponding duration, and the comparator 580 generates a logic 1 on the path 451 for the corresponding duration, causing the switch 515 to also open for the corresponding duration. Thus, the up-conversion circuit 420 is disabled for the corresponding duration. Similarly, when Vout / Vfb changes from a positive value to a negative value at a rate greater than the predetermined rate, Vdiff pulses below Vth4 for a corresponding duration, and the comparator 590 generates a logic 0 on the path 471 for the corresponding duration, causing the switch 525 to also open for the corresponding duration. Thus, the down-conversion circuit 430 is disabled for the corresponding duration.

[0072] The manner in which the transient response control circuit 410 operates to improve the transient response of the voltage regulator by disabling the up-conversion circuit and the down-conversion circuit at the corresponding appropriate times as described above will be described next with reference to Figure 6 .

[0073] 4. Disabling the up-conversion circuit and the down-conversion circuit

[0074] Figure 6 is to illustrate the manner in which the embodiments of the present application Figure 5A andFigure 5B a timing diagram (not to scale) of the response of the circuit shown in Figure 6 Example waveforms are shown for Iload 160, Vfbat node 131 (both in Figure 4 shown in Figure 5B shown in

[0075] It will be appreciated that Figure 6 The specific shape of Vout / Vfb shown in Figure 6 In the description of

[0076] Furthermore, while the change in Iload is shown as a step change, the rise / fall in Iload typically occurs over a non-zero time interval. For example, voltage regulator 400 can be designed to support a maximum rate of change in Iload of 1 A / 1 μs. The transient response period depicted in time interval t610-t619 can be substantially equal to or slightly greater than 1 μs. Thus, Figure 6 Only one change in Iload and the corresponding response within the t610-t619 interval is described. In other words, Iload typically does not change again until after t619.

[0077] Voltage regulator 400 is in a steady state until time t610. Thus, Vfb is substantially equal to Vref, rise transition signal 534 is at logic 1, fall transition signal 554 is at logic 0, and switches 515 and 525 are closed. At time t610, Iload is stepped from its current value Iload-1 to a value Iload-2. Thus, Vfb begins to fall below Vref (undershoot).

[0078] At time t611, when Vfb falls below Vthl, signal 534 goes to logic 0, thereby turning on rise transition circuit 420 (see Figure 5B) of PMOS transistor 530. Up slew current 531 (with a first amplitude (slew-up-FS)) flows from Vcrpl into node 112. Slew-up-FS represents the "full strength" amplitude of the up slew current generated by up slew circuit 420 in response to the occurrence of the down shoot condition at time t610 (the time at which signal 534 goes to logic 0). During time interval t611-t614, signal 534 continues to be at logic 0 (until Vfb rises above Vthl). At time t612, the current of power NMOS 120 is equal to load current Iload-2, and Vfb reaches a valley point Vfb-low 601. Thus, during time interval t610-t612, the slope of Vfb is negative.

[0079] At time t612, Vfb starts to rise as power NMOS 120 is able to meet the load demand (the current through NMOS 120 is equal to Iload-2). Thus, the slope of Vfb changes from negative to positive at time t612 and starts to rise. The change in slope at time t612 exceeds the predetermined rate (as described above), and a positive pulse (not shown) is generated on path Vdiff 544 at time t613, assuming it occurs slightly later than t612. Thus, disable signal 451 goes to logic 1, causing switch 515 to open at time t613, thereby disabling up slew circuit 420. Switch 515 closes after a short time interval. Thus, up slew circuit 420 is disabled at (or slightly later than) the time of the change in slope. Transient response control circuit 410 is designed in such a way that switch 515 remains open at least until signal 534 returns to logic 1.

[0080] At time t614, Vfb rises above Vthl, and signal 534 returns to logic 1. Switch 515 closes shortly thereafter. Subsequently, Vfb overshoots Vref, and continues to rise and exceeds Vth2 at time t615 due to overcorrection as described above. At time t615, when Vfb exceeds Vth2, signal 554 goes to logic 1, thereby turning on NMOS transistor 540 (see Figure 5B ) of down slew circuit 430. During time interval t615-t617, signal 554 continues to be at logic 1 (until Vfb falls below Vth2). Vfb continues to rise until it reaches an upper limit Vfb-limit-1 at time t616, and then starts to fall from time t616. Thus, the slope of Vfb is positive during time interval t612-t616.

[0081] At time t616, the slope of Vfb changes from a positive value to a negative value. The slope change at time t616 exceeds the predetermined rate (as described above), and a negative pulse (not shown) is generated on path 544 (Vdiff) at time t617, assumed to occur slightly later than time t616. Thus, the disable signal 471 goes to logic 0, causing switch 525 to open at time t617, thereby disabling the falling conversion circuit 430. Switch 525 closes after a brief time interval. Thus, the falling conversion circuit 430 is disabled at the time of the slope change (or slightly later). As noted above with respect to the state of switch 515, the transient response control circuit 410 is designed in such a way that switch 525 remains open until signal 554 returns to logic 0.

[0082] At time t618, Vfb falls below Vth2, and signal 554 goes to logic 0. Switch 525 closes shortly thereafter. Vfb reaches the steady state value of Vref at time t619. The amount of overshoot (Vfb-limit-1 minus Vref) is smaller than the corresponding amount of overshoot (Vos1 minus Vref) in the Figure 3 Thus, by disabling the rising conversion circuit at the appropriate time, the voltage regulator 400 minimizes the overshoot (at time t616) due to overcorrection after the undershoot (at time t610) occurs. However, despite the fact that the rising conversion circuit 420 is disabled, the voltage regulator 400 still exhibits an overshoot (at time t651) due to overcorrection after the undershoot (at time t650) occurs. Figure 6 It is possible that one or more undershoots and corresponding overshoots due to overcorrection can still occur after time t619, although they are not shown in

[0083] Referring to Figure 6 , the voltage regulator 400 is in steady state between time interval t619-t650. Thus, Vfb is substantially equal to Vref, the rising conversion signal 534 is at logic 1, the falling conversion signal 554 is at logic 0, and switches 515 and 525 are closed. At time t650, Iload is decreased from its current value Iload-2 to a value Iload-1. Thus, Vfb begins to rise above Vref (overshoot).

[0084] At time t651, when Vfb rises above Vth2, signal 554 goes to logic 1, turning on NMOS transistor 540 (see Figure 5B). The slew-down-FS represents the "full strength" amplitude of the slew-down current generated by the slew-down circuit 430 in response to the overshoot condition occurring at time t650. The signal 554 remains at logic 1 during the time interval t651-t654 (until Vfb falls below Vth2). At time t652, Vfb reaches the peak point Vfb-high 602. Thus, the slope of Vfb is positive during the time interval t650-t652.

[0085] At time t652, the current through the pass transistor is equal to Iload-1, and Vfb starts to fall. Thus, the slope of Vfb changes from positive to negative at time t652 and continues to fall. The change in slope at time t652 exceeds the predetermined rate (as described above), and a negative pulse (not shown) is generated on path Vdiff 544 at time t653, assuming it occurs slightly later than time t652. Thus, the disable signal 471 goes to logic 0, causing the switch 525 to open at time t653, thereby disabling the slew-down circuit 430. The switch 525 closes after a short time interval. Thus, the slew-down circuit 430 is disabled at the time of the slope change (or slightly later). The transient response control circuit 410 is designed in such a way that the switch 525 remains open until the signal 554 returns to logic 0.

[0086] At time t654, Vfb falls below Vth2, and the signal 554 returns to logic 0. The switch 525 closes shortly thereafter. At some time between t654 and t655, Vfb falls below Vref (undershoot). At time t655, Vfb falls below Vthl due to overcorrection as described above. At time t655, when Vfb falls below Vthl, the signal 534 goes to logic 0, thereby turning on the PMOS transistor 530 of the slew-up circuit 420 (see Figure 5B ). During the time interval t655-t657, the signal 534 continues to be at logic 0 (until Vfb rises above Vthl). Vfb continues to fall until it reaches the lower limit Vfb-limit-2 at time t656, and then starts to rise from time t656. Thus, the slope of Vfb is negative during the time interval t652-t656.

[0087] At time t656, the slope of Vfb changes from a negative value to a positive value. The slope change at time t656 exceeds a predetermined rate (as described above), and a positive pulse (not shown) is generated on path Vdiff 544 at time t657, assumed to occur slightly later than time t656. As a result, the disable signal 451 goes to logic 1, causing switch 515 to open at time t657, thereby disabling the rising conversion circuit 420. Switch 515 closes after a brief time interval. As a result, the rising conversion circuit 420 is disabled at the time of the slope change (or slightly later).

[0088] At time t658, Vfb rises above Vthl, and signal 534 goes to logic 1. Switch 515 closes shortly thereafter. Vfbis shown to reach a steady state value of Vref at time t659. As in Figure 3 the value of the undershoot (Vref minus Vfb-limit-2) is smaller than the corresponding undershoot (Vref minus Vusl) in Figure 6 not shown in

[0089] Although the transient response control circuit 410 minimizes overcorrection, it can not be completely eliminated, and the transient response of the voltage regulator 400 can still continue to exhibit oscillatory behavior, although the peak-to-peak amplitude of such oscillations can be smaller than that shown in Figure 3 Although the amplitude of the overcorrection is reduced, oscillations can occur due to the rising conversion and falling conversion paths triggering each other.

[0090] According to another aspect of the present application, the rising conversion circuit and the falling conversion circuit are prevented from triggering each other, to further improve the transient response of the voltage regulator. Reference is made to Figure 7A and Figure 7B Example techniques to achieve this goal are described in detail.

[0091] 5. Preventing the rising conversion circuit and the falling conversion circuit from triggering each other

[0092] As described above in connection with Figure 6 the rising conversion circuit 420 can be enabled due to an undershoot condition triggered by a change in Iload (load transient), or due to overcorrection by the falling conversion circuit 430. Similarly, the falling conversion circuit 430 can be enabled due to an overshoot condition triggered by a change in Iload (load transient), or due to an overshoot condition triggered by overcorrection by the rising conversion circuit 420.

[0093] When enabled in response to a dip / overshoot condition triggered by a load transient, it is desirable for the slew-up and slew-down circuits to generate as strong a slew-up 531 and slew-down 521 current as possible ("full strength" slew-up-FS and slew-down-FS) in order to quickly correct the output voltage. However, when enabled due to over-correction, it is desirable for the slew-up and slew-down circuits to generate a slew-up 531 and slew-down 521 current with a lower magnitude in order to potentially prevent the circuits from triggering each other. In other words, it can be necessary to ensure that when the slew-up circuit is enabled off of steady state, the slew-down current strength is reduced for a predetermined duration of time. Similarly, it can be necessary to ensure that when the slew-down circuit is enabled off of steady state, the slew-up current strength is reduced for a predetermined duration of time.

[0094] Figure 7A is a block diagram illustrating a technique for preventing the slew-up and slew-down circuits from triggering each other in embodiments of the present application. A scaling block 700 is inserted between the comparator and the transistor of Figure 5B The scaling block 700 in combination with the components / blocks of Figure 5B represent modified slew-up and slew-down circuits. Figure 5B The comparators 530 and 540 of Figure 7A are also shown in The scaling block 700 is shown as containing a slew-down scaling circuit 720A and a slew-up scaling circuit 720B.

[0095] The slew-down scaling circuit 720A is shown as containing a multiplier 710A and a circuit block 711A. When the slew-up circuit 420 is enabled in response to a dip in Vout due to Iload, the slew-down scaling circuit 720A operates to reduce the strength of the slew-down current 521. When the slew-up current 531 is ON, the circuit block 711A sets the multiplication factor of the multiplier 710A to a value less than 1 (e.g., 0.25). When the slew-up current 531 is OFF, the circuit block 711A sets the multiplication factor of the multiplier 710A to 1. Thus, in response to a trigger of the slew-up circuit, the gate drive of the transistor 540 is reduced, thereby weakening the pull-down current if the slew-down circuit is triggered due to over-correction.

[0096] Ramp-up scaling circuit 720B is shown as including multiplier 710B and circuit block 711B. Ramp-up scaling circuit 720B operates to reduce the strength of ramp-up current 531 when enabled in response to Vout overshoot due to Iload. Circuit block 711B sets the multiplication factor of multiplier 710B to a value less than 1 (e.g., 0.25) when ramp-down current 521 is ON. Circuit block 711B sets the multiplication factor of multiplier 710B to 1 when ramp-down current 521 is OFF. Thus, in response to triggering of the ramp-down circuit, the gate drive of transistor 530 is reduced, thereby attenuating the pull-up current if the ramp-up circuit is triggered due to over-correction.

[0097] Figure 7B is a circuit diagram illustrating an example implementation of scaling block 700 in embodiments of the present application. Moreover, Figure 7A is a circuit diagram illustrating an example implementation of scaling block 700 in embodiments of the present application. Moreover, Figure 7B is a circuit diagram illustrating an example implementation of scaling block 700 in embodiments of the present application. Moreover,

[0098] Ramp-up scaling circuit 720A is shown as including current-controlled current source 760A and capacitor 770A. Current-controlled current source 760A is connected between Vcrpl and the gate terminal of PMOS transistor 730. Capacitor 770A is connected between the gate terminal of PMOS transistor 730 and ground. The current magnitude in current-controlled current source 760A is controlled by ramp-down current 721 through NMOS transistor 740. In particular, when ramp-down current 721 is ON (and at full strength), current-controlled current source 760A is ON for a predetermined duration. When ramp-down current 721 is OFF, current-controlled current source 760A is OFF.

[0099] Ramp-down scaling circuit 720B is shown as including current-controlled current source 760B and capacitor 770B. Each of current-controlled current source 760B and capacitor 770B is connected between the gate terminal of NMOS transistor 740 and ground. The current magnitude in current-controlled current source 760B is controlled by ramp-up current 731 through PMOS transistor 730. In particular, when ramp-up current 731 is ON (and at full strength), current-controlled current source 760B is ON for a predetermined duration. When ramp-up current 731 is OFF, current-controlled current source 760B is OFF.

[0100] The operation of the modified ramp-up and ramp-down circuits is described below with reference to Figure 8 The operation of the modified ramp-up and ramp-down circuits is described below with reference to

[0101] 6. The operation of the modified ramp-up and ramp-down circuits is described below with reference to

[0102] Figure 8 is a timing diagram illustrating waveforms at various nodes of the voltage regulator in the embodiments of the present application (not to scale). Figure 8 the signal of Figure 6 is the same as the signal of Figure 6 waveforms differ.

[0103] A. Operation of the up-conversion scaling circuit

[0104] i. Steady state condition

[0105] Referring to Figure 8 , in the steady state condition (before time t810, between time t819 and time t850, and after time t859), signal 734 is at logic 1, the gate terminal of PMOS transistor 730 is at logic high, switch 715 is closed, no current flows through current control current source 760A (open circuit), and capacitor 770A is in a discharge state.

[0106] ii. Load transient triggered undershoot condition

[0107] At time t810, an undershoot condition occurs due to a load transient. At time t811, signal 734 goes to logic 0, pulling the gate terminal of PMOS transistor 730 to ground. PMOS transistor 730 turns on and current 731 with "full strength amplitude" (slew-up-FS) flows through PMOS transistor 730. Because NMOS transistor 740 is not turned on, current control current source 760A is in open circuit. Capacitor 770A continues to be in a discharge state.

[0108] At time t813, the up-conversion circuit 420 is disabled by opening switch 715 (in response to signal 451). Current 731 stops flowing. At time t814, signal 734 returns to logic 1 when Vfb rises above Vthl. Thus, it can be appreciated that the increase scaling block 700 does not change the operation of the up-conversion circuit when it is enabled in response to a load transient triggered undershoot condition.

[0109] iii. Down-conversion circuit over-correction triggered undershoot condition

[0110] At time t850, an overshoot condition is triggered by a load transient. At time t851, NMOS transistor 740 turns on and current 721 flows at maximum strength, which in turn turns on current control current source 760A. Capacitor 770A starts charging towards Vcrpl at a rate determined by the strength of current 721. Thus, when comparator 710 tries to drive node 734 to ground, block 720A will prevent node 734 from being pulled to ground. Instead, node 734 will be at a voltage between ground and Vcrpl, thus driving the gate of PMOS transistor 730 at a weaker voltage than otherwise. The combination of component 710 and block 720A operates as a weak gate drive for the predetermined duration described above.

[0111] At time t855, PMOS transistor 730 is weakly pulled up due to the overcorrection of the falling transition circuit, and current 731 flows through PMOS transistor 730 at a magnitude less than the "full strength magnitude" (slew-up-FS). The weak pull-up results in a reduction in the order of magnitude of the drop of node Vfb below Vthl compared to the case where block 720A is not present, thus reducing the probability of triggering the falling transition circuit. In Figure 8 , the operation of block 720A is shown to not further trigger the falling transition circuit, and Vfb is shown to reach steady state at time t859. However, it is noted here that, in general, the operation of block 720A can reduce (but not completely eliminate) the number of times the falling transition circuit is further triggered by the rising transition circuit.

[0112] It can be seen that the undershoot (at time t856) after the overshoot (at time t850) is less than the undershoot Vfb-limit-2665 (at time t656) depicted in Figure 8 . This is due to the reduction in the rising transition current strength as described above. Figure 6

[0113] B. Operation of the falling transition scaling circuit

[0114] i. Steady state condition

[0115] Referring to Figure 8 , in the steady state condition (before time t810, between time t819 and time t850, and after time t859), signal 754 is at logic 0, the gate terminal of NMOS transistor 740 is at logic low, switch 725 is closed, no current flows through current control current source 760B (open circuit) and capacitor 770B discharges.

[0116] ii. Overshoot condition triggered directly by a load transient

[0117] ​At time t850, an overshoot condition occurs due to a load transient. At time t851, signal 754 goes to logic 1, NMOS transistor 740 turns on and current 721 flows through NMOS transistor 740 at a "full-slew-down-FS" amplitude. Because PMOS transistor 730 is not turned on and capacitor 770B does not hold any charge, current control current source 760B is open.

[0118] At time t853, (in response to signal 451) the falling transition circuit 430 is disabled by opening switch 725. Current 721 stops flowing. At time t854, as Vfb goes below Vth2, signal 754 returns to logic 0. Thus, it can be appreciated that the addition of scaling block 700 does not change the operation of the falling transition circuit when it is enabled in response to an overshoot condition triggered directly by a load transient.

[0119] iii. Overshoot condition triggered by over-correction of the rising transition circuit

[0120] An undershoot condition is triggered by a load transient at time t810. At t811, PMOS transistor 730 turns on and current 731 flows at maximum strength, which in turn turns on current control current source 760B. Capacitor 770B discharges to zero volts. When comparator 720 attempts to drive node 754 to Vcrpl, block 720B will prevent node 754 from being pulled all the way to Vcrpl. Instead, node 754 will be at a voltage between ground and Vcrpl, thus driving the gate of NMOS transistor 740 at a weaker voltage than otherwise. The combination of components 720 and 720B operates as a weak gate drive for the predetermined duration described above.

[0121] At time t815, due to over-correction of the rising transition circuit, NMOS transistor 740 is weakly pulled down and current 721 flows through NMOS transistor 740 at an amplitude less than "full-slew-down-FS". The weak pull-down results in a reduction in the magnitude of the offset of node Vfb above Vth2 compared to the case where block 720B is not present, thus reducing the probability of triggering the rising transition circuit. At time t816, the rising transition circuit is triggered. Figure 8 In the example, the operation of block 720B is shown to not further trigger the rising transition circuit, and Vfb is shown to reach steady state at time t819. However, it is noted here that in general, the operation of block 720B can reduce (but not completely eliminate) the number of times the rising transition circuit is further triggered by the falling transition circuit.

[0122] From Figure 8 It can be seen that the overshoot amount (at time t816) after the undershoot (starting at time t810) is less than Figure 6The depicted overshoot Vfb-limit-1664 at time t616. This is due to the falling slew current strength reduction as described above.

[0123] Furthermore, while the description herein is provided in the context of an LDO, several aspects of the present application can be equally well applied to other types of voltage regulators, such as switching voltage regulators, and will be apparent to those skilled in the art upon reading the disclosure herein. Moreover, while several discrete voltages are employed in the embodiments of the present application for illustration, one or more of these voltages can have the same value.

[0124] Aspects of the present application enable a regulator to adjust an output voltage while exhibiting improved transient response. The regulator 400 implemented as described above can be incorporated in a larger device or system as briefly described below.

[0125] 7. System

[0126] Figure 9 A block diagram showing implementation details of a system incorporated in the linear regulator 400 described in detail above is shown in the embodiment of the present application. Figure 9 The system of the present application can be deployed in a base transceiver station (BTS) (eNodeB in LTE - Long Term Evolution) of a cellular telephone system and is referred to herein as a BTS system 900. Broadly, the BTS system 900 facilitates wireless communication between user equipment (UE), which can be a mobile station (e.g., a cell phone) or a fixed user equipment (e.g., a computer with an Internet connection). The BTS system 900 can be implemented in accordance with technologies and standards such as Global System for Mobile Communications (GSM), Code division multiple access (CDMA), 3rd generation (3G), 4th generation (4G), Long Term Evolution (LTE), 5th generation (5G), etc. The BTS system 900 is shown to include transceivers 910A through 910N, duplexers 920A through 920N, a combiner 930, an antenna 940, a battery pack 950, and a power supply 960. The particular components / blocks of the BTS system 900 are shown by way of illustration. However, as is well known in the relevant art, the BTS system 900 can typically include more components / blocks, such as temperature sensors, maintenance and configuration blocks, etc.

[0127] Each of the transceivers 910A to 910N operates to transmit and receive communication signals to and from wireless user equipment via a corresponding duplexer 920A-920N, combiner 930 and antenna 940. Each transceiver includes a transmitter section and a receiver section. Thus, transceiver 910A is shown as including a transmitter section comprising a transmit baseband block 911, a transmit radio frequency (RF) block 912 and a power amplifier 913, and a receiver section comprising a low-noise amplifier (LNA) 916, a receive RF block 915 and a receive baseband block 914.

[0128] The transmit baseband block 911 receives an information signal (e.g., representing voice, data) from a base station controller (BSC) (which in turn receives the communication signal from another user equipment (wireless or fixed) in a BSC downstream network) via a corresponding path shown in bus 999, processes the signal in accordance with a corresponding technology and protocol to perform modulation, channel coding and other operations, and forwards the processed signal to the transmit RF block 912. The transmit RF block 912 can perform the following operations: up-conversion to RF, and forwards the RF signal to the power amplifier 913. The power amplifier 913 amplifies the received RF signal and transmits the power-amplified signal through the duplexer 920A, combiner 930 and antenna 940 to a corresponding wireless user equipment.

[0129] The LNA 916 receives an RF signal from a wireless user equipment via the duplexer 920A, combiner 930 and antenna 940, amplifies the RF signal, and forwards the amplified RF signal to the receive RF block 915. The receive RF block 915 down-converts the RF signal to a baseband frequency and forwards the baseband signal to the receive baseband block 914. The receive baseband block 914 can perform operations such as demodulation, error correction, etc. on the baseband signal to obtain an information signal (e.g., data, voice) and forwards the information signal to a BSC via a corresponding path in bus 999.

[0130] The clock 917 generates one or more clocks required to enable the operation of the digital units in the transceiver 910. For example, the transmit baseband block 911 and receive baseband block 914 can internally include one or more processors that require clocks to enable their operation.

[0131] Figure 9 The operation of the transmitter, receiver and clock of the other transceivers is similar to that described above with respect to transceiver 910A and includes corresponding transmitter and receiver blocks.

[0132] Each of the duplexers 920A through 920N is capable of transmitting and receiving respective transmit and receive signals (i.e., bidirectional (duplex) communication) on a single path between the respective duplexer and the combiner 930. Each of the duplexers 920A through 920N can be implemented with two bandpass filters connected in parallel, where one filter provides the path between the respective transmitter and the combiner 930, and the other filter provides the path between the combiner 930 and the respective receiver.

[0133] The combiner 930 combines signals from / to the transceivers 910A through 910N to enable transmitting and receiving all signals using a single antenna 940.

[0134] The antenna 940 operates to receive wireless signals carrying information from the wireless medium between the transceivers and wireless user devices, and to transmit wireless signals carrying information to the wireless medium.

[0135] The battery pack 950 houses batteries to provide power for the operation of the blocks / units in the BTS system 900.

[0136] The power supply 960 receives power (e.g., 12 volts) from the battery pack 950, and contains a plurality of DC-DC converters 961A through 961M, and a plurality of linear voltage regulators (e.g., implemented as LDOs) 962A through 962L. The DC-DC converters 961A-961M generate various voltages (each DC-DC converter generates a respective voltage, e.g., 0.7V, 1.2V, 2.0V, 3.6V, etc.) for powering one or more blocks / components of the BTS system 900 described above. Specifically, the voltages generated by the DC-DC converters can be used to power blocks and components of the transceivers 910A through 910N that are less sensitive to noise, such as transmit and receive baseband blocks. Thus, a power supply voltage 991C is shown as being generated by the DC-DC converter 961A, and provided to the (transmit and receive baseband blocks) of the transceivers 910. For the sake of clarity and conciseness, Figure 9 Only one power connection directly from a DC-DC converter is shown. However, there will be many more such power connections.

[0137] Each of the LDOs 962A-962L is connected to receive the output voltage of a corresponding DC-DC converter 961A-961M, and generates a corresponding lower voltage as needed by some components / blocks of the transceivers. The voltages generated by the LDOs are used to power noise sensitive blocks and components in the transceivers 910A through 910N, such as transmit RF blocks (e.g., 912), receive RF blocks (e.g., 915), LNAs (e.g., 916), and clocks (e.g., 917) included in the transceivers. For the sake of clarity and conciseness, Figure 9Only two power connections 991A and 991B (from LDO 962A and LDO 962L, respectively) are shown. However, there are many more power connections from the LDOs to the respective blocks in the transceiver. LDOs can have better load and line regulation than DC-DC converters, and thus can provide cleaner power supply voltages with less noise, as required by the noise sensitive blocks described above.

[0138] One or more of the LDOs 962A-962-L are implemented as the linear regulator 400 described in detail above.

[0139] It is noted here that the linear regulator 400 can also be used in other systems, such as standalone transmitters and receivers, mobile phones, etc.

[0140] 8. Conclusion

[0141] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" and "in an embodiment" or similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0142] While in Figure 1 , Figure 4 , Figure 5A , Figure 5B , Figure 7A , Figure 7B and Figure 9 the illustrations of the figures show the ends / nodes as being directly connected (i.e., "connected to") various other ends, it is to be understood that additional components (suitable to the particular environment) can exist in the path, and thus the connections can be viewed as being "electrically coupled" to the same, even though not shown.

[0143] It is to be understood that the particular type of transistor (e.g., NMOS, PMOS, etc.) mentioned above is for illustration only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant art(s) upon reading the disclosure provided herein. For example, PMOS (P-type Metal Oxide Semiconductor) transistors can be substituted for NMOS transistors, with the connections to the power and ground terminals being interchanged.

[0144] Therefore, in this application, the power supply terminal and the ground terminal are referred to as constant reference potentials, the source (emitter) and drain (collector) of the transistor (which provide current paths when turned on and open-circuit paths when turned off) are referred to as current terminals, and the gate (base) is referred to as control terminals.

[0145] While various embodiments of this application have been described above, it should be understood that they are presented as examples only and not as limitations. Therefore, the breadth and scope of this application should not be limited to any of the foregoing embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A voltage regulator for generating a regulated output voltage from an input voltage; characterized by, The voltage regulator comprises: a rising conversion circuit; a transient response control circuit configured to receive a feedback voltage corresponding to the regulated output voltage and determine the regulated output voltage based on the feedback voltage, wherein the feedback voltage has a preset proportional relationship with the regulated output voltage; when the regulated output voltage satisfies a first condition, the rising conversion circuit is enabled to couple a first node of the voltage regulator to a first constant reference potential, and when a rate of change of the feedback voltage changes from a negative value to a positive value and satisfies a predetermined rate, the rising conversion circuit is disabled, wherein the first condition is that the regulated output voltage undershoots to a level less than a first threshold voltage; wherein the first node is one of an output node and an output steering node of the voltage regulator; the transient response control circuit comprises: a differential circuit configured to receive the feedback voltage of the regulated output voltage and generate a first output signal having an amplitude proportional to a rate of change of the feedback voltage; a first comparator configured to receive the first output signal and a third threshold voltage, and generate a first disable signal when the first output signal is greater than the third threshold voltage, the first disable signal being used to disable the rising conversion circuit; a second comparator configured to receive the first output signal and a fourth threshold voltage, and generate a second disable signal when the output signal is less than the fourth threshold voltage, the second disable signal being used to disable a falling conversion circuit.

2. The voltage regulator of claim 1, wherein, The voltage regulator further comprises: a falling conversion circuit; the transient response control circuit is further configured to, when the regulated output voltage satisfies a second condition, enable the falling conversion circuit to couple the first node of the voltage regulator to a second constant reference potential, and when the rate of change of the feedback voltage changes from a positive value to a negative value and satisfies a predetermined rate, disable the falling conversion circuit, wherein the second condition is that the regulated output voltage overshoots to a level greater than a second threshold voltage.

3. The voltage regulator of claim 2, wherein, The voltage regulator further comprises a resistive voltage dividing circuit coupled between the output node and the second constant reference potential, the resistive voltage dividing circuit providing the feedback voltage at a feedback terminal, wherein the feedback voltage is a scaled-down version of the regulated output voltage, wherein the rising conversion circuit comprises: a third comparator configured to receive a scaled-down version of the first threshold voltage and the feedback voltage and generate a first signal, the first signal being a comparison result of the scaled-down version of the first threshold voltage and the feedback voltage, wherein the first signal is used to drive a control terminal of a first transistor at a first amplitude; the first transistor configured to receive the first signal at the control terminal of the first transistor, wherein a first current terminal of the first transistor is coupled to the first node; a first switch coupled between the first constant reference potential and a second current terminal of the first transistor, wherein the first switch is controlled to be closed or opened by the first disable signal, wherein the first transistor is turned on to couple the first node of the voltage regulator to the first constant reference potential when the feedback voltage is less than the scaled down version of the first threshold voltage; wherein the first transistor is turned off when the feedback voltage is greater than the scaled down version of the first threshold voltage; wherein the first disable signal opens the first switch to disable the rising conversion circuit when the first output signal is greater than the third threshold voltage; wherein the first disable signal closes the first switch when the first output signal is less than the third threshold voltage; and wherein the rising conversion circuit is configured to generate a rising conversion current having a first amplitude when enabled by the first signal.

4. The voltage regulator of claim 2 or 3, wherein, the falling conversion circuit comprises: a fourth comparator configured to receive a scaled down version of the second threshold voltage and the feedback voltage and generate a second signal, the second signal being a comparison result of the scaled down version of the second threshold voltage and the feedback voltage, wherein the second signal is configured to drive a control terminal of a second transistor with a second amplitude; the second transistor is configured to receive the second signal at the control terminal of the second transistor, wherein a first current terminal of the second transistor is coupled to the first node; a second switch coupled between the second constant reference potential and a second current terminal of the second transistor, wherein the second switch is controlled to be closed or opened by the second disable signal, wherein the second transistor is turned on to couple the first node of the voltage regulator to the second constant reference potential when the feedback voltage is greater than the scaled down version of the second threshold voltage; wherein the second transistor is turned off when the feedback voltage is less than the scaled down version of the second threshold voltage; wherein the second disable signal opens the second switch to disable the falling conversion circuit when the first output signal is less than the fourth threshold voltage; wherein the second disable signal closes the second switch when the first output signal is greater than the fourth threshold voltage; and wherein the falling conversion circuit is configured to generate a falling conversion current having a second amplitude when enabled by the second signal.

5. The voltage regulator of claim 4, wherein, the transient response control circuit further comprises: a first circuit configured to decrease the drive to the control terminal of the first transistor to a value less than the first amplitude within a predetermined interval immediately following an overshoot of the regulated output voltage, and a second circuit configured to decrease the drive to the control terminal of the second transistor to a value less than the second amplitude within the predetermined interval immediately following an undershoot of the regulated output voltage.

6. The voltage regulator of claim 5, wherein: the first circuit comprises a series combination of a first capacitor and a first current-controlled current source, wherein a connection point of the first capacitor and the first current-controlled current source is coupled to the control terminal of the first transistor, wherein the first current-controlled current source is controlled by the falling conversion current, and the second circuit comprises a series combination of a second capacitor and a second current-controlled current source, wherein a connection point of the second capacitor and the second current-controlled current source is coupled to the control terminal of the second transistor, wherein the second current-controlled current source is controlled by the rising conversion current. The second circuit includes a parallel combination of a second capacitor and a second current-controlled current source, the parallel combination coupled between a control terminal of the second transistor and the second constant reference potential, wherein the second current-controlled current source is controlled by the rising conversion current.

7. The voltage regulator of claim 5, wherein, The voltage regulator is a linear regulator, comprising: a pass transistor having a first current terminal for receiving the input voltage; wherein a second current terminal of the pass transistor is coupled to the output node of the linear regulator and provides the regulated output voltage; an error amplifier having a first input terminal for receiving a reference voltage and a second input terminal for receiving the feedback voltage, the error amplifier for generating an error signal representative of a difference between the reference voltage and the feedback voltage; wherein a control terminal of the pass transistor is for receiving the error signal; wherein the first node is the output steering node of the linear regulator, and wherein the output steering node is a control terminal of the pass transistor.

8. The voltage regulator of claim 5, wherein, The voltage regulator is a linear regulator, comprising: a pass transistor having a first current terminal for receiving the input voltage; wherein a second current terminal of the pass transistor is coupled to the output node of the linear regulator and provides the regulated output voltage; an error amplifier having a first input terminal for receiving a reference voltage and a second input terminal for receiving the feedback voltage, the error amplifier for generating an error signal representative of a difference between the reference voltage and the feedback voltage; wherein a control terminal of the pass transistor is for receiving the error signal, and wherein the first node is the output node of the linear regulator.

9. A BTS system characterized by comprising: a power supply terminal coupled to a power supply; and a power supply unit for receiving power from the power supply terminal; the power supply unit includes a first voltage regulator for receiving the power and generating a first lower supply voltage; wherein the first voltage regulator is the voltage regulator as claimed in any one of claims 1 to 8, and the first lower supply voltage is the regulated output voltage.

10. The system of claim 9, wherein, The system further comprises: an antenna; a first duplexer coupled to the antenna; and a first transceiver, wherein the first lower supply voltage is used to power noise sensitive blocks in the first transceiver, the first transceiver includes a transmitter section and a receiver section, each coupled to the first duplexer, the first transceiver transmits communication signals to a wireless medium via the first duplexer and the antenna, the first transceiver also receives communication signals from the wireless medium via the first duplexer and the antenna.

11. The system of claim 10, wherein, The system further comprises: a combiner coupled to the antenna; a plurality of duplexers, each of the plurality of duplexers coupled to the combiner, the plurality of duplexers including the first duplexer; and a second transceiver, wherein the first lower supply voltage is used to power noise sensitive blocks in the second transceiver, the second transceiver includes a transmitter section and a receiver section, each coupled to the second duplexer, the second transceiver transmits communication signals to a wireless medium via the second duplexer and the antenna, the second transceiver also receives communication signals from the wireless medium via the second duplexer and the antenna. a plurality of transceivers including the first transceiver, each of the plurality of transceivers including a transmitter portion and a receiver portion, one end of the transmitter portion and the receiver portion being coupled to a respective one of the plurality of duplexers, the other end of the transmitter portion and the receiver portion being coupled to a base station controller (BSC); wherein each of the plurality of transceivers is configured to transmit information signals received from the BSC into the wireless medium via the respective one of the plurality of duplexers, the combiner and the antenna, and to forward information signals received from the wireless medium to the BSC via the respective one of the plurality of duplexers, the combiner and the antenna; wherein the power supply unit comprises: a plurality of DC-DC converters configured to receive the power from the power supply terminal and generate respective supply voltages, the plurality of DC-DC converters including a first DC-DC converter configured to generate a first supply voltage, wherein the first supply voltage is configured to power noise-insensitive modules in the first transceiver, wherein the first voltage regulator is configured to receive the first supply voltage from the first DC-DC converter to generate the first lower supply voltage; and a plurality of voltage regulators configured to receive supply voltages from respective ones of the plurality of DC-DC converters and generate respective lower supply voltages, wherein the plurality of voltage regulators includes the first voltage regulator, wherein supply voltages generated by one or more of the DC-DC converters are configured to power noise-insensitive modules in the plurality of transceivers, and wherein supply voltages generated by one or more of the voltage regulators are configured to power noise-sensitive modules in the plurality of transceivers, and wherein at least a second voltage regulator of the plurality of voltage regulators is implemented in the same manner as the first voltage regulator. a plurality of transceivers including the first transceiver, each of the plurality of transceivers including a transmitter portion and a receiver portion, one end of the transmitter portion and the receiver portion being coupled to a respective one of the plurality of duplexers, the other end of the transmitter portion and the receiver portion being coupled to a base station controller (BSC); wherein each of the plurality of transceivers is configured to transmit information signals received from the BSC into the wireless medium via the respective one of the plurality of duplexers, the combiner and the antenna, and to forward information signals received from the wireless medium to the BSC via the respective one of the plurality of duplexers, the combiner and the antenna; wherein the power supply unit comprises: a plurality of DC-DC converters configured to receive the power from the power supply terminal and generate respective supply voltages, the plurality of DC-DC converters including a first DC-DC converter configured to generate a first supply voltage, wherein the first supply voltage is configured to power noise-insensitive modules in the first transceiver, wherein the first voltage regulator is configured to receive the first supply voltage from the first DC-DC converter to generate the first lower supply voltage; and a plurality of voltage regulators configured to receive supply voltages from respective ones of the plurality of DC-DC converters and generate respective lower supply voltages, wherein the plurality of voltage regulators includes the first voltage regulator, wherein supply voltages generated by one or more of the DC-DC converters are configured to power noise-insensitive modules in the plurality of transceivers, and wherein supply voltages generated by one or more of the voltage regulators are configured to power noise-sensitive modules in the plurality of transceivers, and wherein at least a second voltage regulator of the plurality of voltage regulators is implemented in the same manner as the first voltage regulator.

Images