Phase-locked loop (PLL) with operating parameter calibration circuit and method

Abstract

A phase-locked loop (PLL) with an operating parameter calibration circuit and a method are provided. The calibration scheme controls the PLL bandwidth and includes its extension. In the open loop, the VCO control voltage is scanned within a range of values, and the VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency, and the corresponding current amplitude of the variable amplitude charge pump is calculated based on the ratio of a constant to the gain KVCO and associated with the measured output frequency in a lookup table. Once calibration is complete, the PLL loop is closed, and the calculated current amplitude is obtained from the lookup table based on the required output frequency of the PLL circuit. The variable amplitude charge pump circuit is then controlled to generate a charge pump current with an amplitude corresponding to the obtained charge pump current amplitude.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 128968, filed December 22, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to phase-locked loop (PLL) circuits, and more specifically, to the calibration of operating parameters of PLL circuits. Background Technology

[0004] refer to Figure 1 , Figure 1 A block diagram of a phase-locked loop (PLL) circuit 10 is shown. A phase-frequency detector (PFD) circuit 12 has a first input for receiving a reference clock signal CLKref(t) and a second input for receiving a feedback clock signal CLKfb(t). The PFD circuit 12 measures the difference between similar edges (i.e., rising or falling edges) of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t). When the PFD circuit 12 detects that the similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t) are aligned, an upward signal U(t) is pulsed, and a downward signal D(t) is pulsed (the two pulses are synchronized and have the same duration). If the PFD circuit 12 detects that the edge of the reference clock signal CLKref(t) leads the similar edge of the feedback clock signal CLKfb(t), the upward signal U(t) is pulsed for a first duration, and the downward signal D(t) is pulsed for a second duration (less than the first duration), where the length of the first duration depends on the phase error between the similar edges. Conversely, if the edge of the feedback clock signal CLKfb(t) leads the similar edge of the reference clock signal CLKref(t), the PFD circuit 12 pulses the downward signal D(t) for the third duration and pulses the upward signal U(t) for the fourth duration (less than the third duration), where the length of the third duration depends on the phase error between the similar edges.

[0005] Figure 2A block diagram of an embodiment of the PFD circuit 12 is shown. The PFD circuit 12 includes a first D-type flip-flop (FF) circuit 14, which has a data (D) input that receives a logic high voltage (Vdd) and a clock (CLK) input that receives a reference clock signal CLKref(t). The output (Q) of the FF circuit 14 generates an up signal U(t). The PFD circuit 12 also includes a second D-type flip-flop (FF) circuit 16, which has a data (D) input that receives a logic high voltage (Vdd) and a clock (CLK) input that receives a feedback clock signal CLKfb(t). The output (Q) of the FF circuit 16 generates a down signal D(t). A logic AND gate 18 has a first input that receives the up signal U(t) and a second input that receives the down signal D(t). The gate 18 performs a logic AND operation on these signals to generate a reset signal, which is applied to the reset inputs of the first FF circuit 14 and the second FF circuit 16.

[0006] Figure 2 The waveforms of the upward signal U(t) and the downward signal D(t) are also shown in the following operating conditions, where: a) similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t) are aligned; b) the edge of the reference clock signal CLKref(t) leads the similar edge of the feedback clock signal CLKfb(t); and c) the edge of the feedback clock signal CLKfb(t) leads the similar edge of the reference clock signal CLKref(t). In conditions a), b), and c), the smaller pulse widths of the upward signal U(t) and the downward signal D(t) are controlled by the time delay (td) of the operation of the AND gate 18 to reset the first FF circuit 14 and the second FF circuit 16. This is the minimum pulse width of the upward signal U(t) and the downward signal D(t). In cases b) and c), the longer pulse widths of the corresponding upward signal U(t) and downward signal D(t) are controlled by the sum of the minimum pulse width (td) and the time difference (i.e., the phase difference pd) between the similar edges of the reference clock signal CLKref(t) and the feedback clock signal CLKfb(t).

[0007] Reference again Figure 1The charge pump (CP) circuit 20 generates an output current Icp(t) in response to the duration (i.e., width) of pulses of an upward signal U(t) and a downward signal D(t). The CP circuit 20 includes a current supply (path) circuit 20a that operates in response to the upward signal U(t) to provide a supply current contribution of a fixed amplitude (M) to the charge pump output current Icp(t), the duration of which corresponds to the duration of the upward signal U(t). The CP circuit 20 also includes a current absorption (path) circuit 20b that operates in response to the downward signal D(t) to provide an absorption current contribution of the same fixed amplitude (M) to the charge pump output current Icp(t), the duration of which corresponds to the duration of the downward signal D(t). The output current Icp(t) is the difference between the supply current contribution and the absorption current contribution. When the upward and downward signals have identical pulses, as described in case a) above, the output current Icp(t) is zero because the supply current contribution and absorption current contribution caused by the pulses of the upward signal U(t) and the downward signal D(t) cancel each other out. When the duration of the upward signal U(t) pulse is longer than the duration of the downward signal D(t) pulse, as described in case b) above, the output current Icp(t) includes an instantaneous supply current (current pulse 21a) with the fixed amplitude (M), and its duration is the difference in pulse width between the upward signal U(t) and the downward signal D(t). Conversely, when the duration of the downward signal D(t) pulse is longer than the duration of the upward signal U(t) pulse, as described in case c) above, the output current Icp(t) includes an instantaneous absorption current (current pulse 21b) with the fixed amplitude (M), and its duration is the difference in pulse width between the upward signal U(t) and the downward signal D(t).

[0008] A loop filter (LF) circuit 22 filters the output current Icp(t) from the charge pump circuit 20 to generate a control voltage Vctrl(t). In one embodiment, the LF circuit 22 is implemented as an analog integrator circuit, thus generating the control voltage Vctrl(t) by integrating the supply current and the sink current. Therefore, the control voltage Vctrl(t) increases incrementally in response to each current pulse 21a of the output charge pump current Icp(t) and decreases incrementally in response to each current pulse 21b of the output charge pump current Icp(t).

[0009] A voltage-controlled oscillator (VCO) circuit 30 generates an oscillation output signal Vout(t), the frequency of which is controlled by the level of a control voltage Vctrl(t). An increase in the level of the control voltage Vctrl(t) caused by a current pulse 21a of the output charge pump current Icp(t) results in a corresponding increase in the frequency of the oscillation output signal Vout(t). Conversely, a decrease in the level of the control voltage Vctrl(t) caused by a current pulse 21b of the output charge pump current Icp(t) results in a corresponding decrease in the frequency of the oscillation output signal Vout(t).

[0010] The fixed divider and level shifter circuit 32 divides the oscillating output signal Vout(t) by a fixed divisor and shifts the resulting signal level to the desired voltage level. As an example, the fixed division performed by circuit 32 can divide the frequency of the oscillating output signal Vout(t) by a desired integer (e.g., by 4). It should be understood that in some embodiments, the divisor will be equal to 1, and therefore no division will be performed. In this case, circuit 32 only performs the level shifting function. Additionally, it should be understood that the level shifting function of circuit 32 can be omitted if level shifting of the oscillating output signal Vout(t) is not required. In one embodiment, the level shifting and / or fixed division functions of circuit 32 can be integrated into the VCO circuit 30.

[0011] The programmable divider circuit 34 divides the oscillating output signal Vout(t) (divided and level-shifted if needed) to generate a feedback clock signal CLKfb(t). The programmable divider circuit 34 implements a programmable division ratio between the frequency of the oscillating output signal Vout(t) and the frequency of the feedback clock signal CLKfb(t). This programmable division ratio is set by a divisor control signal, which specifies an integer component INTdiv and a fractional component FRACdiv for the divisor.

[0012] The small-signal forward path gain of the PLL circuit 10 is proportional to the charge pump current Icp(t), the gain KVCO of the VCO circuit 30, and the resistance R of the loop filter circuit 22. Conventionally, Icp*R is kept constant by design. However, the expansion of the gain KVCO is fully reflected in the bandwidth of the PLL circuit 10. It should be recognized that the gain KVCO is highly dependent on process, temperature, and frequency variations. For example, the gain KVCO can vary by a factor of two, and up to eight, with variations in process, temperature, and frequency. The design of the PLL circuit 10 can reduce KVCO variation, but this will impose strict constraints on the achievable phase noise of the VCO circuit 30. To tolerate large KVCO variations, the PLL circuit 10 can utilize a large loop stabilizing capacitor (thus increasing the occupied circuit area) and higher power to keep jitter within specifications. However, in many circuit applications, a large circuit area and high power dissipation are not satisfactory.

[0013] Therefore, it is clear that some compensation for the change in VCO gain KVCO is a requirement for the operation of the PLL circuit. Summary of the Invention

[0014] In one embodiment, a circuit is provided for calibrating a variable amplitude charge pump current of a charge pump circuit in a phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) circuit. The circuit includes: a voltage generator circuit configured to apply a scan control voltage to the VCO circuit in a plurality of discrete steps, with voltage differences between steps, when the PLL circuit is in an open-loop configuration; a frequency measurement circuit configured to measure the frequency of a signal output from the VCO circuit at each step; and a processing circuit. The processing circuit operates to: determine a gain of the VCO circuit for each measurement frequency based on the difference between the measured frequencies between steps divided by the voltage differences between the steps; calculate a calibration amplitude for the variable amplitude charge pump current associated with each measurement frequency based on a constant divided by the determined gain for that measurement frequency; identify a measurement frequency among the measurement frequencies, the identified measurement frequency being closest to the desired frequency of the signal output from the VCO circuit; and control the variable amplitude charge pump circuit in the PLL circuit to generate a charge pump current with an amplitude equal to the calibration amplitude for a nominal charge pump current associated with the identified measurement frequency.

[0015] In one embodiment, the phase-locked loop (PLL) circuit includes: a phase-frequency detector configured to compare a reference signal with a feedback signal and generate an up control signal and a down control signal in response to the comparison; a variable amplitude charge pump circuit configured to generate a charge pump output current having an amplitude set in response to the up control signal and the down control signal; a loop filter configured to receive the charge pump output current and generate a control voltage; a voltage-controlled oscillator (VCO) circuit configured to generate an oscillator output signal in response to the control voltage; a loop divider circuit configured to generate a feedback signal based on the oscillator output signal using a frequency division set by a divisor control signal; and processing circuitry including a lookup table that associates multiple measured frequencies of the oscillator output signal with multiple corresponding calibration amplitudes for the charge pump output current. The processing circuit is configured to: determine the desired frequency of the signal output from the VCO circuit in response to the divisor control signal; identify a measurement frequency in a lookup table that is closest to the desired frequency; and generate a digital control signal to set the amplitude of the charge pump output current to be equal to the calibration amplitude associated with the identified measurement frequency.

[0016] In one embodiment, a method is provided for calibrating the charge pump current of a variable amplitude charge pump circuit in a phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) circuit. The method includes: placing the PLL circuit in an open loop, and while in the open loop: applying a scan control voltage to the VCO circuit at voltage differences between multiple discrete steps; measuring the frequency of a signal output from the VCO circuit at each step; determining a gain of the VCO circuit for each measurement frequency based on the difference between the measured frequencies divided by the voltage differences between the steps; calculating a calibration amplitude for the charge pump current associated with each measurement frequency based on a constant divided by the gain determined for that measurement frequency; identifying a measurement frequency among the measurement frequencies that is closest to the desired frequency of the signal output from the VCO circuit; controlling the variable amplitude charge pump circuit in the PLL circuit to generate a charge pump current with an amplitude equal to the calibration amplitude associated with the identified measurement frequency; and placing the PLL circuit in a closed loop. Attached Figure Description

[0017] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0018] Figure 1 This is a block diagram of a phase-locked loop (PLL) circuit;

[0019] Figure 2 Is Figure 1A block diagram of the phase-frequency detector circuit used in the PLL circuit;

[0020] Figure 3 This is a block diagram of the PLL circuit that implements parameter calibration;

[0021] Figure 4 yes Figure 3 A flowchart of the calibration operation mode of the PLL circuit;

[0022] Figure 5 yes Figure 3 A flowchart of the normal operating mode of the PLL circuit;

[0023] Figure 6 An example of a lookup table is shown, and its use in calibrating a PLL circuit is illustrated. Detailed Implementation

[0024] Figure 3 A block diagram of a phase-locked loop (PLL) circuit 50 for implementing parameter calibration is shown. Figure 1 and Figure 3 The same reference numerals in the figures refer to the same or similar components, circuits, parts, signals, etc., and for the sake of brevity, repeated discussion of them is omitted here. See the discussion above.

[0025] The PLL circuit 50 differs from [other circuits] in one respect. Figure 1 Circuit 10 utilizes a variable amplitude charge pump circuit 56 (also referred to by those skilled in the art as a current-to-analog converter (DAC) circuit). The charge pump circuit 56 operates in response to an assertion of an upward signal U(t) to provide a supply current contribution to the charge pump output current Icp(t). The charge pump circuit 56 also operates in response to an assertion of a downward signal D(t) to provide a sink current contribution to the charge pump output current Icp(t). However, with... Figure 1 The circuit 20 used (in which the amplitudes of current pulses 21a and 21b are fixed) is different. Circuit 56 generates supply current pulse 23a and absorb current pulse 23b for the charge pump output current Icp(t), each with a variable amplitude vM set by the digital value of the N-bit charge pump control signal 58.

[0026] Example implementations of the variable amplitude charge pump circuit 56 include N fixed amplitude charge pump circuits 20(1)-20(N) (e.g., similar to...). Figure 1The circuit used comprises N fixed-amplitude charge pump circuits 20(1)-20(N) coupled in parallel to generate a charge pump output current Icp(t). Each fixed-amplitude charge pump circuit 20 includes a current supply (path) circuit 20a that operates in response to an assertion of an upward signal U(t) to provide a supply current contribution and a current absorption (path) circuit 20b that operates in response to an assertion of a downward signal D(t) to provide an absorption current contribution. The fixed-amplitude charge pump circuits 20(1)-20(N) are enabled to operate in response to corresponding bits of the N-bit charge pump control signal 58. The entire circuit 56 is enabled in response to a control signal 68. When each fixed-amplitude charge pump circuit 20 generates a current pulse of the same amplitude, the variable amplitude of the current pulse of the charge pump output current Icp(t) is equal to the fixed amplitude multiplied by the number of bits in the N-bit charge pump control signal 58 that is asserted (e.g., logic high).

[0027] A further difference between PLL circuit 50 and PLL circuit 10 is the addition of a calibration circuit 54. Calibration circuit 54 operates to generate an N-bit charge pump control signal 58, used to set the variable amplitude of the current pulses output by the variable amplitude charge pump circuit 56. The calibration circuit 54 is programmed using knowledge of the gain KVCO of the VCO circuit 30 within the output frequency range of the oscillating output signal Vout(t). Using this knowledge, and the specification of the frequency relationship between the reference clock signal CLKref(t) set by the total loop divisor of the PLL circuit and the oscillating output signal Vout(t), calibration circuit 54 selects digital values ​​for the N-bit charge pump control signal 58 to generate current pulses 23a and 23b with variable amplitude, such that the product of the charge pump current Icp(t) and the gain KVCO equals a certain (nominal) constant value.

[0028] The calibration circuit 54 includes a variable voltage generator circuit 60 configured to generate an output voltage Vswp, which is controlled in response to a voltage control signal 62. In one embodiment, the voltage control signal 62 is a P-bit digital signal, wherein the digital value of the voltage control signal 62 sets the instantaneous amplitude of the output voltage Vswp.

[0029] The calibration circuit 54 also includes a loop switch (SW) 66, which is selectively controlled by a control signal 68. The switch 66 has a first input coupled to receive the charge pump current Icp(t) and a second input coupled to receive the output voltage Vswp. When the switch 66 is controlled by the control signal 68 in the first connected state, the loop of the PLL circuit 50 is closed (whereby the charge pump circuit 56 is enabled to operate), and the output charge pump current Icp(t) is applied to the loop filter 22. This conforms to the normal operating mode of the PLL circuit 50, in which the control voltage Vctrl(t) of the VCO circuit 30 is driven in response to the charge pump current Icp(t). Conversely, when the switch 66 is controlled by the control signal 68 in the second connected state, the loop of the PLL circuit 50 is open (whereby the charge pump circuit 56 is disabled), and the output voltage Vswp is applied to the loop filter 22. This is consistent with the calibration operation mode of PLL circuit 50, in which the control voltage Vctrl(t) of VCO circuit 30 is driven in response to the output voltage Vswp.

[0030] The calibration circuit 54 also includes a frequency measurement circuit 72, which is coupled to receive (if necessary, divided and level-shifted) the oscillation output signal Vout(t). The frequency measurement circuit 72 operates to generate an M-bit digital signal 74, which indicates the measured frequency (f_meas) of the oscillation output signal Vout(t). In one example embodiment, the frequency measurement circuit 72 includes a counter circuit that operates to count the number of periods of the oscillation output signal Vout(t) occurring within a specific number of periods of a reference clock signal CLKref(t), (if necessary, divided and level-shifted). The determined count value is output as an M-bit digital signal 74 indicating the measured frequency. In this embodiment, the measured frequency can be calculated by the following formula:

[0031]

[0032] Where: count is the count value generated by the counter circuit; DIV is the fixed divider value (if any) used by the fixed divider and level shifter circuit 32; fref is the frequency of the reference clock signal CLKref(t); and cycle# is a specific number of periods of the reference clock signal CLKref(t) during which counting is performed. It should be understood that circuits other than the counter circuit can be used as suitable frequency measurement circuits.

[0033] For example, the digital processing circuit, implemented as a state machine circuit 80, receives an M-bit digital signal 74, a reference clock signal CLKref(t), and an integer component INTdiv and a fractional component FRACdiv that set the programmable allocation ratio of the programmable divider circuit 34. The digital processing circuit 80 generates an N-bit charge pump control signal 58, a P-bit voltage control signal 62, and a switch control signal 68.

[0034] Figure 4 A flowchart of the calibration operation mode is shown. The operation of the digital processing circuit 80 combined with the calibration operation mode of the PLL circuit 50 is implemented as follows: The switch control signal 68 controls the switch 66 to enter the second connection state, in which the loop of the PLL circuit 50 is disconnected (step 100). In this case, the charge pump circuit 56 is also disabled by the switch control signal 68. The P-bit voltage control signal 62 sets the amplitude of the output voltage Vswp generated by the variable voltage generator circuit 60 and applied to the loop filter 22 by the switch 66. The initial value of the Vswp level is set in step 100 and then incremented in step 110. After taking into account the operation of the loop filter 22 (step 102) and allowing a stable waiting delay, the control voltage Vctrl(t) of the VCO circuit 30 will be equal to the output voltage Vswp, and the frequency of the oscillating output signal Vout(t) is therefore controlled by the output voltage Vswp. The frequency measurement circuit 72 measures the oscillating output signal Vout(t) and generates an M-bit digital signal 74 indicating the measured frequency (step 102). The calculation of the measured frequency f_meas can be performed by the digital processing circuit 80, or directly provided by the frequency measurement circuit 72. Then, the measured frequency is recorded in the memory of the digital processing circuit 80 using a lookup table (LUT) 82 (see...). Figure 6 ).

[0035] Digital processing circuit 80 can control the generation of the value of P-bit voltage control signal 62 so that variable voltage generator circuit 60 scans the output voltage Vswp within a desired voltage range (e.g., from the minimum control voltage level to the maximum control voltage level of VCO circuit 30), thereby scanning the control voltage Vctrl(t) of VCO circuit 30. This scanning of the control voltage Vctrl(t) can be performed in multiple discrete steps (identified by indices i from 1 to n), where a constant voltage step size (ΔV) exists between successive steps. This is achieved by testing in step 108 whether the final increment of the Vswp level has been reached, and if not, increasing the Vswp level by the constant voltage step size in step 110 before returning to step 102. In step 102, for each step in the scan of control voltage Vctrl(t), the oscillating output signal Vout(t) is measured, and at each index i of the Vswp level, the measured frequency is calculated and stored in lookup table 82.

[0036] Then, in step 104, the digital processing circuit 80 calculates the gain KVCO of the VCO circuit 30 for each step of the control voltage Vctrl(t) based on the voltage level difference of the output voltage Vswp (i.e., the constant voltage step size ΔV), according to two consecutive measurement frequencies of the oscillating output signal Vout(t), which are generated based on the output voltage Vswp. Specifically, the gain KVCO of the (i+1)th step is given by the following formula:

[0037]

[0038] Where: f_meas i+1 It is the measurement frequency at the (i+1)th step; f_meas i It is the measurement frequency at the i-th step, and ΔV is the amplitude difference (Vswp) of the output voltage at these two frequencies. i+1 -Vswp i The calculated gain KVCO value is compared with the measured frequency f_meas at the (i+1)th step. i+1 The calculated VCO gain KVCO is associated with each discrete measurement frequency step of the oscillation output signal Vout(t) and stored in lookup table 82 (step 104). When the calibration operation mode is completed, lookup table 82 will store the calculated VCO gain KVCO associated with each discrete measurement frequency step of the oscillation output signal Vout(t).

[0039] Then, in step 106, the digital processing circuit 80 determines the calculated calibration amplitude ical of the variable amplitude vM of the charge pump pulses 23a and 23b generated by the charge pump circuit 56 of the PLL circuit 50 according to the following relationship:

[0040]

[0041] Where: ICP_KVCO_Product is the expected product of the nominal charge pump current and the gain KVCO to be kept constant (i.e., this is a specific constant value, as mentioned above, which is the nominal product that must be maintained for PLL circuit operation regardless of the operating frequency), and KVCO i It is found in table 82 for the measurement frequency f_meas corresponding to the i-th step. i The VCO gain KVCO is calculated. Then, the digital processing circuit 80 converts this calculated calibrated amplitude of the charge pump current pulse vM into a variable amplitude. i The measurement frequency f at the i-th step i It is stored in lookup table 82 in association (step 106).

[0042] refer to Figure 6 It should be noted that for i=1, there is no calculated amplitude for the gain KVCO or the variable amplitude vM, because these values ​​depend on access to the two measurement frequencies. If desired, the values ​​for i=1 can be extrapolated from other calculated values.

[0043] Then, in step 108, it is determined whether the final Vswp level has been reached. If not, the Vswp level is increased in step 110, and the process returns to step 102. If yes, the calibration operation mode ends, and lookup table 82 is completely filled.

[0044] Figure 5 A flowchart illustrating the normal operating mode of the PLL circuit 50 is shown. The operation of the digital processing circuit 80 and the implementation of the normal operating mode of the PLL circuit 50 are as follows: Based on the frequency of the input reference clock signal CLKref(t), the input integer component INTdiv, and the input fractional component FRACdiv, and knowing the fixed divisor (if any) implemented by the fixed divider and level shift circuit 32, the digital processing circuit 80 can calculate the desired frequency f of the oscillation output signal Vout(t) in step 120 according to the following formula. VCO_des :

[0045] f VCO_des =f ref* (integer#+fractional#)

[0046] Where: f refThis is the frequency of the reference clock signal CLKref(t), integer# is the total integer divisor value (here equal to INTdiv plus the fixed divisor of circuit 32), and fractional# is the total fractional divisor value (here equal to FRACdiv). Then, the desired frequency f is... VCO_des The measured frequency f_meas of the oscillation output signal Vout(t) stored in lookup table 82 i Comparison (e.g., Figure 6 Reference numerals 123, where f VCO_des It was determined to be the closest to f_meas3). This comparison operation is used in step 122 to identify the calibration amplitude ical used for the calculation of the variable amplitude vM. i The measured frequency fi of the oscillation output signal Vout(t) of the variable amplitude vM in LUT 82 most closely matches the desired frequency f. VCO_des Then, in step 124, the digital processing circuit 80 generates a digital value for the N-bit charge pump control signal 58, which causes the current-to-analog (D / A) converter circuit supplied by the charge pump 56 to generate pulses 23a and 23b of the charge pump current Icp(t), the amplitude of which vM substantially matches the identified calculated calibration amplitude ical. i (see Figure 6 (Referring to reference 125, an example of control signal 58 setting circuit 56 to generate a pulse of charge pump current with an amplitude of ical3). Then, in step 126, digital processing circuit 80 generates switch control signal 68 to control switch 66 to enter a first connection state in which the loop of PLL circuit 50 is closed.

[0047] The calibration scheme disclosed herein has the advantage of being independent of the architecture used for the VCO circuit 30. Furthermore, because the gain KVCO is actually measured on-chip by the calibration circuit 54 to calculate the amplitude ical of the variable amplitude vM charge pump current pulse, the scheme is more robust. Moreover, the scheme does not inject any significant error into the loop of the PLL circuit. In fact, the injected error is limited because: a) any analog amplifier gain error can be reduced by increasing the amplifier gain (without strict limitations on amplifier bandwidth); b) the calculations of f_meas, KVCO, and ical are based on measurements using a digital counter exhibiting predictable and controllable errors; and c) using the LUT 82 that correlates f_meas and ical has the advantage of eliminating any frequency-to-voltage and / or voltage-to-frequency conversion errors, since the desired frequency f VCO_des It is directly compared with the measured frequency f_meas in the LUT.

[0048] In summary, to meet the closely related PLL specifications of area, power, and jitter, it is necessary to control the PLL bandwidth and its expansion. The calibration scheme described above can be used to achieve this goal. The PLL loop is disconnected and then calibrated to keep the product of the charge pump current Icp and the gain KVCO constant. The calibration scheme measures the gain KVCO by scanning the VCO control voltage over a range of values, measuring the VCO output frequency at each control voltage level, and calculating the charge pump current pulse amplitude ical, such that the product Icp*KVCO is constant at a predefined (nominal) value. A lookup table associates each measured frequency with the corresponding calculated charge pump current amplitude ical. Once calibration is complete, the PLL loop is closed, and the desired output frequency f of the PLL circuit is determined. VCO_des The calculated charge pump current amplitude ical is obtained from the lookup table. Then, the variable amplitude vM of the current pulse generated by the charge pump circuit of the PLL circuit is controlled to be substantially equal to the obtained charge pump current amplitude ical.

[0049] It should be noted that the correct configuration of the PLL circuit is automated in response to changes in the desired VCO output frequency. Frequency changes are achieved by the user by modifying the input integer component INTdiv and / or the input fractional component FRACdiv. The digital processing circuit 80 will calculate the new desired frequency f. VCO_des Find the closed measurement frequency f_meas in LUT 82 and obtain the corresponding calculated charge pump current amplitude ical to generate an N-bit charge pump control signal 58 with variable amplitude vM to control the charge pump output current pulse in response to the change.

[0050] Regarding the issue of temperature changes, the digital processing circuit 80 can switch back to calibration operation mode. Figure 4 The system generates an updated LUT 82 that takes into account the VCO's operation at the current temperature level. A new calibration operation mode can be triggered in response to a significant change in temperature sensed by the temperature sensor 84 coupled to the digital processing circuitry 80. Alternatively, the calibration process can be pre-performed at multiple temperatures to generate a separate LUT 82 at each temperature level. The digital processing circuitry 80 can then select one of the lookup tables to use in response to the temperature sensed by the temperature sensor 84.

[0051] While the invention has been shown and described in detail in the accompanying drawings and the foregoing description, such showing and description is to be considered illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. A circuit for calibrating the variable amplitude charge pump current of a charge pump circuit in a phase-locked loop (PLL) circuit, the PLL circuit including a voltage-controlled oscillator (VCO) circuit, the circuit comprising: A voltage generator circuit is configured to apply a scan control voltage to the VCO circuit in multiple discrete steps, with the voltage difference between the steps, when the PLL circuit is in an open-loop state. A frequency measurement circuit is configured to measure the frequency of the signal output from the VCO circuit at each discrete step; and The processing circuit is configured as follows: The gain of the VCO circuit is determined for each measurement frequency by dividing the difference in measurement frequencies between the discrete steps by the voltage difference between the discrete steps. The calibration amplitude for the variable amplitude charge pump current associated with each measurement frequency is calculated by dividing the constant by the gain determined for that measurement frequency. Identify a measurement frequency among the measurement frequencies, the identified measurement frequency being closest to the desired frequency of the signal output from the VCO circuit; as well as The variable amplitude charge pump circuit in the PLL circuit is controlled to generate a charge pump current with an amplitude equal to the calibration amplitude used for the nominal charge pump current, which is associated with an identified measurement frequency in the measurement frequency.

2. The circuit of claim 1 further includes a loop switch controlled by the processing circuit to place the PLL circuit in open loop during a calibration operation mode, in which the gain of the VCO circuit is determined and the calibration amplitude for the variable amplitude charge pump current is calculated.

3. The circuit of claim 2, wherein when in the calibration operation mode, the processing circuit further disables the variable amplitude charge pump circuit.

4. The circuit of claim 2, wherein the loop switch is further controlled by the processing circuit to place the PLL circuit in a closed loop during normal operation mode, in which a charge pump current of the variable amplitude charge pump circuit is generated having an amplitude equal to the calibration amplitude.

5. The circuit of claim 4, wherein when in the normal operating mode, the processing circuit further enables the variable amplitude charge pump circuit.

6. The circuit according to claim 1, wherein the processing circuit is a state machine circuit.

7. The circuit of claim 1, wherein the frequency measurement circuit includes a counter circuit configured to count the number of cycles of a signal output from the VCO circuit within a fixed time period, wherein the number of counted cycles indicates the measured frequency.

8. The circuit of claim 7, wherein the fixed time period is set by a specific number of cycles of the reference clock of the PLL circuit.

9. The circuit of claim 1, wherein the processing circuit is configured to control the voltage generator circuit to generate the scan control voltage.

10. The circuit of claim 1, wherein the variable amplitude charge pump circuit comprises: Multiple current circuits are connected in parallel, wherein each current circuit includes: A first current source is configured to supply a first current to the output of the charge pump circuit in response to a first phase difference detected by the PLL circuit; and The second current source is configured to draw a second current from the output of the charge pump circuit in response to a second phase difference detected by the PLL circuit. The multiple current circuits that are enabled to operate set the amplitude of the variable amplitude charge pump circuit to be equal to the calibration amplitude associated with one of the identified measurement frequencies.

11. The circuit of claim 1, wherein the voltage difference between the discrete steps is constant relative to all discrete steps of the scan control voltage.

12. A phase-locked loop (PLL) circuit, comprising: A phase-frequency detector is configured to compare a reference signal with a feedback signal and, in response to the comparison, generate an up control signal and a down control signal; A variable amplitude charge pump circuit is configured to generate a charge pump output current in response to the upward control signal and the downward control signal, the charge pump output current having an amplitude set in response to a digital control signal; A loop filter is configured to receive the charge pump output current and generate a control voltage; A voltage-controlled oscillator (VCO) circuit is configured to generate an oscillator output signal in response to the control voltage. The loop divider circuit is configured to generate the feedback signal based on the oscillator output signal by using a frequency division set by a divisor control signal; as well as The processing circuitry includes a lookup table that associates multiple measurement frequencies of the oscillator output signal with corresponding multiple calibration amplitudes for the charge pump output current, wherein the processing circuitry: In response to the divisor control signal, the desired frequency of the signal output from the VCO circuit is determined; Identify a measurement frequency in the lookup table, wherein the identified measurement frequency is closest to the desired frequency; as well as The digital control signal is generated to set the amplitude of the charge pump output current to be equal to the calibration amplitude associated with one of the identified measurement frequencies.

13. The circuit of claim 12, wherein the variable amplitude charge pump circuit comprises: Multiple current circuits are connected in parallel, wherein each current circuit includes: A first current source is configured to supply a first current to the output of the charge pump circuit in response to a first phase difference detected by the PLL circuit; and The second current source is configured to draw a second current from the output of the charge pump circuit in response to a second phase difference detected by the PLL circuit. The multiple current circuits that are enabled to operate set the amplitude of the charge pump output current to be equal to the calibration amplitude associated with one of the identified measurement frequencies.

14. The circuit of claim 12, further comprising a calibration circuit configured to generate the lookup table during a calibration operation mode.

15. The circuit of claim 14, wherein the calibration circuit comprises: A voltage generator circuit is configured to apply a scan control voltage to the VCO circuit in multiple discrete steps, with the voltage difference between the steps, when the PLL circuit is in an open-loop state. as well as A frequency measurement circuit is configured to measure the frequency of the signal output from the VCO circuit at each discrete step, and input the measured frequency as one of the measured frequencies into the lookup table.

16. The circuit of claim 15, wherein the processing circuit is configured to control the voltage generator circuit to generate the scan control voltage.

17. The circuit of claim 15, wherein the processing circuit is configured to: The gain of the VCO circuit is determined for each measurement frequency by dividing the difference in measurement frequencies between the discrete steps by the voltage difference between the discrete steps; and The calibration amplitude for the charge pump output current associated with each measurement frequency is calculated by dividing the constant by the gain determined for that measurement frequency.

18. The circuit of claim 14, further comprising a loop switch controlled by the processing circuit to place the PLL circuit in open loop during the calibration operation mode.

19. The circuit of claim 18, wherein when in the calibration operation mode, the processing circuit further disables the variable amplitude charge pump circuit.

20. The circuit of claim 18, wherein the loop switch is further controlled by the processing circuit to place the PLL circuit in a closed loop during a normal operating mode, wherein a charge pump output current of the variable amplitude charge pump circuit is generated having an amplitude equal to the calibration amplitude.

21. The circuit of claim 20, wherein when in the normal operating mode, the processing circuit further enables the variable amplitude charge pump circuit.

22. A method for calibrating the charge pump current of a variable amplitude charge pump circuit in a phase-locked loop (PLL) circuit, the PLL circuit including a voltage-controlled oscillator (VCO) circuit, the method comprising: The PLL circuit is placed in an open loop, and when in an open loop: In multiple discrete steps, a scan control voltage is applied to the VCO circuit based on the voltage difference between the steps; At each discrete step, the frequency of the signal output from the VCO circuit is measured; The gain of the VCO circuit is determined for each measurement frequency by dividing the difference in measurement frequencies between the discrete steps by the voltage difference between the discrete steps; and The calibration amplitude for the charge pump current associated with each measurement frequency is calculated by dividing the constant by the gain determined for that measurement frequency. Identify a measurement frequency among the measurement frequencies, the identified measurement frequency being closest to the desired frequency of the signal output from the VCO circuit; The variable amplitude charge pump circuit in the PLL circuit is controlled to generate a charge pump current with an amplitude equal to the calibration amplitude associated with one of the identified measurement frequencies. as well as The PLL circuit is placed in a closed loop.

23. The method of claim 22, further comprising: The variable amplitude charge pump circuit is disabled when in open-loop operation.

24. The method of claim 22, further comprising: The variable amplitude charge pump circuit is activated when in closed-loop operation.

25. The method of claim 22, wherein the frequency measurement comprises: The number of cycles of the signal output from the VCO circuit within a fixed time period is counted, wherein the number of counted cycles indicates the measurement frequency.

26. The method of claim 25, wherein the fixed time period is set by a specific number of cycles of the reference clock of the PLL circuit.

27. The method of claim 22, wherein the voltage difference between the discrete steps is constant relative to all discrete steps of the scan control voltage.

Images