A manufacturing method of a three-dimensional phase change memory and a three-dimensional phase change memory

Abstract

Embodiments of the present invention disclose a three-dimensional phase change memory and a manufacturing method thereof. The manufacturing method includes: providing a semiconductor structure, the semiconductor structure including a storage area and an alignment area, the storage area including a lower-layer first conductive wire and a lower-layer phase change memory cell structure stacked in sequence along a third direction, the lower-layer first conductive wire and the lower-layer phase change memory cell structure extending along a first direction perpendicular to the third direction; forming a first trench in the alignment area; depositing a lower-layer second conductive wire material layer, the lower-layer second conductive wire material layer covering the surface of the semiconductor structure and filling the first trench; etching the lower-layer phase change memory cell structure and the lower-layer second conductive wire material layer along a second direction intersecting with the first direction, so as to form a lower-layer phase change memory cell and a lower-layer second conductive wire extending along the second direction in the storage area, and forming a first alignment mark groove in the first trench.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional memory, and in particular to a manufacturing method of a three-dimensional phase change memory and a three-dimensional phase change memory. Background Art

[0002] A memory is a memory device used to store information in modern information technology. With the continuous increase in the requirements for integration and data storage density of various electronic devices, ordinary two-dimensional storage devices are increasingly difficult to meet the requirements. In this case, three-dimensional (3D) memories have emerged.

[0003] To obtain a high storage density, three-dimensional memories are usually configured to include a multi-layer stacked structure, and a complex stacked structure has higher requirements for the alignment process. Therefore, how to optimize the alignment process of multi-layer stacked three-dimensional memories has become an important research direction in the field of three-dimensional memories. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a manufacturing method of a three-dimensional phase change memory and a three-dimensional phase change memory to solve at least one problem in the background art.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows:

[0006] Embodiments of the present invention provide a manufacturing method of a three-dimensional phase change memory, the method comprising:

[0007] Providing a semiconductor structure, the semiconductor structure including a storage area and an alignment area, the storage area including a lower first conductive wire and a lower phase change memory cell structure body that are sequentially stacked along a third direction, and the lower first conductive wire and the lower phase change memory cell structure body extending along a first direction perpendicular to the third direction;

[0008] Forming a first trench in the alignment area;

[0009] Depositing a lower second conductive wire material layer, the lower second conductive wire material layer covering the surface of the semiconductor structure and filling the first trench;

[0010] Etching the lower phase change memory cell structure body and the lower second conductive wire material layer along a second direction intersecting with the first direction, so as to form a lower phase change memory cell and a lower second conductive wire extending along the second direction in the storage area, and form a first alignment mark groove in the first trench.

[0011] In the above solution, the depth of the first trench is greater than or equal to 20 nm.

[0012] In the above solution, the width of the first alignment mark groove is greater than or equal to 1 μm.

[0013] In the above solution, after etching the lower phase change memory cell structure and the lower second conductive wire material layer, the method further includes: growing an upper first conductive wire material layer and an upper phase change memory cell material stack, where the upper first conductive wire material layer and the upper phase change memory cell material stack form a depression at the first alignment mark groove, and the depression constitutes a first alignment mark.

[0014] In the above solution, after growing the upper first conductive wire material layer and the upper phase change memory cell material stack, the method further includes: etching the upper phase change memory stack material layer, the upper first conductive wire material layer, and the semiconductor structure located in the alignment area with the first alignment mark as an alignment reference point to form a second trench, and the second trench constitutes a second alignment mark.

[0015] In the above solution, after forming the second trench, the method further includes: etching the upper phase change memory stack material and the upper first conductive wire material layer located in the storage area with the second alignment mark as an alignment reference point to form an upper phase change memory cell structure and an upper first conductive wire extending in a second direction;

[0016] In the above solution, after forming the upper phase change memory cell structure and the upper first conductive wire extending in the second direction, the method further includes: depositing an upper second conductive wire material layer; etching the upper phase change memory cell structure and the upper second conductive wire material layer located in the storage area along a first direction; to form an upper phase change memory cell and an upper second conductive wire extending in the first direction.

[0017] In the above solution, before growing the upper first conductive wire material layer and the upper phase change memory cell material stack, it further includes: forming a dielectric layer on the semiconductor structure, and the dielectric layer fills the gaps between the lower phase change memory cells.

[0018] In the above solution, the semiconductor structure further includes a contact trench; before forming the lower second conductive wire material layer on the semiconductor structure, it further includes: filling a conductive material layer in the contact trench.

[0019] An embodiment of the present invention further provides a three-dimensional phase change memory, and the three-dimensional phase change memory is manufactured by using the method described in any one of the above.

[0020] The manufacturing method of a three-dimensional phase change memory and the three-dimensional phase change memory provided by an embodiment of the present invention. Among them, the manufacturing method includes: providing a semiconductor structure, the semiconductor structure includes a storage area and an alignment area, the storage area includes a lower-layer first conductive wire and a lower-layer phase change memory cell structure stacked in sequence along a third direction, and the lower-layer first conductive wire and the lower-layer phase change memory cell structure extend along a first direction perpendicular to the third direction; forming a first trench in the alignment area; depositing a lower-layer second conductive wire material layer, the lower-layer second conductive wire material layer covers the surface of the semiconductor structure and fills the first trench; etching the lower-layer phase change memory cell structure and the lower-layer second conductive wire material layer along a second direction intersecting the first direction to form a lower-layer phase change memory cell and a lower-layer second conductive wire extending along the second direction in the storage area, and forming a first alignment mark groove in the first trench. By first forming a first trench in the alignment area, then depositing a bottom word line material layer to fill the first trench, and forming a first alignment mark groove in the first trench in the embodiment of the present invention, the thickness of the lower-layer second conductive wire material layer in the first trench is effectively increased, thereby improving the quality of the subsequently formed first alignment mark groove, avoiding the damage of the first alignment mark groove by subsequent processes, increasing the alignment process window between device structures, and improving the problem of alignment deviation.

[0021] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present invention. Description of the Drawings

[0022] Figure 1 It is a flowchart of the manufacturing method of the three-dimensional phase change memory provided by an embodiment of the present invention;

[0023] Figures 2a to 2j It is a device structure diagram during the preparation of the three-dimensional phase change memory provided by an embodiment of the present invention;

[0024] Figure 3 It is an alignment mark pattern composed of a plurality of first alignment mark grooves.

[0025] Reference Numerals:

[0026] 20 - Substrate; 20a - Storage area; 20b - Alignment area; 21 - First interlayer filling layer; 22 - Second interlayer dielectric layer; 23 - Contact plug; 24 - Insulating layer; 25 - Lower first conductive wire; 25' - Lower first conductive wire material layer; 26 - Lower phase change memory cell; 26' - Lower phase change memory cell material layer; 26" - Lower phase change memory cell structure body, 261 - Lower first electrode; 261' - Lower first electrode material layer; 262 - Lower select gate layer; 262' - Lower select gate material layer; 263 - Lower second electrode; 263' - Lower second electrode material layer; 264 - Lower phase change memory layer; 264' - Lower phase change memory material layer; 265 - Lower third electrode layer; 265' - Lower third electrode material layer; 27 - Lower second conductive wire; 27' - Lower second conductive wire material layer; 28 - First trench; 281 - First alignment mark groove; 282 - First alignment mark; 283 - Second alignment mark; 29 - Contact trench; 291 - Conductive material layer; 30 - Dielectric layer; 31 - Upper first conductive wire; 31' - Upper first conductive wire material layer; 32 - Upper phase change memory cell; 32' - Upper phase change memory stack material; 32" - Upper phase change memory cell structure body; 321 - Upper first electrode; 321' - Upper first electrode material layer; 322 - Upper select gate layer; 322' - Upper select gate material layer; 323 - Upper second electrode; 323' - Upper second electrode material layer; 324 - Upper phase change memory layer; 324' - Upper phase change memory material layer; 325 - Upper third electrode layer; 325' - Upper third electrode material layer; 33 - Upper second conductive wire. Detailed implementation manners

[0027] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention disclosed can be completely conveyed to those skilled in the art.

[0028] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention can be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present invention; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0029] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0030] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that there must be a first element, component, region, layer or portion in the present invention.

[0031] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0033] In some related technologies, in a multi-layer stacked three-dimensional phase change memory, the memory cells belonging to different layers are aligned with each other in the vertical direction, and the top cell word line also needs to be aligned with the bottom cell word line. The above alignment needs to introduce alignment marks in the manufacturing process of the three-dimensional phase change memory to achieve.

[0034] However, in the above related technologies, considering the process and design aspects, the thickness of the bottom cell word line cannot be too thick, which results in a low depth and poor quality of the alignment mark groove formed based on the bottom cell word line. After subsequent processes such as etching and planarization, it often causes fatal wear to the alignment mark groove, and the alignment mark groove cannot effectively record the position information of the bottom cell word line, thus unable to achieve the alignment between the upper and lower device structures.

[0035] Based on this, the following technical solutions of the embodiments of the present invention are proposed:

[0036] The embodiments of the present invention provide a manufacturing method of a three-dimensional phase change memory. For details, please refer to Figure 1 。

[0037] As shown in the figure, the method includes the following steps:

[0038] Step 101: Provide a semiconductor structure, where the semiconductor structure includes a storage area and an alignment area. The storage area includes a lower-layer first conductive wire and a lower-layer phase change memory cell structure body that are sequentially stacked along a third direction. The lower-layer first conductive wire and the lower-layer phase change memory cell structure body extend along a first direction perpendicular to the third direction;

[0039] Step 102: Form a first trench in the alignment area;

[0040] Step 103: Deposit a lower-layer second conductive wire material layer, where the lower-layer second conductive wire material layer covers the surface of the semiconductor structure and fills the first trench;

[0041] Step 104: Etch the lower-layer phase change memory cell structure body and the lower-layer second conductive wire material layer along a second direction intersecting the first direction to form a lower-layer phase change memory cell and a lower-layer second conductive wire extending along the second direction in the storage area, and form a first alignment mark groove in the first trench.

[0042] In the embodiments of the present invention, by first forming a first trench in the alignment area, then depositing a bottom word line material layer to fill the first trench, and forming a first alignment mark groove in the first trench. It effectively increases the thickness of the lower-layer second conductive wire material layer in the first trench, thereby improving the quality of the subsequently formed first alignment mark groove, avoiding the damage to the first alignment mark groove by subsequent processes, increasing the alignment process window between device structures, and improving the problem of alignment deviation.

[0043] The following is combined with Figures 2a - 2j When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

[0044] The method starts at step 101, such as Figure 2b As shown, a semiconductor structure is provided, which includes a storage area 20a and an alignment area 20b, wherein the storage area 20a includes a lower first conductive line 25 and a lower phase change memory unit structure 26" which are sequentially stacked and distributed along a third direction, and the lower first conductive line 25 and the lower phase change memory unit structure 26" extend along a first direction perpendicular to the third direction.

[0045] In some embodiments, as shown in the attached Figure 2a As shown, the semiconductor structure provided includes: providing a substrate 20, forming a lower first conductive line material layer 25' and a lower phase change memory unit material layer stack 26' above the substrate; etching the lower first conductive line material layer 25' and the lower phase change memory unit material layer 26' along a first direction to form a lower first conductive line 25 and a lower phase change memory unit structure 26" extending along the first direction. Figure 2a and Figure 2b It is a plan view from the second direction. It should be understood that, in the three-dimensional space, the lower first conductive line 25 and the lower phase-change memory unit structure 26" extend in the first direction in a wall shape.

[0046] Here, the substrate may be a semiconductor substrate, and may include at least one single semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, and the silicon substrate may be doped or undoped. The lower first conductive line may be used as a bit line, and the material of the lower first conductive line includes but is not limited to tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0047] In some embodiments, the alignment region 20b is disposed adjacent to the storage region 20a. In an actual process, the semiconductor structure is formed on a wafer and may include a plurality of storage regions 20a and a plurality of alignment regions 20b. In subsequent processes, the alignment regions will be cut and removed from the wafer, and the storage regions 20a will be separated into a plurality of individual devices. In some embodiments, the alignment region 20b may also be annular, and the alignment region 20b surrounds the storage region 20a.

[0048] In one embodiment, the semiconductor structure further includes an insulating layer 24 located on the substrate 20, and a lower-layer first conductive wire material layer 25' and a lower-layer phase change memory cell material stack layer 26' are located within the insulating layer 24. The material of the insulating layer 24 includes, but is not limited to, insulating materials such as tetraethyl orthosilicate (TEOS), silicon dioxide, silicon nitride, or silicon oxynitride.

[0049] In one embodiment, the semiconductor structure further includes a first interlayer dielectric layer 21 and a second interlayer dielectric layer 22 located between the substrate 20 and the insulating layer 24, and the second interlayer dielectric layer 22 is located on the first interlayer dielectric layer 21. In a specific embodiment, a plurality of interconnects 211 are disposed within the first interlayer dielectric layer 21, and the second interlayer dielectric layer 22 is used to protect the interconnects 211. In a more specific embodiment, at least one of the interconnects 211 is electrically connected to the lower-layer first conductive wire 25 through a contact plug 23. Here, the material of the first interlayer dielectric layer 21 and the material of the insulating layer 24 may be the same. The material of the second interlayer dielectric layer 22 may include silicon nitride. The material of the interconnects 211 may include conductive materials such as tungsten, cobalt, copper, aluminum, graphene, or carbon nanotubes. The material of the contact plug 23 may include, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0050] In one embodiment, the lower phase change memory cell material stack 26' may include a lower first electrode material layer 261', a lower select gate material layer 262', a lower second electrode material layer 263', a lower phase change memory material layer 264', and a lower third electrode material layer 265' that are stacked in sequence along a third direction. The lower first electrode material layer 261', the lower select gate material layer 262', the lower second electrode material layer 263', the lower phase change memory material layer 264', and the lower third electrode material layer 265' are respectively used to form a lower first electrode 261, a lower select gate layer 262, a lower second electrode 263, a lower phase change memory layer 264, and a lower third electrode layer 265. The materials of the lower first electrode material layer 261', the lower second electrode material layer 263', and the lower third electrode material layer 265' may be the same. In a specific embodiment, the materials of the lower first electrode material layer 261', the lower second electrode material layer 263', and the lower third electrode material layer 265' include carbon materials, such as amorphous carbon or carbon nanotubes. The material of the lower select gate material layer 262 may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z etc. The material of the lower phase change memory material layer 264' may be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material.

[0051] In one embodiment, the lower phase change memory cell material stack 26' further includes an adhesive layer (not shown) on the lower surface of the lower first electrode material layer 261', an adhesive layer on the upper surface of the lower third electrode material layer, a barrier layer (not shown) between the lower second electrode material layer 263' and the lower phase change memory material layer 264', and a barrier layer (not shown) between the lower phase change memory material layer 264' and the lower third electrode material layer 265'. The material of the adhesive layer (not shown) includes metal nitrides, such as tungsten nitride or titanium nitride. The material of the barrier layer includes conductive materials such as tungsten, tantalum, and titanium nitride.

[0052] The above-mentioned layers are formed using one or more thin film deposition processes; specifically, the formation processes of the layer structures include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process, or a combination thereof.

[0053] Next, as shown in the appendix Figure 2c Execute step 102 to form a first trench in the alignment area. In actual operation, before forming the first trench, the gaps between the phase change memory cell structures 26" can also be filled with a filling material.

[0054] In some embodiments, the depth of the first trench is greater than or equal to 20 nm, and exemplary values can be 35 nm, 75 nm, or 95 nm. Thus, after subsequently depositing the lower second conductive wire material layer, the thickness of the lower second conductive wire material layer can be effectively increased, thereby improving the quality of the first alignment mark groove formed subsequently. In actual operation, the depth of the first trench can be 30 nm - 60 nm. Within the above depth range, the first alignment mark groove formed subsequently is less likely to be damaged by subsequent processes and can obtain obvious contrast to facilitate improving the alignment accuracy. In some specific embodiments, the depth of the first trench is less than or equal to 100 nm. Thus, when subsequently depositing the lower second conductive wire material layer, it is easy to fill the first trench and voids are not likely to be generated in the first trench, so as not to reduce the quality of the first alignment mark formed subsequently.

[0055] Next, as shown in the appendix Figure 2d Execute step 103 to deposit a lower second conductive wire material layer 27', and the lower second conductive wire material layer 27' covers the surface of the semiconductor structure and fills the first trench 28. The material of the lower second conductive wire material layer 27' includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some specific embodiments, the material of the lower second conductive wire material layer 27' is tungsten.

[0056] In some embodiments, the thickness of the lower second conductive wire material layer located above the storage area is less than or equal to 50 nm. Exemplarily, the thickness range of the lower second conductive wire material layer can be 20 nm - 45 nm, and more specifically, for example, 34 nm or 28 nm. The lower second conductive wire material layer is used to form a lower second conductive wire, and the lower second conductive wire can be used as a word line. Considering process and design aspects, the thickness of the lower second conductive wire material layer cannot be too thick. An overly thick lower second conductive wire material layer has a greater impact on etching, and a thinner lower second conductive wire material layer has good heat dissipation effect and low manufacturing cost.

[0057] In some embodiments, as shown in the appendix Figure 2cAs shown, the semiconductor structure further includes a contact trench 29; before forming the lower second conductive wire material layer on the semiconductor structure, it further includes: filling a conductive material layer 291 in the contact trench. The conductive material layer is filled to form a contact, and the contact is used for electrically connecting the lower second conductive wire and related devices. In some embodiments, the contact further includes an adhesive layer (not shown) located at the top of the contact trench.

[0058] In some embodiments, the contact trench and the first trench are formed simultaneously by the same process. In this way, one mask is saved, the cost is reduced, and the production efficiency is effectively improved.

[0059] In some embodiments, filling the conductive material layer in the contact trench includes: depositing a conductive material layer on the semiconductor structure, and planarizing the conductive material layer so that the lower phase change memory cell structure body is flush with the conductive material layer. Here, the conductive material layer can be filled by physical vapor deposition or chemical vapor deposition, etc., and the material of the conductive material layer can be the same as the material of the lower second conductive wire material layer. In actual operation, the planarization includes a chemical mechanical polishing process, a back etching process, or a combination thereof.

[0060] Finally, perform step 104, see Appendix Figure 2e , etch the lower phase change memory cell structure body 26” and the lower second conductive wire material layer 27’ along a second direction intersecting with the first direction to form a lower phase change memory cell 26 and a lower second conductive wire 27 extending along the second direction in the storage area, and form a first alignment mark groove 281 in the first trench 28. In actual operation, the first alignment mark groove and the lower second conductive wire satisfy a preset specific positional relationship, and the first alignment mark groove is used to form an alignment mark in subsequent processes. In actual operation, the first direction and the second direction can intersect, and in some specific embodiments, they can be perpendicular to each other. Specifically, the lower first electrode material layer 261’, the lower select gate material layer 262’, the lower second electrode material layer 263’, the lower phase change memory material layer 264’, and the lower third electrode material layer 265’ respectively form a lower first electrode 261, a lower select gate layer 262, a lower second electrode 263, a lower phase change memory layer 264, and a lower third electrode layer 265.

[0061] In one embodiment, the number of the first alignment mark grooves 281 is multiple, and the multiple first alignment mark grooves 281 can form any one of the alignment mark patterns commonly used in the art. In one specific embodiment, the multiple first alignment mark grooves 281 form multiple such as Figure 3The alignment mark pattern shown. In some embodiments, a plurality of first alignment mark grooves 281 extending in a first direction are arranged in parallel at equal intervals. In other embodiments, a plurality of first alignment mark grooves 281 extending in a second direction are arranged in parallel at equal intervals. Refer to the attached Figure 3 , in actual operation, the alignment mark pattern may include a plurality of first alignment mark grooves 281 extending in a first direction and in a second direction.

[0062] In one embodiment, the width of the first alignment mark groove is greater than or equal to 1 μm. Exemplarily, the width range of the first alignment mark groove may be, for example, 1.5 μm - 3 μm, and more specifically, for example, 1.75 μm or 2.5 μm. If the width of the first alignment mark groove is too narrow, it is not easy to form a depression after depositing the upper first conductive wire material layer and the upper phase change memory cell material stack subsequently, which is not conducive to forming the first alignment mark. At the same time, increasing the groove width can obtain obvious contrast to facilitate improving the alignment accuracy.

[0063] In one embodiment, refer to the attached Figure 2f and the attached Figure 2g , after etching the lower phase change memory cell structure body and the lower second conductive wire material layer, the method further includes: growing an upper first conductive wire material layer 31' and an upper phase change memory cell material stack 32', and depressions are formed in the upper first conductive wire material layer 31' and the upper phase change memory cell material stack 32' at the first alignment mark grooves 281, and the depressions constitute the first alignment marks 282. Thus, the position information of the first alignment mark grooves is transferred to the upper phase change memory cell material stack through the depressions.

[0064] In one embodiment, as shown in the attached Figure 2f , before growing the upper first conductive wire material layer and the upper phase change memory cell material stack, it further includes: forming a dielectric layer 30 on the semiconductor structure, and the dielectric layer 30 fills the voids between the lower phase change memory cells 26. Here, the dielectric layer 30 may be made of the same material as the insulating layer 24 to support the subsequent growth of the upper first conductive wire material layer.

[0065] In one embodiment, the upper phase change memory cell material stack 32' may include an upper first electrode material layer 321', an upper select gate material layer 322', an upper second electrode material layer 323', an upper phase change memory material layer 324', and an upper third electrode material layer 325' that are sequentially stacked and distributed in a third direction. The upper first electrode material layer 321', the upper select gate material layer 322', the upper second electrode material layer 323', the upper phase change memory material layer 324', and the upper third electrode material layer 325' are respectively used to form an upper first electrode 321, an upper select gate layer 322, an upper second electrode 323, an upper phase change memory layer 324, and an upper third electrode layer 325. The materials of the upper first electrode material layer 321', the upper second electrode material layer 323', and the upper third electrode material layer 325' may be the same. In a specific embodiment, the materials of the upper first electrode material layer 321', the upper second electrode material layer 323', and the upper third electrode material layer 325' include carbon materials, such as amorphous carbon or carbon nanotubes. The material of the upper select gate material layer 262 may include any suitable two-way threshold switch (OTS) material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z etc. The material of the upper phase change memory material layer 324' may be a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material.

[0066] In one embodiment, the upper phase change memory cell material stack 32' further includes an adhesive layer (not shown) on the upper surface of the upper first electrode material layer 321', an adhesive layer on the upper surface of the upper third electrode material layer 325', a barrier layer (not shown) between the upper second electrode material layer 323' and the upper phase change memory material layer 324', and a barrier layer (not shown) between the upper phase change memory material layer 324' and the upper third electrode material layer 325'. The material of the adhesive layer (not shown) includes metal nitrides, such as tungsten nitride or titanium nitride. The material of the barrier layer includes conductive materials such as tungsten, tantalum, and titanium nitride.

[0067] The above layers are formed using one or more thin film deposition processes; specifically, the formation processes of the layer structures include, but are not limited to, chemical vapor deposition (CVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, or combinations thereof.

[0068] In one embodiment, as shown in the Figure 2h accompanying drawings, after growing the upper first conductive line material layer and the upper phase change memory cell material stack, the method further includes: using the first alignment mark 282 as an alignment reference point to etch the upper phase change memory stack material layer 32', the upper first conductive line material layer 31', and the semiconductor structure located in the alignment region to form a second trench, and the second trench constitutes a second alignment mark 283. In this way, the subsequent relative position relationship between the second alignment mark and the lower second conductive line can be utilized to form the upper first conductive line aligned with the lower second conductive line.

[0069] In one embodiment, as shown in the Figure 2i accompanying drawings, after forming the second trench, the method further includes: using the second alignment mark 283 as an alignment reference point to etch the upper phase change memory stack 32' and the upper first conductive line material layer 31' located in the storage region to form an upper phase change memory cell structure 32" and an upper first conductive line 31 extending in the second direction. At this point in the process, through the improved high-quality first alignment mark groove of the present invention, the alignment process window can be increased, enabling the upper first conductive line and the lower second conductive line to be aligned one by one. Here, the upper first conductive line and the lower second conductive line are jointly used as word lines.

[0070] In one embodiment, as shown in the Figure 2j accompanying drawings, after forming the upper phase change memory cell structure and the upper first conductive line extending in the second direction, the method further includes: depositing an upper second conductive line material layer; etching the upper phase change memory cell structure 32" and the upper second conductive line material layer located in the storage region along the first direction; to form an upper phase change memory cell 32 and an upper second conductive line 33 extending in the first direction. Specifically, the upper first electrode material layer 321', the upper select gate material layer 322', the upper second electrode material layer 323', the upper phase change memory material layer 324', and the upper third electrode material layer 325' respectively form an upper first electrode 321, an upper select gate layer 322, an upper second electrode 323, an upper phase change memory layer 324, and an upper third electrode layer 325. Here, the upper second conductive line can be used as a bit line, and the material of the upper second conductive line includes but is not limited to tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

[0071] The present invention also provides a three-dimensional phase change memory, and the three-dimensional phase change memory is manufactured by using the method described in any one of the above.

[0072] It can be seen that in the embodiment of the present invention, a first trench is first formed in the alignment area, then a bottom word line material layer is deposited to fill the first trench, and a first alignment mark groove is formed in the first trench. This effectively increases the thickness of the lower second conductive wire material layer in the first trench, thereby improving the quality of the subsequently formed first alignment mark groove, avoiding damage to the first alignment mark groove in subsequent processes, increasing the alignment process window between device structures, and improving the problem of alignment deviation.

[0073] It should be noted that those skilled in the art can make possible transformations between the above step sequences without departing from the protection scope of the present invention.

[0074] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A manufacturing method of a three-dimensional phase change memory, characterized in that, Comprising: Providing a semiconductor structure, the semiconductor structure including a storage area and an alignment area, the storage area including a lower first conductive wire and a lower phase change memory cell structure stacked in sequence along a third direction, the lower first conductive wire and the lower phase change memory cell structure extending along a first direction perpendicular to the third direction; Forming a first trench in the alignment area; Depositing a lower second conductive wire material layer, the lower second conductive wire material layer covering the surface of the semiconductor structure and filling the first trench; Etching the lower phase change memory cell structure and the lower second conductive wire material layer to form a lower phase change memory cell and a lower second conductive wire extending along a second direction in the storage area, and forming a first alignment mark groove in the first trench.

2. The method according to claim 1, wherein The depth of the first trench is greater than or equal to 20 nm.

3. The method according to claim 1, wherein The width of the first alignment mark groove is greater than or equal to 1 μm.

4. The method according to claim 1, wherein After etching the lower phase change memory cell structure and the lower second conductive wire material layer, the method further includes: Growing an upper first conductive wire material layer and an upper phase change memory cell material stack, the upper first conductive wire material layer and the upper phase change memory cell material stack forming a depression at the first alignment mark groove, the depression constituting a first alignment mark.

5. The method according to claim 4, wherein After growing the upper first conductive wire material layer and the upper phase change memory cell material stack, the method further includes: Etching the upper phase change memory stack material layer, the upper first conductive wire material layer and the semiconductor structure located in the alignment area with the first alignment mark as an alignment reference point to form a second trench, the second trench constituting a second alignment mark.

6. The method according to claim 5, wherein After forming the second trench, the method further includes: Etching the upper phase change memory stack material and the upper first conductive wire material layer located in the storage area with the second alignment mark as an alignment reference point to form an upper phase change memory cell structure and an upper first conductive wire extending along a second direction.

7. The method according to claim 6, characterized in that, After forming the upper phase change memory cell structure and the upper first conductive wire extending along a second direction, the method further includes: Depositing an upper second conductive wire material layer; Etching the upper phase change memory cell structure and the upper second conductive wire material layer located in the storage area; to form an upper phase change memory cell and an upper second conductive wire extending along a first direction.

8. The method according to claim 4, wherein Before growing the upper first conductive wire material layer and the upper phase change memory cell material stack, it further includes: Forming a dielectric layer on the semiconductor structure, the dielectric layer filling the gaps between the lower phase change memory cells.

9. The method according to claim 1, wherein The semiconductor structure further includes a contact trench; Before forming the lower second conductive wire material layer on the semiconductor structure, it further includes: filling a conductive material layer in the contact trench.

10. A three-dimensional phase change memory, characterized in that, The three-dimensional phase change memory is fabricated by the method according to any one of claims 1-9.

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