Phase change memory and its manufacturing method

Abstract

Embodiments of the present disclosure disclose a phase change memory and a method for manufacturing the same. The phase change memory includes: a phase change memory cell, including: a first electrode layer, a phase change memory layer, and a second electrode layer that are sequentially stacked from bottom to top; the phase change memory cell further includes: a conductive buffer layer located between the first electrode layer and the phase change memory layer, and / or located between the phase change memory layer and the second electrode layer, for buffering the stress generated during the phase change between the crystalline state and the amorphous state of the phase change memory layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a phase change memory and a method for manufacturing the same. Background Art

[0002] A phase change memory (PCM) is a resistive non-volatile memory, which has the advantages of high-speed reading, high erasable and writable times, non-volatility, small element size, low power consumption, etc. Moreover, the phase change memory can also obtain a high storage density through three-dimensional stacking, and is considered to be a new type of non-volatile memory with great development prospects.

[0003] The phase change memory uses a phase change material (such as a chalcogenide compound) as the storage medium, and uses the low-resistance state corresponding to the crystalline state and the high-resistance state corresponding to the amorphous state of the phase change material to write "1" and "0" respectively, so as to realize data storage. However, there are still some problems affecting its reliability in the phase change memory, which need to be solved urgently. Summary of the Invention

[0004] According to a first aspect of the present disclosure, there is provided a phase change memory, including:

[0005] A phase change storage unit, including: a first electrode layer, a phase change storage layer, and a second electrode layer stacked in sequence from bottom to top;

[0006] The phase change storage unit further includes: a conductive buffer layer, located between the first electrode layer and the phase change storage layer, and / or, located between the phase change storage layer and the second electrode layer, for buffering the stress generated during the transformation process of the phase change storage layer between the crystalline state and the amorphous state.

[0007] In some embodiments, the buffer layer includes a material having a quasi-two-dimensional structure.

[0008] In some embodiments, the crystallization temperature of the buffer layer is less than the crystallization temperature of the phase change storage layer.

[0009] In some embodiments, the material of the buffer layer includes at least one of antimony, tellurium, bismuth, antimony telluride, or bismuth telluride.

[0010] In some embodiments, the buffer layer includes:

[0011] A first sub-buffer layer and a second sub-buffer layer; wherein, the second sub-buffer layer is located between the first sub-buffer layer and the phase change storage layer;

[0012] The material of the first sub-buffer layer includes at least one of antimony, tellurium, or bismuth;

[0013] The material of the second sub-buffer layer includes antimony telluride and / or bismuth telluride.

[0014] According to a second aspect of the present disclosure, there is provided a method for manufacturing a phase change memory, including:

[0015] Forming a first electrode layer, a first buffer layer, a phase change memory layer, and a second electrode layer that are stacked in sequence from bottom to top; wherein, the first buffer layer is conductive, and the first buffer layer is used to buffer the stress generated during the crystalline state and amorphous state transition process of the phase change memory layer.

[0016] In some embodiments, the manufacturing method further includes:

[0017] After forming the phase change memory layer, forming a conductive second buffer layer on the phase change memory layer; wherein, the second buffer layer is located between the phase change memory layer and the second electrode layer, and is used to buffer the stress generated during the crystalline state and amorphous state transition process of the phase change memory layer.

[0018] According to a third aspect of the present disclosure, there is provided a method for manufacturing a phase change memory, including:

[0019] Forming a first electrode layer, a phase change memory layer, a buffer layer, and a second electrode layer that are stacked in sequence from bottom to top; wherein, the buffer layer is conductive, and the buffer layer is used to buffer the stress generated during the crystalline state and amorphous state transition process of the phase change memory layer.

[0020] In some embodiments, the buffer layer includes a material having a quasi-two-dimensional structure; and / or,

[0021] The crystallization temperature of the buffer layer is less than the crystallization temperature of the phase change memory layer; and / or,

[0022] The material of the buffer layer includes at least one of antimony, tellurium, bismuth, antimony telluride, or bismuth telluride.

[0023] In some embodiments, the buffer layer includes: a first sub-buffer layer and a second sub-buffer layer;

[0024] The step of forming the buffer layer includes:

[0025] Forming the stacked first sub-buffer layer and the second sub-buffer layer; wherein, the material of the first sub-buffer layer includes at least one of antimony, tellurium, or bismuth, and the material of the second sub-buffer layer includes antimony telluride and / or bismuth telluride.

[0026] In the embodiments of the present disclosure, a buffer layer is provided between the first electrode layer and the phase change memory layer, and / or a buffer layer is provided between the second electrode layer and the phase change memory layer. The buffer layer can reduce the stress generated during the transition between the crystalline state and the amorphous state of the phase change memory layer, buffer the influence of the stress on the phase change process of the phase change memory layer, reduce the probability of damage to the phase change memory layer, and reduce the probability of peeling between the phase change memory layer and the first electrode layer and the second electrode layer, thereby improving the reliability and service life of the phase change memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. is a schematic structural diagram of a phase change memory provided by an embodiment of the present disclosure;

[0028] Figure 2 is Figure 1 a cross-sectional view of the phase change memory shown;

[0029] Figure 3 FIG. is a schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0030] Figure 4 FIG. is a schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0031] Figure 5 FIG. is a schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0032] Figure 6a FIG. is a schematic structural diagram of a first electrode layer and a buffer layer provided by an embodiment of the present disclosure;

[0033] Figure 6b FIG. is a schematic structural diagram of another first electrode layer and a buffer layer provided by an embodiment of the present disclosure;

[0034] Figure 7 FIG. is a schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0035] Figure 8 FIG. is a schematic flow chart of a method for manufacturing a phase change memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings of the specification and specific embodiments.

[0037] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "depth", "upper", "lower", "outer", etc. is based on the orientation or positional relationship shown in the drawings. These terms are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0038] Figure 1 FIG. is a schematic structural diagram of a phase change memory provided by an embodiment of the present disclosure. Figure 2 is Figure 1 a partial cross-sectional view of the phase change memory shown. As Figure 1 and Figure 2 shown, the phase change memory includes a bit line 10 extending in the X direction and a word line 70 extending in the Y direction. In the Z direction, the bit line 10 and the word line 70 are alternately stacked. The phase change memory cell is located at the intersection of the bit line 10 and the word line 70, and each phase change memory cell has the same structure. Specifically, each phase change memory cell includes a bottom electrode 20, a select layer 30, an intermediate electrode 40, a phase change memory layer 50, and a top electrode 60 stacked in sequence along the Z direction.

[0039] The basic principle of the phase change memory is as follows: When a narrow and strong electrical pulse is applied to the phase change memory cell, due to the Joule heat and other effects, a part of the phase change memory layer in the initial crystalline state melts because the temperature is higher than the melting temperature. After the electrical pulse is interrupted, the molten part rapidly cools and stays in the amorphous state with low atomic order, thus completing the conversion from low resistance to high resistance. This is the erasing (Reset) process. In this process, the molten part is called the programming volume. If a relatively wide and medium-strength electrical pulse is applied, so that the temperature within the programming volume reaches above the crystallization temperature and below the melting temperature, and lasts for a sufficient time to crystallize the amorphous structure within the programming volume, a low-resistance state is obtained. This is the writing (Set) process.

[0040] In the reversible phase change process of the phase change memory layer between the crystalline state and the amorphous state, in addition to the change in resistivity, there are also changes in physical properties such as density, Young's modulus, coefficient of thermal expansion, and thermal conductivity. These changes in physical properties cause stresses such as thermal stress and phase change stress in the phase change memory layer during the phase change process. The release of these stresses will cause structural damage to the phase change memory cell, such as the peeling of the phase change memory layer and the intermediate electrode layer, thereby leading to deterioration of the durability of the phase change memory cell.

[0041] In addition, when the phase change memory cell includes multiple layers of different nano-sized materials arranged in a stacked manner, and there are significant differences in physical properties such as lattice constant, Young's modulus, and coefficient of thermal expansion among these materials, it will also cause non-negligible stress in the phase change memory cell. This stress can usually be eliminated by high-temperature annealing process. However, the high-temperature annealing process is not applicable to phase change memories. The reason is that the bit lines, word lines, and some electrodes of phase change memories usually use metal materials such as tungsten, cobalt, and copper. To eliminate the stress between the metal materials and other materials (such as phase change materials), the temperature generally needs to be raised to the thermal annealing temperature of the metal materials, and the thermal annealing temperatures of these metal materials far exceed the temperature range that the phase change materials can withstand.

[0042] For example, taking the material of the phase change storage layer as germanium antimony tellurium compound, it usually crystallizes in the range of 160 °C to 200 °C. Considering the physical properties of other materials (such as the select gate layer) in the phase change memory cell, the temperature of the entire process line of the general phase change memory is controlled below 350 °C. The annealing temperature of tungsten is generally 700 °C to 800 °C. At such a high temperature, the structures of the phase change storage layer and the select gate layer will be damaged, resulting in the scrapping of the phase change memory.

[0043] In view of this, the embodiments of the present disclosure provide a phase change memory, as Figure 3 shown. The phase change memory includes: a phase change memory cell 200, and the phase change memory cell 200 includes: a first electrode layer 201, a phase change storage layer 202, and a second electrode layer 203 that are sequentially stacked from bottom to top;

[0044] The phase change memory cell 200 further includes: a conductive buffer layer 204, located between the first electrode layer 201 and the phase change storage layer 202, for buffering the stress generated during the phase change between the crystalline state and the amorphous state of the phase change storage layer 202.

[0045] Here, the up-down direction is defined as the Z direction. The phase change memory further includes a first conductive line 100 and a second conductive line 300, which are respectively disposed at both ends of the phase change memory cell 200 along the Z direction. The first conductive line 100 and the second conductive line 300 are perpendicular to each other and both perpendicular to the Z direction. Exemplarily, the first conductive line 100 is parallel to the X direction, and the second conductive line 300 is parallel to the Y direction. Here, the first conductive line 100 can be a bit line, and the second conductive line 300 is a word line. Or, the first conductive line 100 can be a word line, and the second conductive line 300 is a bit line.

[0046] See Figure 3, the phase change memory cell 200 provided by the embodiments of the present disclosure further includes a selection layer 206 and a third electrode layer 207. Among them, the third electrode layer 207 is located on the side of the first electrode layer 201 relatively far from the phase change memory layer 202, and the selection layer 206 is located between the third electrode layer 207 and the first electrode layer 201.

[0047] In some embodiments, the third electrode layer 207 may also be located on the side of the second electrode layer 203 relatively far from the phase change memory layer 202, and the selection layer 206 is located between the third electrode layer 207 and the second electrode layer 203.

[0048] Exemplarily, the material of the phase change memory layer 202 includes at least one of the following: germanium telluride (Ge-Te) compound; antimony telluride (Sb-Te) compound; germanium antimony telluride (Ge-Sb-Te) compound; silicon antimony telluride (Si-Sb-Te) compound; titanium antimony telluride (Ti-Sb-Te) compound; aluminum antimony telluride (Al-Sb-Te) compound. In some embodiments, the constituent material of the phase change memory layer 202 may also include a mixture formed by doping at least one of elements such as carbon, nitrogen, oxygen, bismuth, or tin into the above compounds.

[0049] Exemplarily, the materials of the first electrode layer 201, the second electrode layer 203, and the third electrode layer 207 include at least one of the following: carbon, amorphous carbon, titanium nitride, tantalum nitride, tantalum carbide, metal (the metal may include copper, tungsten, aluminum, gold, cobalt, titanium, or tantalum, etc.). The materials of the first electrode layer 201, the second electrode layer 203, and the third electrode layer 207 may be the same or different.

[0050] Exemplarily, the material of the selection layer 206 may include an Ovonic Threshold Switch (OTS) material. The Ovonic Threshold Switch material may include a chalcogenide compound, such as zinc telluride, zinc selenotelluride, germanium selenide, etc. In some embodiments, the selection layer 206 may also be a diode, and the diode may include a PN junction formed by a P-doped semiconductor material and an N-doped semiconductor material.

[0051] In the embodiments of the present disclosure, the buffer layer 204 is set to have conductivity to reduce the influence of the buffer layer 204 on the electrical performance of the phase change memory cell 200. The electrical performance includes threshold voltage, read voltage, etc.

[0052] It can be understood that if the resistivity of the buffer layer 204 is high, then after the buffer layer 204 is added to the phase change memory cell 200, the current flowing through the phase change memory cell 200 will decrease, resulting in a decrease in the partial voltage of the select layer 206 and an increase in the total partial voltage of the phase change memory layer 202 and the buffer layer 204, thereby causing a relatively large change in the electrical properties of the phase change memory cell 200 (for example, the threshold voltage will increase). In the embodiments of the present disclosure, since the buffer layer 204 has conductivity, adding the buffer layer 204 to the phase change memory cell 200 has a relatively small or even negligible impact on the partial voltage of the phase change memory cell 200, and thus has a relatively small or even negligible impact on the electrical properties of the phase change memory cell 200.

[0053] Generally, the region where the phase change memory layer 202 undergoes the crystalline and amorphous state transitions (i.e., the programming volume) is closer to the side of the phase change memory layer 202 that is relatively close to the select layer 206. Therefore, by disposing the buffer layer 204 between the first electrode layer 201 and the phase change memory layer 202, the stress generated during the crystalline and amorphous state transitions of the phase change memory layer 202 can be buffered well.

[0054] It can be understood that in some embodiments, when the third electrode layer 207 is located on the side of the second electrode layer 203 that is relatively far from the phase change memory layer 202, and the select layer 206 is located between the third electrode layer 207 and the second electrode layer 203, the conductive buffer layer 204 can be located between the phase change memory layer 202 and the second electrode layer 203 to buffer well the stress generated during the crystalline and amorphous state transitions of the phase change memory layer 202.

[0055] In the embodiments of the present disclosure, when the phase change memory material within the programming volume in the phase change memory layer 202 undergoes a transition between the crystalline and amorphous states, due to the different densities of the phase change memory material in the crystalline and amorphous states, the volume size of the programming volume will change, generating phase change stress. The buffer layer 204 located between the first electrode layer 201 and the phase change memory layer 202 can adapt to the volume size change of the programming volume by deforming, thereby buffering the phase change stress.

[0056] Furthermore, during the crystalline and amorphous state transitions of the phase change memory layer 202, the phase change memory layer 202 and the first electrode layer 201 are heated and cooled. Since the thermal expansion coefficients and thermal conductivities of the phase change memory layer 202 and the first electrode layer 201 are different, the volume contractions are not synchronized during the cooling process, and thermal stress will be generated at the bonding interface.

[0057] The buffer layer 204 can adapt to the volume changes of the phase change memory layer 202 and the first electrode layer 201 by deforming to buffer the stress between the phase change memory layer 202 and the first electrode layer 201. Moreover, the buffer layer 204 can also be used to buffer the stress between the phase change memory layer 202 and the first electrode layer 201 by undergoing spontaneous reconstruction.

[0058] Moreover, the material of the phase change memory layer 202 is different from that of the first electrode layer 201. A large lattice mismatch rate at the interface between the phase change memory layer 202 and the first electrode layer 201 will affect the crystallization process of the phase change memory layer 202, and thus affect the performance of the phase change memory layer 202. In the embodiments of the present disclosure, the lattice mismatch rate at the interface between the buffer layer 204 and the phase change memory layer 202 can be made smaller than the lattice mismatch rate at the interface between the phase change memory layer 202 and the first electrode layer 201, so as to reduce the influence on the crystallization process of the phase change memory layer 202.

[0059] In addition, in some embodiments, the material of the first electrode layer 201 includes tungsten, and tungsten deposited by physical vapor deposition (PVD) often has strong compressive stress and is difficult to eliminate. Therefore, adding the buffer layer 204 to isolate the phase change memory layer 202 and the first electrode layer 201 can buffer the influence of the thin film stress caused by the manufacturing process on the phase change process.

[0060] Here, the material of the first electrode layer 201 includes tungsten, which may mean that the first electrode layer 201 includes a first sub-electrode layer and a second sub-electrode layer. Among them, the second sub-electrode layer is located between the first sub-electrode layer and the phase change memory layer. The material of the first sub-electrode layer includes carbon or amorphous carbon, and the material of the second sub-electrode layer includes tungsten. The tungsten in the second sub-electrode layer can block the element diffusion of the first sub-electrode layer into the phase change memory layer 202, reduce the influence on the performance of the phase change memory layer 202, and further reduce the probability of deterioration of the phase change memory performance.

[0061] In some embodiments, as Figure 4 shown, the phase change memory cell 200 includes: a third electrode layer 207, a select gate layer 206, a first electrode layer 201, a phase change memory layer 202, and a second electrode layer 203, which are stacked in sequence from bottom to top;

[0062] The phase change memory cell 200 includes: two conductive buffer layers 204 and 205, namely the first buffer layer 204 and the second buffer layer 205. The first buffer layer 204 is located between the first electrode layer 201 and the phase change memory layer 202, and the second buffer layer 205 is located between the phase change memory layer 202 and the second electrode layer 203. The first buffer layer 204 and the second buffer layer 205 are used to buffer the stress generated during the phase change process of the phase change memory layer 202 between the crystalline state and the amorphous state.

[0063] Here, the materials of the first buffer layer 204 and the second buffer layer 205 can be the same or different.

[0064] During the process of the phase change storage layer 202 transitioning between the crystalline state and the amorphous state, in addition to the first electrode layer 201 and the phase change storage layer 202 heating up and cooling down, and the phase change storage layer 202 undergoing reversible phase change, the second electrode layer 203 also heats up and cools down. Since the thermal expansion coefficients and thermal conductivities of the phase change storage layer 202 and the second electrode layer 203 are different, their volume contractions are out of sync during the cooling process, and thermal stress will be generated at the bonding interface. The second buffer layer 205 located between the phase change storage layer 202 and the second electrode layer 203 can buffer the stress between the phase change storage layer 202 and the second electrode layer 203 by deforming to adapt to the volume changes of the phase change storage layer 202 and the second electrode layer 203. Moreover, the second buffer layer 205 can also be utilized to undergo spontaneous reconstruction to buffer the stress between the phase change storage layer 202 and the second electrode layer 203.

[0065] In addition, in some embodiments, the material of the second electrode layer 203 may include tungsten. During the deposition of the second electrode layer 203, the second buffer layer 205 can buffer the stress applied by the second electrode layer 203 to the phase change storage layer 202 through deformation, thereby reducing the influence of the stress of the second electrode layer 203 on the phase change process.

[0066] Here, the material of the second electrode layer 203 includes tungsten, which may mean that the second electrode layer 203 includes a third sub - electrode layer and a fourth sub - electrode layer. Among them, the third sub - electrode layer is located between the fourth sub - electrode layer and the phase change storage layer 202. The material of the fourth sub - electrode layer includes carbon or amorphous carbon, and the material of the third sub - electrode layer includes tungsten. The tungsten in the third sub - electrode layer can block the element diffusion of the fourth sub - electrode layer into the phase change storage layer 202, reduce the influence on the performance of the phase change storage layer 202, and further reduce the probability of deterioration of the performance of the phase change memory.

[0067] It can be seen that in this embodiment, by providing the first buffer layer 204 and the second buffer layer 205 between the phase change storage layer 202, the first electrode layer 201, and the second electrode layer 203, the stress generated by the phase change storage layer 202 during the transition between the crystalline state and the amorphous state can be better buffered.

[0068] In addition, in some embodiments, only the second buffer layer 205 may be provided between the phase change storage layer 202 and the second electrode layer 203 to buffer the thermal stress generated by the different thermal expansion coefficients and conductivities of the phase change storage layer 202 and the second electrode layer 203, and when the material of the second electrode layer 203 is tungsten, to buffer the compressive stress applied by the second electrode layer 203 to the phase change storage layer 202.

[0069] In summary, the buffer layer can reduce the stress generated during the crystalline and amorphous state transitions of the phase change memory layer by undergoing deformation, spontaneously reconstructing, reducing the lattice mismatch rate, etc., buffer the impact of the stress on the phase change process of the phase change memory layer, and reduce the probability of the phase change memory layer being damaged and the probability of delamination between the phase change memory layer and the first electrode layer and the second electrode layer, thereby improving the reliability and service life of the phase change memory.

[0070] In some embodiments, the buffer layer comprises a material having a quasi-two-dimensional structure.

[0071] The material with a quasi-two-dimensional structure includes multiple atomic layers or molecular layers, which are connected by strong covalent bonds or ionic bonds within the layer, while the layers are bonded by relatively weak van der Waals forces. Due to the relatively weak van der Waals forces between the layers, the material with a quasi-two-dimensional structure has the characteristics of soft texture, large elasticity, low plasticity and toughness.

[0072] When the phase change memory layer changes from the crystalline state to the amorphous state and the volume increases due to the decrease in density, the buffer layer can be compressed to cause elastic deformation of the buffer layer, reducing the stress generated by the volume increase of the phase change memory layer. When the phase change memory layer changes from the amorphous state to the crystalline state and the volume decreases due to the increase in density, the stress applied to the buffer layer decreases and the buffer layer can return to its original state. That is, the buffer layer with a quasi-two-dimensional structure can buffer the stress generated during the crystalline and amorphous state transitions of the phase change memory layer by undergoing elastic deformation.

[0073] In addition, during the crystalline and amorphous state transitions of the phase change memory layer, when the volume changes of the phase change memory layer and the first electrode layer and the second electrode layer are not synchronized during the cooling process, the buffer layer can buffer the stress between the phase change memory layer and the first electrode layer and the second electrode layer by generating elastic deformations with different deformation amounts on its upper and lower sides.

[0074] It can be understood that the material of the buffer layer does not necessarily have a quasi-two-dimensional structure, and some other materials with relatively soft texture and good elasticity can also be used to form the buffer layer.

[0075] In some embodiments, the crystallization temperature of the buffer layer is less than the crystallization temperature of the phase change memory layer.

[0076] The crystallization of the phase change material refers to the phase change material changing from the amorphous state to the crystalline state. The crystallization temperature of the phase change material is defined as: the temperature point corresponding to the sudden change in the resistance value of the material during the heating process.

[0077] In this embodiment, there is also a transition process from the amorphous state to the crystalline state in the buffer layer during the heating process, and the crystallization temperature of the buffer layer is less than the crystallization temperature of the phase change memory layer. Therefore, when the initial buffer layer is in the amorphous state, whether in the write operation or the erase operation of the phase change memory cell, during the application of the electrical pulse, the amorphous buffer layer will preferentially transform into the crystalline state.

[0078] The crystalline buffer layer has good electrical conductivity and has little influence on the electrical properties of the phase change memory cell.

[0079] In some embodiments, the crystalline buffer layer has a quasi-two-dimensional structure.

[0080] In some embodiments, the material of the buffer layer includes at least one of antimony, tellurium, bismuth, antimony telluride or bismuth telluride.

[0081] Antimony, tellurium and bismuth are difficult to be amorphous at room temperature and temperatures above room temperature. That is, at room temperature and temperatures above room temperature, the solid state structures of these materials are crystalline and have a quasi-two-dimensional structure. Here, room temperature generally refers to 25°C.

[0082] Antimony telluride and bismuth telluride have relatively low crystallization temperatures, which are lower than the crystallization temperature of the phase change memory layer. For example, the crystallization temperature of antimony telluride is about 120°C, while the crystallization temperature range of the germanium antimony telluride compound commonly used in the phase change memory layer is in the range of 150°C to 180°C. Therefore, in the erase / write operation, antimony telluride and bismuth telluride will transform into the crystalline state prior to the phase change memory layer, and the crystalline antimony telluride and bismuth telluride have a quasi-two-dimensional structure.

[0083] Since antimony, tellurium, bismuth, antimony telluride and bismuth telluride are all materials with a quasi-two-dimensional structure. These materials are soft and elastic, and can buffer the stress caused by the transformation between the crystalline state and the amorphous state of the phase change memory layer through deformation.

[0084] Furthermore, antimony telluride and bismuth telluride will spontaneously reconstruct at the interface with a relatively large lattice mismatch. A buffer layer is provided between the phase change memory layer and the first electrode layer, and the interfaces of the buffer layer and the phase change memory layer and the interface of the buffer layer and the first electrode layer are used to replace the interface of the phase change memory layer and the first electrode layer. Since the buffer layer can spontaneously and slowly reconstruct through several atomic layers, reducing the stress at the interface between the buffer layer and the phase change memory layer and the interface between the buffer layer and the first electrode layer, therefore, the stress between the phase change memory layer and the first electrode layer is reduced.

[0085] Taking bismuth telluride as an example of the material of the buffer layer, at the interface between the buffer layer and the first electrode layer, the interface is rough. The nascent bismuth telluride will first fill the gaps on the rough surface of the first electrode layer, and then bismuth telluride with a quasi-two-dimensional structure will grow on the nascent bismuth telluride. Since the nascent bismuth telluride grows on the surface of the first electrode layer, its grain orientation is affected by the lattice constant of the first electrode layer and the rough interface, resulting in stress due to the different grain orientations between some of the nascent bismuth telluride and the subsequently grown bismuth telluride with a quasi-two-dimensional structure. In addition, the crystal constants of bismuth telluride and the first electrode layer are different, which will also cause stress between the nascent bismuth telluride and the first electrode layer. However, since bismuth telluride can spontaneously undergo atomic reconstruction, the nascent bismuth telluride can slowly return to the quasi-two-dimensional structure through the structure of one or several atomic layers, reducing the stress at the interface between the buffer layer and the first electrode layer.

[0086] At the interface between the buffer layer and the phase change memory layer, bismuth telluride can also reduce the stress between the buffer layer and the phase change memory layer through atomic reconstruction.

[0087] Similarly, by setting a buffer layer of bismuth telluride and / or antimony telluride between the phase change memory layer and the second electrode layer, the stress between the phase change memory layer and the second electrode layer can also be reduced through the spontaneous reconstruction of bismuth telluride and antimony telluride.

[0088] Furthermore, taking the buffer layer as antimony telluride, the phase change memory layer as Ge2Sb2Te5, and the first electrode layer as tungsten as an example, the lattice constant a of tungsten is 0.3157 nm, the lattice constant a of Ge2Sb2Te5 is 0.42 nm, and the lattice constant of antimony telluride is 0.433 nm. It can be seen that the lattice constant of antimony telluride is closer to that of Ge2Sb2Te5, making the stress between the buffer layer and the phase change memory layer smaller than the stress between the first electrode layer and the phase change memory layer.

[0089] In addition, the electrical conductivities of elemental antimony, elemental tellurium, elemental bismuth, antimony telluride, and bismuth telluride are relatively high, and the influence on the partial pressure of the phase change memory cell by adding the buffer layer is small or even negligible. Therefore, the influence on the electrical properties of the phase change memory cell is small or even negligible.

[0090] Furthermore, the material of the phase change memory layer generally includes chalcogenide phase change memory materials. Chalcogenide phase change memory materials are very sensitive to changes in constituent elements. Changes in constituent elements are likely to cause changes in the physical properties (such as resistivity, crystallization temperature, etc.) of the phase change memory layer, and further lead to changes in the electrical properties of the phase change memory cell.

[0091] In the embodiments of the present disclosure, the elements of antimony, tellurium, and bismuth contained in elemental antimony, elemental tellurium, elemental bismuth, antimony telluride, and bismuth telluride are elements commonly used in the phase change memory layer. Therefore, at least one of elemental antimony, elemental tellurium, elemental bismuth, antimony telluride, or bismuth telluride can be adaptively selected according to the material of the phase change memory layer, so that no new elements are introduced into the phase change memory layer, thereby not having too much impact on the physical properties of the phase change memory layer, and further not having too much impact on the electrical performance of the phase change memory cell.

[0092] Furthermore, the preparation processes of elemental antimony, elemental tellurium, elemental bismuth, antimony telluride, and bismuth telluride have a high degree of compatibility with the preparation process of the phase change memory layer. Therefore, adding a buffer layer in the phase change memory cell has a relatively small impact on the preparation process and preparation cycle of the phase change memory cell.

[0093] In some embodiments, as Figure 5 shown, the first buffer layer 204 located between the first electrode layer 201 and the phase change memory layer 202 includes: a first sub-buffer layer 2041 and a second sub-buffer layer 2042; wherein, the second sub-buffer layer 2042 is located between the first sub-buffer layer 2041 and the phase change memory layer 202;

[0094] The material of the first sub-buffer layer 2041 includes at least one of elemental antimony, elemental tellurium, or elemental bismuth;

[0095] The material of the second sub-buffer layer 2042 includes antimony telluride and / or bismuth telluride.

[0096] Taking the material of the first sub-buffer layer 2041 as elemental tellurium and the material of the second sub-buffer layer 2042 as antimony telluride as an example, in combination with Figure 6a and Figure 6b to illustrate the functions of the first sub-buffer layer 2041 and the second sub-buffer layer 2042.

[0097] In some embodiments, as Figure 6a shown, a buffer layer 204 including only antimony telluride can be directly formed on the first electrode layer 201, reducing the process steps and shortening the process cycle on the premise of ensuring the stress generated during the crystalline and amorphous state transitions of the buffer phase change memory layer.

[0098] In some embodiments, as Figure 6bAs shown, a first sub-buffer layer 2041 may be first formed on the surface of the first electrode layer 201, and then a second sub-buffer layer 2042 is formed on the first sub-buffer layer 2041. The first sub-buffer layer 2041 includes a layer of tellurium atoms deposited on the surface of the first electrode layer 201, which can change the crystal structure of the surface of the first electrode layer 201 and is more conducive to forming the second sub-buffer layer 2042 with a regular quasi-two-dimensional structure. In this way, the buffer layer 204 can have better elasticity, better adapt to the volume change of the phase change memory layer when the volume of the phase change memory layer expands or contracts, and reduce the stress during the phase change process.

[0099] In addition, in some embodiments, as Figure 7 shown, the first buffer layer 204 includes a first sub-buffer layer 2041 and a second sub-buffer layer 2042;

[0100] The second buffer layer 205 located between the phase change memory layer 202 and the second electrode layer 203 includes a third sub-buffer layer 2051 and a fourth sub-buffer layer 2052, where the third sub-buffer layer 2051 is located between the fourth sub-buffer layer 2052 and the phase change memory layer 202;

[0101] The material of the third sub-buffer layer 2051 includes antimony telluride and / or bismuth telluride;

[0102] The material of the fourth sub-buffer layer 2052 includes at least one of antimony, tellurium, or bismuth.

[0103] It can be understood that in some embodiments, the initially formed third sub-buffer layer 2051 (such as bismuth telluride) is amorphous, and in the erase / write operation, the initially amorphous third sub-buffer layer 2051 transforms into a crystalline state prior to the phase change memory layer 202. The fourth sub-buffer layer 2052 (such as tellurium) can change the crystal structure of the surface of the second electrode layer 203, making it more conducive for the amorphous third sub-buffer layer 2051 to transform into a regular quasi-two-dimensional structure.

[0104] Here, the materials of the third sub-buffer layer 2051 and the second sub-buffer layer 2042 may be the same or different. The materials of the fourth sub-buffer layer 2052 and the first sub-buffer layer 2041 may be the same or different.

[0105] In the embodiments of the present disclosure, the first buffer layer 204 is provided to include a first sub-buffer layer 2041 and a second sub-buffer layer 2042, and the second buffer layer 205 is provided to include a third sub-buffer layer 2051 and a fourth sub-buffer layer 2052, which can enable both the first buffer layer 204 and the second buffer layer 205 to obtain a regular quasi-two-dimensional structure, obtain better elasticity, and better buffer the stress during the crystalline and amorphous state transition process of the phase change memory layer 202. Moreover, it can also reduce the stress between the first buffer layer 204 and the first electrode layer 201, and between the second buffer layer 205 and the second electrode layer 203.

[0106] In addition, in some embodiments, the buffer layer includes at least two buffer regions with different materials. In this way, at least two buffer regions with different materials can be correspondingly arranged in the buffer layer according to the different stresses in different regions of the phase change memory layer.

[0107] Exemplarily, the stress in the middle region of the phase change memory layer is larger during the phase change process, while the stress in the edge region is smaller during the phase change process. Then, a material with a softer texture can be selected for the middle region of the buffer layer than that of the edge region.

[0108] The embodiments of the present disclosure also provide a method for manufacturing a phase change memory, including: forming a first electrode layer, a conductive first buffer layer, a phase change memory layer, and a second electrode layer that are stacked in sequence from bottom to top; wherein, the first buffer layer is used to buffer the stress generated during the crystalline and amorphous state transition process of the phase change memory layer.

[0109] Next, in combination with Figure 8 , the method for manufacturing the phase change memory provided by the embodiments of the present disclosure will be described in detail. As Figure 8 shown, the method for manufacturing the phase change memory includes:

[0110] S100: Form a first conductive wire layer and a storage stack structure; wherein, the storage stack structure includes a first electrode material layer, a conductive first buffer material layer, a phase change memory material layer, and a second electrode material layer that are stacked in sequence from bottom to top;

[0111] S200: Etch to form a plurality of first trenches that penetrate the storage stack structure and the first conductive wire layer in the up-down direction; wherein, the plurality of first trenches are arranged side by side in the second direction, and each first trench is parallel to the first direction; the first direction and the second direction are perpendicular to each other and both are perpendicular to the up-down direction;

[0112] S300: Fill the first trenches to form a first isolation layer;

[0113] S400: Form a second conductive wire layer covering the first isolation layer and the storage stack structure;

[0114] S500: Etch to form a plurality of second trenches penetrating the second conductive line layer and the storage stack structure in the up-and-down direction; wherein, the plurality of second trenches are arranged side by side in the first direction, and each second trench is parallel to the second direction; the plurality of first trenches and the plurality of second trenches divide the storage stack structure into a plurality of independent phase change memory cells;

[0115] S600: Fill the second trenches to form a second isolation layer.

[0116] Exemplarily, the materials of the first isolation layer and the second isolation layer include, but are not limited to, silicon nitride, silicon oxide, etc. The first isolation layer and the second isolation layer are used for electrically isolating independent phase change memory cells, and the material of the filling layer has a low thermal conductivity, which can reduce the heat transfer between adjacent phase change memory cells, thereby reducing crosstalk caused by heat transfer and ensuring better reliability of the phase change memory.

[0117] Here, in step S200, the first trenches divide the first conductive line layer, and the remaining material of the first conductive line layer forms a plurality of first conductive lines. And, the plurality of first conductive lines are arranged side by side in the second direction, and each first conductive line is parallel to the first direction.

[0118] In step S400, the second trenches divide the second conductive line layer, and the remaining material of the second conductive line layer forms a plurality of second conductive lines. And, the plurality of second conductive lines are arranged side by side in the first direction, and each second conductive line is parallel to the second direction.

[0119] It should be noted that the second trenches only penetrate the second conductive line layer and the storage stack structure in the up-and-down direction, without penetrating the first conductive line layer, and the bottom of the second trenches exposes the remaining first conductive line layer.

[0120] Here, the up-and-down direction is defined as the Z direction. Exemplarily, the first direction is the X direction, and the second direction is the Y direction. Correspondingly, the first conductive line is parallel to the X direction, and the second conductive line is parallel to the Y direction. Here, the first conductive line can be a bit line, and the second conductive line is a word line. Or, the first conductive line can be a word line, and the second conductive line is a bit line.

[0121] The first trenches and the second trenches divide the storage stack structure into a plurality of independent phase change memory cells, and the plurality of independent phase change memory cells are arranged in an array. Each phase change memory cell includes a first electrode layer, a first buffer layer, a phase change memory layer, and a second electrode layer stacked in sequence from bottom to top. Each phase change memory cell is in contact connection with the first conductive line and the second conductive line at both ends in the up-and-down direction, and is used to apply an operation pulse to the phase change memory cell through the first conductive line and the second conductive line, thereby changing the resistance of the phase change memory layer of the phase change memory cell.

[0122] In the embodiments of the present disclosure, the buffer layer is provided with conductivity, so that adding the buffer layer in the phase change memory cell has little or even negligible influence on the voltage division of the phase change memory cell, and thus has little or even negligible influence on the electrical performance of the phase change memory cell.

[0123] Exemplarily, one or more thin film deposition processes may be used to sequentially form a first conductive wire, a first electrode layer, a first buffer layer, a phase change memory layer, a second electrode layer, and a second conductive wire. The thin film deposition process includes but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering deposition, etc.

[0124] In some embodiments, the method for manufacturing the phase change memory further includes:

[0125] Before forming the first electrode layer, a third electrode layer and a select gate layer are formed which are stacked in sequence from bottom to top; wherein, the select gate layer is located between the third electrode layer and the first electrode layer.

[0126] Exemplarily, one or more thin film deposition processes may be used to sequentially form the third electrode layer and the select gate layer. The thin film deposition process includes but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering deposition, etc.

[0127] Exemplarily, the material of the phase change memory layer includes at least one of the following: germanium telluride (Ge-Te) compound, antimony telluride (Sb-Te) compound; germanium antimony telluride (Ge-Sb-Te) compound; silicon antimony telluride (Si-Sb-Te) compound; titanium antimony telluride (Ti-Sb-Te) compound; aluminum antimony telluride (Al-Sb-Te) compound. In some embodiments, the composition material of the phase change memory layer may further include a mixture formed by doping at least one of elements such as carbon, nitrogen, oxygen, bismuth, or tin into the above compounds.

[0128] Exemplarily, the material of the first electrode layer, the second electrode layer, and the third electrode layer includes at least one of the following: carbon, amorphous carbon, titanium nitride, tantalum nitride, tantalum carbide, metal, and the metal may include copper, tungsten, aluminum, gold, cobalt, titanium, tantalum, etc. The materials of the first electrode layer, the second electrode layer, and the third electrode layer may be the same or different.

[0129] Exemplarily, the material of the select gate layer may include an Ovonic Threshold Switch (OTS) material. The Ovonic Threshold Switch material may include chalcogenide compounds, such as zinc telluride, zinc selenium telluride, germanium selenide, etc. In some embodiments, the select gate layer may also be a diode, and the diode may include a PN junction formed by a P-doped semiconductor material and an N-doped semiconductor material.

[0130] Generally, the region where the phase change storage layer undergoes the crystalline and amorphous state transitions (i.e., the programming volume) is closer to the side of the phase change storage layer that is relatively closer to the selection layer. Therefore, by providing a buffer layer between the first electrode layer and the phase change storage layer, the stress generated during the crystalline and amorphous state transitions of the phase change storage layer can be better buffered.

[0131] In some embodiments, the method for manufacturing the phase change memory further includes:

[0132] After forming the phase change storage layer, a conductive second buffer layer is formed on the phase change storage layer; wherein, the second buffer layer is located between the phase change storage layer and the second electrode layer and is used to buffer the stress generated during the crystalline and amorphous state transitions of the phase change storage layer.

[0133] In this embodiment, by providing buffer layers between the phase change storage layer and both the first electrode layer and the second electrode layer, the stress generated during the crystalline and amorphous state transitions of the phase change storage layer can be better buffered.

[0134] In addition, in some embodiments, a buffer layer may be provided only between the phase change storage layer and the second electrode layer, without providing a buffer layer between the phase change storage layer and the first electrode layer. Correspondingly, the method for manufacturing the phase change memory includes:

[0135] Forming a first electrode layer, a phase change storage layer, a conductive buffer layer, and a second electrode layer that are sequentially stacked from bottom to top; wherein, the buffer layer is used to buffer the stress generated during the crystalline and amorphous state transitions of the phase change storage layer.

[0136] In this embodiment, the buffer layer is used to buffer the stress generated during the crystalline and amorphous state transitions of the phase change storage layer, and when the material of the second electrode layer is tungsten, it buffers the compressive stress applied by the second electrode layer to the phase change storage layer.

[0137] In the method for manufacturing the phase change memory provided by the embodiments of the present disclosure, a buffer layer is provided between the first electrode layer and the phase change storage layer, and / or a buffer layer is provided between the phase change storage layer and the second electrode layer. The buffer layer can reduce the stress generated during the crystalline and amorphous state transitions of the phase change storage layer by means such as undergoing deformation, spontaneously reconstructing, and reducing the lattice mismatch rate, buffer the influence of the stress on the phase change process of the phase change storage layer, reduce the probability of the phase change storage layer being damaged, and reduce the probability of the phase change storage layer peeling off from the first electrode layer and the second electrode layer, thereby improving the reliability and service life of the phase change memory.

[0138] In some embodiments, the buffer layer includes a material having a quasi-two-dimensional structure.

[0139] In some embodiments, the crystallization temperature of the buffer layer is lower than the crystallization temperature of the phase change storage layer.

[0140] In some embodiments, the material of the buffer layer includes at least one of antimony, tellurium, bismuth, antimony telluride, or bismuth telluride.

[0141] In some embodiments, the first buffer layer includes a first sub-buffer layer and a second sub-buffer layer;

[0142] The step of forming the conductive first buffer layer specifically includes:

[0143] The first sub-buffer layer and the second sub-buffer layer are sequentially formed on the first electrode layer; wherein, the material of the first sub-buffer layer includes at least one of antimony, tellurium, or bismuth, and the material of the second sub-buffer layer includes antimony telluride and / or bismuth telluride.

[0144] In some embodiments, the second buffer layer includes a third sub-buffer layer and a fourth sub-buffer layer;

[0145] After forming the phase change memory layer, the step of forming the conductive second buffer layer on the phase change memory layer specifically includes:

[0146] The third sub-buffer layer and the fourth sub-buffer layer are sequentially formed on the phase change memory layer; wherein, the material of the third sub-buffer layer includes antimony telluride and / or bismuth telluride, and the material of the fourth sub-buffer layer includes at least one of antimony, tellurium, or bismuth.

[0147] In the embodiments of the present disclosure, setting the first buffer layer to include a first sub-buffer layer and a second sub-buffer layer, and the second buffer layer to include a third sub-buffer layer and a fourth sub-buffer layer can enable both the first buffer layer and the second buffer layer to obtain a regular quasi-two-dimensional structure, obtain better elasticity, and better buffer the stress during the crystalline and amorphous state transition process of the phase change memory layer. Moreover, it can also make the stress between the first buffer layer and the first electrode layer, and between the second buffer layer and the second electrode layer smaller.

[0148] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A phase change memory, characterized in that, Comprising: A phase change memory cell, comprising: a first electrode layer, a phase change memory layer, and a second electrode layer which are stacked in sequence from bottom to top; The phase change memory cell further comprises: a conductive buffer layer located between the first electrode layer and the phase change memory layer, and / or between the phase change memory layer and the second electrode layer, for buffering the stress generated during the crystalline and amorphous state transition process of the phase change memory layer; Wherein, the buffer layer comprises: a first sub-buffer layer and a second sub-buffer layer, and the second sub-buffer layer is located between the first sub-buffer layer and the phase change memory layer; The material of the first sub-buffer layer comprises at least one of antimony, tellurium, or bismuth; The material of the second sub-buffer layer comprises antimony telluride and / or bismuth telluride.

2. The phase change memory according to claim 1, characterized in that The second sub-buffer layer in the crystalline state has a quasi-two-dimensional structure.

3. The phase change memory according to claim 1, wherein The crystallization temperature of the second sub-buffer layer is less than the crystallization temperature of the phase change memory layer.

4. The phase change memory according to claim 1, wherein The material of the first sub-buffer layer comprises one of antimony, tellurium, or bismuth.

5. The phase change memory according to claim 1, characterized in that, The first sub-buffer layer comprises a single atomic layer.

6. A method for preparing a phase change memory, characterized in that, Comprising: Form a first electrode layer, a first buffer layer, a phase change memory layer, and a second electrode layer which are stacked in sequence from bottom to top; Wherein, the first buffer layer is conductive, the first buffer layer is used for buffering the stress generated during the crystalline and amorphous state transition process of the phase change memory layer, the first buffer layer comprises: a first sub-buffer layer and a second sub-buffer layer, the second sub-buffer layer is located between the first sub-buffer layer and the phase change memory layer, the material of the first sub-buffer layer comprises at least one of antimony, tellurium, or bismuth, and the material of the second sub-buffer layer comprises antimony telluride and / or bismuth telluride.

7. The method for preparing a phase change memory according to claim 6, characterized in that, The preparation method further comprises: After forming the phase change memory layer, form a conductive second buffer layer on the phase change memory layer; wherein, the second buffer layer is located between the phase change memory layer and the second electrode layer, and is used for buffering the stress generated during the crystalline and amorphous state transition process of the phase change memory layer.

8. A method for preparing a phase change memory, characterized in that, Comprising: Form a first electrode layer, a phase change memory layer, a buffer layer, and a second electrode layer which are stacked in sequence from bottom to top; wherein, the buffer layer is conductive, the buffer layer is used for buffering the stress generated during the crystalline and amorphous state transition process of the phase change memory layer, the buffer layer comprises: a first sub-buffer layer and a second sub-buffer layer, the second sub-buffer layer is located between the first sub-buffer layer and the phase change memory layer, the material of the first sub-buffer layer comprises at least one of antimony, tellurium, or bismuth, and the material of the second sub-buffer layer comprises antimony telluride and / or bismuth telluride.

9. The manufacturing method of the phase change memory according to claim 6 or 8, characterized in that, The second sub-buffer layer in the crystalline state has a quasi-two-dimensional structure; The crystallization temperature of the second sub-buffer layer is less than the crystallization temperature of the phase change memory layer.

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