Error amplifier, power chip and electronic device

Abstract

The application relates to the technical field of integrated circuits, in particular to an error amplifier, a power supply chip and an electronic device, wherein the error amplifier comprises a differential amplification stage, a push-pull output stage and a compensation output stage; the differential amplification stage comprises a differential input pair tube and a voltage reduction triode; the voltage reduction triode is arranged at an input end of the differential input pair tube; the differential amplification stage is used for amplifying a differential input; the voltage reduction triode is used for reducing the input voltage of the differential input pair tube so as to improve the input voltage margin of the error amplifier; the push-pull output mode is adopted to increase the bandwidth of the error amplifier; based on the principle of the error amplifier, the push-pull output mode is adopted to increase the bandwidth of the error amplifier; based on the design requirement of a low-voltage and high-threshold voltage circuit, the error amplifier can work normally in the low-voltage and high-threshold voltage circuit, and the structure is simple and easy to realize.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to error amplifiers, power supply chips, and electronic devices. Background Technology

[0002] An error amplifier is an amplifier used to amplify errors. It has two input terminals: one connected to a reference voltage and the other connected to the circuit feedback signal. When there is a difference between the feedback signal and the reference voltage, the error amplifier amplifies this difference and then clamps the feedback signal to match the reference voltage through a negative feedback loop.

[0003] Transconductance error amplifiers are fundamental units in analog integrated circuits, widely used in signal processing, analog-to-digital conversion, and power supply systems. As the operating voltage range of electronic products increases, the demand for high-speed, high-linearity amplifiers also rises. Traditional error amplifiers employ a two-stage amplification structure. The first stage typically uses a fully differential input, single-ended output structure. Compared to differential output, single-ended output has reduced bandwidth and limited speed. Furthermore, in traditional error amplifiers with wide input voltage ranges, using NMOS transistors with higher threshold voltages increases the input voltage, consuming input voltage margin. Conversely, directly using PMOS transistors can lead to difficulties in turning on the differential input pair at low temperatures.

[0004] Therefore, designing an error amplifier that can operate normally in low-voltage and high-threshold-voltage circuits with a wide input voltage range is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of this application provide an error amplifier, a power supply chip, and electronic equipment, which aim to solve the problem that traditional error amplifiers have a small voltage input range and cannot work normally in low-voltage, high-threshold voltage circuits.

[0006] A first aspect of this application provides an error amplifier, including:

[0007] A differential amplifier stage, comprising a differential input pair transistor and a buck transistor, wherein the buck transistor is disposed at the input terminal of the differential input pair transistor, and the buck transistor is used to reduce the input voltage of the differential input pair transistor to improve the input voltage margin of the error amplifier; the differential amplifier stage is used to amplify the differential input.

[0008] A push-pull output stage, connected to the differential amplifier stage, is used to output the output of the differential amplifier stage in a push-pull manner;

[0009] A compensation output stage, connected to the push-pull output stage, is used to improve the phase margin of the error amplifier.

[0010] In one embodiment, the step-down transistor is an NPN transistor.

[0011] In one embodiment, the error amplifier uses the output voltage of the common-emitter stage of the buck transistor as the input voltage of the differential input pair.

[0012] In one embodiment, the differential amplifier stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first NPN transistor, a second NPN transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a fourth PMOS transistor, wherein the second PMOS transistor and the third PMOS transistor serve as the differential input pair, and the first NPN transistor and the second NPN transistor serve as the buck transistor;

[0013] The source of the first PMOS transistor is connected to the power supply, and the drain of the first PMOS transistor, the source of the second PMOS transistor, and the source of the third PMOS transistor are all connected together.

[0014] The drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, the source of the first NMOS transistor is grounded, and the gate and drain of the first NMOS transistor are connected.

[0015] The drain of the second NMOS transistor is connected to the drain of the third PMOS transistor, the source of the second NMOS transistor is grounded, and the gate and drain of the second NMOS transistor are connected.

[0016] The collector of the first NPN transistor is connected to the power supply, the emitter of the first NPN transistor is connected to the gate of the second PMOS transistor, and the base of the first NPN transistor is used to connect to the reference voltage.

[0017] The collector of the second NPN transistor is connected to the power supply, the emitter of the second NPN transistor is connected to the gate of the third PMOS transistor, and the base of the second NPN transistor is used to connect to the feedback voltage.

[0018] The drain of the third NMOS transistor is connected to the emitter of the first NPN transistor, the drain of the fourth NMOS transistor is connected to the emitter of the second NPN transistor, the source of the third NMOS transistor, the source of the fourth NMOS transistor, and the source of the fifth NMOS transistor are all grounded, and the gate of the third NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the fifth NMOS transistor are all connected to a bias voltage source.

[0019] The drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fourth PMOS transistor is connected to the power supply, the gate of the fourth PMOS transistor is connected to the gate of the first PMOS transistor, and the gate of the fourth PMOS transistor is also connected to its drain.

[0020] In one embodiment, the second PMOS transistor and the third PMOS transistor are the same size, and the first NMOS transistor and the second NMOS transistor are the same size.

[0021] In one embodiment, the push-pull output stage includes a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;

[0022] The gate of the sixth NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0023] The gate of the seventh NMOS transistor is connected to the drain of the third PMOS transistor, the drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the seventh NMOS transistor is grounded.

[0024] The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to the power supply. The gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor. The gate of the fifth PMOS transistor is also connected to its drain.

[0025] In one embodiment, the compensation output stage includes a Miller compensation capacitor, a first resistor, a second resistor, and a seventh PMOS transistor;

[0026] The first terminal of the Miller compensation capacitor is connected to the drain of the sixth PMOS transistor, and the second terminal of the Miller compensation capacitor is connected to the output terminal of the error amplifier.

[0027] The first end of the first resistor is connected to the second end of the Miller compensation capacitor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is grounded, and the series node of the first resistor and the second resistor is connected to the base of the second NPN transistor.

[0028] The drain of the seventh PMOS transistor is connected to the second terminal of the Miller compensation capacitor, the source of the seventh PMOS transistor is connected to the power supply, and the gate of the seventh PMOS transistor is connected to the first terminal of the Miller compensation capacitor.

[0029] In one embodiment, the buck transistor is forward-biased when the error amplifier is operating normally, and the emitter voltage of the buck transistor is lower than its base voltage by the voltage of a PN junction.

[0030] A second aspect of this application provides a power supply chip, including the error amplifier in any of the above embodiments.

[0031] A third aspect of this application provides an electronic device including the power chip provided in the second aspect of this application.

[0032] The advantages of the error amplifier in this application compared to the prior art are:

[0033] (1) Based on the principle of error amplifier, push-pull output method is adopted as the output stage of error amplifier. Compared with the single-ended output of traditional error amplifier, the bandwidth of error amplifier is increased by adopting fully differential push-pull output method.

[0034] (2) The internal circuit based on the wide input voltage range needs to operate at low voltage and high threshold voltage. The step-down transistor is used to reduce the input voltage of the differential input pair transistor, so that the error amplifier can operate normally in the low voltage and high threshold voltage circuit. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a circuit schematic of an error amplifier in the prior art;

[0037] Figure 2 A circuit schematic diagram of an error amplifier provided in one embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the small-signal equivalent circuit of an error amplifier provided in another embodiment of this application. Detailed Implementation

[0039] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0040] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0043] Figure 1 The diagram shows the circuit structure of a traditional error amplifier, which employs a two-stage amplification structure, with the first stage being a differential amplifier. (The diagram is incomplete and requires further context.) Figure 1 As shown in (a), NMOS transistors are used as differential input pairs. The differential circuit structure has symmetry, can resist common-mode noise, and has better common-mode signal suppression characteristics. At the same time, the differential circuit can cancel even harmonics and provide better output linearity characteristics. Therefore, the structure of differential op-amps is commonly found in internal circuits. In contrast, the first stage of a traditional two-stage op-amp generally adopts a fully differential input single-ended output structure. The single-ended output has one more mirror pole than the differential output. By using Miller capacitor compensation, the mirror pole is pushed to the origin of the coordinate system and becomes the new dominant pole, which leads to a reduction in bandwidth and a limitation on speed.

[0044] In traditional error amplifiers, to ensure the MOSFETs can withstand voltages up to the upper limit of the operating voltage over a wide input voltage range, high-voltage MOSFETs are used. High-voltage MOSFETs have a larger threshold voltage, which increases the minimum input voltage and consumes the input voltage margin. Figure 1 As shown in (b), using NMOS as the differential input pair can easily lead to difficulties in turning on the differential input pair at low temperatures. On the other hand, using PMOS directly as the differential input pair will consume a large voltage margin, making it difficult to meet the current low-voltage operating requirements.

[0045] To address the aforementioned technical problems, the first aspect of this application provides an error amplifier, such as... Figure 2 As shown, the error amplifier includes a differential amplifier stage 10, a push-pull output stage 20, and a compensation output stage 30. The differential amplifier stage 10 includes a differential input pair and a buck transistor. The buck transistor is located at the input terminal of the differential input pair. The differential amplifier stage 10 amplifies the differential input. The buck transistor reduces the input voltage of the differential input pair to improve the input voltage margin of the error amplifier. The push-pull output stage 20 is connected to the differential amplifier stage 10 and provides a push-pull output. The compensation output stage 30 is connected to the push-pull output stage 20 and provides phase compensation for the output of the error amplifier, improving the system stability of the error amplifier.

[0046] The error amplifier provided in the first aspect of this application is based on the principle of error amplifiers and adopts a push-pull output method as the output stage of the error amplifier, which increases the bandwidth of the error amplifier. Based on the design requirements of low-voltage, high-threshold voltage circuits, a step-down transistor is used to reduce the input voltage of the differential input pair transistors, so that the error amplifier can work normally in low-voltage, high-threshold voltage circuits, and the structure is simple and easy to implement.

[0047] In one embodiment, see Figure 2 The step-down transistor is an NPN transistor. When an NPN transistor is normally turned on, its emitter voltage is lower than its base voltage by one PN junction voltage. Compared to traditional error amplifiers that use voltage divider resistors to reduce the magnitude of the reference voltage output value, this embodiment of the application uses the method that when an NPN transistor is normally turned on, its emitter voltage is lower than its base voltage by one PN junction voltage, thus avoiding increasing the difficulty and complexity of the reference circuit compensation.

[0048] In one embodiment, see Figure 2 The error amplifier uses the output voltage of the common-emitter stage of the buck transistor as the input voltage of the differential input pair, that is, the base and collector input of the buck transistor, and the emitter and collector output of the buck transistor.

[0049] In one embodiment, see Figure 2 The differential amplifier stage 10 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first NPN transistor Q1, a second NPN transistor Q2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a fourth PMOS transistor MP4. Among them, the second PMOS transistor MP2 and the third PMOS transistor MP3 serve as a differential input pair, and the first NPN transistor Q1 and the second NPN transistor Q2 serve as step-down transistors.

[0050] The source of the first PMOS transistor MP1 is connected to the power supply VDD. The drains of the first PMOS transistor MP1, the sources of the second PMOS transistor MP2, and the source of the third PMOS transistor MP3 are all connected together. The drain of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2. The source of the first NMOS transistor MN1 is grounded, and the gate and drain of the first NMOS transistor MN1 are connected together. The drain of the second NMOS transistor MN2 is connected to the drain of the third PMOS transistor MP3. The source of the second NMOS transistor MN2 is grounded, and the gate and drain of the second NMOS transistor MN2 are connected together.

[0051] The collector of the first NPN transistor Q1 is connected to the power supply VDD, the emitter of the first NPN transistor Q1 is connected to the gate of the second PMOS transistor MP2, and the base of the first NPN transistor Q1 is used to connect to the reference voltage V. REF By using the common-emitter output voltage of an NPN transistor as the input voltage of the differential pair, the reference level voltage is reduced, enabling the error amplifier to operate normally in low-voltage, high-threshold-voltage circuits.

[0052] The collector of the second NPN transistor Q2 is connected to the power supply VDD, the emitter of the second NPN transistor Q2 is connected to the gate of the third PMOS transistor MP3, and the base of the second NPN transistor Q2 is used to connect the feedback voltage V. in .

[0053] The drain of the third NMOS transistor MN3 is connected to the emitter of the first NPN transistor Q1, and the drain of the fourth NMOS transistor MN4 is connected to the emitter of the second NPN transistor Q2. The sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are all grounded. The gates of the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are all connected to the bias voltage source V. bias Bias voltage source V bias The generation circuit is not the focus of this patent and will not be described in detail here.

[0054] The drain of the fourth PMOS transistor MP4 is connected to the drain of the fifth NMOS transistor MN5. The source of the fourth PMOS transistor MP4 is connected to the power supply VDD. The gate of the fourth PMOS transistor MP4 is connected to the gate of the first PMOS transistor MP1. The gate of the fourth PMOS transistor MP4 is also connected to its drain.

[0055] In one embodiment, the second PMOS transistor MP2 and the third PMOS transistor MP3 have the same dimensions, and the first NMOS transistor MN1 and the second NMOS transistor MN2 have the same dimensions.

[0056] In one embodiment, see Figure 2 The push-pull output stage 20 includes a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor.

[0057] The gate of the sixth NMOS transistor MN6 is connected to the drain of the second PMOS transistor MP2, the drain of the sixth NMOS transistor MN6 is connected to the drain of the fifth PMOS transistor MP5, and the source of the sixth NMOS transistor MN6 is grounded.

[0058] The gate of the seventh NMOS transistor MN7 is connected to the drain of the third PMOS transistor MP3, the drain of the seventh NMOS transistor MN7 is connected to the drain of the sixth PMOS transistor MP6, and the source of the seventh NMOS transistor MN7 is grounded.

[0059] The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected to the power supply. The gate of the fifth PMOS transistor MP5 is connected to the gate of the sixth PMOS transistor MP6. The gate of the fifth PMOS transistor MP5 is also connected to its drain.

[0060] The push-pull output method used in the output stage of differential amplifier stage 10 increases the transconductance of the error amplifier, expands the bandwidth of the overall circuit, and at the same time, the push-pull output method has stronger driving capability.

[0061] In one embodiment, see Figure 2 The compensation output stage 30 includes a Miller compensation capacitor Cc, a first resistor R1, a second resistor R2, and a seventh PMOS transistor MP7.

[0062] The first terminal of the Miller compensation capacitor Cc is connected to the drain of the sixth PMOS transistor MP6, and the second terminal of the Miller compensation capacitor Cc is connected to the output terminal VOUT of the error amplifier. The first terminal of the first resistor R1 is connected to the second terminal of the Miller compensation capacitor Cc, the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is grounded, and the series node of the first resistor R1 and the second resistor R2 is connected to the base of the second NPN transistor Q2. The drain of the seventh PMOS transistor MP7 is connected to the second terminal of the Miller compensation capacitor Cc, the source of the seventh PMOS transistor MP7 is connected to the power supply VDD, and the gate of the seventh PMOS transistor MP7 is connected to the first terminal of the Miller compensation capacitor Cc.

[0063] In one embodiment, the buck transistor is forward-biased when the error amplifier is operating normally, and its emitter voltage is lower than its base voltage by the voltage of one PN junction. By using the buck transistor to reduce the input voltage of the differential input pair, the error amplifier can operate normally in low-voltage, high-threshold-voltage circuits.

[0064] The error amplifier provided in the above embodiments uses a push-pull output method as the output stage, which increases the bandwidth of the error amplifier. Based on the design requirements of low-voltage, high-threshold voltage circuits, a step-down transistor is used to reduce the input voltage of the differential input pair, enabling the error amplifier to operate normally in low-voltage, high-threshold voltage circuits, and the structure is simple and easy to implement. To better illustrate the working principle of the error amplifier provided in this application embodiment, the equivalent small-signal circuit of the error amplifier will be further explained below.

[0065] Please see Figure 2 , 3 , Figure 3 The diagram shown is an equivalent small-signal circuit diagram of the differential amplifier stage 10 and the push-pull output stage 20, where V in This represents the feedback voltage of the error amplifier, specifically the voltage at the base of the second NPN transistor, V. P V represents the emitter voltage of the second NPN transistor Q2, V1 represents the gate voltage of the sixth NMOS transistor, and V2 represents the gate voltage of the second PMOS transistor. O1 This represents the voltage at the drain of the sixth NMOS transistor, i.e., the output terminal of push-pull output stage 20, g. Q1 g P5 g N3 g P4 g N2 g N5 g P2 g P3 g N6 R represents the transconductance of the second NPN transistor Q2, the third PMOS transistor MP3, the second NMOS transistor MN2, the second PMOS transistor MP2, the first NMOS transistor MN1, the sixth NMOS transistor MN6, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh NMOS transistor MN7, respectively. ON1 R ON R OP Given the source follower output impedance, the on-resistance of the seventh NMOS transistor MN7, and the on-resistance of the sixth PMOS transistor MP6, respectively, based on the node current equation (KCL equation), we can obtain:

[0066] 1.

[0067] 2. g P3 V P +g N2 V1+g P2 V P +g N1 V1 = 0

[0068] 3, g N6 V1-gP5 V2 = 0

[0069] 4.

[0070] By simplifying formulas 1-4 above, we can obtain:

[0071]

[0072] The formula for calculating its unity-gain bandwidth W is:

[0073]

[0074] As can be seen from the unity-gain bandwidth formula, using a push-pull output method as the first output stage of the error amplifier can improve the unity-gain bandwidth of the entire error amplifier.

[0075] The error amplifier provided in the first aspect of this application is based on the principle of error amplifiers and adopts a push-pull output method as the output stage of the error amplifier. Compared with the traditional single-ended output structure of error amplifiers, the push-pull output fully differential output structure increases the bandwidth of the error amplifier. Based on the design requirements of low-voltage, high-threshold voltage circuits, a step-down transistor is used to reduce the input voltage of the differential input pair transistors, so that the error amplifier can work normally in low-voltage, high-threshold voltage circuits, and the structure is simple and easy to implement.

[0076] A second aspect of this application provides a power supply chip, including the error amplifier described in the above embodiments.

[0077] A third aspect of this application provides an electronic device, including a power chip provided in the second aspect of this application.

[0078] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An error amplifier characterized by, The error amplifier comprises: a differential amplification stage comprising a differential input pair tube and a voltage reduction triode, the voltage reduction triode is arranged at the input end of the differential input pair tube, and the voltage reduction triode is used to reduce the input voltage of the differential input pair tube to improve the input voltage margin of the error amplifier, and the differential amplification stage is used to amplify the difference between a reference voltage and a feedback voltage of an output stage; wherein the differential input pair tube is a PMOS tube, and the voltage reduction triode is an NPN triode; a push-pull output stage connected with the differential amplification stage and used to perform push-pull output on the output of the differential amplification stage; an output stage connected with the push-pull output stage and the differential amplification stage and used as the output end of the error amplifier and for improving the output phase margin of the error amplifier.

2. The error amplifier of claim 1, wherein, The error amplifier uses the output voltage of the common emitter of the voltage reduction triode as the input voltage of the differential input pair tube.

3. The error amplifier of claim 1, wherein, The differential amplification stage comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first NPN triode, a second NPN triode, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a fourth PMOS tube, wherein the second PMOS tube and the third PMOS tube are used as the differential input pair tube, and the first NPN triode and the second NPN triode are used as the voltage reduction triode; the source of the first PMOS tube is connected with a power supply, and the drain of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are commonly connected; the drain of the first NMOS tube is connected with the drain of the second PMOS tube, the source of the first NMOS tube is grounded, and the gate and the drain of the first NMOS tube are connected; the drain of the second NMOS tube is connected with the drain of the third PMOS tube, the source of the second NMOS tube is grounded, and the gate and the drain of the second NMOS tube are connected; the collector of the first NPN triode is connected with a power supply, the emitter of the first NPN triode is connected with the gate of the second PMOS tube, and the base of the first NPN triode is used to input a reference voltage; the collector of the second NPN triode is connected with a power supply, the emitter of the second NPN triode is connected with the gate of the third PMOS tube, and the base of the second NPN triode is used to input a feedback voltage; the drain of the third NMOS tube is connected with the emitter of the first NPN triode, the drain of the fourth NMOS tube is connected with the emitter of the second NPN triode, the source of the third NMOS tube, the source of the fourth NMOS tube and the source of the fifth NMOS tube are commonly grounded, and the gate of the third NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are commonly connected with a bias voltage source. The drain of the fourth PMOS tube is connected with the drain of the fifth NMOS tube, the source of the fourth PMOS tube is connected with a power supply, the gate of the fourth PMOS tube is connected with the gate of the first PMOS tube, and the gate of the fourth PMOS tube is also connected with the drain of the fourth PMOS tube.

4. The error amplifier of claim 3, wherein, The second PMOS tube and the third PMOS tube have the same size, and the first NMOS tube and the second NMOS tube have the same size.

5. The error amplifier of claim 3, wherein, The push-pull output stage comprises a sixth NMOS tube, a seventh NMOS tube, a fifth PMOS tube and a sixth PMOS tube. The gate of the sixth NMOS tube is connected with the drain of the second PMOS tube, the drain of the sixth NMOS tube is connected with the drain of the fifth PMOS tube, and the source of the sixth NMOS tube is grounded. The gate of the seventh NMOS tube is connected with the drain of the third PMOS tube, the drain of the seventh NMOS tube is connected with the drain of the sixth PMOS tube, and the source of the seventh NMOS tube is grounded. The source of the fifth PMOS tube and the source of the sixth PMOS tube are connected with a power supply, the gate of the fifth PMOS tube is connected with the gate of the sixth PMOS tube, and the gate of the fifth PMOS tube is also connected with the drain of the fifth PMOS tube.

6. The error amplifier of claim 5, wherein, The compensation output stage comprises a Miller compensation capacitor, a first resistor, a second resistor and a seventh PMOS tube. The first end of the Miller compensation capacitor is connected with the drain of the sixth PMOS tube, and the second end of the Miller compensation capacitor is connected with the output terminal of the error amplifier. The first end of the first resistor is connected with the second end of the Miller compensation capacitor, the second end of the first resistor is connected with the first end of the second resistor, the second end of the second resistor is grounded, and the node in series connection of the first resistor and the second resistor is connected with the base of the second NPN transistor. The drain of the seventh PMOS tube is connected with the second end of the Miller compensation capacitor, the source of the seventh PMOS tube is connected with a power supply, and the gate of the seventh PMOS tube is connected with the first end of the Miller compensation capacitor.

7. The error amplifier of claim 1, wherein, The voltage of the emitter of the voltage reduction transistor is lower than the voltage of the base of the voltage reduction transistor by one PN junction voltage when the error amplifier is normally working.

8. A power supply chip, characterized by comprising: The error amplifier comprises the error amplifier as claimed in any one of claims 1 to 7.

9. An electronic device, comprising: The power supply chip comprises the power supply chip as claimed in claim 8.

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