Electronic device starting method and electronic device

Abstract

The application provides an electronic device starting method and an electronic device. The electronic device comprises a processor, a memory and a CPLD. The CPLD comprises a static storage module in which SPD information is stored. After the electronic device is powered on, the CPLD completes its own starting, sends a storage address of the SPD information to the processor and triggers the processor to start up. The processor reads the SPD information according to the storage address and initializes the memory according to the SPD information. The processor completes the starting of an operating system. The SPD information is stored in the static storage module of the existing CPLD, and an EEPROM does not need to be arranged for each memory, so that the number of EEPROMs in the electronic device can be reduced, thereby saving the hardware cost. Moreover, the SPD information in the static storage module of the CPLD can be directly modified without being removed and burned, so that the replacement process of the memory can be simplified and errors can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to an electronic device starting method and an electronic device. BACKGROUND

[0002] In an embedded system, when a processor (for example, an X86 processor) is connected with an external DDR (Double Data Rate) memory, a common use scenario is to be connected through a memory plug-in strip, as shown in FIG. 1. The SPD (Serial Presence Detect) information of the memory is stored in an EEPROM (Electrically Erasable Programmable read only memory) in the memory strip, the SPD information is read by the processor, and is configured into a DDR controller in the processor to complete the initialization of the memory, so that the DDR controller can normally access the memory. Figure 1

[0003] However, for some embedded systems, due to requirements such as volume, motion intensity and cost, the plug-in memory strip scheme is not adopted, but a DDR chip is directly welded to a hardware board, as shown in FIG. 2. In this case, a corresponding EEPROM is arranged for each DDR chip to store SPD information. When the processor is started, the SPD information in the EEPROM can be read to complete the initialization of the memory. Figure 2

[0004] However, as shown in FIG. 3, when the DDR chip is replaced, the EEPROM corresponding to the DDR chip for storing SPD information also needs to be replaced, or the EEPROM is removed and then reprogrammed by using a special programming device, which leads to a complex DDR replacement process and is prone to errors. In addition, arranging a corresponding EEPROM for each DDR chip also increases the cost of the electronic device. Figure 2 SUMMARY

[0005] The embodiments of the present application aim to provide an electronic device starting method and an electronic device to at least solve the above problems. The specific technical solutions are as follows.

[0006] In a first aspect, the embodiments of the present application provide an electronic device starting method applied to an electronic device, wherein the electronic device includes a processor, a memory and a CPLD (Complex Programmable Logic Device), the CPLD includes a static storage module, the SPD information is stored in the static storage module, and the method includes the following steps.

[0007] ​​​After the electronic device is powered on, the CPLD completes self-starting;

[0008] The CPLD acquires the storage address of the SPD information from the static storage module;

[0009] The CPLD triggers the processor to start up and sends the storage address of the SPD information to the processor;

[0010] The processor reads the SPD information according to the storage address and initializes the memory according to the SPD information;

[0011] The processor completes starting of an operating system.

[0012] In a possible implementation, the static storage module stores a plurality of SPD information, and each of the SPD information corresponds to a memory of a different preset model; acquiring the storage address of the SPD information in the static storage module comprises:

[0013] The CPLD selects a specified SPD information identified by a preset flag bit from the plurality of SPD information according to the preset flag bit and acquires the storage address of the specified SPD information.

[0014] In a possible implementation, the static storage module stores a plurality of SPD information, and each of the SPD information corresponds to a memory of a different preset model; acquiring the storage address of the SPD information in the static storage module comprises:

[0015] The CPLD selects a specified SPD information specified by a preset logic version from the plurality of SPD information according to the preset logic version and acquires the storage address of the specified SPD information.

[0016] In a possible implementation, the method further comprises:

[0017] After receiving SPD update information, the CPLD updates the SPD information in the static storage module according to the SPD update information;

[0018] After the SPD information is updated, the electronic device is restarted.

[0019] In a possible implementation, the method further comprises:

[0020] After receiving SPD update information, the CPLD updates the SPD information in the static storage module according to the SPD update information;

[0021] After the SPD information is updated, the CPLD acquires a storage address of the SPD information in the static storage module;

[0022] The CPLD triggers the processor to start up and sends the storage address of the SPD information to the processor;

[0023] The processor reads the SPD information according to the storage address and initializes the memory according to the SPD information;

[0024] The processor completes the start-up of the operating system.

[0025] In a second aspect, an electronic device is provided, comprising:

[0026] A processor, a memory and a CPLD, the CPLD comprising a static storage module, and the static storage module storing SPD information;

[0027] The CPLD is configured to complete the start-up of the CPLD itself after the electronic device is powered on, acquire a storage address of the SPD information in the static storage module, trigger the processor to start up and send the storage address of the SPD information to the processor;

[0028] The processor is configured to read the SPD information according to the storage address, initialize the memory according to the SPD information, and complete the start-up of the operating system.

[0029] In a possible implementation, the static storage module stores a plurality of SPD information, and each of the SPD information corresponds to a memory of a different preset model; the CPLD is specifically configured to select a specified SPD information identified by a preset flag bit from the plurality of SPD information according to the preset flag bit, and acquire a storage address of the specified SPD information.

[0030] In a possible implementation, the static storage module stores a plurality of SPD information, and each of the SPD information corresponds to a memory of a different preset model; the CPLD is specifically configured to select a specified SPD information specified by a preset logic version from the plurality of SPD information according to the preset logic version, and acquire a storage address of the specified SPD information.

[0031] In a possible implementation, the CPLD is further configured to update the SPD information in the static storage module according to SPD update information after the SPD update information is received, and restart the electronic device after the SPD information is updated.

[0032] In a possible implementation, the CPLD is further configured to update the SPD information in the static storage module according to the SPD update information after receiving the SPD update information; obtain the storage address of the SPD information in the static storage module after the SPD information is updated; and trigger the processor to start and send the storage address of the SPD information to the processor.

[0033] The embodiments of the present application have the following beneficial effects:

[0034] The electronic device startup method and the electronic device provided by the embodiments of the present application, the electronic device comprising a processor, a memory and a complex programmable logic device (CPLD), the CPLD comprising a static storage module, and the static storage module storing SPD information, the method comprising: after the electronic device is powered on, the CPLD completes its startup; the CPLD obtains the storage address of the SPD information from the static storage module; the CPLD triggers the processor to start and sends the storage address of the SPD information to the processor; the processor reads the SPD information according to the storage address and initializes the memory according to the SPD information; and the processor completes the startup of an operating system. Instead of setting an EEPROM for each memory, the SPD information is stored in the existing static storage module of the CPLD, and the SPD information can be obtained from the static storage module of the CPLD when the electronic device starts, which can reduce the number of EEPROMs in the electronic device and thus save hardware costs. Moreover, the SPD information in the static storage module of the CPLD can be directly modified, and when the memory is replaced, the SPD information in the static storage module can be updated through the CPLD without dismounting and burning, which can simplify the replacement process of the memory and reduce errors. Of course, implementing any product or method of the present application does not necessarily achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0036] Figure 1 It is a first schematic diagram of an electronic device in the related art;

[0037] Figure 2 It is a second schematic diagram of an electronic device in the related art;

[0038] Figure 3 It is a first schematic diagram of an electronic device startup method in the embodiments of the present application;

[0039] Figure 4 A schematic diagram of a complex programmable logic device according to an embodiment of the present application;

[0040] Figure 5 A second schematic diagram of an electronic device startup method according to an embodiment of the present application;

[0041] Figure 6 A third schematic diagram of an electronic device startup method according to an embodiment of the present application;

[0042] Figure 7 A schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0044] In an embedded electronic device as shown in Figure 2 , a corresponding EEPROM needs to be set for each DDR chip respectively, for storing SPD information. When the processor is started, the SPD information in the EEPROM can be read, so as to complete the initialization of the memory. However, in the manner as shown in Figure 2 , when the DDR chip is replaced, the EEPROM for storing SPD corresponding to the DDR chip also needs to be replaced, which leads to complex DDR replacement procedures, prone to errors, and setting a corresponding EEPROM for each DDR chip also increases the cost of the electronic device

[0045] The inventor finds in research that in an embedded electronic device, a CPLD (Complex Programming Logic Device) is generally provided for processing most of the logic switches and interface expansion functions, and can replace the power management module to provide power-on timing control function for the processor. In view of this, an electronic device startup method is provided in the embodiments of the present application, applied to an electronic device, the above-mentioned electronic device comprising a processor, a memory and a CPLD, the above-mentioned CPLD comprising a static storage module, the above-mentioned static storage module storing SPD information, referring to Figure 3 , the method comprises:

[0046] S301, after the above-mentioned electronic device is powered on, the above-mentioned CPLD completes the startup of itself.

[0047] The electronic device startup method in the embodiments of the present application is specifically implemented by the electronic device. The electronic device can be specifically an embedded electronic device, for example, an embedded electronic device based on an X86 system. After the electronic device is powered on, the CPLD first completes its own startup.

[0048] In S302, the CPLD obtains the storage address of the SPD information from the static storage module.

[0049] The SPD information of the memory is stored in the static storage module of the CPLD. The CPLD obtains the storage address of the SPD information in the static storage module.

[0050] In S303, the CPLD triggers the processor to be powered on and started, and sends the storage address of the SPD information to the processor.

[0051] The CPLD triggers the processor to be powered on and started. When the processor is started, the CPLD is equivalent to an IIC (Inter-Integrated Circuit, Inter-Integrated Circuit) receiving device. When the processor needs to read the SPD information, the SPD information can be read from the static storage module of the CPLD according to the storage address.

[0052] In S304, the processor reads the SPD information according to the storage address, and initializes the memory according to the SPD information.

[0053] The processor configures the read SPD information to the memory controller in the processor, so as to complete the initialization of the memory. Thereafter, the processor can normally access the memory. In an example, the memory is a DDR memory, and the memory controller is a DDR controller.

[0054] In S305, the processor completes the startup of the operating system.

[0055] After the processor can normally access the memory, the processor can load the operating system data into the memory, so as to complete the startup of the operating system.

[0056] In the embodiments of the present application, instead of setting an EEPROM for each memory, the SPD information is stored in the existing static storage module of the CPLD. The SPD information can be obtained from the static storage module of the CPLD when the electronic device is started. The number of EEPROMs in the electronic device can be reduced, so as to save the hardware cost. Moreover, the SPD information in the static storage module of the CPLD can be directly modified. When the memory is replaced, the EEPROM does not need to be removed and burned. The SPD information in the static storage module can be directly updated by the CPLD. The replacement process of the memory can be simplified, and the error can be reduced.

[0057] In one possible implementation, the static storage module can specifically be a UFM (User Flash Memory) module. In one example, a complex programmable logic device can be, for instance... Figure 4 As shown, it includes: a SysCLOCK (system clock) PLL (Phase Locked Loop), an EFB (Embedded Function Block), a UFM module, an EBR (SysMEM Embedded Block RAM), a Configuration memory, PIOs arranged into sysIO Banks, and PFUs (Programmable Function Units with Distributed RAM). Flash refers to flash memory, and NVCM0 and NVCM1 represent specific model numbers. Those skilled in the art will understand that these model numbers are merely illustrative, and any equivalent substitutions made within the scope of this application are within the protection scope of this application. The storage capacity of a UFM module is typically around 256Kb, while the size of an SPD (Signal Detection and Processing) information is 2Kb. One SPD information in this application can be understood as one SPD file. Multiple SPD information can be stored in the UFM module as needed to adapt to different memory chip models. The electronic device described above may contain one or more memory modules, and the models of different memory modules may be the same or different.

[0058] In one possible implementation, the static storage module stores multiple SPD information entries, each SPD information entry corresponding to a different preset type of memory; obtaining the storage address of the SPD information in the static storage module includes:

[0059] The CPLD selects the specified SPD information identified by the preset flag bit from the multiple SPD information according to the preset flag bit, and obtains the storage address of the specified SPD information.

[0060] CPLDs can use external pull-up and pull-down resistors to implement flag bits, representing SPD information for different memory models using different flag bits. The model numbers of each memory module in the electronic device are pre-obtained, and then the corresponding model flag bits are set as preset flag bits using pull-up and pull-down resistors. If the memory modules in the electronic device have different models, the flag bits corresponding to each memory model can be set sequentially according to a preset memory initialization order.

[0061] In a possible implementation, the static storage module stores a plurality of SPD information, and the plurality of SPD information correspond to different preset models of memories respectively; the storage address of the SPD information in the static storage module comprises:

[0062] The CPLD selects a designated SPD information specified by a preset logic version from the plurality of SPD information according to the preset logic version, and obtains the storage address of the designated SPD information.

[0063] The CPLD can include a preset logic version, which specifies which SPD information or which SPD information is selected as the designated SPD information, and can include the order in which the processor loads the SPD information (specifically, the order in which the storage address is sent to the processor can be controlled to control the order in which the processor loads the SPD information). The preset logic version can be specifically set according to the initialization order of the memory in the processor, and its specific encoding manner can refer to the encoding manner of the CPLD logic version in the related art, which will not be described here.

[0064] When the memory is replaced or the SPD information is updated (the SPD information update scenario includes increasing or decreasing the main frequency, increasing or decreasing the memory capacity, and modifying the memory parameters), the SPD information in the CPLD static storage module can be directly updated without removing the static storage module from the electronic device and reprogramming. In a possible implementation, referring to Figure 5 The method further comprises:

[0065] S501, after receiving the SPD update information, the CPLD updates the SPD information in the static storage module according to the SPD update information.

[0066] The SPD update information can be full update data of the SPD information, or incremental update data. In one example, after receiving the SPD update information, the processor parses the SPD update information to obtain update data (which can be full update data or incremental update data) of the SPD information. The processor sends the update data of the SPD information to the CPLD, and the SPD information in the static storage module of the CPLD is updated. In one example, the CPLD can directly use the SPD update information to complete the update of the SPD information in the static storage module of the CPLD.

[0067] S502, after the SPD information is updated, the electronic device is restarted.

[0068] After the updating of the SPD information in the static storage module of the CPLD is completed, the electronic device can be restarted (if the memory is replaced, the replacement of the memory in the electronic device can be completed before the electronic device is restarted, and then the electronic device is restarted) to complete the application of the updated SPD information. The specific starting mode of the electronic device can be referred to the starting mode of the electronic device in the above embodiment, which will not be described here.

[0069] In the embodiment of the present application, the SPD information in the static storage module of the CPLD can be directly modified through the CPLD, and the static storage module does not need to be removed for programming when the memory is replaced or the SPD information is updated. The SPD information in the static storage module can be directly updated through the CPLD, which can simplify the replacement process of the memory and reduce errors.

[0070] When the SPD information is updated in scenarios such as increasing or decreasing the main frequency, increasing or decreasing the memory capacity, and modifying the memory parameters, in a possible implementation, referring to Figure 6 The above method further includes:

[0071] S601, after receiving the SPD update information, the CPLD updates the SPD information in the static storage module according to the SPD update information.

[0072] The SPD update information can be full update data of the SPD information or incremental update data. In one example, after receiving the SPD update information, the processor parses the SPD update information to obtain update data (which can be full update data or incremental update data) of the SPD information. The processor sends the update data of the SPD information to the CPLD, and the SPD information in the static storage module of the CPLD is updated. In one example, the CPLD can directly use the SPD update information to complete the updating of the SPD information in the static storage module of the CPLD.

[0073] S602, after the updating of the SPD information is completed, the CPLD obtains the storage address of the SPD information in the static storage module.

[0074] S603, the CPLD triggers the processor to be powered on and started, and sends the storage address of the SPD information to the processor.

[0075] S604, the processor reads the SPD information according to the storage address, and initializes the memory according to the SPD information.

[0076] The CPLD triggers the processor to start up. When the processor starts up, the CPLD functions as an IIC (Inter-Integrated Circuit) receiving device. When the processor needs to read the SPD information, the SPD information can be read from the static storage module of the CPLD according to the storage address. The processor configures the read SPD information to the memory controller in the processor, thereby completing the initialization of the memory. Thereafter, the processor can normally access the memory by using the memory controller. In an example, the memory is a DDR memory, and the memory controller is a DDR controller.

[0077] In S605, the processor completes the start-up of the operating system.

[0078] After the processor can normally access the memory, the processor can load the operating system data into the memory, thereby completing the start-up of the operating system.

[0079] In the embodiment of the application, the SPD information in the static storage module of the CPLD can be directly modified through the CPLD. When the memory is replaced or the SPD information is updated, the static storage module does not need to be removed for programming. The SPD information in the static storage module can be directly updated through the CPLD, which can simplify the replacement procedure of the memory and reduce errors. Moreover, the restart of the processor can be realized without power-off of the CPLD, which can increase the restart speed.

[0080] The embodiment of the application further provides an electronic device, referring to Figure 7 , comprising:

[0081] The processor 11, the memory 12, and the CPLD 13. The CPLD 13 includes a static storage module. The static storage module stores SPD information.

[0082] The CPLD 13 is configured to complete the start-up of the CPLD itself after the electronic device is powered on, obtain the storage address of the SPD information in the static storage module, trigger the processor to start up, and send the storage address of the SPD information to the processor.

[0083] The processor 11 is configured to read the SPD information according to the storage address and initialize the memory according to the SPD information. The processor completes the start-up of the operating system.

[0084] The number of memories in the electronic device can be one or more, which are all within the protection scope of the application. The processor includes a memory controller. In an example, the memory can be a DDR memory, and the memory controller in the processor can be a DDR controller.

[0085] In a possible implementation, the static storage module stores a plurality of SPD information, and each of the SPD information corresponds to a memory of a different preset model; and the CPLD is specifically configured to select a specified SPD information identified by a preset flag from the plurality of SPD information according to the preset flag, and acquire a storage address of the specified SPD information.

[0086] In a possible implementation, the static storage module stores a pluralityity of SPD information, and each of the SPD information corresponds to a memory of a different preset model; and the CPLD is specifically configured to select a specified SPD information specified by a preset logic version from the plurality of SPD information according to the preset logic version, and acquire a storage address of the specified SPD information.

[0087] In a possible implementation, the CPLD is further configured to update the SPD information in the static storage module according to SPD update information after the SPD update information is received; and restart the electronic device after the SPD information is updated.

[0088] In a possible implementation, the CPLD is further configured to update the SPD information in the static storage module according to SPD update information after the SPD update information is received; acquire the storage address of the SPD information in the static storage module after the SPD information is updated; and trigger the processor to start and send the storage address of the SPD information to the processor.

[0089] The components in the electronic device can communicate through a communication bus, which can be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The communication bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0090] The electronic device can further include a communication interface for communication between the electronic device and other devices.

[0091] The electronic device can further include a memory for storing operating system data and the like of the electronic device, and the memory can include a RAM (Random Access Memory) and can further include a NVM (Non-Volatile Memory), such as at least one disk memory. Alternatively, the memory can be at least one storage device located away from the aforementioned processor.

[0092] The processor can be a processor of an X86 architecture, an X64 architecture, or an ARM architecture in terms of an operation architecture, and can be a general-purpose processor including a CPU (Central Processing Unit), an NP (Network Processor), and the like in terms of a hardware type of the processor. The processor can further be a DSP (Digital Signal Processing), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0093] The embodiments of the present application further provide a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement any of the electronic device starting methods.

[0094] In another embodiment provided by the present application, a computer program product containing instructions, which when executed on a computer, causes the computer to perform any of the electronic device starting methods.

[0095] In the embodiments described above, all or some of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or some of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into and executed by a computer, all or some of the processes or functions according to the embodiments described in the specification are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, DVD), or semiconductor media (for example, Solid State Disk (SSD)) and the like.

[0096] It should be noted that in this paper, the technical features in each optional scheme can be combined as long as they are not contradictory, and these schemes are within the scope disclosed in this paper. The relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0097] Each embodiment in the specification is described in a related manner, and the same and similar parts between each embodiment can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the embodiments of electronic devices, computer program products and storage media, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0098] The above merely provides the preferred embodiment of the present application, and not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An electronic device startup method, characterized by, The application is applied to an electronic device, which comprises a processor, a memory and a complex programmable logic device (CPLD). The CPLD comprises a static storage module, and a plurality of SPD information is stored in the static storage module. Each SPD information corresponds to a different preset model of memory. The method comprises the following steps: After the electronic device is powered on, the CPLD completes its own startup; The CPLD selects a specified SPD information identified by a preset flag in the plurality of SPD information, and acquires a storage address of the specified SPD information, or the CPLD selects a specified SPD information specified by a preset logic version in the plurality of SPD information, and acquires a storage address of the specified SPD information; The CPLD triggers the processor to start up and sends the storage address of the SPD information to the processor; The processor reads the SPD information according to the storage address, and initializes the memory according to the SPD information; The processor completes the startup of an operating system.

2. The method of claim 1, wherein, The method further comprises the following steps: After receiving SPD update information, the CPLD updates the SPD information in the static storage module according to the SPD update information; After the SPD information is updated, the electronic device is restarted.

3. The method of claim 1, wherein, The method further comprises the following steps: After receiving SPD update information, the CPLD updates the SPD information in the static storage module according to the SPD update information; After the SPD information is updated, the CPLD acquires the storage address of the SPD information in the static storage module; The CPLD triggers the processor to start up and sends the storage address of the SPD information to the processor; The processor reads the SPD information according to the storage address, and initializes the memory according to the SPD information; The processor completes the startup of an operating system.

4. An electronic device, comprising: The application comprises the following steps: A processor, a memory and a CPLD, wherein the CPLD comprises a static storage module, and a plurality of SPD information is stored in the static storage module. Each SPD information corresponds to a different preset model of memory. The CPLD is used to complete the startup of the CPLD itself after the electronic device is powered on. A specified SPD information identified by a preset flag is selected in the plurality of SPD information, and a storage address of the specified SPD information is acquired, or a specified SPD information specified by a preset logic version is selected in the plurality of SPD information, and a storage address of the specified SPD information is acquired. The processor is triggered to start up and the storage address of the SPD information is sent to the processor. The processor is used to read the SPD information according to the storage address, and initialize the memory according to the SPD information. And complete the startup of an operating system.

5. The electronic device of claim 4, wherein, The CPLD is further configured to update the SPD information in the static storage module according to the SPD update information after receiving the SPD update information; and restart the electronic device after the SPD information is updated.

6. The electronic device of claim 4, wherein, The CPLD is further configured to update the SPD information in the static storage module according to the SPD update information after receiving the SPD update information; obtain the storage address of the SPD information in the static storage module after the SPD information is updated; and trigger the processor to start up and send the storage address of the SPD information to the processor.

Images