Method for reading data from non-volatile storage unit and method for reading in-memory calculation data

Abstract

The embodiments of the present application provide a method for reading data from a non-volatile memory cell and a method for reading in-memory calculation data, which belong to the field of semiconductor technology. The method includes: in response to a first data read instruction, applying a first voltage to one end of the non-volatile memory device connected to the bit line, and applying a second voltage to one end of the three-terminal switch element connected to the source line, wherein the second voltage is lower than the first voltage, and the difference between the first voltage and the second voltage is greater than the threshold voltage of the three-terminal switch element; obtaining the storage data of the non-volatile memory device through the one end of the non-volatile memory device connected to the bit line. The present application can effectively avoid the problem that in the existing reverse reading process, a high voltage needs to be applied to the source line connected to the non-volatile memory device, resulting in a bias effect on the switch element, which in turn causes the threshold voltage of the switch element to change, affecting the reading speed and margin of the memory cell.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for reading data from a non-volatile storage unit and a method for reading in-memory computing data. Background Art

[0002] With the development of applications like artificial intelligence and big data, the amount of data computers must process has expanded dramatically. Under the traditional von Neumann computer architecture, the computational speeds of the processor and memory differ significantly. This massive amount of data exchange leads to increasing computational latency and energy consumption, a phenomenon known as the memory wall. In-memory computing is a key technology for addressing the memory wall problem. However, existing in-memory computing requires applying a high voltage to the source line connected to the memory cell when reading data from the memory array. This causes a bias effect on the switching element, which in turn shifts the switching element's threshold voltage, resulting in long reverse read times and low reverse read margins. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a method for reading data from a non-volatile storage unit and a method for reading in-memory computing data to solve the above-mentioned problems.

[0004] To achieve the above-mentioned objectives, the present application provides, in a first aspect, a method for reading data from a non-volatile memory cell, wherein the non-volatile memory cell includes a non-volatile memory device and a three-terminal switch element connected in series, and the reading method includes:

[0005] In response to a first data read instruction, applying a first voltage to a terminal of the nonvolatile memory device connected to a bit line, and applying a second voltage to a terminal of the three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0006] The storage data of the nonvolatile memory device is obtained through one end of the nonvolatile memory device connected to the bit line.

[0007] Optionally, the reading method further includes:

[0008] In response to a second data read instruction, applying a third voltage to a terminal of the three-terminal switch element connected to a source line, and applying a fourth voltage to a terminal of the non-volatile memory device connected to a bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element;

[0009] The storage data of the nonvolatile memory device is obtained through one end of the three-terminal switch element connected to the source line.

[0010] Optionally, one terminal of the nonvolatile memory device is connected to a bit line, the other terminal is connected to a first terminal of the three-terminal switch element, a second terminal of the three-terminal switch element is connected to a word line, and a third terminal of the three-terminal switch element is connected to a source line;

[0011] The word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply a first voltage or a fourth voltage to one end of the non-volatile memory device connected to the bit line, and the source line is used to apply a second voltage or a third voltage to one end of the three-terminal switch element connected to the source line.

[0012] Optionally, the stored data is a mapping of the current value on the bit line when the bit line voltage is a first voltage and the source line voltage is a second voltage when the current resistance state of the non-volatile memory device is in a state where the source line voltage is a third voltage and the bit line voltage is a fourth voltage.

[0013] Optionally, the first voltage is equal to the fourth voltage.

[0014] Optionally, the second voltage is equal to the third voltage.

[0015] Optionally, the non-volatile memory unit is a resistive random access memory.

[0016] Optionally, the resistive random access memory is a 1T1R resistive random access memory.

[0017] A second aspect of the present application provides a method for reading in-memory computing data, which is applied to an in-memory computing system. The in-memory computing system includes a non-volatile memory cell array composed of a plurality of non-volatile memory cells arranged in an array, wherein the non-volatile memory cells include a non-volatile memory device and a three-terminal switch element connected in series. The reading method includes:

[0018] In response to a first data read instruction, applying a first voltage to one end of each target nonvolatile memory device connected to a bit line, and applying a second voltage to one end of each target three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0019] The storage data of the nonvolatile memory devices outputted at one end connected to the bit line of all target nonvolatile memory devices are acquired.

[0020] Optionally, the reading method further includes:

[0021] In response to a second data read instruction, applying a third voltage to one end of each target three-terminal switch element connected to a source line, and applying a fourth voltage to one end of each target non-volatile memory device connected to a bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element;

[0022] The storage data of the nonvolatile memory device outputted at one end of all target three-terminal switch elements connected to the source line is acquired.

[0023] Optionally, one end of the non-volatile memory device is connected to a bit line, and the other end is connected to the first end of the three-terminal switch element, the second end of the three-terminal switch element is connected to a word line, and the third end of the three-terminal switch element is connected to a source line; each row of non-volatile memory cells is connected to the same word line and the same bit line, and each column of non-volatile memory cells is connected to the same source line, the word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply the first voltage or the fourth voltage to the end of the non-volatile memory device connected to the bit line, and the source line is used to apply the second voltage or the third voltage to the end of the three-terminal switch element connected to the source line.

[0024] Optionally, the bit line connected to the target non-volatile memory device is taken as the target bit line, and the source line connected to the target three-terminal switch element is taken as the target source line; the stored data is a mapping of the current value on the target bit line when the source line voltage on the target bit line is a second voltage, and the current resistance state of all non-volatile memory devices when the bit line voltage of the target bit line is a first voltage and the source line voltage of the target source line is a second voltage; or, the stored data is a mapping of the current value on the target source line when the bit line voltage of all non-volatile memory devices when the bit line voltage on the target source line is a fourth voltage and the source line voltage of the target source line is a third voltage and the bit line voltage of the target bit line is a fourth voltage.

[0025] Optionally, the first voltage is equal to the fourth voltage.

[0026] Optionally, the second voltage is equal to the third voltage.

[0027] Optionally, the non-volatile memory unit is a resistive random access memory.

[0028] Optionally, the resistive random access memory is a 1T1R resistive random access memory.

[0029] A third aspect of the present application provides a non-volatile memory cell data reading device, wherein the non-volatile memory cell includes a non-volatile memory device and a three-terminal switch element connected in series, and the device includes:

[0030] a control module configured to, in response to a first data read instruction, apply a first voltage to a terminal of the nonvolatile memory device connected to a bit line, and apply a second voltage to a terminal of the three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0031] The reading module is configured to obtain the storage data of the non-volatile memory device through one end of the non-volatile memory device connected to the bit line.

[0032] Optionally, the control module is further configured to, in response to a second data read instruction, apply a third voltage to a terminal of the three-terminal switch element connected to the source line, and apply a fourth voltage to a terminal of the non-volatile memory device connected to the bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element;

[0033] The read module is further configured to obtain storage data of the nonvolatile memory device through one end of the three-terminal switch element connected to the source line.

[0034] Optionally, one terminal of the nonvolatile memory device is connected to a bit line, the other terminal is connected to a first terminal of the three-terminal switch element, a second terminal of the three-terminal switch element is connected to a word line, and a third terminal of the three-terminal switch element is connected to a source line;

[0035] The word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply a first voltage or a fourth voltage to one end of the non-volatile memory device connected to the bit line, and the source line is used to apply a second voltage or a third voltage to one end of the three-terminal switch element connected to the source line.

[0036] Optionally, the stored data is a mapping of the current value on the bit line when the bit line voltage is a first voltage and the source line voltage is a second voltage when the current resistance state of the non-volatile memory device is in a state where the source line voltage is a third voltage and the bit line voltage is a fourth voltage.

[0037] A fourth aspect of the present application provides an in-memory computing data reading device, which is applied to an in-memory computing system. The in-memory computing system includes a non-volatile memory cell array composed of a plurality of non-volatile memory cells arranged in an array, wherein the non-volatile memory cells include a non-volatile memory device and a three-terminal switch element connected in series. The device includes:

[0038] a control module configured to, in response to a first data read instruction, apply a first voltage to one end of each target non-volatile memory device connected to a bit line, and apply a second voltage to one end of each target three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0039] The read module is configured to obtain storage data of the non-volatile memory devices outputted from one end of all target non-volatile memory devices connected to the bit line.

[0040] Optionally, the control module is further configured to, in response to a second data read instruction, apply a third voltage to a terminal of each target three-terminal switch element connected to a source line, and apply a fourth voltage to a terminal of each target non-volatile memory device connected to a bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element;

[0041] The read module is further configured to obtain storage data of the non-volatile memory device outputted at one end of all target three-terminal switch elements connected to the source line.

[0042] Optionally, one end of the non-volatile memory device is connected to a bit line, and the other end is connected to the first end of the three-terminal switch element, the second end of the three-terminal switch element is connected to a word line, and the third end of the three-terminal switch element is connected to a source line; each row of non-volatile memory cells is connected to the same word line and the same bit line, and each column of non-volatile memory cells is connected to the same source line, the word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply the first voltage or the fourth voltage to the end of the non-volatile memory device connected to the bit line, and the source line is used to apply the second voltage or the third voltage to the end of the three-terminal switch element connected to the source line.

[0043] Optionally, the bit line connected to the target non-volatile memory device is taken as the target bit line, and the source line connected to the target three-terminal switch element is taken as the target source line; the stored data is a mapping of the current value on the target bit line when the source line voltage on the target bit line is a second voltage, and the current resistance state of all non-volatile memory devices when the bit line voltage of the target bit line is a first voltage and the source line voltage of the target source line is a second voltage; or, the stored data is a mapping of the current value on the target source line when the bit line voltage of all non-volatile memory devices when the bit line voltage on the target source line is a fourth voltage and the source line voltage of the target source line is a third voltage and the bit line voltage of the target bit line is a fourth voltage.

[0044] In a fifth aspect, the present application provides a machine-readable storage medium having instructions stored thereon, which, when executed by a processor, configure the processor to execute the above-mentioned non-volatile storage unit data reading method, or, when executed by a processor, configure the processor to execute the above-mentioned in-memory computing data reading method.

[0045] When reversely reading the stored data in the non-volatile memory cell, the present application fixes the non-volatile memory device terminal of the non-volatile memory cell to a high voltage, and selects the non-volatile memory device based on controlling the three-terminal switch element terminal of the non-volatile memory cell to a low voltage, thereby effectively avoiding the problem of applying a high voltage to the source line connected to the non-volatile memory device during the existing reverse reading process, causing the switching element to produce a bias effect, which in turn causes the threshold voltage of the switching element to change, affecting the reading speed and margin of the memory cell.

[0046] Other features and advantages of the embodiments of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present application but do not constitute a limitation on the embodiments of the present application. In the accompanying drawings:

[0048] Figure 1 A flow chart of a method for reading data from a non-volatile storage unit provided in a preferred embodiment of the present application;

[0049] Figure 2 A schematic diagram of reverse reading of a resistive random access memory in the prior art;

[0050] Figure 3 A schematic diagram showing a comparison of the speeds of forward reading and reverse reading in the prior art;

[0051] Figure 4 Schematic diagram showing the comparison of the margins of forward reading and reverse reading in the prior art;

[0052] Figure 5 A schematic diagram of forward reading of a resistive random access memory provided by a preferred embodiment of the present application;

[0053] Figure 6 A schematic diagram of the in-memory computing system structure provided in a preferred embodiment of the present application;

[0054] Figure 7 A schematic block diagram of a non-volatile storage unit data reading device provided in a preferred embodiment of the present application. DETAILED DESCRIPTION

[0055] To make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the specific implementation methods described herein are only used to illustrate and explain the embodiments of the present application and are not used to limit the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0056] It should be noted that the technical solutions between the various embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0057] In order to solve the above problems, Figure 1 As shown, in a first aspect of this embodiment, a method for reading data from a non-volatile memory cell is provided. The non-volatile memory cell includes a non-volatile memory device and a three-terminal switch element connected in series. The reading method includes:

[0058] In response to a first data read instruction, applying a first voltage to a terminal of the nonvolatile memory device connected to the bit line, and applying a second voltage to a terminal of the three-terminal switch element connected to the source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0059] The storage data of the nonvolatile memory device is obtained through one end of the nonvolatile memory device connected to the bit line.

[0060] In this way, when reading the stored data in the non-volatile memory cell in reverse, this embodiment fixes the non-volatile memory device terminal of the non-volatile memory cell to a high voltage, and selects the non-volatile memory device based on controlling the three-terminal switch element terminal of the non-volatile memory cell to a low voltage, thereby effectively avoiding the problem of applying a high voltage to the source line connected to the non-volatile memory device during the existing reverse reading process, causing the switching element to produce a bias effect, and then causing the threshold voltage of the switching element to change, thereby affecting the reading speed and margin of the memory cell.

[0061] In existing in-memory computing, non-volatile memory cells are typically constructed based on memristors. These cells include a non-volatile memory device and a three-terminal switch connected in series. One end of the non-volatile memory device is connected to a bit line BL, and the other end is connected to the first end of the three-terminal switch. The second end of the three-terminal switch is connected to a word line WL, and the third end of the three-terminal switch is connected to a source line SL. The word line is used to provide a power supply voltage VDD to the three-terminal switch. The three-terminal switch is a MOS transistor. Currently, commonly used memristors include magnetic effect memristors, phase change effect memristors, and resistive random access memory. In a preferred embodiment of the present application, the non-volatile memory is a resistive random access memory (RRAM), preferably a 1T1R RRAM. Among them, the resistance state of the resistive memory includes a high resistance state and a low resistance state, which represent logic 0 and 1 respectively. The transition of its resistance state is achieved by applying voltages of different polarities at both ends of the resistive memory, corresponding to a write operation. For example, a reset operation is the process of changing the resistance state of the resistive memory from a low resistance state to a high resistance state, corresponding to writing 0; conversely, a set operation is the process of changing the resistance state of the resistive memory from a high resistance state to a low resistance state, corresponding to writing 1; a read operation is to read the resistance state of the resistive memory by applying a read voltage at both ends of the non-volatile memory cell. Since the current flowing through the resistive memory is different when the resistance state of the resistive memory is in a high resistance state and a low resistance state, the resistance state of the resistive memory can be obtained according to the read current.

[0062] When reading a resistive memory of a non-volatile memory cell, when a voltage greater than the threshold voltage of the MOS tube is added to the source line and the bit line, for example, the bit line is a high voltage V READ When the bit line is at a low level 0 or the two are opposite, a current determined by the resistance state of the resistive memory will be generated on the source line and the bit line. When the resistance state of the resistive memory is high resistance, that is, corresponding to 0, the current generated is low, and the read result corresponds to 0; when the resistance state of the resistive memory is low resistance, that is, corresponding to 1, the current generated is high, and the read result corresponds to 1.

[0063] like Figure 2 As shown, in the prior art, when performing reverse reading of a resistive memory, a fixed low level needs to be applied to the bit line. When the resistive memory is selected, that is, when the stored data of the resistive memory is to be read, a high voltage is applied to the source line corresponding to the resistive memory, thereby obtaining the stored data of the resistive memory on the bit line. However, since there is no other device blocking the source line and the MOS transistor in this case, a bias effect will be generated in the MOS transistor, resulting in a change in the switching threshold voltage of the MOS transistor, which in turn causes a time delay for the voltage difference between the source and drain of the MOS transistor to reach the switching threshold voltage of the MOS transistor, affecting the speed and margin of reverse reading, resulting in a time difference between the reverse reading and the forward reading. Figure 3 and Figure 4 As shown, in the existing reading method, the reverse reading speed is 33% of the forward reading speed, and the margin of the reverse reading is 80% of the margin of the forward reading.

[0064] In order to solve this problem, when the first data read instruction of the present application is to instruct to read the resistive memory in reverse, the read circuit is first controlled to set the bit line connected to the resistive memory to a fixed high level V READ , so as to apply a first voltage to the non-volatile memory device terminal of the non-volatile memory cell, and at the same time, set the source line connected to the MOS tube to a low level 0, so as to apply a second voltage to the three-terminal switch element terminal of the non-volatile memory cell. Since in this embodiment, the stored data is the current value of the current on the bit line when the bit line voltage is the first voltage and the source line voltage is the second voltage, the current I output on the bit line is read at this time. BL , after being decoded by the decoder, the current I BL In the reverse reading method of the present application, since the high level is blocked by the resistive memory and the MOS transistor, the MOS transistor will not produce a bias effect, thereby effectively improving the reverse reading speed and margin of the resistive memory.

[0065] In this embodiment, the reading method further includes: in response to a second data read instruction, applying a third voltage to one end of the three-terminal switch element connected to the source line, and applying a fourth voltage to one end of the non-volatile memory device connected to the bit line, the third voltage is lower than the fourth voltage, and the difference between the third voltage and the fourth voltage is greater than the threshold voltage of the three-terminal switch element; and obtaining the storage data of the non-volatile memory device through the one end of the three-terminal switch element connected to the source line.

[0066] Wherein, the second data read instruction is a forward read instruction, such as Figure 5 As shown in FIG, when a forward read instruction is received, the read circuit is first controlled to apply a fixed low level 0 to the source line connected to the MOS transistor, so as to apply a third voltage to the three-terminal switch element of the non-volatile memory cell, and at the same time, a high level V is applied to the bit line connected to the resistive memory. READ , to apply a fourth voltage to the non-volatile memory device terminal of the non-volatile memory unit. Since in this embodiment, the stored data is a mapping of the current value on the source line when the source line voltage is the third voltage and the bit line voltage is the fourth voltage, a current based on the resistance state of the resistive memory is generated on the source line and the bit line, and is output through the source line, and the current I output on the source line is read. SL , after being decoded by the decoder, the current I SLThe first voltage and the fourth voltage may be equal or unequal, and the second voltage and the third voltage may be equal or unequal. In a preferred embodiment of this embodiment, to facilitate read and write control, the first voltage and the fourth voltage are equal, and the second voltage and the third voltage are equal.

[0067] A second aspect of this embodiment provides a method for reading in-memory computing data, which is applied to an in-memory computing system. The in-memory computing system includes a non-volatile memory cell array composed of a plurality of non-volatile memory cells arranged in an array. The non-volatile memory cells include non-volatile memory devices and three-terminal switching elements connected in series. The non-volatile memory device end of the non-volatile memory cell is connected to a bit line, and the three-terminal switching element end is connected to a source line. Specifically, in the non-volatile memory cell array, one end of the non-volatile memory device is connected to a bit line, and the other end is connected to a first end of the three-terminal switching element. The second end of the three-terminal switching element is connected to a word line, and the third end of the three-terminal switching element is connected to a source line. Each row of non-volatile memory cells is connected to the same word line and the same bit line, and each column of non-volatile memory cells is connected to the same source line. The word line is used to provide a power supply voltage to the three-terminal switching element. The reading method includes:

[0068] In response to a first data read instruction, applying a first voltage to a terminal of each target nonvolatile memory device connected to a bit line, and applying a second voltage to a terminal of each target three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0069] The storage data of the nonvolatile memory devices outputted at one end connected to the bit line of all target nonvolatile memory devices are acquired.

[0070] In this embodiment, the bit line connected to the target non-volatile memory device is referred to as the target bit line, and the source line connected to the target three-terminal switch element is referred to as the target source line. Thus, by acquiring the stored data of all non-volatile memory devices on each target bit line whose source line voltage is a second voltage, the stored data of all non-volatile memory devices outputted at the target non-volatile memory device terminals can be acquired. The stored data is a mapping of the current value on the target bit line, representing the current state of all non-volatile memory devices on the target bit line whose source line voltage is the second voltage, when the bit line voltage of the target bit line is a first voltage and the source line voltage of the target source line is a second voltage.

[0071] like Figure 6As shown, in this embodiment, the in-memory computing system also includes WL and BL registers (WL & BL Registers), an input driver module (Input Driver for FF & BP), a CIM controller (CIM Controller), an analog-to-digital converter (ADC) and a shift adder (Shift & Adder) for processing data in each column of the non-volatile memory cell array, and an analog-to-digital converter (ADC) and a shift adder (Shift & Adder) for processing data in each row of the non-volatile memory cell array. The non-volatile memory cell array of this embodiment includes m×n non-volatile memory cells, wherein the non-volatile memory cells are also preferably 1T1R resistive random access memory. In the nonvolatile memory cell array of this embodiment, each row of nonvolatile memory cells shares a word line and a bit line, and each column of nonvolatile memory cells shares a source line. That is, for each row of nonvolatile memory cells, all resistive memory devices are connected to the same bit line, the gates of all MOS transistors are connected to the same word line, and for each column of nonvolatile memory cells, the control terminals of all MOS transistors are connected to the same source line. In addition, each word line, bit line, and source line in the nonvolatile memory cell array is connected to an input driver module. The bit line shared by each row of nonvolatile memory cells is connected to a row digital-to-analog converter, and the source line shared by each column of nonvolatile memory cells is connected to a column digital-to-analog converter. It can be understood that in a specific application, each row in the nonvolatile memory cell array can be used to store a binary number, and each resistive memory device in the row can store a bit value of the binary number.

[0072] Among them, the WL and BL registers are at least used to store array data representing the arrangement of word lines and bit lines in the non-volatile memory array. It can be understood that the array data can also include the arrangement data of source lines in the non-volatile memory array; the CIM controller is used to receive external control instructions and transmit the control instructions to the input driver module; the input driver module reads the array data in the WL and BL registers, and completes the read or write function by controlling the high and low levels of the corresponding bit lines and source lines in the non-volatile memory cells according to the control instructions and based on the array data; the non-volatile memory cell array, that is, the resistive memory array, is used to store data information, and outputs the stored data information in the form of current under the control of the input driver module; the analog-to-digital converter is used to convert the current signal output by the resistive memory array into a digital signal, and the shift adder is used to process the digital signal output by the analog-to-digital converter, complete the corresponding operation, and realize storage and calculation integration, wherein the shift adder includes a shift register and a full adder array.

[0073] When reverse reading the data in the resistive memory array, the CIM controller first parses and determines the resistive memory selected to read data in the first data read instruction, and then sends the instruction to the input driver module. The input driver module determines the control line corresponding to the selected resistive memory based on the selected resistive memory and the array data in the WL and BL registers, that is, the target bit line and target source line corresponding to the selected resistive memory. At the same time, the input driver module applies a fixed high voltage to the selected target bit line to apply a first voltage to the target non-volatile memory device terminal, and then applies a low voltage to the selected target source line to apply a second voltage to the target three-terminal switch element terminal, thereby selecting the corresponding resistive memory and obtaining the current I output on each bit line. BL , the output current I on each bit line is obtained BL After being decoded by the row analog-to-digital converter, it is input into the row shift adder for further calculation, thereby completing the reverse reading of the data and realizing the in-memory calculation. It can be understood that in this embodiment, the logical representations of high voltage and low voltage correspond to 1 and 0 respectively. In addition, if a high voltage is applied to the source line, it means that the resistive memory corresponding to the source line cannot be selected. In addition, when reading in reverse, a fixed high voltage can be applied only to the selected target bit line, or a fixed high voltage can be applied to all bit lines in the array. For any selected resistive memory, the output of the resistive memory is actually the product of the vector of the source line connected to it and the stored data of the resistive memory. For the bit line of any row in the resistive memory array, the output current I BL It can be mapped to the sum of the products of the storage data of each selected resistive memory and the vector of the source line corresponding to the resistive memory. It can be understood that when reading in reverse, when the source line is selected, the applied voltage of the source line is a low voltage, that is, 0, then the vector of the source line can be represented as 0, and when the resistance state of the resistive memory is a high resistance state, its storage data is represented as 0, and so on.

[0074] In this embodiment, when reading in the forward direction, the reading method further includes:

[0075] In response to a second data read instruction, applying a third voltage to each target source line and applying a fourth voltage to each target bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element;

[0076] Acquire storage data of all non-volatile memory devices on each target source line whose bit line voltage is the fourth voltage, where the storage data is a mapping of the current value on the target source line when the source line voltage of the target source line is the third voltage and the bit line voltage of the target bit line is the fourth voltage, respectively.

[0077] During forward reading, the input driver module applies a fixed low voltage to the selected target source line to apply a third voltage to the target three-terminal switch element, and then applies a high voltage to the selected target bit line to apply a fourth voltage to the target non-volatile memory device, thereby selecting the corresponding resistive memory and obtaining the current I output on each bit source. SL , the output current I on each source line will be obtained SL After being decoded by the column analog-to-digital converter, the input data enters the column shift adder for further calculation, thereby completing the forward reading of the data and implementing in-memory calculation. The first voltage and the fourth voltage may be equal or unequal, and the second voltage and the third voltage may be equal or unequal. In a preferred embodiment of this embodiment, to facilitate read and write control, the first voltage and the fourth voltage are equal, and the second voltage and the third voltage are equal.

[0078] It can be understood that in this embodiment, forward reading and reverse reading can correspond to the forward propagation calculation and reverse propagation calculation of the convolutional neural network respectively.

[0079] like Figure 7 As shown, a third aspect of this embodiment provides a non-volatile memory unit data reading device, wherein the non-volatile memory unit includes a non-volatile memory device and a three-terminal switch element connected in series, and the device includes:

[0080] a control module configured to, in response to a first data read instruction, apply a first voltage to a terminal of the nonvolatile memory device connected to the bit line, and apply a second voltage to a terminal of the three-terminal switch element connected to the source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0081] The reading module is configured to obtain the storage data of the non-volatile memory device through one end of the non-volatile memory device connected to the bit line.

[0082] Optionally, the control module is further configured to apply a third voltage to one end of the three-terminal switch element connected to the source line, and apply a fourth voltage to one end of the non-volatile memory device connected to the bit line in response to a second data read instruction, wherein the third voltage is lower than the fourth voltage, and the difference between the third voltage and the fourth voltage is greater than the threshold voltage of the three-terminal switch element; the reading module is further configured to obtain the storage data of the non-volatile memory device through one end of the three-terminal switch element connected to the source line.

[0083] Optionally, one end of the non-volatile memory device is connected to the bit line, the other end is connected to the first end of the three-terminal switching element, the second end of the three-terminal switching element is connected to the word line, and the third end of the three-terminal switching element is connected to the source line; the word line is used to provide a power supply voltage to the three-terminal switching element, the bit line is used to apply the first voltage or the fourth voltage to the end of the non-volatile memory device connected to the bit line, and the source line is used to apply the second voltage or the third voltage to the end of the three-terminal switching element connected to the source line.

[0084] Optionally, the stored data is a mapping of the current value on the bit line when the bit line voltage is a first voltage and the source line voltage is a second voltage, and the current resistance state of the non-volatile memory device is stored; or, the stored data is a mapping of the current value on the source line when the source line voltage is a third voltage and the bit line voltage is a fourth voltage, and the current resistance state of the non-volatile memory device is stored.

[0085] A fourth aspect of this embodiment provides an in-memory computing data reading device, which is applied to an in-memory computing system. The in-memory computing system includes a non-volatile memory cell array composed of a plurality of non-volatile memory cells arranged in an array, wherein the non-volatile memory cells include a non-volatile memory device and a three-terminal switch element connected in series. The device includes:

[0086] a control module configured to, in response to a first data read instruction, apply a first voltage to one end of each target non-volatile memory device connected to a bit line, and apply a second voltage to one end of each target three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element;

[0087] The read module is configured to obtain storage data outputted from one end of all target non-volatile memory devices connected to the bit line.

[0088] Optionally, the control module is further configured to apply a third voltage to one end of each target three-terminal switch element connected to the source line, and apply a fourth voltage to one end of each target non-volatile memory device connected to the bit line in response to a second data read instruction, wherein the third voltage is lower than the fourth voltage, and the difference between the third voltage and the fourth voltage is greater than the threshold voltage of the three-terminal switch element; the read module is further configured to obtain the storage data of the non-volatile memory device output at one end of all target three-terminal switch elements connected to the source line.

[0089] Optionally, one end of the non-volatile memory device is connected to a bit line, and the other end is connected to the first end of the three-terminal switch element, the second end of the three-terminal switch element is connected to a word line, and the third end of the three-terminal switch element is connected to a source line; each row of non-volatile memory cells is connected to the same word line and the same bit line, and each column of non-volatile memory cells is connected to the same source line, the word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply the first voltage or the fourth voltage to the end of the non-volatile memory device connected to the bit line, and the source line is used to apply the second voltage or the third voltage to the end of the three-terminal switch element connected to the source line.

[0090] Optionally, the bit line connected to the target non-volatile memory device is taken as the target bit line, and the source line connected to the target three-terminal switch element is taken as the target source line; the stored data is a mapping of the current value on the target bit line when the source line voltage on the target bit line is a second voltage, and the current resistance state of all non-volatile memory devices when the bit line voltage of the target bit line is a first voltage and the source line voltage of the target source line is a second voltage; or, the stored data is a mapping of the current value on the target source line when the bit line voltage of all non-volatile memory devices when the bit line voltage on the target source line is a fourth voltage and the source line voltage of the target source line is a third voltage and the bit line voltage of the target bit line is a fourth voltage.

[0091] It can be understood that in this embodiment, the control module and the reading module can be integrated on the same hardware or deployed on different hardware, which is not limited here.

[0092] The fifth aspect of this embodiment provides a machine-readable storage medium, which stores instructions. When the instructions are executed by the processor, the processor is configured to execute the above-mentioned non-volatile storage unit data reading method, or when the instructions are executed by the processor, the processor is configured to execute the above-mentioned in-memory computing data reading method.

[0093] Machine-readable storage media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0094] In summary, the present application can be applied to a convolutional neural network storage and computing integrated circuit implemented based on resistive random access memory. When the stored data in the resistive random access memory is read in reverse, one end of the resistive random access memory connected to the bit line is fixed to a high voltage, and the resistive random access memory is selected based on controlling the source line connected to the resistive random access memory to be a low voltage, thereby effectively avoiding the need to apply a high voltage to the source line connected to the resistive random access memory during the existing reverse reading process, resulting in a bias effect on the MOS tube, and then causing the threshold voltage of the MOS tube to change, affecting the reading speed and margin of the storage unit.

[0095] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0096] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0097] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0099] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0100] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A method for reading data from a non-volatile memory cell, wherein the non-volatile memory cell comprises a non-volatile memory device and a three-terminal switch element connected in series, wherein: The reading method comprises: In response to a first data read instruction, applying a first voltage to a terminal of the nonvolatile memory device connected to a bit line, and applying a second voltage to a terminal of the three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element; Acquiring storage data of the nonvolatile memory device through one end of the nonvolatile memory device connected to the bit line; The non-volatile storage unit is a 1T1R resistive random access memory, and the first data read instruction instructs reverse reading of the resistive random access memory.

2. The method for reading data from a non-volatile memory cell according to claim 1, wherein: The reading method further comprises: In response to a second data read instruction, applying a third voltage to a terminal of the three-terminal switch element connected to a source line, and applying a fourth voltage to a terminal of the non-volatile memory device connected to a bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element; Acquiring the storage data of the non-volatile memory device through one end of the three-terminal switch element connected to the source line; The second data read instruction is for instructing to read the resistive random access memory in the forward direction.

3. The method for reading data from a non-volatile memory cell according to claim 2, wherein: One end of the nonvolatile memory device is connected to a bit line, the other end is connected to a first end of the three-terminal switch element, a second end of the three-terminal switch element is connected to a word line, and a third end of the three-terminal switch element is connected to a source line; The word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply a first voltage or a fourth voltage to one end of the non-volatile memory device connected to the bit line, and the source line is used to apply a second voltage or a third voltage to one end of the three-terminal switch element connected to the source line.

4. The method for reading data from a non-volatile memory cell according to claim 3, wherein: The stored data is a mapping of the current value on the bit line when the bit line voltage is a first voltage and the source line voltage is a second voltage in the current resistance state of the non-volatile memory device; or, the stored data is a mapping of the current value on the source line when the source line voltage is a third voltage and the bit line voltage is a fourth voltage in the current resistance state of the non-volatile memory device.

5. The method for reading data from a non-volatile memory cell according to claim 2, wherein: The first voltage is equal to the fourth voltage.

6. The method for reading data from a non-volatile memory cell according to claim 2, wherein: The second voltage is equal to the third voltage.

7. A method for reading in-memory computing data, applied to an in-memory computing system, wherein the in-memory computing system includes a non-volatile memory cell array composed of a plurality of non-volatile memory cells arranged in an array, wherein the non-volatile memory cells include a non-volatile memory device and a three-terminal switch element connected in series, characterized in that: The reading method comprises: In response to a first data read instruction, applying a first voltage to one end of each target nonvolatile memory device connected to a bit line, and applying a second voltage to one end of each target three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element; Acquiring storage data of the non-volatile memory devices outputted at one end of all target non-volatile memory devices connected to the bit line; The non-volatile storage unit is a 1T1R resistive random access memory, and the first data read instruction instructs reverse reading of the resistive random access memory.

8. The method for reading in-memory computing data according to claim 7, wherein: The reading method further comprises: In response to a second data read instruction, applying a third voltage to one end of each target three-terminal switch element connected to a source line, and applying a fourth voltage to one end of each target non-volatile memory device connected to a bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element; Acquiring storage data of the non-volatile memory device outputted at one end of all target three-terminal switch elements connected to the source line; The second data read instruction is for instructing to read the resistive random access memory in the forward direction.

9. The method for reading in-memory computing data according to claim 8, wherein: One end of the non-volatile memory device is connected to a bit line, and the other end is connected to a first end of the three-terminal switch element. The second end of the three-terminal switch element is connected to a word line, and the third end of the three-terminal switch element is connected to a source line. Each row of non-volatile memory cells is connected to the same word line and the same bit line, and each column of non-volatile memory cells is connected to the same source line. The word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply a first voltage or a fourth voltage to the end of the non-volatile memory device connected to the bit line, and the source line is used to apply a second voltage or a third voltage to the end of the three-terminal switch element connected to the source line.

10. The method for reading in-memory computing data according to claim 9, characterized in that: A bit line connected to a target non-volatile memory device is taken as a target bit line, and a source line connected to a target three-terminal switch element is taken as a target source line; the stored data is a mapping of the current value on the target bit line when the source line voltage on the target bit line is a second voltage, and the current resistance state of all non-volatile memory devices when the bit line voltage of the target bit line is a first voltage and the source line voltage of the target source line is a second voltage; or the stored data is a mapping of the current value on the target source line when the bit line voltage of all non-volatile memory devices when the bit line voltage of the target source line is a fourth voltage and the source line voltage of the target source line is a third voltage and the bit line voltage of the target bit line is a fourth voltage.

11. The method for reading in-memory computing data according to claim 8, wherein: The first voltage is equal to the fourth voltage.

12. The method for reading in-memory computing data according to claim 8, wherein: The second voltage is equal to the third voltage.

13. A non-volatile memory unit data reading device, wherein the non-volatile memory unit comprises a non-volatile memory device and a three-terminal switch element connected in series, characterized in that: The device comprises: a control module configured to, in response to a first data read instruction, apply a first voltage to a terminal of the nonvolatile memory device connected to a bit line, and apply a second voltage to a terminal of the three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element; a reading module configured to obtain storage data of the non-volatile memory device through one end of the non-volatile memory device connected to the bit line; The non-volatile storage unit is a 1T1R resistive random access memory, and the first data read instruction instructs reverse reading of the resistive random access memory.

14. The non-volatile memory unit data reading device according to claim 13, wherein: The control module is further configured to, in response to a second data read instruction, apply a third voltage to a terminal of the three-terminal switch element connected to the source line, and apply a fourth voltage to a terminal of the non-volatile memory device connected to the bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element; The reading module is further configured to obtain the storage data of the non-volatile memory device through one end of the three-terminal switch element connected to the source line; The second data read instruction is for instructing to read the resistive random access memory in the forward direction.

15. The non-volatile memory unit data reading device according to claim 14, wherein: One end of the nonvolatile memory device is connected to a bit line, the other end is connected to a first end of the three-terminal switch element, a second end of the three-terminal switch element is connected to a word line, and a third end of the three-terminal switch element is connected to a source line; The word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply a first voltage or a fourth voltage to one end of the non-volatile memory device connected to the bit line, and the source line is used to apply a second voltage or a third voltage to one end of the three-terminal switch element connected to the source line.

16. The non-volatile memory unit data reading device according to claim 15, wherein: The stored data is a mapping of the current value on the bit line when the bit line voltage is a first voltage and the source line voltage is a second voltage in the current resistance state of the non-volatile memory device; or, the stored data is a mapping of the current value on the source line when the source line voltage is a third voltage and the bit line voltage is a fourth voltage in the current resistance state of the non-volatile memory device.

17. An in-memory computing data reading device, applied to an in-memory computing system, wherein the in-memory computing system includes a non-volatile memory cell array composed of a plurality of non-volatile memory cells arranged in an array, wherein the non-volatile memory cells include a non-volatile memory device and a three-terminal switch element connected in series, characterized in that: The device comprises: a control module configured to, in response to a first data read instruction, apply a first voltage to one end of each target non-volatile memory device connected to a bit line, and apply a second voltage to one end of each target three-terminal switch element connected to a source line, wherein the second voltage is lower than the first voltage, and a difference between the first voltage and the second voltage is greater than a threshold voltage of the three-terminal switch element; a reading module configured to obtain storage data of the non-volatile memory devices outputted from one end of all target non-volatile memory devices connected to the bit line; The non-volatile storage unit is a 1T1R resistive random access memory, and the first data read instruction instructs reverse reading of the resistive random access memory.

18. The in-memory computing data reading device according to claim 17, characterized in that: The control module is further configured to, in response to a second data read instruction, apply a third voltage to one end of each target three-terminal switch element connected to the source line, and apply a fourth voltage to one end of each target non-volatile memory device connected to the bit line, wherein the third voltage is lower than the fourth voltage, and a difference between the third voltage and the fourth voltage is greater than a threshold voltage of the three-terminal switch element; The read module is further configured to obtain storage data of the non-volatile memory device outputted at one end of all target three-terminal switch elements connected to the source line; The second data read instruction is for instructing to read the resistive random access memory in the forward direction.

19. The in-memory computing data reading device according to claim 18, characterized in that: One end of the non-volatile memory device is connected to a bit line, and the other end is connected to a first end of the three-terminal switch element. The second end of the three-terminal switch element is connected to a word line, and the third end of the three-terminal switch element is connected to a source line. Each row of non-volatile memory cells is connected to the same word line and the same bit line, and each column of non-volatile memory cells is connected to the same source line. The word line is used to provide a power supply voltage to the three-terminal switch element, the bit line is used to apply a first voltage or a fourth voltage to the end of the non-volatile memory device connected to the bit line, and the source line is used to apply a second voltage or a third voltage to the end of the three-terminal switch element connected to the source line.

20. The in-memory computing data reading device according to claim 19, characterized in that: A bit line connected to a target non-volatile memory device is taken as a target bit line, and a source line connected to a target three-terminal switch element is taken as a target source line; the stored data is a mapping of the current value on the target bit line when the source line voltage on the target bit line is a second voltage, and the current resistance state of all non-volatile memory devices when the bit line voltage of the target bit line is a first voltage and the source line voltage of the target source line is a second voltage; or the stored data is a mapping of the current value on the target source line when the bit line voltage of all non-volatile memory devices when the bit line voltage of the target source line is a fourth voltage and the source line voltage of the target source line is a third voltage and the bit line voltage of the target bit line is a fourth voltage.

21. A machine-readable storage medium having instructions stored thereon, characterized in that: When this instruction is executed by a processor, the processor is configured to execute the non-volatile storage unit data reading method described in any one of claims 1 to 6, or when this instruction is executed by a processor, the processor is configured to execute the in-memory computing data reading method described in any one of claims 7 to 12.

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