Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The method includes: forming a mask structure on a semiconductor substrate, forming a first opening and a second opening between the mask structures to expose the semiconductor substrate; etching the semiconductor substrate to form a first groove and a second groove in the semiconductor substrate, with the semiconductor substrate between the first groove and the second groove serving as a substrate lead-out region; removing a portion of the mask structure to expose the upper surface of the substrate lead-out region; performing ion implantation to form continuous ion-doped regions at the bottom of the first groove, the bottom of the second groove, the upper surface of the substrate lead-out region, and the side surfaces of the substrate lead-out region; and filling the first and second grooves with a dielectric to form a double isolation trench. By forming the ion-doped regions with high doping concentrations in the semiconductor substrate, gaps in the isolation structure are avoided, achieving better isolation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor technology, lateral double-diffused metal oxide semiconductor field-effect transistors (LDMOS) have become widely used due to their excellent short-channel characteristics. As a power switching device, LDMOS features relatively high operating voltage, simple manufacturing, and compatibility with low-voltage CMOS circuits.

[0003] In traditional LDMOS devices, an isolation ring is often required to separate the LDMOS from the substrate. However, traditional isolation rings no longer meet the electrical characteristics and small size requirements of semiconductor devices, becoming one of the factors that restrict device performance.

[0004] Therefore, it is necessary to provide a semiconductor device and a manufacturing method thereof to solve the above problems. Summary of the Invention

[0005] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0007] Providing a semiconductor substrate, forming a mask structure on the semiconductor substrate, forming a first opening and a second opening between the mask structures, wherein the first opening and the second opening expose the semiconductor substrate;

[0008] Etching the semiconductor substrate based on the first opening and the second opening to form a first groove and a second groove in the semiconductor substrate, wherein the semiconductor substrate between the first groove and the second groove serves as a substrate lead-out region;

[0009] removing a portion of the mask structure to expose the upper surface of the substrate lead-out region;

[0010] Performing ion implantation to form ion-doped regions that are continuous with each other on the bottom of the first groove, the bottom of the second groove, the upper surface of the substrate lead-out region, and the side surface of the substrate lead-out region;

[0011] A dielectric is filled in the first groove and the second groove to obtain a double isolation groove.

[0012] Furthermore, the method of providing a semiconductor substrate, forming a mask structure on the semiconductor substrate, forming a first opening and a second opening between the mask structures, wherein the first opening and the second opening expose the semiconductor substrate, further comprises:

[0013] Providing a semiconductor substrate, on which a first mask structure having a pre-opening is formed, wherein the pre-opening exposes the semiconductor substrate;

[0014] A second mask structure is formed on the semiconductor substrate exposed by the pre-opening, and a first opening and a second opening exposing the semiconductor substrate are formed between the second mask structure and the first mask structure.

[0015] Furthermore, the width of the pre-opening ranges from 0.8 μm to 3 μm, the widths of the first opening and the second opening range from 0.2 μm to 0.6 μm, the depth of the first groove ranges from 10 μm to 20 μm, and the depth of the second groove ranges from 10 μm to 20 μm.

[0016] Further, the notch area of ​​the first groove is larger than the bottom area of ​​the groove, the notch area of ​​the first groove is larger than the bottom area of ​​the groove, the second groove includes a first vertical sidewall and a first inclined sidewall, the second groove includes a second vertical sidewall and a second inclined sidewall, and the first inclined sidewall and the second inclined sidewall are the side surfaces of the substrate lead-out area.

[0017] Furthermore, the dose range of the ion implantation is 1E15 atoms / cm 2 -1E16atoms / cm 2 , and\or, the energy range of the ion implantation is 5KeV-30KeV.

[0018] Furthermore, the ion doping region is a highly doped ion doping region with a doping concentration greater than 1E20 atoms / cm 3 .

[0019] The present invention also provides a semiconductor device, comprising:

[0020] semiconductor substrates;

[0021] A first groove and a second groove are located in the semiconductor substrate and are both filled with a dielectric to serve as a double isolation trench, and the semiconductor substrate between the first groove and the second groove is a substrate lead-out region;

[0022] Continuous ion doping regions are formed at the bottom of the first groove, the bottom of the second groove, the upper surface of the substrate lead-out region, and the side surface of the substrate lead-out region to lead the semiconductor substrate out from between the double isolation grooves to the upper surface of the semiconductor substrate.

[0023] Furthermore, the notch area of ​​the first groove is larger than the groove bottom area of ​​the groove, the notch area of ​​the second groove is larger than the groove bottom area of ​​the groove, the first groove includes a first vertical sidewall and a first inclined sidewall, the second groove includes a second vertical sidewall and a second inclined sidewall, and the first inclined sidewall and the second inclined sidewall are the side surfaces of the substrate lead-out area.

[0024] Furthermore, the ion doping region is a highly doped ion doping region with a doping concentration greater than 1E20 atoms / cm 3 .

[0025] Furthermore, the groove depth of the first groove is in the range of 10 μm-20 μm, and the groove depth of the second groove is in the range of 10 μm-20 μm.

[0026] According to the semiconductor device and manufacturing method provided by the present invention, double isolation trenches are used, and no complex process of high-energy implantation and doping is required. Ordinary ion implantation is performed on the substrate lead-out region between the double isolation trenches, so that an ion doping region can be formed in the semiconductor substrate to realize the lead-out of the semiconductor substrate. This avoids the use of polycrystalline filling to lead out the semiconductor substrate. No gaps will appear in the substrate lead-out region, effectively reducing the resistance of the substrate lead-out region and achieving a better isolation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features, and advantages of the present invention will become more apparent through a more detailed description of the embodiments of the present invention with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and are not intended to limit the present invention. In the drawings, the same reference numerals generally represent the same components or steps.

[0028] In the attached figure:

[0029] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0030] Figures 2A-2G Schematic cross-sectional views of devices obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0031] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0032] It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0033] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0037] In LDMOS devices, a PN junction isolation ring separates the LDMOS from the substrate. To reduce the LDMOS area, this PN junction isolation ring can be replaced with a deep trench isolation ring. However, filling deep trenches with polysilicon inevitably creates gaps. These gaps are often located in the center, causing excessive etching in the subsequent etching step, resulting in a deep V-shaped pattern and hindering subsequent processing.

[0038] In addition, as the lead-out electrode (I-sub) at the isolation end, the polysilicon in the deep trench isolation ring must have a high P-type doping concentration. In production practice, the cost of separately equipping P-type doping equipment is high and the utilization rate is low.

[0039] Reference Figure 1 and Figures 2A-2G ,in Figure 1 A schematic flow chart showing a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention is shown. Figures 2A-2G Schematic cross-sectional views of devices obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention are shown.

[0040] The present invention provides a method for preparing a semiconductor device, such as Figure 1 As shown, the main steps of the preparation method include:

[0041] Step S101: providing a semiconductor substrate, forming a mask structure on the semiconductor substrate, forming a first opening and a second opening between the mask structures, wherein the first opening and the second opening expose the semiconductor substrate;

[0042] Step S102: etching the semiconductor substrate based on the first opening and the second opening to form a first groove and a second groove in the semiconductor substrate, wherein the semiconductor substrate between the first groove and the second groove serves as a substrate lead-out region;

[0043] Step S103: removing a portion of the mask structure to expose the upper surface of the substrate lead-out region;

[0044] Step S104: performing ion implantation to form continuous ion doping regions at the bottom of the first groove, the bottom of the second groove, the upper surface of the substrate lead-out region, and the side surface of the substrate lead-out region;

[0045] Step S105: filling the first groove and the second groove with a dielectric to obtain a double isolation groove.

[0046] According to an embodiment of the present invention, the method for manufacturing a semiconductor device of the present invention specifically includes the following steps:

[0047] First, execute step S101 to obtain Figure 2C A semiconductor substrate 200 is provided, on which a mask structure is formed, wherein a first opening 204 and a second opening 205 are formed between the mask structures, wherein the first opening 204 and the second opening 205 expose the semiconductor substrate 200 .

[0048] Further, if Figures 2A-2C As shown, a semiconductor substrate 200 is provided, a mask structure is formed on the semiconductor substrate 200, a first opening 204 and a second opening 205 are formed between the mask structure, and the first opening 204 and the second opening 205 expose the semiconductor substrate 200, and further includes:

[0049] A semiconductor substrate 200 is provided, on which a first mask structure 201 having a pre-opening 202 is formed, wherein the pre-opening 202 exposes the semiconductor substrate 200;

[0050] A second mask structure 203 is formed on the semiconductor substrate 200 exposed by the pre-opening 202 . A first opening 204 and a second opening 205 exposing the semiconductor substrate 200 are formed between the second mask structure 203 and the first mask structure 201 .

[0051] For example, the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and its specific doping concentration is not limited by the present invention. The semiconductor substrate 200 can be formed by epitaxial growth or can be a wafer substrate.

[0052] Illustratively, a well region (not shown) is formed in the semiconductor substrate 200 .

[0053] Exemplarily, a well implantation process is used to form a well region in the semiconductor substrate 200. The well region has a different doping type from that of the semiconductor substrate 200. In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and the well region is an N-type well region. Specifically, an N-well window is first formed on the P-type substrate, ion implantation is performed in the N-well window, and then an annealing step is performed to form the N-well.

[0054] Reference Figure 2A , providing a semiconductor substrate 200, forming a first mask structure 201 having a pre-opening 202 on the semiconductor substrate 200, wherein the pre-opening 202 exposes the semiconductor substrate 200, and further comprising:

[0055] First, a mask layer is formed on the semiconductor substrate 200 .

[0056] Exemplarily, the mask layer includes a hard mask layer, which includes an oxide layer, a nitride layer, or a stacked structure of the two, to protect the upper surface of the semiconductor substrate 200 during the manufacturing process of the LDMOS device. In this embodiment, the mask layer is a silicon oxide layer.

[0057] Next, the mask layer is patterned to form a first mask structure 201 having a pre-opening 202 . The pre-opening 202 exposes the semiconductor substrate 200 .

[0058] In an exemplary embodiment of the present invention, a photoresist layer (not shown) is first formed on the mask layer, and then an opening pattern is formed in the photoresist through exposure and development processes; then, the mask layer is etched using the patterned photoresist layer as a mask to transfer the opening pattern to the mask layer, forming a first mask structure 201 with a pre-opening 202, and the pre-opening 202 exposes the semiconductor substrate 200.

[0059] Exemplarily, the width of the pre-opening 202 ranges from 0.8 μm to 3 μm.

[0060] Exemplarily, dry etching can be used to etch the mask layer. Exemplarily, the dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination thereof. A single etching method can also be used, or more than one etching method can also be used.

[0061] For example, the sidewalls of the pre-opening 202 must be vertical, that is, the sidewalls of the pre-opening 202 are perpendicular to the plane of the semiconductor substrate 200. The vertical sidewalls are used to maintain the vertical morphology of the sidewalls of the etched semiconductor substrate 200 during subsequent etching of the semiconductor substrate 200.

[0062] Next, refer to Figures 2B-2C A second mask structure 203 is formed on the semiconductor substrate 200 exposed by the pre-opening 202 , and a first opening 204 and a second opening 205 are formed between the second mask structure 203 and the first mask structure 201 to expose the semiconductor substrate 200 .

[0063] In an exemplary embodiment of the present invention, a photoresist layer is first formed in the pre-opening 202, and then a square photoresist mask 203' is formed through exposure and development processes. Figure 2B A first opening 204 and a second opening 205 are formed between the photoresist mask 203 ′ and the first mask structure 201 , and both the first opening 204 and the second opening 205 expose the semiconductor substrate 200 .

[0064] Exemplarily, the width of the photoresist mask 203 ′ is in the range of 0.6 μm-2.4 μm; the width of the first opening 204 is in the range of 0.2 μm-0.6 μm, and the width of the second opening 205 is in the range of 0.2 μm-0.6 μm.

[0065] Furthermore, the photoresist mask 203' is etched to form a second mask structure 203, wherein the second mask structure 203 is a trapezoidal shape. Figure 2C That is, the sidewalls of the second mask structure 203 are inclined sidewalls.

[0066] Exemplarily, the photoresist mask 203 ′ is etched by introducing a dry etching source gas, wherein the dry etching source gas includes a fluorine-based gas (eg, CF 4 and CHF 3 ).

[0067] Next, execute step S102 to obtain Figure 2DThe semiconductor substrate 200 is etched based on the first opening 204 and the second opening 205 to form a first groove 206 and a second groove 207 in the semiconductor substrate 200 . The semiconductor substrate between the first groove 206 and the second groove 207 serves as a substrate lead-out region 208 .

[0068] For example, because the groove etching morphology will continue the morphology of the mask barrier layer, and the sidewalls of the first mask structure 201 are vertical sidewalls, and the sidewalls of the second mask structure 203 are inclined sidewalls, the notch area of ​​the obtained first groove 206 is larger than the bottom area of ​​the groove, and the notch area of ​​the second groove 207 is larger than the bottom area of ​​the groove. The first groove 206 includes a first vertical sidewall and a first inclined sidewall, and the second groove 207 includes a second vertical sidewall and a second inclined sidewall. The first inclined sidewall and the second inclined sidewall are the side surfaces of the substrate lead-out area 208.

[0069] Exemplarily, the method for forming the first groove 206 and the second groove 207 can be deep reactive ion etching (DRIE). Specifically, silicon hexafluoride (SF6 / CH4) gas is selected as the process gas, and a radio frequency power supply is applied to make the silicon hexafluoride reaction gas form a highly ionized state. During the etching step, the pressure is controlled at 15mT to 45mT, the source power is controlled at 400W to 600W, the bias power is controlled at -180V to -240V, the etching gas SF6 is controlled at 50sccm to 70sccm, O2 is controlled at 60sccm to 85sccm, and He is controlled at 100sccm to 400sccm to ensure the requirements of anisotropic etching. The deep reactive ion etching system can be selected from commonly used equipment and is not limited to a certain model.

[0070] Exemplarily, the groove depth of the first groove ranges from 10 μm to 20 μm, and the groove depth of the second groove ranges from 10 μm to 20 μm.

[0071] Furthermore, the first groove 206 and the second groove 207 are arranged around the well region.

[0072] Next, step S103 is performed to remove a portion of the mask structure to expose the upper surface of the substrate lead-out region 208;

[0073] Exemplarily, the removing of a portion of the mask structure to expose the upper surface of the substrate lead-out region further includes:

[0074] The portion of the mask structure is the second mask structure 203 .

[0075] In an embodiment, an ashing process is used to remove the second mask structure 203. Specifically, the semiconductor device is placed in a reactive etching apparatus. An additional heating device, such as a halogen lamp, is used to directly heat the chamber of the reactive etching apparatus at a temperature ranging from 150°C to 300°C. Then, an oxygen-containing gas is supplied to the heated chamber of the reactive etching apparatus. The oxygen-containing gas is selected from O2, H2O, N2, or any combination thereof. The flow rate of the oxygen-containing gas is 4000 sccm to 8000 sccm, and the ashing power is 300W to 1200W.

[0076] Next, execute step S104 to obtain Figure 2E The device structure shown in FIG. Ion implantation is performed to form continuous ion-doped regions 209 at the bottom of the first groove 206, the bottom of the second groove 207, the upper surface of the substrate lead-out region 208, and the side surface of the substrate lead-out region 208. The semiconductor substrate is sequentially led out to the upper surface of the semiconductor substrate through the bottom of the first groove 206 or the bottom of the second groove 207, the side surface of the substrate lead-out region 208, and the upper surface of the substrate lead-out region 208.

[0077] For example, ion implantation is performed using the first mask structure 201 as a mask toward the bottom of the first groove 206, the bottom of the second groove 207, the upper surface of the substrate lead-out region 208, and the side surface of the substrate lead-out region 208. Furthermore, the implanted ions are P-type ions, and the dose range of the ion implantation is 1E15 atoms / cm 2 -1E16atoms / cm 2 The energy range of the ion implantation is 5KeV-30KeV.

[0078] Furthermore, the ion implantation is performed to form ion-doped regions 209 that are continuous with each other at the bottom of the first groove 206 , the bottom of the second groove 207 , the upper surface of the substrate lead-out region 208 , and the side surface of the substrate lead-out region 208 , and further includes:

[0079] Heat treatment is performed to form an ion doping region in the entire substrate lead-out region 208. The ion doping region of the substrate lead-out region 208, the ion doping region at the bottom of the first groove 206, and the ion doping region at the bottom of the second groove 207 are connected to each other, and the following is obtained: Figure 2F The device structure shown.

[0080] In an exemplary embodiment of the present invention, the heat treatment is a long-term high-temperature heat treatment step similar to the push-well process, the heat treatment temperature is 900°C-1100°C, and the heat treatment time is 30min-300min, but is not limited to the numerical range.

[0081] For example, the ion doping region 209 is a highly doped ion doping region with a doping concentration greater than 1E20 atoms / cm 3 .like Figure 2F As shown, the ion-doped region 209 is trapezoidal in shape and is connected to the ion-doped region at the bottom of the first groove 206 and the ion-doped region at the bottom of the second groove 207 .

[0082] The method of the present invention forms the ion doped region 209, eliminating the need to purchase equipment specifically for producing P-type doped polysilicon, thereby avoiding increased production costs and the problem of gaps in the polysilicon filling process. Furthermore, the doping concentration of the formed ion doped region 209 is greater than 1E20 atoms / cm 3 , which is higher than the doping concentration of ordinary furnace tube preparation, which is only 1E16 atoms / cm 3 The doping concentration of the Isub lead-out region is increased, which is beneficial to the lead-out of Isub, reduces the resistance of the Isub end, and achieves better isolation effect.

[0083] Next, execute step S105 to obtain Figure 2G The first groove 206 and the second groove 207 are filled with dielectric to obtain a double isolation groove.

[0084] In an exemplary embodiment of the present invention, a silicon oxide layer is grown on the inner walls of the first groove 206 and the second groove 207 using a furnace tube process to serve as the dielectric layer 210. Specifically, wet oxidation is performed by introducing water vapor into the furnace tube. Compared to dry oxidation without introducing water vapor into the furnace tube, the wet oxidation method has a faster oxidation rate, which facilitates the formation of a thicker dielectric layer 210.

[0085] Optionally, after performing the thermal oxidation, a step of filling the first groove 206 and the second groove 207 with a dielectric material is further included.

[0086] In an exemplary embodiment of the present invention, when the dielectric layer 210 formed by thermal oxidation can completely fill the first groove 206 and the second groove 207, no subsequent filling step is required; however, when the dielectric layer 210 formed by thermal oxidation can only fill the lower parts of the first groove 206 and the second groove 207, and there are still gaps in the upper parts of the first groove 206 and the second groove 207, it is necessary to fill the first groove 206 and the second groove 207 with dielectric material.

[0087] For example, the method for filling the first groove 206 and the second groove 207 with the dielectric material may be selected from low-pressure chemical vapor deposition (LPCVD) such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), laser ablation deposition (LAD), and selective epitaxial growth (SEG). In exemplary embodiments of the present invention, chemical vapor deposition (CVD) is preferred.

[0088] After trench filling, a double isolation trench is formed. The substrate on one side of the double isolation trench serves as the first device region, while the other side serves as the second device region. The Isub current generated by the first device region during operation travels along a path with lower resistivity (i.e., the substrate lead-out region) to the Isub end (i.e., the upper surface of the substrate lead-out region), significantly minimizing its impact on the second device region and effectively isolating the first and second device regions.

[0089] According to the semiconductor device and manufacturing method provided by the present invention, double isolation trenches are used, and no complex process of high-energy implantation and doping is required. Ordinary ion implantation is performed on the substrate lead-out region between the double isolation trenches, so that an ion doping region can be formed in the semiconductor substrate to realize the lead-out of the semiconductor substrate. This avoids the use of polycrystalline filling to lead out the semiconductor substrate. No gaps will appear in the substrate lead-out region, effectively reducing the resistance of the substrate lead-out region and achieving a better isolation effect.

[0090] The present invention also provides a semiconductor device, such as Figures 2A-2G Shown, including:

[0091] a semiconductor substrate 200;

[0092] A first groove 206 and a second groove 207 are located in the semiconductor substrate 200 and are filled with a dielectric to serve as a double isolation trench. The semiconductor substrate between the first groove 206 and the second groove 207 is a substrate lead-out region 208;

[0093] Continuous ion doping regions 209 are formed at the bottom of the first groove 206, the bottom of the second groove 207, the upper surface of the substrate lead-out region 208, and the side surface of the substrate lead-out region 208 to lead the semiconductor substrate out from between the double isolation grooves to the upper surface of the semiconductor substrate 200.

[0094] Exemplarily, the semiconductor device includes an LDMOS device.

[0095] For example, the semiconductor substrate 200 may be at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In this embodiment, the semiconductor substrate 200 is a P-type silicon substrate (P-sub), and its specific doping concentration is not limited by the present invention. The semiconductor substrate 200 can be formed by epitaxial growth or can be a wafer substrate.

[0096] Illustratively, a well region (not shown) is formed in the semiconductor substrate 200 , and the double isolation trenches are disposed around the well region.

[0097] Exemplarily, the notch area of ​​the first groove 206 is larger than the bottom area of ​​the groove, the notch area of ​​the second groove 207 is larger than the bottom area of ​​the groove, the first groove 206 includes a first vertical sidewall and a first inclined sidewall, the second groove 207 includes a second vertical sidewall and a second inclined sidewall, and the first inclined sidewall and the second inclined sidewall are the side surfaces of the substrate lead-out area.

[0098] For example, the doping ions in the ion doping region 209 are P-type ions, and the doping concentration of the ion doping region 209 is greater than 1E20 atoms / cm 3 .

[0099] Exemplarily, the groove depth of the first groove 206 is in the range of 10 μm-20 μm, and the groove depth of the second groove is in the range of 10 μm-20 μm.

[0100] For example, the doping concentration of the ion doping region 209 is greater than 1E20 atoms / cm 3 The method of the present invention forms the ion doping region 209, eliminating the need to purchase equipment specifically for producing P-type doped polysilicon, thereby avoiding increased production costs and the problem of gaps in polysilicon filling. Furthermore, the doping concentration of the formed ion doping region 209 is greater than 1E20 atoms / cm 3 , which is higher than the doping concentration of ordinary furnace tube preparation, which is only 1E16 atoms / cm 3 The doping concentration of the Isub lead-out region is increased, which is beneficial to the lead-out of Isub, reduces the resistance of the Isub end, and achieves better isolation effect.

[0101] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, forming a mask structure on the semiconductor substrate, forming a first opening and a second opening between the mask structures, wherein the first opening and the second opening expose the semiconductor substrate; Etching the semiconductor substrate based on the first opening and the second opening to form a first groove and a second groove in the semiconductor substrate, wherein the semiconductor substrate between the first groove and the second groove serves as a substrate lead-out region; removing a portion of the mask structure to expose the upper surface of the substrate lead-out region; Performing ion implantation to form ion-doped regions that are continuous with each other on the bottom of the first groove, the bottom of the second groove, the upper surface of the substrate lead-out region, and the side surface of the substrate lead-out region; A dielectric is filled in the first groove and the second groove to obtain a double isolation groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further comprises providing a semiconductor substrate, forming a mask structure on the semiconductor substrate, forming a first opening and a second opening between the mask structures, wherein the first opening and the second opening expose the semiconductor substrate, and further comprising: Providing a semiconductor substrate, on which a first mask structure having a pre-opening is formed, wherein the pre-opening exposes the semiconductor substrate; A second mask structure is formed on the semiconductor substrate exposed by the pre-opening, and the first opening and the second opening exposing the semiconductor substrate are formed between the second mask structure and the first mask structure.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The width of the pre-opening is in the range of 0.8 μm-3 μm, the width of the first opening and the second opening are both in the range of 0.2 μm-0.6 μm, the depth of the first groove is in the range of 10 μm-20 μm, and the depth of the second groove is in the range of 10 μm-20 μm.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The notch area of ​​the first groove is larger than the groove bottom area of ​​the groove, the notch area of ​​the second groove is larger than the groove bottom area of ​​the groove, the first groove includes a first vertical sidewall and a first inclined sidewall, the second groove includes a second vertical sidewall and a second inclined sidewall, and the first inclined sidewall and the second inclined sidewall are the side surfaces of the substrate lead-out area.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The dose range of the ion implantation is 1E15 atoms / cm 2 -1E16atoms / cm 2 , and\or, the energy range of the ion implantation is 5KeV-30KeV.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The ion doping region is a highly doped ion doping region with a doping concentration greater than 1E20 atoms / cm 3 .

7. A semiconductor device, characterized in that: The semiconductor device is obtained by the manufacturing method according to any one of claims 1 to 6, and the semiconductor device comprises: semiconductor substrates; A first groove and a second groove are located in the semiconductor substrate and are both filled with a dielectric to serve as a double isolation trench, and the semiconductor substrate between the first groove and the second groove is a substrate lead-out region; Continuous ion doping regions are formed at the bottom of the first groove, the bottom of the second groove, the upper surface of the substrate lead-out region, and the side surface of the substrate lead-out region to lead the semiconductor substrate out from between the double isolation grooves to the upper surface of the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein The notch area of ​​the first groove is larger than the groove bottom area of ​​the groove, the notch area of ​​the second groove is larger than the groove bottom area of ​​the groove, the first groove includes a first vertical sidewall and a first inclined sidewall, the second groove includes a second vertical sidewall and a second inclined sidewall, and the first inclined sidewall and the second inclined sidewall are the side surfaces of the substrate lead-out area.

9. The semiconductor device according to claim 7, wherein The ion doping region is a highly doped ion doping region with a doping concentration greater than 1E20 atoms / cm 3 .

10. The semiconductor device according to claim 7, wherein The first groove has a depth ranging from 10 μm to 20 μm, and the second groove has a depth ranging from 10 μm to 20 μm.

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