A test structure and monitoring method for floating source contact etching process

Abstract

The present application discloses a test structure and monitoring method for a floating source contact etching process. The test structure includes: a semiconductor substrate configured as a lower plate, the semiconductor substrate includes an active area and an inactive area; a barrier layer, located on the active area of ​​the semiconductor substrate; a dielectric layer, covering the semiconductor substrate and the barrier layer; a plurality of upper plates arranged at intervals from each other, the plurality of upper plates are located above the active area, the upper plates include holes and conductive materials filled in the holes, the holes penetrate the dielectric layer and extend to the barrier layer; a contact hole, penetrates the dielectric layer and extends to the semiconductor substrate; an upper plate metal interconnection, located above the plurality of upper plates and electrically connected to the plurality of upper plates, and the plurality of upper plates are connected in parallel and electrically connected to the upper plate pad; a lower plate metal interconnection, located above the contact hole and electrically connected to the contact hole, and the semiconductor substrate is electrically connected to the lower plate pad.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a test structure and a monitoring method for a floating source contact etching process. Background Art

[0002] Currently, the industry often uses metal plate, floating source contact, or gate plate to enhance the surface field (RESUF) reduction for the device architecture of medium voltage (16-80V) NLDMOS, so as to achieve an increase in the off-state voltage (BVoff) at the same Rsp capability.

[0003] Among them, the floating metal of the bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor process (BCD) is integrated into the through-hole etching process (no additional layer of photoresist is required to define the floating metal, and the technology is named floating source contact). Generally, the process monitoring after through-hole etching is to measure the critical dimension (CD) and perform microscopic inspection after etching. However, after integrating the floating source contact etching technology, it is not enough to only monitor the through-hole CD and microscopic inspection, because the distance between the bottom of the floating source contact and the substrate surface will directly affect the electric field distribution of the drift region through RESUF, thereby affecting the off-state breakdown voltage capability of the high-voltage device. Therefore, it is necessary to increase the corresponding floating source contact process stability monitoring, including monitoring the fluctuation between different batches, monitoring between wafers in the same batch (wafer to wafer), and uniformity monitoring within the same wafer.

[0004] The current monitoring technology can only slice after etching is completed to confirm whether the hovering distance meets the requirements. The disadvantages of the existing technology are high cost, low efficiency, and cannot be monitored in real time.

[0005] Therefore, it is necessary to improve the current preparation method to solve the above problems. Summary of the invention

[0006] In view of the problems existing in the prior art, the present application provides a test structure for a floating source contact etching process, the test structure comprising:

[0007] A semiconductor substrate configured as a lower plate, wherein the semiconductor substrate includes an active region and an inactive region;

[0008] A barrier layer, located on the active area of ​​the semiconductor substrate;

[0009] a dielectric layer, covering the semiconductor substrate and the barrier layer;

[0010] A plurality of upper plates spaced apart from each other, the plurality of upper plates being located above the active area, the upper plates comprising holes and a conductive material filled in the holes, the holes penetrating the dielectric layer and extending to the barrier layer;

[0011] A contact hole, penetrating the dielectric layer and extending to the semiconductor substrate;

[0012] An upper electrode plate metal interconnection is located above the plurality of upper electrode plates and is electrically connected to the plurality of upper electrode plates, and the plurality of upper electrode plates are connected in parallel and then electrically connected to the upper electrode plate pad;

[0013] The lower plate metal interconnection is located above the contact hole and electrically connected to the contact hole, and electrically connects the semiconductor substrate to the lower plate pad.

[0014] Optionally, the projections of the multiple upper plates on the horizontal plane are in the shape of a long strip, the length of the upper plates extends along a first direction, the multiple upper plates are arranged in parallel at equal intervals along a second direction, and the first direction and the second direction are perpendicular to each other.

[0015] Optionally, the length of the upper electrode plate is greater than 50um, and the width ranges from 0.2um to 1um.

[0016] Optionally, the test structure further includes:

[0017] A plurality of doped regions, located on the surface of the semiconductor substrate and not covered by the barrier layer, serve as lead-out regions of the semiconductor substrate.

[0018] Optionally, the upper plate pad and the lower plate pad are located on the dielectric layer on the non-active area of ​​the semiconductor substrate.

[0019] Optionally, the barrier layer includes a plasma oxide layer, a silicon nitride layer and a silicon oxynitride layer stacked in sequence from the surface of the semiconductor substrate.

[0020] Optionally, a size of the active region in the first direction is 50 um to 75 um, and a size of the active region in the second direction is 50 um to 500 um.

[0021] The present application also provides a monitoring method based on the test structure described above, the monitoring method comprising:

[0022] After forming the hole groove in the dielectric layer, measuring the depth of the hole groove in real time;

[0023] After forming the barrier layer and the dielectric layer, measuring the sum of the thicknesses of the barrier layer and the dielectric layer in real time;

[0024] Calculating the physical thickness of the barrier layer between the upper plate and the lower plate according to the depth of the hole groove and the sum of the thickness of the barrier layer and the dielectric layer;

[0025] After forming the upper plate metal interconnection and the lower plate metal interconnection, measuring the capacitance value between the upper plate pad and the lower plate pad;

[0026] The electrical thickness of the barrier layer between the upper electrode plate and the lower electrode plate is calculated using the capacitance value.

[0027] Optionally, the depth of the hole and / or the sum of the thickness of the barrier layer and the dielectric layer is measured by an optical critical dimension scattering measurement method.

[0028] Optionally, the monitoring method further includes:

[0029] Monitoring the floating source contact etching process by the thickness of the barrier layer between the upper plate and the lower plate comprises:

[0030] Determine whether the thickness of the barrier layer between the upper electrode plate and the lower electrode plate is within the target thickness range, and if the error exceeds a set threshold, feedback is given to the hole and groove etching machine;

[0031] The hole and groove etching machine adjusts the hole and groove etching process according to the feedback information so that the thickness of the barrier layer between the upper electrode plate and the lower electrode plate is within the target thickness range.

[0032] In parallel, in order to solve the current technical problems, the present application provides a test structure and a monitoring method for a floating source contact etching process, which can be used for both physical thickness monitoring of the source contact hovering distance and electrical thickness monitoring during WAT testing.

[0033] The advantages of this application are:

[0034] 1. The physical thickness and electrical thickness can be collected on the same test key, the process control capability of source contact is improved, and the space occupied by multiple test structures is reduced.

[0035] 2. It can realize real-time and accurate monitoring and save slicing costs.

[0036] 3. The test structure can stabilize the process to the greatest extent and effectively resist various factors that are not conducive to process stability: fluctuations in the thickness of the front-layer medium, fluctuations in the CD of the front-layer photolithography, changes in the etching rate before, during and after the life time of the station, changes in the gas environment of the etching chamber, etc., and ultimately output stable high-voltage device characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,

[0038] Figure 1 is a schematic top view of a test structure described in an embodiment of the present application;

[0039] Figure 2 For this application Figure 1 A schematic diagram of the cross-sectional structure of the test structure along the A-A1 direction;

[0040] Figure 3 This is a flow chart of a monitoring method described in one embodiment of the present application;

[0041] Figure 4 A block diagram of the monitoring method described in another embodiment of the present application. DETAILED DESCRIPTION

[0042] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0043] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0045] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] In order to thoroughly understand the present application, a detailed structure will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail as follows, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0048] In order to solve the existing problems, the present application provides a test structure for a floating source contact etching process, such as Figure 1 and Figure 2 As shown, the test structure includes:

[0049] A semiconductor substrate 101, configured as a lower plate, the semiconductor substrate comprising an active region and an inactive region;

[0050] A barrier layer 102, located on the active region of the semiconductor substrate 101;

[0051] A dielectric layer, covering the semiconductor substrate 101 and the barrier layer 102;

[0052] A plurality of upper plates 103 are arranged at intervals from each other, the plurality of upper plates are located above the active area, the upper plates include holes and a conductive material filled in the holes, the holes penetrate the dielectric layer and extend to the barrier layer;

[0053] A contact hole 106, penetrating the dielectric layer and extending to the semiconductor substrate;

[0054] An upper plate metal interconnect 104 is located above the plurality of upper plates 104 and is electrically connected to the plurality of upper plates 104 , and the plurality of upper plates 104 are connected in parallel and then electrically connected to an upper plate pad;

[0055] The bottom plate metal interconnection 107 is located above the contact hole 106 and is electrically connected to the contact hole 106 , and electrically connects the semiconductor substrate 101 to the bottom plate pad.

[0056] The test structure described in this application is described in detail below with reference to the accompanying drawings. Figure 1 is a schematic top view of a test structure described in an embodiment of the present application; Figure 2 Schematic diagram of the cross-sectional structure of the test structure described in one embodiment of the present application.

[0057] like Figure 1 As shown, in the test structure, the semiconductor substrate 101 can be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0058] The semiconductor substrate 101 is N-type doped, and the doping concentration is not limited to a certain numerical range and is not limited here.

[0059] Optionally, the semiconductor substrate 101 is used in the present application to form a lower plate of a capacitor. In order to lead out the lower plate, a doping region 105 is further formed in the edge area of ​​the semiconductor substrate 101, wherein the doping concentration of the doping region 105 is greater than the doping concentration of the N-type doping.

[0060] Optionally, the doping region 105 is N-type doped.

[0061] Furthermore, the doping region 105 is formed in an edge region of the semiconductor substrate 101 , for example, the doping region 105 is formed in an outer ring of the semiconductor substrate 101 .

[0062] Furthermore, the region in the semiconductor substrate 101 for forming the test structure may be in the shape of a square, that is, the projection of the semiconductor substrate 101 on a horizontal plane is in the shape of a square.

[0063] The semiconductor substrate 101 includes an active region and an inactive region. The active region may be formed in a central region of the semiconductor substrate 101 .

[0064] The barrier layer 102 is located in the central area of ​​the semiconductor substrate 101 , covers the central area and the active area of ​​the semiconductor substrate 101 , and exposes the doped area 105 in the edge area of ​​the semiconductor substrate 101 to be configured for subsequent lead-out of the lower electrode.

[0065] The barrier layer 102 is made of insulating material, and the portion of the barrier layer 102 between the upper electrode plate 103 and the lower electrode plate is configured as a dielectric material of a capacitor.

[0066] The barrier layer 102 includes at least one of a plasma enhanced oxide layer PEOX, SIN, and SION.

[0067] In one embodiment of the present application, the barrier layer 102 includes plasma enhanced oxide layers PEOX, SIN, and SION stacked in sequence from the surface of the semiconductor substrate.

[0068] A dielectric layer is further formed on the semiconductor substrate 101 and the barrier layer 102 , and the dielectric layer may be at least one of BPSG and TEOS.

[0069] In an embodiment of the present application, the dielectric layer includes BPSG and TEOS deposited sequentially.

[0070] A plurality of upper plates 103 having a physical thickness corresponding to a hovering distance from the semiconductor substrate 101 are formed above the semiconductor. The plurality of upper plates 103 are spaced apart from each other to form a plurality of capacitors connected in parallel.

[0071] The upper plate 103 includes a hole and a conductive material filled in the hole, the hole penetrates the dielectric layer and extends to the barrier layer, for example, the hole penetrates the dielectric layer and is partially embedded in the barrier layer 102. The upper plate 103 and the lower plate are two plates of the capacitor, and the barrier layer 102 located between the upper plate 103 and the lower plate serves as the dielectric of the capacitor.

[0072] The upper electrode plate 103 is formed in the active area of ​​the test structure.

[0073] Among them, Figure 1 As shown, the plurality of upper plates 103 are in a long strip structure, for example, a rectangular structure, the length of the upper plates 103 extends along a first direction B-B1, and the plurality of upper plates 103 are arranged side by side along a second direction A-A1, and the first direction B-B1 and the second direction A-A1 are perpendicular to each other.

[0074] In one embodiment of the present application, the plurality of upper plates 103 are arranged in parallel at equal intervals in the second direction.

[0075] In one embodiment of the present application, Figure 1 As shown, the upper electrode plates 103 extend in the left-right direction, and the upper electrode plates 103 are arranged in parallel in the up-down direction of the paper to form an array of the upper electrode plates 103. The upper electrode plates 103 are arranged at intervals.

[0076] In order to realize the parallel connection of capacitors in the present application, the test structure further includes an upper plate metal interconnect 104 for connecting the plurality of upper plates 103 in parallel, and the upper plate metal interconnect 104 is connected to the upper plate pad.

[0077] The upper plate metal interconnect 104 is a square structure, for example, completely covers the upper plate 103 , and is electrically connected to the top of the upper plate 103 .

[0078] In the present application, the length c of the hole groove is greater than or equal to 50um, and the width a varies from 0.2 to 1um, so as to facilitate monitoring of NLDMOS with different voltage levels (the drift region size will be different for different NLDMOS voltage levels, and the size of the required floating source contact will also change. The distance b between the hole grooves is 0.2 to 1um.

[0079] Among them, the test structure also includes: multiple contact holes 106, one end of the contact hole 106 is located on the doping area 105 and forms an electrical connection with the doping area 105, and the other end of the contact hole 106 is electrically connected to the lower electrode metal interconnection 107, wherein the lower electrode metal interconnection 107 and the lower electrode pad further lead out the lower electrode.

[0080] In one embodiment of the present application, Figure 1 As shown, the lower plate metal interconnection 107 is in the form of a square ring with an opening, and is disposed around the upper plate metal interconnection 104 .

[0081] Among them, Figure 1 As shown, in the second direction A-A1, the doping regions 105 are located on both sides of the plurality of upper plates 103. The contact holes 106 are located on both sides of the plurality of upper plates 103.

[0082] Furthermore, the critical dimension f of the contact hole 106 is in the range of 0.17um to 0.24um, serving as a lower plate lead-out port.

[0083] The test structure described in the present application utilizes the characteristics of a floating source contact (source floating contact) and the presence of a barrier layer 102 on the surface of a semiconductor substrate 101 to design a capacitor structure, in which an upper plate 103 is a floating source contact, and a lower plate is a semiconductor substrate 101, which are respectively led to an upper plate metal interconnect 104 and a lower plate metal interconnect 107. Then, the stability of the test capacitance value can be monitored by WAT, and the thickness of the barrier layer 102 between the upper plate 103 and the lower plate is calculated by the capacitance value to evaluate the stability of the electrical thickness.

[0084] The plurality of upper plates 103 are formed in the active area, and the active area is a square structure. The size of the active area has special requirements, so as to realize online film thickness machine monitoring (the film thickness instrument adopts Optical Critical DimensionScatterometry Measurements-OCD for short, with a spot size of about 50um*50um). As shown in Figure 1, the active width d is controlled at 50-55um to facilitate placing the structure in a 60um wide scribe groove. If an 80um scribe groove is selected, d can be controlled at 70-75um.

[0085] The active region length e is controlled within a range of 50 um to 500 um, wherein the specific length needs to be considered to be suitable for detection considering the size of the total capacitance value.

[0086] In the present application, the test structure can also be used to test the physical thickness of the source contact hovering distance. In the present application, after the hole groove is formed, the physical thickness of the source contact hovering distance can be monitored in real time by an online film thickness machine.

[0087] For example, in one embodiment of the present application, after the hole is formed, the sum of the thicknesses of the barrier layer and the dielectric layer is measured by OCD, and then the depth of the hole is measured, and the difference between the two is the physical thickness of the source contact hovering distance.

[0088] The test structure described in the present application can be used for both physical thickness monitoring of the source contact hovering distance and electrical thickness monitoring during WAT testing. Physical thickness and electrical thickness can be collected on the same set of test structures (test key), the process control capability of the source contact is improved, and the space occupied by multiple test structures is reduced.

[0089] The present application also provides a monitoring method based on the test structure described above, such as Figure 3 As shown, the monitoring method includes:

[0090] Step S1: After forming the hole groove in the dielectric layer, measuring the depth of the hole groove in real time;

[0091] Step S2: After forming the barrier layer and the dielectric layer, measuring the sum of the thicknesses of the barrier layer and the dielectric layer in real time;

[0092] Step S3: calculating the physical thickness of the barrier layer between the upper plate and the lower plate according to the depth of the hole and the sum of the thickness of the barrier layer and the dielectric layer;

[0093] Step S4: after forming the upper plate metal interconnection and the lower plate metal interconnection, measuring the capacitance value between the upper plate pad and the lower plate pad;

[0094] Step S5: Calculating the electrical thickness of the barrier layer between the upper electrode plate and the lower electrode plate according to the capacitance value.

[0095] The depth of the hole groove and the sum of the thickness of the barrier layer and the dielectric layer can be measured by a film thickness meter, for example, by using the method of optical critical dimension scatterometry measurements, that is, the thickness difference, that is, the thickness of the barrier layer between the upper plate and the lower plate, is calculated by the time difference between the light irradiating the bottom of the hole groove and the surface of the dielectric layer and the light received after reflection and the speed of light. The method for calculating the thickness is not limited to the above example.

[0096] Among them, calculating the thickness of the barrier layer between the upper electrode plate and the lower electrode plate by using the capacitance value is a conventional method, which will not be repeated here.

[0097] The monitoring method in the present application further includes feeding back the thickness information after obtaining the thickness of the barrier layer between the upper plate and the lower plate to monitor the floating source contact etching process.

[0098] In one example of the present application, after obtaining the thickness of the barrier layer between the upper electrode plate and the lower electrode plate, it is determined whether the thickness of the barrier layer between the upper electrode plate and the lower electrode plate is within the target thickness range. If the error exceeds the set threshold, it is fed back to the hole groove etching machine; for example, if the thickness is too large or too small and the degree of thickness being too large or too small.

[0099] Then, the hole groove etching machine adjusts the hole groove etching process according to the feedback information so that the thickness of the barrier layer between the upper electrode plate and the lower electrode plate meets the error requirement. For example, if the thickness is too large, the etching process can be adjusted on the hole groove etching machine to select an etching process with a longer etching time and a larger etching amount. If the thickness is too small, the etching process can be adjusted on the hole groove etching machine to select an etching process with a shorter etching time and a smaller etching amount, such as Figure 4 shown.

[0100] The test structure and monitoring method described in this application can accurately grasp the fluctuations of the process and provide real-time feedback to the online process, thereby realizing automatic correction of the process and achieving optimal stability.

[0101] Based on the test structure, OCD measurement and feedback system design can stabilize the process to the greatest extent. It can effectively resist various factors that are not conducive to process stability, such as fluctuations in the thickness of the front-layer dielectric, fluctuations in the CD of the front-layer photolithography, changes in the etching rate before, during and after the life of the station, changes in the gas environment of the etching chamber, etc., and finally output stable high-voltage device characteristics.

[0102] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0103] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0105] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0106] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0107] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0108] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0109] It should be noted that the above embodiments illustrate rather than limit the present application, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A test structure for a floating source contact etching process, characterized in that: The test structure includes: A semiconductor substrate configured as a lower plate, wherein the semiconductor substrate includes an active region and an inactive region; A barrier layer, located on the active area of ​​the semiconductor substrate; a dielectric layer, covering the semiconductor substrate and the barrier layer; A plurality of upper plates spaced apart from each other, the plurality of upper plates being located above the active area, the upper plates comprising holes and a conductive material filled in the holes, the holes penetrating the dielectric layer and extending to the barrier layer; the upper plates serving as floating source contacts; A contact hole, penetrating the dielectric layer and extending to the semiconductor substrate; An upper electrode plate metal interconnection is located above the plurality of upper electrode plates and is electrically connected to the plurality of upper electrode plates, and the plurality of upper electrode plates are connected in parallel and then electrically connected to the upper electrode plate pad; The lower plate metal interconnection is located above the contact hole and electrically connected to the contact hole, and electrically connects the semiconductor substrate to the lower plate pad.

2. The test structure according to claim 1, characterized in that: The projections of the multiple upper plates on the horizontal plane are in the shape of a long strip, the length of the upper plates extends along the first direction, the multiple upper plates are arranged in parallel at equal intervals along the second direction, and the first direction and the second direction are perpendicular to each other.

3. The test structure according to claim 2, characterized in that: The length of the upper plate is greater than 50um and the width ranges from 0.2um to 1um; or The critical dimension of the contact hole is 0.17um to 0.24um.

4. The test structure according to claim 2, characterized in that: The test structure also includes: A plurality of doped regions, located on the surface of the semiconductor substrate and not covered by the barrier layer, serve as lead-out regions of the semiconductor substrate.

5. The test structure according to claim 1, characterized in that: The upper electrode pad and the lower electrode pad are located on the dielectric layer on the non-active area of ​​the semiconductor substrate.

6. The test structure according to claim 1, characterized in that: The barrier layer includes a plasma oxide layer, a silicon nitride layer and a silicon oxynitride layer which are sequentially stacked on the surface of the semiconductor substrate.

7. The test structure according to claim 2, characterized in that: The size of the active area in the first direction is 50um-75um, and the size of the active area in the second direction is 50um-500um.

8. A monitoring method based on the test structure according to any one of claims 1 to 7, characterized in that: The monitoring method comprises: After forming the hole groove in the dielectric layer, measuring the depth of the hole groove in real time; After forming the barrier layer and the dielectric layer, measuring the sum of the thicknesses of the barrier layer and the dielectric layer in real time; Calculating the physical thickness of the barrier layer between the upper plate and the lower plate according to the depth of the hole groove and the sum of the thickness of the barrier layer and the dielectric layer; After forming the upper plate metal interconnection and the lower plate metal interconnection, measuring the capacitance value between the upper plate pad and the lower plate pad; The electrical thickness of the barrier layer between the upper electrode plate and the lower electrode plate is calculated using the capacitance value.

9. The monitoring method according to claim 8, characterized in that: The depth of the hole and the sum of the thickness of the barrier layer and the dielectric layer are measured by an optical critical dimension scattering measurement method.

10. The monitoring method according to any one of claims 8 to 9, characterized in that: The monitoring method further comprises: Monitoring the floating source contact etching process by the thickness of the barrier layer between the upper plate and the lower plate comprises: Determine whether the thickness of the barrier layer between the upper electrode plate and the lower electrode plate is within the target thickness range, and if the error exceeds a set threshold, feedback is given to the hole and groove etching machine; The hole and groove etching machine adjusts the hole and groove etching process according to the feedback information so that the thickness of the barrier layer between the upper electrode plate and the lower electrode plate is within the target thickness range.

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