A semiconductor device, a manufacturing method thereof, and a memory device

Abstract

This invention discloses a semiconductor device and its fabrication method. It provides a semiconductor substrate with a conductive structure. On the semiconductor substrate, a plug connected to the conductive structure is fabricated above it. An impregnation layer, which is an intermetallic compound, is formed on the surface of the semiconductor substrate with the plug. The intermetallic compound contains a metal wire element, an anti-electromigration metal element, and a bonding metal element. An upper metal layer containing the metal wire element is formed above the impregnation layer. The impregnation layer and the upper metal layer are patterned to obtain interconnects connecting the conductive structure. This invention enables the formation of a uniformly thick impregnation layer and upper metal layer, thereby improving reliability in areas such as electromigration and stress migration, and ensuring the quality of semiconductor products.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, and particularly relates to a method for fabricating a semiconductor device, as well as the semiconductor device and memory device. Background Technology

[0002] Depending on the type of semiconductor device and fabrication process, there are various metallization structures. In memory devices (such as DRAM), Al or Cu metallization structures are used as connections for power lines, requiring strict control of process windows at each stage. Generally, Al metallization structures consist of a wetting layer, an Al or aluminum alloy, and a capping layer. Considering the dielectric properties and adhesion of oxides, Ti films are typically used as the wetting layer in Al metallization structures. During subsequent Al grain growth, the uncontrollable reaction between the Ti and Al elements in the wetting layer produces TiAlx compounds, leading to high resistance and uneven thickness of the metallization structure. To address these issues, existing technologies reduce the grain growth temperature, which results in reliability degradation issues such as electromigration and stress migration. Summary of the Invention

[0003] To address the problems existing in the prior art, embodiments of the present invention provide a semiconductor device, a method for fabricating the same, and a memory device, to form a uniformly thick impregnation layer and an upper metal layer in the semiconductor device, thereby optimizing the reliability of the semiconductor device in terms of electromigration, stress migration, etc.

[0004] In a first aspect, embodiments of the present invention provide a method for fabricating a semiconductor device, comprising:

[0005] A semiconductor substrate is provided, on which a conductive structure is formed;

[0006] A plug connected to the conductive structure is prepared above the conductive structure;

[0007] An impregnation layer is formed on the surface of the semiconductor substrate on which the plug is formed. The impregnation layer is an intermetallic compound containing metal wire elements, anti-electromigration metal elements, and adhesive metal elements.

[0008] An upper metal layer containing the metal wire elements is formed above the impregnation layer;

[0009] The impregnation layer and the upper metal layer are patterned to obtain interconnects connecting the conductive structure.

[0010] Optionally, the metal wire element is aluminum or an aluminum alloy.

[0011] Optionally, the intermetallic compound is TiAlCu, TaAlCu, CrAlCu, or NiAlCu.

[0012] Optionally, the thickness of the wetting layer is less than 100 nm.

[0013] Optionally, forming an upper metal layer containing the metal wire element above the impregnation layer includes:

[0014] The upper metal layer is formed under deposition conditions of 350~500℃.

[0015] Optionally, forming an upper metal layer containing the metal wire element above the impregnation layer includes:

[0016] The upper metal layer is formed at room temperature;

[0017] The deposited upper metal layer is annealed at 500~600℃.

[0018] Optionally, before patterning the wetting layer and the upper metal layer, the method further includes:

[0019] A cover layer is formed on top of the upper metal layer.

[0020] Optionally, the covering layer specifically comprises:

[0021] TiN layer, or

[0022] A composite layer formed by TiN and Ti.

[0023] Optionally, a plug connected to the conductive structure is prepared above the conductive structure, comprising:

[0024] A contact hole is formed above the conductive structure;

[0025] The plug is formed within the contact hole.

[0026] Optionally, the plug is formed within the contact hole, comprising:

[0027] A barrier layer is deposited inside the contact hole using PVD, CVD, or ALD processes.

[0028] The plug is formed in the contact hole where the barrier layer has been deposited using PVD, CVD, ALD, or electroplating processes.

[0029] In a second aspect, embodiments of the present invention provide a semiconductor device, comprising:

[0030] Semiconductor substrate;

[0031] A conductive structure is located above the semiconductor substrate;

[0032] A plug is located above the conductive structure and is connected to the conductive structure;

[0033] An interconnect comprising a patterned impregnation layer and a patterned upper metal layer, the impregnation layer being located on the surface of a semiconductor substrate on which the plug is formed, the upper metal layer being located above the impregnation layer, the impregnation layer being an intermetallic compound containing a metal wire element, an anti-electromigration metal element, and an adhesive metal element.

[0034] Optionally, the metal wire element is Al or an aluminum alloy.

[0035] Optionally, the intermetallic compound is TiAlCu, TaAlCu, CrAlCu, or NiAlCu.

[0036] Thirdly, embodiments of the present invention provide a storage device, including any of the semiconductor devices described in the second aspect.

[0037] The semiconductor device, its fabrication method, and memory device provided in this invention include a semiconductor substrate with a conductive structure; a plug connected to the conductive structure is fabricated on the semiconductor substrate; a wetting layer is formed on the surface of the semiconductor substrate with the plug, the wetting layer being an intermetallic compound containing a metal wire element, an anti-electromigration metal element, and a bonding metal element; an upper metal layer containing the metal wire element is formed above the wetting layer; and the wetting layer and the upper metal layer are patterned to obtain interconnects connecting the conductive structure. Because the wetting layer is formed using an intermetallic compound containing a metal wire element, an anti-electromigration metal element, and a bonding metal element, the reaction between the anti-electromigration metal element in the wetting layer and the metal wire element in the upper metal layer is avoided during the formation of the upper metal layer. This suppresses the formation of excessive intermetallic compounds at the contact point between the wetting layer and the upper metal layer, ensuring sufficient grain growth during the formation of the upper metal layer to form a uniformly thick wetting layer and upper metal layer. This optimizes reliability indicators such as electromigration and stress migration, ensuring the quality of the semiconductor product. Attached Figure Description

[0038] Figures 1-9 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0039] To address the problem in existing technologies where the uncontrollable reaction between Ti elements in the wetting layer and Al elements during grain growth produces TiAlx compounds, leading to high resistance and uneven thickness of the metallized structure, this invention provides a semiconductor device, its fabrication method, and a memory device.

[0040] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0041] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0043] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0044] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Example 1

[0046] This embodiment provides a method for fabricating a semiconductor device, which will be described below in conjunction with the appendix. Figures 1-9 The embodiments of the present invention will be described in detail below.

[0047] First, a semiconductor substrate is provided. (Reference) Figure 1As shown, a conductive structure 1 is formed on a semiconductor substrate. Specifically, the conductive structure 1 can be a lower metal line or a gate, etc. The lower metal line is formed by depositing gold materials such as W, Al, or Cu.

[0048] Next, a plug 5 connected to the conductive structure 1 is prepared on top of the conductive structure 1.

[0049] Specifically, to prepare the plug 5 connected to the conductive structure 1, a contact hole 3 needs to be formed on the top of the conductive structure 1 first, and then the plug 5 needs to be formed inside the contact hole 3.

[0050] Specifically, regarding the formation of contact holes 3 above the conductive structure 1, an interlayer dielectric 2 is first deposited above the conductive structure 1 using PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (atomic layer deposition), or SOD (spin-on insulating dielectric) processes. See [link to relevant documentation] for details. Figure 2 As shown. The interlayer dielectric 2 can be one of SiH4, TEOS, or a low dielectric constant material. Etching is then performed on the deposited interlayer dielectric 2 to form contact holes 3, exposing the conductive structure 1 within the contact holes 3. See [reference needed] for details. Figure 3 As shown.

[0051] Specifically, regarding the formation of the plug 5 within the contact hole 3, a barrier layer 4 is first formed within the contact hole 3 using PVD (Chemical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Alternating Current) processes. See [link / reference] for details. Figure 4 As shown. The barrier layer 4 can be one of the deposited materials Ti, TiN, W, WN, Ta, and TaN. From... Figure 4 As can be seen, by forming the barrier layer 4, both the surface of the interlayer dielectric 2 and the exposed conductive structure 1 are covered by the barrier layer 4, serving as a transition layer. Then, using PVD, CVD, ALD, or electroplating processes, plug material is deposited within the contact holes 3 where the barrier layer 4 has been formed. (See the attached document for details.) Figure 5 As shown. Then, the exposed plug material outside the contact hole 3 is removed by etching or CMP processes, forming the plug 5 and achieving separation between the plugs 5. See the attached document for details. Figure 6 As shown.

[0052] Next, a wetting layer 6 is formed on the surface of the semiconductor substrate on which the plug 5 is formed, as detailed in the following reference. Figure 7 As shown.

[0053] The wetting layer 6 is formed by depositing an intermetallic compound containing metal wire elements. Specifically, the intermetallic compound contains metal wire elements, anti-electromigration metal elements, and binding metal elements. The formed wetting layer 6 covers the exposed plug 5 and the barrier layer 4.

[0054] In practical implementation, PVD process can be used to deposit intermetallic compounds to form the wetting layer 6, wherein the thickness of the wetting layer 6 is less than 100 nm.

[0055] Among them, the metal wire element in the intermetallic compound is related to the metal material that subsequently forms the upper metal layer 7. The anti-electromigration metal element can be Cu, or other metal elements with the same or similar electron mobility as Cu. The metal element that plays a bonding role can be any one of Ti, Ta, and Ni.

[0056] Next, an upper metal layer 7 containing metal wire elements is formed above the impregnation layer 6, as detailed in the following reference. Figure 8 As shown.

[0057] The metal wire elements contained in the upper metal layer 7 are the same as those contained in the wetting layer 6. For example, if the metal wire elements contained in the upper metal layer 7 are Al or aluminum alloy, then the upper metal layer 7 specifically contains Al, for example, Al or aluminum alloy. This suppresses the reaction between the Al element in the upper metal layer 7 and the metal elements (Ti, Ta, or Ni) that act as binders in the wetting layer 6, thus allowing for sufficient grain growth.

[0058] To ensure high reliability, a high-temperature deposition process can be used for grain growth to form the upper metal layer 7. Specifically, the high-temperature deposition temperature is 350~500℃, allowing for sufficient grain growth of Al or aluminum alloy. Alternatively, Al or aluminum alloy can first be grown at room temperature to form the upper metal layer 7, and then annealed at 500~600℃, achieving the same level of sufficient grain growth.

[0059] If Al or aluminum alloy is used to form the upper metal layer 7 above the wetting layer 6, the intermetallic compound forming the wetting layer 6 can be any one of TiAlCu, TaAlCu, CrAlCu and NiAlCu.

[0060] Next, refer to Figure 8 As shown, a capping layer 8 is formed above the upper metal layer 7. The capping layer 8 is specifically a TiN layer, or a composite layer formed of TiN and Ti.

[0061] Finally, after the cover layer 8 is formed, the impregnation layer 6 and the upper metal layer 7 are patterned to obtain the interconnects connecting the conductive structure 1.

[0062] Example 2

[0063] Based on the same inventive concept, this embodiment of the invention also provides a semiconductor device, including: a semiconductor substrate; a conductive structure 1 located above the semiconductor substrate; a plug 5 located above the conductive structure 1 and connected to the conductive structure 1; and an interconnect comprising a patterned impregnation layer 6 and a patterned upper metal layer 7, wherein the impregnation layer 6 is located on the surface of the semiconductor substrate on which the plug 5 is formed, and the upper metal layer 7 is located above the impregnation layer 6, the impregnation layer 6 being an intermetallic compound, and the intermetallic compound containing a metal wire element, an anti-electromigration metal element, and an adhesive metal element.

[0064] Specifically, the metal wire element is Al or an aluminum alloy. The intermetallic compound is TiAlCu, TaAlCu, CrAlCu, or NiAlCu.

[0065] The structure of semiconductor devices has been described in detail in the semiconductor device fabrication method. For specific implementation details, please refer to the examples of semiconductor device fabrication methods described above. For the sake of brevity, it will not be repeated here.

[0066] Example 3

[0067] Based on the same inventive concept, embodiments of the present invention provide a storage device, including the semiconductor device described above. Specific implementation details can be found in the embodiments of the semiconductor device fabrication method described above, and will not be repeated here for the sake of brevity.

[0068] The semiconductor device, its fabrication method, and memory device provided in this invention include a semiconductor substrate with a conductive structure; a plug connected to the conductive structure is fabricated above the conductive structure on the semiconductor substrate; a wetting layer is formed on the surface of the semiconductor substrate with the plug, the wetting layer being an intermetallic compound containing a metal wire element, an anti-electromigration metal element, and a bonding metal element; an upper metal layer containing the metal wire element is formed above the wetting layer; and the wetting layer and the upper metal layer are patterned to obtain interconnects connecting the conductive structure. Because an intermetallic compound containing a metal wire element, an anti-electromigration metal element, and a bonding metal element is used to form the wetting layer, the reaction between the anti-electromigration metal element in the wetting layer and the metal wire element in the upper metal layer is avoided during the formation of the upper metal layer. This suppresses the formation of excessive intermetallic compound at the contact point between the wetting layer and the upper metal layer, ensuring sufficient grain formation during the formation of the upper metal layer, resulting in a uniformly thick wetting layer and upper metal layer. This improves reliability in areas such as electromigration and stress migration, ensuring the quality of the semiconductor product.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, on which a conductive structure is formed; A plug connected to the conductive structure is prepared above the conductive structure; A wetting layer is formed on the surface of the semiconductor substrate on which the plug is formed. The wetting layer is an intermetallic compound containing a metal wire element, an anti-electromigration metal element, and a binding metal element. The metal wire element in the intermetallic compound is related to the metal material of the subsequent upper metal layer. The anti-electromigration metal element is Cu, or other metal elements with the same or similar electron mobility as Cu. The binding metal element is any one of Ti, Ta, and Ni. The metal wire element is aluminum or an aluminum alloy. The intermetallic compound is TiAlCu, TaAlCu, CrAlCu, or NiAlCu. An upper metal layer containing the metal wire elements is formed above the impregnation layer; The impregnation layer and the upper metal layer are patterned to obtain interconnects connecting the conductive structure.

2. The method as described in claim 1, characterized in that, The thickness of the wetting layer is less than 100 nm.

3. The method as described in claim 1, characterized in that, The formation of an upper metal layer containing the metal wire elements above the impregnation layer includes: The upper metal layer is formed under deposition conditions of 350~500℃.

4. The method as described in claim 1, characterized in that, The formation of an upper metal layer containing the metal wire elements above the impregnation layer includes: The upper metal layer is formed at room temperature; The deposited upper metal layer is annealed at 500~600℃.

5. The method as described in claim 1, characterized in that, Before patterning the wetting layer and the upper metal layer, the method further includes: A cover layer is formed on top of the upper metal layer.

6. The method as described in claim 5, characterized in that, The covering layer is specifically: TiN layer, or A composite layer formed by TiN and Ti.

7. The method as described in claim 1, characterized in that, A plug connected to the conductive structure is prepared above the conductive structure, comprising: A contact hole is formed above the conductive structure; The plug is formed within the contact hole.

8. The method as described in claim 7, characterized in that, Forming the plug within the contact hole includes: A barrier layer is deposited inside the contact hole using PVD, CVD, or ALD processes. The plug is formed in the contact hole where the barrier layer has been deposited using PVD, CVD, ALD, or electroplating processes.

9. A semiconductor device, characterized in that, include: Semiconductor substrate; A conductive structure is located above the semiconductor substrate; A plug is located above the conductive structure and is connected to the conductive structure; An interconnect comprising a patterned impregnation layer and a patterned upper metal layer, the impregnation layer being located on the surface of a semiconductor substrate on which the plug is formed, the upper metal layer being located above the impregnation layer, the impregnation layer being an intermetallic compound containing a wire element, an anti-electromigration metal element, and a bonding metal element, wherein the wire element in the intermetallic compound is related to the metal material subsequently forming the upper metal layer; the anti-electromigration metal element is Cu, or other metal elements with the same or similar electron mobility as Cu; the bonding metal element is any one of Ti, Ta, and Ni; the wire element is aluminum or an aluminum alloy; and the intermetallic compound is TiAlCu, TaAlCu, CrAlCu, or NiAlCu.

10. The semiconductor device of claim 9, wherein the metal wire element is Al or an aluminum alloy.

11. The semiconductor device as claimed in claim 10, characterized in that, The intermetallic compound is TiAlCu, TaAlCu, CrAlCu, or NiAlCu.

12. A storage device, characterized in that, Includes the semiconductor device described in any one of claims 9-11.

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