Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: forming a first well region in the first region after forming a gate layer; forming a second well region in the second region after forming the gate layer, the second well region having a different conductivity type from the first well region; doping a first doping ion in the first well region to form a doped region, the doped region having the same conductivity type as the first well region, and a distance between the doped region and a gate layer sidewall adjacent to the doped region in a direction parallel to a surface of the substrate being less than or equal to a preset size; and a contact interface formed by diffusion of the dopant in the first well region and the dopant in the second well region, improving electrical properties of the device such as threshold voltage, breakdown voltage, etc. The doped region suppresses channel effect and reduces the impact on a channel formed between the source and the second well region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] LDMOS (Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor), a type of high-voltage power device, exhibits good compatibility with CMOS device processes due to the lateral current flow across its surface. Furthermore, compared to traditional power devices, LDMOS devices are widely used due to their high breakdown voltage and low on-resistance.

[0003] The trade-off between breakdown voltage and on-resistance is prominent in conventional LDMOS devices. Researchers have proposed various solutions, including surface-varying doping techniques, light doping techniques, and field plates. In addition to these two performance characteristics, LDMOS devices also need to meet other performance requirements, such as low leakage current and stable threshold voltage.

[0004] The existing LDMOS devices require further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure that can improve the performance of the semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including an adjacent first region and a second region; a gate layer located on the substrate, a portion of the gate layer being located on the first region and another portion of the gate layer being located on the second region; a first well region located within the first region; a second well region located within the second region, the conductivity type of the second well region being different from that of the first well region; a doped region located within the first well region, the conductivity type of the doped region being the same as that of the first well region, and the distance between the doped region and the gate layer sidewall adjacent to the doped region in a direction parallel to the substrate surface being less than or equal to a preset size; a drain and a source located on both sides of the gate layer, the drain being located within the second well region and the source being located within the doped region, the conductivity type of the source and drain being the same as that of the second well region.

[0007] Optionally, the preset size range is from 0 nm to 20 nm.

[0008] Optionally, the first well region includes a third region and a fourth region adjacent to the third region, the third region being located at the bottom of the gate layer, and the depth of the third region being less than or equal to the depth of the fourth region in the direction perpendicular to the surface of the substrate; the second well region includes a fifth region and a sixth region adjacent to the fifth region, the fifth region being located at the bottom of the gate layer, and the depth of the fifth region being less than or equal to the depth of the sixth region in the direction perpendicular to the surface of the substrate.

[0009] Optionally, it may also include: an isolation structure located within the second well region, the isolation structure being situated between the drain and the gate layer and partially covered by the gate layer.

[0010] Optionally, the material of the isolation structure includes silicon oxide.

[0011] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including an adjacent first region and a second region; forming a gate layer on the substrate, a portion of the gate layer being located on the first region and another portion of the gate layer being located on the second region; after forming the gate layer, forming a first well region in the first region; after forming the gate layer, forming a second well region in the second region, the conductivity type of the second well region being different from that of the first well region; doping the first well region with a first dopant ion to form a doped region, the conductivity type of the doped region being the same as that of the first well region, and the distance between the doped region and the gate layer sidewall adjacent to the doped region in a direction parallel to the surface of the substrate being less than or equal to a preset size; forming a drain and a source on both sides of the gate layer, the drain being located in the second well region and the source being located in the doped region, the conductivity type of the source and drain being the same as that of the second well region.

[0012] Optionally, the first doped ion includes a first ion, which is a P-type ion or an N-type ion.

[0013] Optionally, the process parameters of the first doping ion process include: the first ion includes boron or boron fluoride ions, the implantation angle is 0 to 15 degrees from the substrate normal direction, and the ion concentration is 1E13 atom / cm³. 3 Up to 1E14 atom / cm 3 The implantation energy range for boron is 15 keV to 40 keV, and the implantation energy range for boron fluoride is 30 keV to 80 keV.

[0014] Optionally, the first doped ion may further include a second ion, the second ion having an opposite conductivity type to the first ion.

[0015] Optionally, the process parameters of the first doping ion process further include: the second ion includes phosphorus ions, the implantation angle is 0 to 10 degrees from the substrate normal direction, and the ion concentration is 5E12 atom / cm². 3 Up to 5E13 atom / cm 3 The injection energy range is from 15keV to 50keV.

[0016] Optionally, the method for forming the doped region includes: forming a first mask layer on the surface of the second region and the surface of the gate layer; forming the doped region using the first mask layer as a mask; and removing the first mask layer after forming the doped region.

[0017] Optionally, the material of the first mask layer includes photoresist.

[0018] Optionally, the method for forming the first well region includes: forming a second mask layer covering the surface of the second region and a portion of the gate layer; using the second mask layer as a mask, doping the first region with second doped ions to form the first well region; and removing the second mask layer after forming the first well region.

[0019] Optionally, the material of the second mask layer includes photoresist.

[0020] Optionally, the method for forming the second well region includes: forming a third mask layer covering the surface of the first region and a portion of the gate layer; using the third mask layer as a mask, doping the second region with third dopant ions to form the second well region; and removing the third mask layer after forming the second well region.

[0021] Optionally, the material of the third mask layer includes photoresist.

[0022] Optionally, the method for forming the gate layer includes: forming a gate material layer on the surface of the substrate, patterning the gate material layer, and forming the gate layer.

[0023] Optionally, before forming the source and drain, the method further includes forming a sidewall on the sidewall surface of the gate layer.

[0024] Optionally, the sidewall material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0025] Optionally, before forming the source and the drain, the method further includes: forming an isolation structure within the second well region, the isolation structure being located between the drain and the gate layer and being partially covered by the gate layer.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor structure formation method of the present invention, after forming the gate layer, a first well region is formed in the first region; after forming the gate layer, a second well region is formed in the second region, wherein the conductivity type of the second well region is different from that of the first well region; a first dopant ion is doped in the first well region to form a doped region, wherein the conductivity type of the doped region is the same as that of the first well region; the contact interface formed by the diffusion of the dopant in the first well region and the dopant in the second well region to each other is different from the contact interface formed by directly injecting dopant ions of different conductivity types on both sides of the interface position. This avoids the problem of channel length, channel dopant concentration, etc., being different from the target values ​​due to misalignment of doping positions, thereby improving the electrical performance of the device, such as threshold voltage and breakdown voltage. The source electrode is located within the doped region. The doped region increases the concentration of the source electrode and the barrier height, effectively suppressing the barrier reduction effect, improving the threshold voltage of the device, and improving the breakdown voltage and other performance characteristics of the device. Furthermore, the distance between the doped region and the gate layer sidewall adjacent to the doped region in the direction parallel to the substrate surface is less than or equal to a preset size, reducing the impact of the doped region on the channel formed between the source electrode and the second well region, and ultimately effectively improving the electrical performance of the device, such as the threshold voltage and breakdown voltage.

[0028] Furthermore, the first doped ion includes a first ion, which is a P-type ion or an N-type ion, and the first doped ion also includes a second ion, the second ion having a conductivity type opposite to that of the first ion. Due to the compensating effect of the second ion and the first ion, the lateral diffusion of surface doped ions into the channel can be reduced, thereby reducing the short-channel effect of the device, improving the breakdown voltage of the device, and enhancing the electrical performance of the device. Attached Figure Description

[0029] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process;

[0030] Figures 4 to 9 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, the performance of semiconductor structures formed using existing lateral double-diffused metal-oxide-semiconductor field-effect transistors urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0032] Figures 1 to 3 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0033] Please refer to Figure 1A substrate 100 is provided, the substrate 100 including a base 101 and a field oxygen region 102 located within the substrate 100; a first photoresist layer 103 is formed on a portion of the surface of the substrate 100, the first photoresist layer 103 also covering the surface of the field oxygen region 102; using the first photoresist layer 103 as a mask, an N-type first doped ion body region 104 is implanted into the substrate 100; after forming the body region 104, the first photoresist layer 103 is removed.

[0034] Please refer to Figure 2 A second photoresist layer 105 is formed by covering the body region 104; using the second photoresist layer 105 as a mask, P-type second doped ions are implanted into the substrate 100 to form a drift region 106, the drift region 106 being adjacent to the body region 104 and having a field oxygen region 102; after forming the drift region 106, the second photoresist layer 105 is removed.

[0035] Please refer to Figure 3 A gate layer 107 is formed on the surface of the substrate 100, the gate layer 107 covering a portion of the body region 104, a portion of the drift region 106, and a portion of the field oxide region 102; a source electrode 108 and a drain electrode 109 are formed in the substrate 100 on both sides of the gate layer 107, the source electrode 108 is located in the body region 104, and the drain electrode 109 is located in the drift region 106 and adjacent to the field oxide region 102.

[0036] The above method is used in NLDMOS devices to form a channel at the bottom of the gate layer 107, between the source 108 and the drift region 106. The annealing step in the formation process of the source 108 and drain 109 causes dopant ions to diffuse into the channel due to thermal diffusion, resulting in changes in the channel dopant ion concentration. This can even cause electric field lines to cross from the drain 109 to the source 108, lowering the barrier height at the source 108 and causing leakage problems. Furthermore, in the above method, during the formation of the body region 104 and the drift region 106, two photolithography processes are required. Due to the influence of the photolithography process, such as potential overlay errors between the two processes, N-type dopant ions in the body region 104 may be implanted into the drift region 106, or P-type dopant ions in the drift region 106 may be implanted into the body region 104. This affects the doping concentration at the interface between the body region 104 and the drift region 106, and also causes uneven channel length in the device. Both of these situations make the characteristics of LDMOS devices difficult to predict, resulting in poor controllability of device performance. This may lead to problems such as a decrease in breakdown voltage, device leakage, or an increase in on-resistance.

[0037] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure in which, after forming a gate layer, a first well region is formed in the first region; after forming the gate layer, a second well region is formed in the second region, wherein the conductivity type of the second well region is different from that of the first well region; a first dopant ion is doped in the first well region to form a doped region, wherein the conductivity type of the doped region is the same as that of the second well region; the contact interface formed by the diffusion of dopant in the first well region and dopant in the second well region to each other is different from the contact interface formed by directly injecting dopant ions of different conductivity types on both sides of the interface position. This avoids the problem of channel length, channel dopant concentration, etc., being different from the target values ​​due to misalignment of doping positions, thereby improving the electrical performance of the device, such as threshold voltage and breakdown voltage. The source electrode is located within the doped region. The doped region increases the concentration of the source electrode and the barrier height, effectively suppressing the barrier reduction effect, improving the threshold voltage of the device, and improving the breakdown voltage and other performance characteristics of the device. Furthermore, the distance between the doped region and the gate layer sidewall adjacent to the doped region in the direction parallel to the substrate surface is less than or equal to a preset size, reducing the impact of the doped region on the channel formed between the source electrode and the second well region, and ultimately effectively improving the electrical performance of the device, such as the threshold voltage and breakdown voltage.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 9 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention.

[0040] Please refer to Figure 4 A substrate 200 is provided, the substrate 200 including adjacent first region I and second region II.

[0041] The substrate 200 further includes: a base 201, and an isolation structure 202 located within the second region II. The isolation structure 202 serves as the field oxide region of the LDMOS device, used to improve the breakdown voltage performance of the LDMOS device.

[0042] In this embodiment, the substrate 201 is made of silicon. In other embodiments, the substrate 201 may also be a silicon-on-insulator (SOI) structure or a germanium-on-insulator structure.

[0043] In this embodiment, the method for forming the isolation structure 202 includes: etching trenches within the substrate 200; and forming an isolation layer in the trenches. The formation process of the isolation layer includes high-density plasma chemical vapor deposition; the material of the isolation layer includes silicon oxide.

[0044] Subsequently, a first well region is formed in the first region I; and a second well region is formed in the second region II.

[0045] Please refer to Figure 5 A gate layer 203 is formed on the substrate 200, with a portion of the gate layer 203 located on the first region I and another portion of the gate layer 203 located on the second region II.

[0046] The gate layer 203 is made of silicon or a metal. In this embodiment, the gate layer 203 is made of polycrystalline silicon. In other embodiments, the gate layer is made of silicon nitride, silicon carbide, amorphous silicon, polycrystalline silicon, or monocrystalline silicon, and may also be made of a metal.

[0047] The method for forming the gate layer 203 includes: forming a gate material layer (not shown in the figure) on the substrate 200; and patterning the gate material layer to form the gate layer 203.

[0048] In this embodiment, the gate layer 203 is also located on the isolation structure 202.

[0049] Please refer to Figure 6 After the gate layer 203 is formed, a first well region 205 is formed in the first region I.

[0050] The method for forming the first well region 205 includes: forming a second mask layer 204 covering the second region II and part of the surface of the gate layer 203; using the second mask layer 204 as a mask, doping the first region I with second doped ions to form the first well region 205; and removing the second mask layer 204 after forming the first well region 205.

[0051] The material of the second mask layer 204 includes photoresist.

[0052] The second doped ion includes either a p-type ion or a n-type ion. In this embodiment, the conductivity type of the first well region is p-type, and the second doped ion is a boron ion with a doping concentration of 1E18 atom / cm³. 3 Up to 1E19 atom / cm 3 Energy range: 150keV-300keV.

[0053] The first well region 205 includes a third region A and a fourth region B adjacent to the third region A. The fourth region B is located at the bottom of the gate layer 203, and in the direction perpendicular to the surface of the substrate 200, the depth of the fourth region B is less than or equal to the depth of the third region A. The fourth region B is formed by the diffusion of the second dopant ions towards the bottom of the gate layer 203.

[0054] Please refer to Figure 7 After the gate layer 203 is formed, a second well region 207 is formed in the second region II. The conductivity type of the second well region 207 is different from that of the first well region 205.

[0055] The method for forming the second well region 207 includes: forming a third mask layer 206 covering the first region I and a portion of the surface of the gate layer 203; using the third mask layer 206 as a mask, doping the second region II with third doped ions to form the second well region 207; and removing the third mask layer 206 after forming the second well region 207.

[0056] The material of the third mask layer 206 includes photoresist.

[0057] The third dopant ion includes P-type ions or N-type ions. The second well region 207 serves as the drift region of the LDMOS device, possessing higher resistance and the ability to withstand higher voltages; therefore, the second well region 207 employs a lower concentration of ion doping. In this embodiment, the conductivity type of the second well region 207 is N-type, and the third dopant ion is phosphorus ion, with a doping concentration of 1E18 to 3E19 ions per cubic centimeter and an energy range of 200keV-500keV.

[0058] The second well region 207 includes a fifth region C and a sixth region D adjacent to the fifth region C. The fifth region C is located at the bottom of the gate layer 203, and in the direction perpendicular to the surface of the substrate 200, the depth of the fifth region C is less than or equal to the depth of the sixth region D. The fifth region C is formed by the diffusion of the third dopant ions towards the bottom of the gate layer 203.

[0059] In this embodiment, the first well region 205 is formed first, followed by the second well region 207. In other embodiments, the second well region 207 is formed first, followed by the first well region 205.

[0060] The dopant ions in the first well region 205 and the second well region 207 have different conductivity types, and a PN junction contact interface will be formed between them. The first well region 205 and the second well region 207 are formed after the gate layer 203 is formed. After the second dopant ions and the third dopant ions are implanted, the contact interface is indirectly formed through the diffusion of the dopant due to the concentration diffusion towards the bottom of the gate layer 203, rather than being determined by the positions of the two patterned layers. This avoids the problem of misalignment of the dopant positions, such as partial overlap of the positions of the two patterned layers, or inconsistency between the relative position with the gate layer and the target position. This prevents the channel length, channel dopant concentration, etc. of the subsequently formed device from differing from the target values, thereby improving the threshold voltage, breakdown voltage, and other performance characteristics of the formed device.

[0061] Please refer to Figure 8 A first doped ion is doped in the first well region 205 to form a doped region 209. The conductivity type of the doped region 209 is the same as that of the first well region 205, and the distance X between the doped region 209 and the sidewall of the gate layer 203 adjacent to the doped region 209 in the direction parallel to the surface of the substrate 200 is less than or equal to a preset size.

[0062] The method for forming the doped region 209 includes: forming a first mask layer 208 on the surface of the second region II and a portion of the surface of the gate layer 203; forming the doped region 209 using the first mask layer 208 as a mask; and removing the first mask layer 208 after forming the doped region 209.

[0063] The material of the first mask layer 208 includes photoresist.

[0064] The preset size ranges from 0 nm to 20 nm.

[0065] In this embodiment, the first mask layer 208 is also located on a portion of the surface of the first region I, and the preset size is 10 nm. The significance of selecting this preset size range is twofold: firstly, the preset size needs to be greater than or equal to 0 nm, i.e., to prevent the doped region 209 from penetrating below the gate layer 203, thus avoiding any impact on the channel of the formed device; secondly, the preset size needs to be less than or equal to 20 nm. This is because the subsequent heat treatment process will increase the diffusion of ions within the doped region 209. Ions diffused from the doped region 209 to below the gate layer 203 will increase the threshold voltage of the device. If the doped region 209 is too far from the gate layer 203, the ions within it will not diffuse below the gate layer 203 during subsequent heat treatment, thus failing to increase the device threshold voltage.

[0066] The first doping ion includes a first ion, which is a p-type ion or an n-type ion. In this embodiment, the first ion is a p-type ion. The process parameters for the first doping ion process include: the first ion includes boron or boron fluoride ions, the implantation angle is 0 to 15 degrees from the substrate normal direction, and the ion concentration is 1E13 atom / cm³. 3 Up to 1E14atom / cm 3 The implantation energy range for boron is 25 keV to 50 keV, and the implantation energy range for boron fluoride is 30 keV to 80 keV.

[0067] Subsequently, a source electrode is formed within the doped region 209. The doped region 209 increases the source electrode concentration and barrier height, effectively suppressing the barrier reduction effect, improving the device's threshold voltage, and simultaneously improving the device's breakdown voltage and other performance characteristics. Furthermore, the distance X between the sidewalls of the gate layer 203 adjacent to the doped region 209 and the sidewalls in the direction parallel to the surface of the substrate 200 is less than or equal to a preset size, reducing the impact of the doped region 209 on the channel formed between the source electrode and the first well region 205, ultimately effectively improving the device's threshold voltage, breakdown voltage, and other electrical performance characteristics.

[0068] In this embodiment, the first doped ion further includes a second ion, the second ion having a conductivity type opposite to that of the first ion. Due to the compensating effect of the second ion and the first ion, the lateral diffusion of surface doped ions into the channel can be reduced, thereby reducing the short-channel effect of the device, improving the breakdown voltage of the device, and enhancing the electrical performance of the device.

[0069] In this embodiment, the first ion is a P-type ion and the second ion is an N-type ion; the process parameters of the first doping ion process also include: the second ion includes phosphorus ions, the implantation angle is 0 degrees to 10 degrees with the substrate normal direction, the ion concentration is 5E12 atom / cm3 to 5E13 atom / cm3, and the implantation energy range is 15keV to 50keV.

[0070] Please refer to Figure 9 A drain 210 and a source 211 are formed on both sides of the gate layer 203, respectively. The drain 211 is located in the second well region 207, and the source 210 is located in the doped region 209. The conductivity type of the source 210 and the drain 211 is the same as that of the second well region 207.

[0071] This embodiment further includes forming a sidewall 212 on the sidewall surface of the gate layer 203. The material of the sidewall 212 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0072] The doped ions in the source 210 and drain 211 are N-type or P-type ions. In this embodiment, the conductivity type of the source 210 and drain 211 is N-type, and the doped ions are phosphorus ions.

[0073] In this embodiment, the method for forming the source 210 and the drain 211 includes: using the sidewall 212 as a mask, implanting N-type or P-type ions into the substrate 200 through a self-aligned process, forming the source 210 in the first well region 205, and forming the drain 211 in the second well region 207.

[0074] The isolation structure 202 is located between the drain 211 and the gate layer 203, and is partially covered by the gate layer 203.

[0075] Accordingly, the present invention also provides a semiconductor structure formed by the above-described forming method. Please refer to the following: Figure 9 The system includes: a substrate 200, which includes adjacent first region I and second region II; a gate layer 203 located on the substrate 200, a portion of the gate layer 203 being located on the first region I and another portion of the gate layer 203 being located on the second region II; a first well region 205 located within the first region I; a second well region 207 located within the second region II, the conductivity type of the second well region 207 being different from that of the first well region 205; and a doped region 209 located within the first well region 205. The conductivity type of the doped region 209 is the same as that of the first well region 205, and the distance X between the doped region 209 and the gate layer sidewall adjacent to the doped region in the direction parallel to the surface of the substrate 200 is less than or equal to a preset size; the drain 211 and the source 210 are located on both sides of the gate layer 203, the drain 211 is located in the second well region 207, the source 210 is located in the doped region 209, and the conductivity type of the source 210 and the drain 211 is the same as that of the second well region.

[0076] The preset size range is 0 nm to 20 nm. The doped region 209 increases the source concentration and barrier height, effectively suppressing the barrier reduction effect, improving the threshold voltage of the device, and improving the breakdown voltage and other performance characteristics of the device. Furthermore, the distance X between the sidewalls of the gate layer 203 adjacent to the doped region 209 in the direction parallel to the surface of the substrate 200 is less than or equal to the preset size, reducing the impact of the doped region 209 on the channel formed between the source and the first well region 205, and ultimately effectively improving the electrical performance of the device, such as the threshold voltage and breakdown voltage.

[0077] The first well region 205 includes a third region B and a fourth region A adjacent to the third region B. The third region B is located at the bottom of the gate layer 203, and in the direction perpendicular to the surface of the substrate 200, the depth of the third region B is less than or equal to the depth of the fourth region A. The second well region 207 includes a fifth region C and a sixth region D adjacent to the fifth region C. The fifth region C is located at the bottom of the gate layer 203, and in the direction perpendicular to the surface of the substrate 200, the depth of the fifth region C is less than or equal to the depth of the sixth region D.

[0078] The semiconductor structure further includes an isolation structure 202 located within the second well region 207, the isolation structure 202 being located between the drain 211 and the gate layer 203, and being partially covered by the gate layer 203.

[0079] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising adjacent first and second regions; A gate layer located on the substrate, wherein a portion of the gate layer is located on the first region and another portion of the gate layer is located on the second region; A first well region is located within the first region, the first well region includes a third region and a fourth region adjacent to the third region, the third region is located at the bottom of the gate layer, and in the direction perpendicular to the surface of the substrate, the depth of the third region is less than or equal to the depth of the fourth region; The second well region is located within the second region. The conductivity type of the second well region is different from that of the first well region. The second well region includes a fifth region and a sixth region adjacent to the fifth region. The fifth region is located at the bottom of the gate layer, and in the direction perpendicular to the surface of the substrate, the depth of the fifth region is less than or equal to the depth of the sixth region. The doped region is located within the first well region and outside the bottom of the gate layer. The conductivity type of the doped region is the same as that of the first well region, and the distance between the doped region and the gate layer sidewall adjacent to the doped region in a direction parallel to the substrate surface is less than or equal to a preset size. The drain and source are located on both sides of the gate layer, with the drain located in the second well region and the source located in the doped region. The conductivity type of the source and drain is the same as that of the second well region.

2. The semiconductor structure as described in claim 1, characterized in that, The preset size range is 0 nm to 20 nm.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation structure located within the second well region, the isolation structure being situated between the drain and the gate layer, and partially covered by the gate layer.

4. The semiconductor structure as described in claim 3, characterized in that, The material of the isolation structure includes silicon dioxide.

5. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an adjacent first region and a second region; A gate layer is formed on the substrate, with a portion of the gate layer located on the first region and another portion of the gate layer located on the second region; After the gate layer is formed, a first well region is formed in the first region. The first well region includes a third region and a fourth region adjacent to the third region. The third region is located at the bottom of the gate layer, and in the direction perpendicular to the surface of the substrate, the depth of the third region is less than or equal to the depth of the fourth region. After the gate layer is formed, a second well region is formed in the second region. The conductivity type of the second well region is different from that of the first well region. The second well region includes a fifth region and a sixth region adjacent to the fifth region. The fifth region is located at the bottom of the gate layer, and in the direction perpendicular to the surface of the substrate, the depth of the fifth region is less than or equal to the depth of the sixth region. Within the first well region, and outside the bottom of the gate layer, a first doped region is formed by doping with first doped ions. The conductivity type of the doped region is the same as that of the first well region, and the distance between the doped region and the gate layer sidewall adjacent to the doped region in a direction parallel to the substrate surface is less than or equal to a preset size. A drain and a source are formed on both sides of the gate layer, respectively. The drain is located in the second well region, and the source is located in the doped region. The conductivity type of the source and drain is the same as that of the second well region.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The first doped ion includes a first ion, which is a P-type ion.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process parameters for the first doping ion process include: the first ion comprises boron or boron fluoride ions; the implantation angle is 0 to 15 degrees from the substrate normal direction; and the ion concentration is 1E13 atom / cm³. 3 Up to 1E14 atom / cm 3 The implantation energy range for boron is 15 keV to 40 keV, and the implantation energy range for boron fluoride is 30 keV to 80 keV.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first doped ion also includes a second ion, the second ion having the opposite conductivity type to the first ion.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process parameters for the first doping ion process also include: the second ion comprises phosphorus ions, the implantation angle is 0 to 10 degrees from the substrate normal direction, and the ion concentration is 5E12 atom / cm³. 3 Up to 5E13 atom / cm 3 The injection energy range is from 15 keV to 50 keV.

10. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the doped region includes: forming a first mask layer on the surface of the second region and the surface of the gate layer; forming the doped region using the first mask layer as a mask; and removing the first mask layer after forming the doped region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the first mask layer includes photoresist.

12. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the first well region includes: forming a second mask layer covering the surface of the second region and a portion of the gate layer; doping the first region with second doped ions using the second mask layer as a mask to form the first well region; and removing the second mask layer after forming the first well region.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the second mask layer includes photoresist.

14. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the second well region includes: forming a third mask layer covering the surface of the first region and a portion of the gate layer; using the third mask layer as a mask, doping the second region with third dopant ions to form the second well region; and removing the third mask layer after forming the second well region.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The material of the third mask layer includes photoresist.

16. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the gate layer includes: forming a gate material layer on the surface of the substrate, patterning the gate material layer, and forming the gate layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, Before forming the source and drain, the method further includes forming a sidewall on the sidewall surface of the gate layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The sidewall material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

19. The method for forming a semiconductor structure as described in claim 5, characterized in that, Before forming the source and the drain, the method further includes forming an isolation structure within the second well region, the isolation structure being located between the drain and the gate layer and being partially covered by the gate layer.

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