Power supply monitoring circuit and switching power supply

Abstract

The present invention discloses a power supply monitoring circuit and a switching power supply. The power supply monitoring circuit includes: a core sampling control module, which is used to output a first control signal with a first logic level according to the level state of the power supply voltage; a charge pump, which is used to generate a corresponding reference voltage according to the effective level state of different reset indication signals; a logic level conversion module, which is used to convert the logic level of the first control signal according to the reference voltage to output a second control signal with a second logic level; an output module, which includes at least one switch tube, the gate of which receives the second control signal, and the switch tube is used to output an effective reset indication signal at the drain when it is turned on, and the switch tube is a depletion type transistor. The circuit can work normally when the power supply voltage is 0V, and occupies a small area, and has high stability and accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a power supply monitoring circuit and a switching power supply. Background Art

[0002] For circuits such as power monitoring chips, the output pins are required to be able to provide the correct indication voltage at the lowest possible power supply voltage and provide a sufficiently low output impedance. In order to prevent power failure, in most circuit systems, power monitoring chips are used to monitor the system power supply voltage. When the power supply voltage is lower than the system operating voltage, the power monitoring chip outputs a logic high or logic low level to the core circuit to reset the circuit. This requires the power monitoring chip to provide the correct reset indication to the system's subsequent chips at extremely low power supply voltages, which requires the reset chip to work at extremely low voltages.

[0003] The typical circuit structure of the power supply monitoring chip circuit (hereinafter referred to as the power supply monitoring circuit) 10 can be referred to Figure 1 , including an output circuit 11 and a core sampling control circuit 12 connected to the output circuit 11, the output circuit 11 includes a transistor M10 and a transistor M11 connected in series between the input terminal of the power supply voltage VCC and the reference ground GND, and the gates of the transistors M0 and M1 are connected to the output terminal of the core sampling control circuit 12. Taking the low level as an effective reset level as an example, for the above-mentioned problem, the traditional solution is usually to increase the width-to-length ratio of the transistors M10 and M11 in the output circuit 11, reduce the on-resistance of the output circuit 11, and connect an external resistor R at the output terminal. For this solution, adding the external resistor R will increase the overall power consumption of the system. Increasing the width-to-length ratio of the transistors M10 and M11 in the output circuit 11 not only increases the chip area, but the circuit does not completely solve the problem of low voltage operation, and it usually requires the core circuit to be able to operate at low voltage.

[0004] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a power supply monitoring circuit and a switching power supply. The power supply monitoring circuit can work normally when the power supply voltage is 0V, occupies a small area, and has high stability and accuracy.

[0006] According to a first aspect of the present disclosure, there is provided a power supply monitoring circuit, comprising: a core sampling control module connected to a power supply voltage input terminal, and configured to output a first control signal having a first logic level according to a level state of the power supply voltage;

[0007] A charge pump, used for generating a corresponding reference voltage according to the effective level state of different reset indication signals;

[0008] a logic level conversion module, connected to the output module, the core sampling control module and the charge pump respectively, and configured to convert the logic level of the first control signal according to the reference voltage to output a second control signal with a second logic level;

[0009] an output module, configured to provide a reset indication signal according to the second control signal, wherein the reset indication signal is used to indicate a level state of the power supply voltage,

[0010] Wherein, the output module includes at least one switch tube, the gate of which receives the second control signal, the switch tube is used to output the valid reset indication signal at the drain when turned on, and the switch tube is a depletion-type transistor.

[0011] Optionally, the output module includes: a first switch tube and a second switch tube,

[0012] The first switch tube and the second switch tube are connected in series between the power supply voltage input terminal and the reference ground in sequence, the gate of the first switch tube receives the first control signal or the second control signal, and the gate of the second switch tube receives the second control signal.

[0013] Among them, the first switch tube is an enhancement-type PMOS transistor, the second switch tube is a depletion-type NMOS transistor, the output module outputs the reset indication signal at the drain of the second switch tube, and the reset indication signal is valid when it is in a low level state.

[0014] Optionally, the output module includes: a first resistor and a third switch tube,

[0015] The first resistor and the third switch tube are connected in series between the power supply voltage input terminal and the reference ground in sequence, and the gate of the third switch tube receives the second control signal.

[0016] Wherein, the third switch tube is a depletion-type NMOS transistor, the output module outputs the reset indication signal at the drain of the third switch tube, and the reset indication signal is valid when it is in a low level state.

[0017] Optionally, the output module includes: a fourth switch tube and a fifth switch tube,

[0018] The fourth switch tube and the fifth switch tube are connected in series between the power supply voltage input terminal and the reference ground in sequence, the gate of the fourth switch tube receives the first control signal or the second control signal, and the gate of the fifth switch tube receives the second control signal.

[0019] Among them, the fourth switch tube is a depletion-type PMOS transistor, the fifth switch tube is an enhancement-type NMOS transistor, the output module outputs the reset indication signal at the drain of the fourth switch tube, and the reset indication signal is valid when it is in a high level state.

[0020] Optionally, the output module includes: a sixth switch tube and a second resistor,

[0021] The sixth switch tube and the second resistor are connected in series between the power supply voltage input terminal and the reference ground in sequence, and the gate of the sixth switch tube receives the second control signal.

[0022] Wherein, the sixth switch tube is a depletion-type PMOS transistor, the output module outputs the reset indication signal at the drain of the sixth switch tube, and the reset indication signal is valid when it is in a high level state.

[0023] Optionally, the charge pump generates a reference voltage having a negative voltage.

[0024] Optionally, the charge pump generates a reference voltage greater than the power supply voltage.

[0025] Optionally, when the first logic level is the power supply voltage, the second logic level is also the power supply voltage;

[0026] When the first logic level is 0, the second logic level is the reference voltage.

[0027] Optionally, when the first logic level is the power supply voltage, the second logic level is 0;

[0028] When the first logic level is 0, the second logic level is the reference voltage.

[0029] According to a second aspect of the present disclosure, a switching power supply is provided, comprising a control circuit and a power circuit, wherein the control circuit comprises a control module and the power supply monitoring circuit as described above.

[0030] The beneficial effects of the present invention are as follows: the present invention relates to a power supply monitoring circuit and a switching power supply, in which a depletion-type transistor is used as an output-stage transistor for outputting a reset indication signal in the power supply monitoring circuit. Due to the conduction characteristics of the depletion-type transistor, the power supply monitoring circuit can be normally turned on even when the power supply voltage is very low, and correctly outputs a valid reset indication signal. At the same time, a charge pump and a logic level conversion module are also provided in the power supply monitoring circuit, and the logic level of the control signal output to the switch tube is converted by the logic level conversion module based on the reference voltage output by the charge pump, so that the switch tube can still be correctly turned on and off after the power supply voltage is increased and the core circuit works normally, effectively ensuring the accuracy of the output reset indication signal.

[0031] On the other hand, the circuit can realize the correct reset indication signal output without external resistors, thereby occupying a very small area.

[0032] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0034] Figure 1 A schematic diagram of the circuit structure of an existing power supply monitoring circuit is shown;

[0035] Figure 2 A structural block diagram of a power supply monitoring circuit provided according to an embodiment of the present disclosure is shown;

[0036] Figure 3 A schematic diagram of the circuit structure of a power supply monitoring circuit provided according to the first embodiment of the present disclosure is shown;

[0037] Figure 4 A circuit structure diagram of a power supply monitoring circuit provided according to a second embodiment of the present disclosure is shown;

[0038] Figure 5 A schematic diagram of the circuit structure of a power supply monitoring circuit provided according to a third embodiment of the present disclosure is shown;

[0039] Figure 6 A circuit structure schematic diagram of a power supply monitoring circuit provided according to a fourth embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0042] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0043] refer to Figure 2 , Figure 2 A structural block diagram of a power supply monitoring circuit provided according to an embodiment of the present disclosure is shown.

[0044] like Figure 2 As shown, in the present disclosure, the power monitoring chip mainly includes a power supply voltage VCC input terminal, an output terminal OUT and a reference ground GND. And the internal circuit structure of the power monitoring chip, i.e., the power monitoring circuit 20, mainly includes a core sampling control module 21, a charge pump 22, a logic level conversion module 23 and an output module 24.

[0045] The core sampling control module 21 and the output module 24 are respectively connected between the power supply voltage VCC input terminal and the reference ground GND, the logic level conversion module 23 is connected between the output terminal of the core sampling control module 21 and the control terminal of the output module 24, and the charge pump 22 is connected to the logic level conversion module 23.

[0046] The core sampling control module 21 is used to output a first control signal with a first logic level according to the level state of the power supply voltage VCC. The charge pump 22 is used to generate a corresponding reference voltage according to the effective level state of different reset indication signals. The logic level conversion module 23 is used to convert the logic level of the first control signal according to the reference voltage to output a second control signal with a second logic level. The output module 24 is used to provide a reset indication signal according to the second control signal, and the reset indication signal is used to characterize the level state of the power supply voltage VCC (for example, when the reset indication signal is valid, it characterizes that the power supply voltage VCC is less than the threshold voltage, and when the reset indication signal is invalid, it characterizes that the power supply voltage VCC is greater than the threshold voltage). Optionally, the valid reset indication signal can also be used to trigger the core circuit that generates the power supply voltage VCC to reset.

[0047] In the present disclosure, the output module 24 includes at least one switch tube, the gate of which receives the second control signal, and the switch tube is used to output a valid reset indication signal at the drain of the switch tube when it is turned on. Furthermore, in the present disclosure, the switch tube is a depletion-type transistor. In this way, based on the conduction characteristics of the depletion-type transistor, the power monitoring circuit 20 can be normally turned on even when the power supply voltage is very low, and correctly output a valid reset indication signal.

[0048] At the same time, the reference voltage generated by the charge pump 22 has a logic level that can cut off the switch tube. Therefore, the logic level conversion module 23 converts the logic level of the control signal output to the switch tube based on the reference voltage output by the charge pump 22, so that the switch tube can still be correctly turned on and off after the power supply voltage VCC increases and the core circuit works normally, effectively ensuring the accuracy of the reset indication signal output during the change of the power supply voltage VCC.

[0049] The specific working principle of the power monitoring circuit 20 in the present disclosure is described below in conjunction with specific embodiments:

[0050] Embodiment 1

[0051] In this embodiment, the reset indication signal is effective when it is in a low level state.

[0052] refer to Figure 3 The output module 24 includes: a first switch tube MP0 and a second switch tube MN0. The first switch tube MP0 and the second switch tube MN0 are connected in series between the power supply voltage VCC input terminal and the reference ground GND in sequence. The gate of the first switch tube MP0 receives the first control signal or the second control signal A, and the gate of the second switch tube MN0 receives the second control signal A. The first switch tube MP0 is an enhancement type PMOS transistor, and the second switch tube MN0 is a depletion type NMOS transistor. The output module 24 outputs a reset indication signal to the output terminal OUT at the drain of the second switch tube MN0.

[0053] Furthermore, in this embodiment, the charge pump 22 generates a reference voltage having a negative voltage VSS.

[0054] The specific working principle is as follows:

[0055] 1) When the voltage value of the power supply voltage VCC is very low and lower than the normal working voltage of the core sampling control module 21, the core sampling control module 21, the charge pump 22 and the logic conversion module 23 do not work. At this time, the logic level of the second control signal A received by the control end of the output module 24 is almost 0V.

[0056] Since the depletion-type NMOS tube can be turned on at 0V, the first switch tube MP0 is in the off state and the second switch tube MN0 is in the on state, so that the reset indication signal output by the output module 24 to the output terminal OUT is in a low-level effective state. At the same time, the second switch tube MN0 in the on state can provide an extremely low on-resistance, so that when the power supply voltage VCC is in the range between 0V and the minimum operating voltage of the core sampling control module 21, the output terminal OUT always provides a low-resistance circuit to the ground, so that the voltage of the output terminal OUT is 0V, thereby correctly outputting a low-level effective reset indication signal.

[0057] 2) When the power supply voltage VCC rises to the operating voltage of the core sampling control module 21, the core sampling control module 21, the charge pump 22 and the logic conversion module 23 all start to work normally. Then the charge pump 22 provides a negative voltage VSS relative to the ground as a reference voltage, and the voltage is lower than the cut-off level of the second depletion-type switch tube MNO.

[0058] At this time, if the power supply voltage VCC is less than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage VCC, and the second logic level of the second control signal A output by the logic level conversion module 23 is also the power supply voltage VCC, and then the second control signal A can control the first switch tube MP0 to be in the off state and control the second switch tube MN0 to be in the on state, so that the reset indication signal output by the output module 24 to the output terminal OUT is in a low-level effective state.

[0059] At this time, if the power supply voltage VCC is greater than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage 0V, and the second logic level of the second control signal A output by the logic level conversion module 23 will be converted to the negative voltage VSS of the reference voltage, and then the second control signal A can control the first switch tube MP0 to be in the on state and the second switch tube MN0 to be in the off state, so that the reset indication signal output by the output module 24 to the output terminal OUT is in the high level invalid state. That is, the reset function of the reset indication signal is released.

[0060] Based on the above description, it can be known that the power monitoring circuit 20 disclosed in this embodiment can work when the power supply voltage VCC is 0V, so as to provide a correct reset indication signal to the system. At the same time, after each module of the circuit 20 works, it can still provide a correct reset indication signal, thereby controlling the correct opening and closing of the core circuit of the switching power supply.

[0061] Embodiment 2

[0062] In this embodiment, the reset indication signal is effective when it is in a high level state.

[0063] refer to Figure 4 The output module 24 includes: a fourth switch tube MP1 and a fifth switch tube MN1. The fourth switch tube MP1 and the fifth switch tube MN1 are connected in series between the power supply voltage VCC input terminal and the reference ground GND in sequence. The gate of the fourth switch tube MP1 receives the first control signal or the second control signal A, and the gate of the fifth switch tube MN1 receives the second control signal A. The fourth switch tube MP1 is a depletion-type PMOS transistor, and the fifth switch tube MN1 is an enhancement-type NMOS transistor. The output module 24 outputs a reset indication signal to the output terminal OUT at the drain of the fourth switch tube MP1.

[0064] Furthermore, in this embodiment, the charge pump 22 generates a reference voltage greater than the power supply voltage VCC.

[0065] The specific working principle is as follows:

[0066] 1) When the voltage value of the power supply voltage VCC is very low and lower than the normal working voltage of the core sampling control module 21, the core sampling control module 21, the charge pump 22 and the logic conversion module 23 do not work. At this time, the logic level of the second control signal A received by the control end of the output module 24 is almost 0V.

[0067] Since the depletion-type PMOS tube can be turned on at 0V, the fourth switch tube MP1 is in the on state and the fifth switch tube MN1 is in the off state at this time, so that the reset indication signal output by the output module 24 to the output terminal OUT is in a high-level valid state. At the same time, the fourth switch tube MP1 in the on state can provide an extremely low on-resistance, so that when the power supply voltage VCC is in the range between 0V and the minimum working voltage of the core sampling control module 21, the output terminal OUT always provides a low-resistance circuit to the power supply voltage input terminal, so that the voltage of the output terminal OUT is high, thereby correctly outputting a high-level valid reset indication signal.

[0068] 2) When the power supply voltage VCC rises to the operating voltage of the core sampling control module 21, the core sampling control module 21, the charge pump 22 and the logic conversion module 23 all start to work normally. Then the charge pump 22 provides a voltage greater than the power supply voltage VCC as a reference voltage, and the voltage is lower than the cut-off level of the fourth depletion-type switch tube MP1.

[0069] At this time, if the power supply voltage VCC is less than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage VCC, and the second logic level of the second control signal A output by the logic level conversion module 23 is 0V, and then the second control signal A can control the fourth switch tube MP1 to be in the on state and the fifth switch tube MN1 to be in the off state, so that the reset indication signal output by the output module 24 to the output terminal OUT is in the effective state of the high level.

[0070] At this time, if the power supply voltage VCC is greater than the threshold voltage, the first logic level of the first control signal output by the core sampling control module 21 is the power supply voltage 0V, and the second logic level of the second control signal A output by the logic level conversion module 23 will be converted to a voltage value of the reference voltage greater than the power supply voltage VCC, and then the second control signal A can control the fourth switch tube MP1 to be in the off state and the fifth switch tube MN1 to be in the on state, so that the reset indication signal output by the output module 24 to the output terminal OUT is in the low level invalid state. That is, the reset function of the reset indication signal is released.

[0071] Based on the above description, it can be known that the embodiment of the present disclosure only needs to appropriately change the type of switch tube in the output module 24 and the corresponding charge pump 22 and the output level of the logic level conversion module 23 for different effective states of the reset indication signal, so as to realize the correct output of the reset indication signal by the power supply monitoring circuit 20 when the power supply voltage VCC is 0V or after the various modules of the circuit 20 are working.

[0072] Furthermore, the principle description parts in the above-mentioned embodiments 1 and 2 are all explained by taking the gate of the enhancement mode transistor receiving the second control signal A as an example, but it can be understood that when the gate of the enhancement mode transistor receives the first control signal, the above description is also applicable, so no further explanation will be given here.

[0073] Embodiment 3

[0074] In this embodiment, the reset indication signal is effective when it is in a low level state.

[0075] refer to Figure 5 The output module 24 includes: a first resistor R1 and a third switch tube MN2. The first resistor R1 and the third switch tube MN2 are connected in series between the power supply voltage VCC input terminal and the reference ground GND, and the gate of the third switch tube MN2 receives the second control signal A. The third switch tube MN2 is a depletion type NMOS transistor. And the output module 24 outputs a reset indication signal at the drain of the third switch tube MN2.

[0076] Furthermore, in this embodiment, the charge pump 22 generates a reference voltage having a negative voltage VSS.

[0077] The power monitoring circuit 20 in this embodiment is compared with the power monitoring circuit 20 in the first embodiment, except that the PMOS transistor in the output module 24 is replaced by a resistor. Its specific working principle is basically the same as that described in the first embodiment, so it will not be repeated here. Please refer to the first embodiment for details.

[0078] Embodiment 4

[0079] In this embodiment, the reset indication signal is effective when it is in a high level state.

[0080] refer to Figure 6 The output module 24 includes: a sixth switch tube MP2 and a second resistor R2. The sixth switch tube MP2 and the second resistor R2 are connected in series between the power supply voltage VSS input terminal and the reference ground GND, and the gate of the sixth switch tube MP2 receives the second control signal A. The sixth switch tube MP2 is a depletion type PMOS transistor. The output module 24 outputs a reset indication signal at the drain of the sixth switch tube MP2.

[0081] Furthermore, in this embodiment, the charge pump 22 generates a reference voltage greater than the power supply voltage VCC.

[0082] The power monitoring circuit 20 in this embodiment is compared with the power monitoring circuit 20 in the second embodiment, except that the NMOS transistor in the output module 24 is replaced by a resistor. Its specific working principle is basically the same as that described in the second embodiment, so it will not be repeated here. Please refer to the second embodiment for details.

[0083] Compared with the push-pull output mode of the output module 24 in the first or second embodiment of the present disclosure, the output module 24 in the third and fourth embodiments of the present disclosure adopts a source open output structure, but can also achieve the same function, thus providing more choices for users.

[0084] The present disclosure also relates to a switching power supply, which includes a control circuit and a power circuit. The control circuit in the switching power supply further includes a control module and a Figures 2 to 6 The power supply monitoring circuit 20 described in .

[0085] In summary, the power monitoring circuit and switching power supply involved in the present disclosure use depletion-type transistors as output-stage transistors for outputting reset indication signals in the power monitoring circuit. Due to the conduction characteristics of depletion-type transistors, the power monitoring circuit can be normally turned on even when the power supply voltage is very low, and correctly outputs a valid reset indication signal. At the same time, a charge pump and a logic level conversion module are also provided in the power monitoring circuit. The logic level of the control signal output to the switch tube is converted by the logic level conversion module based on the reference voltage output by the charge pump, so that the switch tube can still be correctly turned on and off after the power supply voltage is increased and the core circuit works normally, effectively ensuring the accuracy of the output reset indication signal.

[0086] Furthermore, the circuit can realize the correct reset indication signal output without an external resistor, thereby occupying a very small area.

[0087] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0088] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A power supply monitoring circuit, wherein: include: A core sampling control module, connected to the power supply voltage input terminal, and configured to output a first control signal having a first logic level according to a level state of the power supply voltage; A charge pump, used for generating a corresponding reference voltage according to the effective level state of different reset indication signals; a logic level conversion module, connected to the output module, the core sampling control module and the charge pump respectively, and configured to convert the logic level of the first control signal according to the reference voltage to output a second control signal with a second logic level; an output module, configured to provide a reset indication signal according to the second control signal, wherein the reset indication signal is used to indicate a level state of the power supply voltage, Wherein, the output module includes at least one switch tube, the gate of which receives the second control signal, the switch tube is used to output the valid reset indication signal at the drain when turned on, and the switch tube is a depletion-type transistor; During the period when the power supply voltage is less than the threshold voltage and greater than the operating voltage of the core sampling control module, the second logic level is the power supply voltage when the reset indication signal is in a low level state and is valid, and the second logic level is 0 when the reset indication signal is in a high level state and is valid; During a period when the power supply voltage is greater than the threshold voltage, the second logic level is the reference voltage, and the reference voltage has a logic level that turns off the switch tube.

2. The power monitoring circuit according to claim 1, wherein: The output module includes: a first switch tube and a second switch tube, The first switch tube and the second switch tube are connected in series between the power supply voltage input terminal and the reference ground in sequence, the gate of the first switch tube receives the first control signal or the second control signal, and the gate of the second switch tube receives the second control signal. Among them, the first switch tube is an enhancement type PMOS transistor, the second switch tube is a depletion type NMOS transistor, the output module outputs the reset indication signal at the drain of the second switch tube, and the reset indication signal is valid when it is in a low level state.

3. The power supply monitoring circuit according to claim 1, wherein: The output module includes: a first resistor and a third switch tube, The first resistor and the third switch tube are connected in series between the power supply voltage input terminal and the reference ground in sequence, and the gate of the third switch tube receives the second control signal. Wherein, the third switch tube is a depletion-type NMOS transistor, the output module outputs the reset indication signal at the drain of the third switch tube, and the reset indication signal is valid when it is in a low level state.

4. The power supply monitoring circuit according to claim 1, wherein: The output module includes: a fourth switch tube and a fifth switch tube, The fourth switch tube and the fifth switch tube are connected in series between the power supply voltage input terminal and the reference ground in sequence, the gate of the fourth switch tube receives the first control signal or the second control signal, and the gate of the fifth switch tube receives the second control signal. Among them, the fourth switch tube is a depletion-type PMOS transistor, the fifth switch tube is an enhancement-type NMOS transistor, the output module outputs the reset indication signal at the drain of the fourth switch tube, and the reset indication signal is valid when it is in a high level state.

5. The power monitoring circuit according to claim 1, wherein: The output module includes: a sixth switch tube and a second resistor, The sixth switch tube and the second resistor are connected in series between the power supply voltage input terminal and the reference ground in sequence, and the gate of the sixth switch tube receives the second control signal. Wherein, the sixth switch tube is a depletion-type PMOS transistor, the output module outputs the reset indication signal at the drain of the sixth switch tube, and the reset indication signal is valid when it is in a high level state.

6. The power supply monitoring circuit according to any one of claims 2 and 3, wherein: The charge pump generates a reference voltage having a negative voltage.

7. The power supply monitoring circuit according to any one of claims 4 and 5, wherein: The charge pump generates a reference voltage greater than the power supply voltage.

8. The power supply monitoring circuit according to claim 6, wherein: When the first logic level is the power supply voltage, the second logic level is also the power supply voltage; When the first logic level is 0, the second logic level is the reference voltage.

9. The power supply monitoring circuit according to claim 7, wherein: When the first logic level is the power supply voltage, the second logic level is 0; When the first logic level is 0, the second logic level is the reference voltage.

10. A switching power supply, comprising a control circuit and a power circuit, wherein: The control circuit comprises a control module and a power supply monitoring circuit as claimed in any one of claims 1 to 9.

Images