Integrated Circuit Synthesis Method, Apparatus, Computer Device, and Storage Medium

Abstract

The present disclosure provides a comprehensive method, apparatus, computer device, and storage medium for an integrated circuit. Among them, the method includes: obtaining an initial timing constraint file of the integrated circuit and the register transfer level (RTL) circuit of the integrated circuit; the initial timing constraint file includes: timing constraint information obtained by performing timing settings on input / output (I / O) data of each functional module in the integrated circuit; based on the RTL, performing correction processing on the timing constraint information in the initial timing constraint file to obtain a target timing constraint file; performing circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and in particular, to a method, apparatus, computer device, and storage medium for synthesizing an integrated circuit. Background Art

[0002] The design steps of an integrated circuit generally include: generating a behavioral description, generating a register transfer level (RTL) circuit description, converting the behavioral description or RTL-level description into a gate-level circuit, and generating a physical layout (integrated circuit layout) based on the gate-level circuit. The process of converting the behavioral description circuit and / or RTL to the gate-level circuit is called synthesis. Before synthesis, it is necessary to set timing constraint information for the input or output (I / O) data of each functional module in the integrated circuit by the integrated circuit designer, generate a corresponding timing constraint file, and then use the timing constraint file to synthesize the RTL to obtain a gate-level circuit.

[0003] However, with the continuous growth of the design scale of system-on-chip (SOC), the number of transistors integrated on a single chip has reached billions or tens of billions. Due to the continuous evolution of the process, more and more modules are integrated on a chip, and the interfaces of the chip and internal modules are also increasing to implement more and more complex functions, which also leads to an increasing number of I / Os inside the integrated circuit. Manual setting of I / O constraints may result in errors such as omissions and typos, leading to incomplete or incorrect constraints. During the synthesis of RTL, a large amount of computing resources, manpower, and time are required to solve the timing constraint problem of I / O data, resulting in low synthesis efficiency and high cost of the integrated circuit. Summary of the Invention

[0004] Embodiments of the present disclosure provide at least a method, apparatus, computer device, and storage medium for synthesizing an integrated circuit.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for synthesizing an integrated circuit, including: obtaining an initial timing constraint file of the integrated circuit and the register transfer level (RTL) circuit of the integrated circuit; the initial timing constraint file includes: timing constraint information obtained by setting timing for the input or output (I / O) data of each functional module in the integrated circuit; based on the RTL, performing correction processing on the timing constraint information in the initial timing constraint file to obtain a target timing constraint file; performing circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit.

[0006] In this way, the register transfer level (RTL) circuit corrects the initial timing constraint file before logic synthesis to obtain a target timing constraint file. Therefore, when performing logic synthesis on each functional module of the integrated circuit, it is not necessary to consider the integrity and accuracy of the I / O timing constraints, reducing the number of iterations of logic synthesis and improving the integrated circuit synthesis efficiency.

[0007] In an alternative embodiment, the timing constraint information includes: the first identification information of the I / O data, the clock name of the clock corresponding to the I / O data, and the clock period corresponding to the I / O data; wherein, the clock corresponding to the I / O data is used to control the clock period of the corresponding I / O data.

[0008] In this way, by setting the first identification information of the I / O data, the clock name of the clock corresponding to the I / O data, and the clock period corresponding to the I / O data, a timing constraint file is generated, providing a basis for timing analysis and optimizing subsequent logic synthesis and gate-level circuits.

[0009] In an alternative embodiment, the correcting the timing constraint information in the initial timing constraint file based on the RTL to obtain a target timing constraint file includes: parsing the RTL to obtain the second identification information of the I / O data of each functional module in the RTL integrated circuit; based on the second identification information and the initial timing constraint file, determining whether there is first target I / O data for which the timing constraint is not set in the I / O data; in response to the existence of the first target I / O data, determining the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data; and obtaining the target timing constraint file based on the timing constraint information of the first target I / O data.

[0010] In this way, by using the second identification information and the initial timing constraint file, the first target I / O data for which the timing constraint is not set is determined. Furthermore, the timing constraint is set for the rated clock period corresponding to the first target I / O data to obtain a target timing constraint file, thereby completing the adjustment of the timing constraint of the I / O data before logic synthesis, reducing the number of iterations of logic synthesis, and improving the logic synthesis efficiency.

[0011] In an alternative embodiment, the determining whether there is first target I / O data for which the timing constraint is not set in the I / O data based on the second identification information and the initial timing constraint file includes: matching the second identification information and the first identification information; in response to any second identification information and the first identification information failing to match, determining the I / O data corresponding to the unmatched second identification information as the first target I / O data.

[0012] In this way, the first target I / O data can be filtered out by matching the I / O data corresponding to the second identification information of the matching failure, and then the I / O data for which timing constraint information needs to be set can be determined, ignoring the I / O data for which timing constraint information has already been set, thereby improving the efficiency of setting timing constraints.

[0013] In an alternative embodiment, before determining the timing constraint information of the first target I / O data based on the nominal clock period of the clock corresponding to the first target I / O data in response to the existence of the first target I / O data, it further includes: based on the second identification information of the determined first target I / O data, parsing the clock corresponding to the first target I / O data and the nominal clock period from the RTL; or,

[0014] Parsing the RTL to obtain the clocks corresponding to the I / O data of each functional module in the integrated circuit and the nominal clock period; based on the second identification information of the determined first target I / O data, screening the clocks corresponding to the first target I / O data and the nominal clock period from the clocks corresponding to the I / O data of each functional module in the integrated circuit and the nominal clock period.

[0015] In this way, based on the clock corresponding to the obtained first target I / O data and the nominal clock period, the setting of the timing constraint information for the first target I / O data can be achieved.

[0016] In an alternative embodiment, determining the timing constraint information of the first target I / O data based on the nominal clock period of the clock corresponding to the first target I / O data includes: generating the timing constraint information of the first target I / O data based on the nominal clock period of the clock corresponding to the first target I / O data and a preset coefficient.

[0017] In this way, by calculating between the nominal clock period of the clock corresponding to the first target I / O data and the preset coefficient, the timing constraint information of the first target I / O data is obtained.

[0018] In an alternative embodiment, obtaining the target timing constraint file based on the timing constraint information of the first target I / O data includes: writing the timing constraint information of the first target I / O data into the initial timing constraint file to generate the target timing constraint file.

[0019] In this way, by writing the obtained timing constraint information of the first target I / O data into the initial timing constraint file, the purpose of checking for missing I / O constraints and supplementing the constraints is achieved.

[0020] In an alternative embodiment, obtaining the target timing constraint file based on the timing constraint information of the first target I / O data includes: writing, based on the timing constraint information of the first target I / O data, another timing constraint file different from the initial timing constraint file, and generating the target timing constraint file.

[0021] In this way, by writing the timing constraint information of the obtained first target I / O data into another timing constraint file different from the initial timing constraint file, the two files will be logically synthesized together during logical synthesis, achieving the purpose of checking for missing I / O constraints and supplementing the constraints.

[0022] In an alternative embodiment, performing circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit includes: performing circuit logic synthesis based on the target timing constraint file, the initial timing constraint file, and the RTL to obtain the gate-level circuit of the integrated circuit.

[0023] In this way, after circuit logic synthesis using the target constraint file, the initial timing constraint file, and the RTL, the gate-level circuit of the integrated circuit is obtained.

[0024] In an alternative embodiment, the method further includes: determining, based on the second identification information and the initial timing constraint file, whether there is second target I / O data in the initial timing constraint file that is not included in the integrated circuit; in response to the existence of the second target I / O data, deleting the timing constraint information of the second target I / O data from the initial timing constraint file.

[0025] In this way, by deleting the timing constraint information of the second target I / O data from the initial timing constraint file, duplicate I / O data can be avoided, the logical synthesis time can be reduced, and thus the logical synthesis efficiency can be improved.

[0026] In a second aspect, an integrated circuit synthesis device provided by an embodiment of the present disclosure includes:

[0027] An acquisition module, configured to acquire an initial timing constraint file of an integrated circuit and the register transfer level circuit RTL of the integrated circuit; the initial timing constraint file includes: timing constraint information corresponding to input or output I / O data of functional modules in the integrated circuit; a matching module, configured to perform correction processing on the timing constraint information in the initial timing constraint file based on the RTL to obtain a target timing constraint file; a logic synthesis module, configured to perform circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit.

[0028] In an alternative embodiment, the timing constraint information includes: the first identification information of the I / O data, the clock name of the clock corresponding to the I / O data, and the clock period corresponding to the I / O data; wherein, the clock corresponding to the I / O data is used to control the clock period of the corresponding I / O data.

[0029] In an alternative embodiment, the apparatus further includes a parsing module, and the parsing module is further configured to: parse the RTL to obtain the second identification information of the I / O data of each functional module in the RTL integrated circuit; the matching module is further configured to: based on the second identification information and the initial timing constraint file, determine whether there is first target I / O data for which the timing constraint is not set in the I / O data; in response to the existence of the first target I / O data, determine the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data; and obtain the target timing constraint file based on the timing constraint information of the first target I / O data.

[0030] In an alternative embodiment, the matching module is further configured to: match the second identification information and the first identification information; in response to any second identification information and the first identification information failing to match, determine the I / O data corresponding to the second identification information that fails to match as the first target I / O data.

[0031] In an alternative embodiment, the parsing module is further configured to: based on the second identification information of the determined first target I / O data, parse the clock corresponding to the first target I / O data and the rated clock period from the RTL; or, parse the RTL to obtain the clocks corresponding to the I / O data of each functional module in the integrated circuit and the rated clock periods; and screen the clocks corresponding to the first target I / O data and the rated clock periods from the clocks corresponding to the I / O data of each functional module in the integrated circuit and the rated clock periods based on the second identification information of the determined first target I / O data.

[0032] In an alternative embodiment, the matching module is further configured to: generate the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data and a preset coefficient.

[0033] In an alternative embodiment, the matching module is further configured to: write the timing constraint information of the first target I / O data into the initial timing constraint file to generate the target timing constraint file.

[0034] In an alternative embodiment, the matching module is further configured to: based on the timing constraint information of the first target I / O data, write another timing constraint file different from the initial timing constraint file to generate the target timing constraint file.

[0035] In an alternative embodiment, the logic synthesis module is further configured to: perform circuit logic synthesis on the target timing constraint file, the initial timing constraint file, and the RTL to obtain the gate-level circuit of the integrated circuit.

[0036] In an alternative embodiment, the matching module is further configured to: in response to the existence of the second target I / O data, delete the timing constraint information of the second target I / O data from the initial timing constraint file.

[0037] In a third aspect, an embodiment of the present disclosure further provides a computer device, including: a processor, a memory, and a bus, where the memory stores machine-readable instructions executable by the processor. When the computer device runs, the processor communicates with the memory through the bus. When the machine-readable instructions are executed by the processor, the steps in the first aspect, or any possible implementation manner in the first aspect, are executed.

[0038] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the steps in the first aspect, or any possible implementation manner in the first aspect, are executed.

[0039] For the effect description of the above integrated circuit synthesis device, computer device, and computer-readable storage medium, refer to the description of the above integrated circuit synthesis method, which will not be repeated here.

[0040] An integrated circuit synthesis method, device, computer device, and computer-readable storage medium provided by an embodiment of the present disclosure determine whether there is first target I / O data without set timing constraints in the initial timing constraint file SDC, and uniformly perform timing constraints on all first target I / O data without set timing constraints, so as to correct the timing constraint information of the I / O with omissions or incorrect settings in the initial timing constraint file, avoid problems such as clerical errors caused by human factors or omissions in the I / O timing constraints, achieve the purpose of checking for omitted I / O constraints and supplementing I / O constraints, reduce the situation of excessive synthesis iteration times caused by problems with I / O constraints, improve the synthesis efficiency of the integrated circuit, and reduce costs.

[0041] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specific embodiments are given, and detailed descriptions are made in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0042] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. The drawings herein are incorporated into the specification and constitute a part of this specification. These drawings show embodiments that conform to the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 Shows a flowchart of a comprehensive method for an integrated circuit provided by an embodiment of the present disclosure;

[0044] Figure 2 Shows a flowchart of a method for checking for missing I / O constraints and supplementing constraints provided by an embodiment of the present disclosure.

[0045] Figure 3 Shows a schematic diagram of an integrated circuit synthesis device provided by an embodiment of the present disclosure;

[0046] Figure 4 Shows a schematic diagram of the structure of a computer device provided by an embodiment of the present disclosure. Detailed Description of the Embodiments

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments. Usually, the components of the embodiments of the present disclosure described and shown here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the present disclosure that is claimed, but merely represents the selected embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0048] It has been found that before synthesizing the RTL in an integrated circuit, the designers of the integrated circuit need to write the timing constraint information of the I / O data into the timing constraint file based on the I / O data of each module in the integrated circuit; when synthesizing the RTL, the timing constraint file is used as the input of the synthesis process. After synthesizing the RTL, a corresponding timing constraint check report will be obtained. The integrated circuit designers can check the integrity and correctness of the I / O constraints in the timing constraint file through the timing constraint check report; if the I / O constraints are incomplete or there are errors, it is necessary to confirm the location of the problem in the timing constraint file, modify the location of the problem in the timing constraint file, and then use the obtained modified timing constraint file to resynthesize the RTL; iterate the above process until all problems with the I / O constraints are solved.

[0049] However, due to the large number of I / Os, manual setting of I / O constraints may result in omissions, typos and other errors, leading to incomplete or incorrect constraints. This causes the adjustment process of the timing constraint file to require multiple iterations in many cases, and in each iteration, it is necessary to resynthesize the RTL. However, the synthesis process consumes a large amount of time and computing resources, resulting in low efficiency and high cost in the synthesis process of the integrated circuit.

[0050] Based on the above research, the present disclosure provides a synthesis method for an integrated circuit. Before synthesizing the integrated circuit, the timing constraint information in the initial timing constraint file is corrected using the RTL, so that the timing constraint information of the I / Os with omissions or incorrect settings in the initial timing constraint file is corrected, thereby using the target timing constraint file to synthesize the RTL, reducing the situation of excessive synthesis iterations caused by problems with the I / O constraints, improving the synthesis efficiency of the integrated circuit, and reducing costs.

[0051] All the defects existing in the above solutions are the results obtained by the inventors after practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by the present disclosure below for the above problems should be the contributions made by the inventors to the present disclosure during the process of the present disclosure.

[0052] It should be noted that similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0053] As used herein, the term "and / or" merely describes an associated relationship and indicates that there can be three relationships. For example, A and / or B can represent three cases: A exists alone, both A and B exist simultaneously, and B exists alone. Additionally, the term "at least one" as used herein means any one of multiple items or any combination of at least two of multiple items. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set composed of A, B, and C.

[0054] To facilitate the understanding of this embodiment, first, a comprehensive method for an integrated circuit disclosed in the embodiments of the present disclosure will be introduced in detail. The execution subject of the circuit layout comprehensive method provided in the embodiments of the present disclosure is generally a computer device with certain computing capabilities. In some possible implementation manners, this circuit layout comprehensive method can be implemented by a processor calling computer-readable instructions stored in a memory.

[0055] See Figure 1 As shown in the flowchart of a comprehensive method for an integrated circuit provided by the embodiments of the present disclosure, the method includes steps S101 to S103, where:

[0056] S101: Obtain an initial timing constraint file for the integrated circuit and the register transfer level (RTL) circuit of the integrated circuit; the initial timing constraint file includes: timing constraint information obtained by setting the timing of input or output (I / O) data of each functional module in the integrated circuit.

[0057] An integrated circuit is a microelectronic device or component. Using a certain process, components such as transistors, resistors, capacitors, and inductors required in a circuit, as well as the wiring, are interconnected and fabricated on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then encapsulated in a package to form a micro-structure with the required circuit functions.

[0058] Before an integrated circuit enters production, an integrated circuit layout corresponding to the integrated circuit needs to be generated. And synthesis based on RTL is a step in the integrated circuit layout generation process.

[0059] The design process of an integrated circuit generally includes two stages: logical design and physical design:

[0060] The logical design stage includes the following a1 to a5:

[0061] a1: Design preparation, overall description of functions, drawing of the system architecture, system state transition diagram, division of multiple functional modules, detailed description of the functions of each functional module, and provision of functional design diagrams and timing diagrams.

[0062] a2: Design input, which is a design input that describes the system at the functional level in the form of a Hardware Description Language (HDL) or a circuit schematic diagram;

[0063] a3: Functional simulation, which is an input for performing functional and timing simulation verification on the functional-level description and converting it into an RTL-level description suitable for a synthesizer after verifying the correct functionality;

[0064] a4: After completing the design input and functional simulation, according to step a1, formulate an initial timing constraint file.

[0065] a5: Logic Synthesis, which converts the description of a high-level design into an optimized gate-level circuit using a certain standard cell library according to certain constraint conditions. The designer only needs to focus on the hierarchical division, high-level design, accurate description of constraint conditions, and optimization of cells in the standard cell library. A large amount of other work is automatically completed by the logic synthesis tool. After multiple interactive processes, the logic synthesis tool finally generates the most optimized gate-level circuit; Pre-layout simulation, which simulates the gate-level circuit with cell delay information added after synthesis to check whether the I / O data of each functional module meets the design system specifications and interface specifications in terms of timing.

[0066] The synthesis described in the embodiments of the present disclosure is the above-mentioned a4 synthesis stage; The timing constraint file includes timing constraint information determined for the I / O data of each functional module in the integrated circuit.

[0067] The physical design stage includes the following b1 to b4:

[0068] b1: Floorplanning, whose task is to select a good layout scheme for each module and the entire chip. Generally, estimate the area of the module based on the number of devices it contains, and then estimate the shape and relative position of the module based on the connection relationship between this module and other modules and the shape of the upper-level module or chip. This process is generally completed manually;

[0069] b2: Placement, determining the position layout of each unit in the module is a relatively complex problem, generally divided into two steps: initial placement and improved placement;

[0070] b3: Routing, usually divided into two steps: Global Routing and Detailed Routing. Global Routing distributes the nets to suitable routing areas without caring about the specific positions of the traces, and Detailed Routing finally determines the specific positions of the connections;

[0071] b4: Parameter extraction to determine the resistance and capacitance at each connection point and the distributed parameters of the interconnecting wires; post-simulation, perform timing simulation again after adding various parasitic electrical parameters added by layout and wiring, and perform Electrical Rule Checking (ERC) and Design Rule Checking (DRC), and finally perform Layout Versus Schematic (LVS) verification of the netlist to confirm the correctness of the layout.

[0072] The RTL level means: not paying attention to the details of registers and combinational logic (such as how many logic gates are used, the connection topology between logic gates, etc.). The goal of RTL-level description is logic synthesis, that is, it can be converted to a gate-level circuit.

[0073] A functional module, also known as a sub-module in an integrated circuit, refers to a sub-circuit that can implement a certain function in an integrated circuit and is composed of circuit elements. Circuit elements include, for example: registers, multipliers, selectors, adders, gate circuits, etc. In the same integrated circuit, multiple levels of functional modules can be included, and each level of functional module can also include at least one functional module. Correspondingly, the description information corresponding to each functional module refers to the descriptive characteristic information such as the functions and attributes possessed by each functional module. Specifically, it can include hardware behavior description, structural description, data flow description, etc. for circuit elements.

[0074] The timing constraint information of I / O includes: the first identification information of I / O data, the clock name corresponding to the clock for I / O data, and the clock period corresponding to I / O data; wherein, the clock corresponding to I / O data is used to control the clock period of the corresponding I / O data.

[0075] Specifically, the first identification information of I / O data can include: the name corresponding to I / O data, identification codes, etc. Through the first identification information of I / O data, the corresponding timing constraint information of I / O can be read from the timing constraint file. If a certain I / O data does not have artificially set timing constraint information before logic synthesis, or an error occurs in the first identification information of I / O data during setting, the first identification information corresponding to the I / O data cannot be found in the timing constraint file.

[0076] Exemplarily, due to the large number of I / Os in an integrated circuit, it is easy to miss or make a clerical error in setting I / O timing constraints, resulting in incomplete or incorrect I / O constraints. Therefore, in the initially obtained timing constraint file, there may be problems such as omission or incorrect setting of the above timing constraint information.

[0077] Following the above S101, the integrated circuit synthesis method provided by the present disclosure further includes:

[0078] S102: Based on the RTL, perform correction processing on the timing constraint information in the initial timing constraint file to obtain a target timing constraint file.

[0079] In specific implementation, the timing constraint file is used to save the timing constraint information corresponding to the I / O data of each functional module in the integrated circuit. During the integrated circuit design process, the integrated circuit design constraint (Synopsys Design Constraints, SDC) file includes the timing constraint file. In addition to the timing constraint information, the SDC also constrains the area and power consumption of the integrated circuit. The SDC determines whether the chip meets the design requirement specifications. An SDC file represents all the I / O timing constraint information included in a functional module in the integrated circuit.

[0080] Exemplarily, for example, the following method can be adopted to perform correction processing on the timing constraint information in the initial timing constraint file: create a timing constraint detection script, where the timing constraint detection script includes: relevant codes for I / O constraint integrity check; execute the timing constraint detection script to implement correction processing on the timing constraint information in the initial timing constraint file.

[0081] Among them, the timing constraint detection script can be applicable to multiple integrated circuits. Through the timing constraint detection script, the I / O timing constraint information in the initial timing constraint files corresponding to each functional module of the integrated circuit can be uniformly detected and corrected, improving the generality and detection efficiency.

[0082] Exemplarily, for example, the following steps A to C can be adopted to perform correction processing on the timing constraint information:

[0083] Step A: Parse the RTL to obtain the second identification information of the I / O data of each functional module in the RTL integrated circuit.

[0084] Specifically, the RTL circuit describes the sequential logic and combinational logic of the circuit, that is, the RTL reflects the register structure and number of the circuit, the topological structure of the circuit, the combinational logic function between registers, and the combinational logic function between registers and I / O ports. By parsing the RTL code, the second identification information of the I / O data of each functional module in the RTL integrated circuit can be obtained;

[0085] Among them, the second identification information obtained by parsing the RTL code can be the names, identification codes, etc. corresponding to all the I / O data of each functional module of the integrated circuit.

[0086] Exemplarily, the RTL description can be represented as a finite state machine, or a sequential state machine that can perform register transfer on a predetermined clock cycle boundary, and is usually described in two languages, VHDL / Verilog. Therefore, when parsing the RTL, it can be to traverse the RTL code, detect whether there is identification information of I / O from the traversed code, and if so, read out the identification information. For example, a table can be exported for the obtained second identification information, the table contains corresponding functional modules, and the functional modules are sorted in a preset manner. For example, they are sorted in the order of traversing the functional modules. The number of I / O data corresponding to the first functional module traversed is 8, and the second identification information of the 8 I / O data is s1 to s8 respectively. The number of I / O data corresponding to the second functional module is 4, and the second identification information of the 4 I / O data is s9 to s12 respectively. Then, in the exported table, the sorting of I / O can include, for example: s1 to s8, s9 to s12.

[0087] The table is just a storage method, and it can also be a list, or other storage methods such as storing in the order of traversing the second identification information, which is not limited here.

[0088] Step B: Based on the second identification information and the initial timing constraint file, determine whether there is first target I / O data without set timing constraints.

[0089] In a specific implementation, the process of determining the first target I / O data is shown in the following steps b1 to b2, for example:

[0090] Step b1: Match the second identification information and the first identification information.

[0091] When matching the second identification information and the first identification information, for example, for each piece of second identification information, each piece of first identification information in the initial timing constraint file can be compared with this second identification information; if any one of the first identification information is consistent with this piece of second identification information, then this second identification information and this piece of first identification information are successfully matched.

[0092] If for a certain piece of second identification information, there is no consistent first identification information in the initial timing constraint file, then this second identification information and the first identification information fail to match.

[0093] Exemplarily, the first identification information is s1 to sm respectively, and the second identification information is x1 to xn respectively. Assuming that there may be omissions or inconsistencies in the first identification information, and the second identification information is obtained continuously from the RTL, so it is considered correct.

[0094] For x1: Compare s1 with x1. If they are inconsistent, compare s2 with x1. If they are still inconsistent, compare s3 with x1. If they are consistent, then s3 and x1 are successfully matched.

[0095] For x2: Compare s1 with x2. If they are inconsistent, compare s2 with x2. If they are still inconsistent, then compare s3 with x2,... compare sm with x2. If they are still inconsistent, then x2 fails to match the first identification information.

[0096] In this way, for each second identification information among x1 to xn, check in the RTL constraint file whether it has the same first identification information. If the match fails, it is considered that the timing constraint information corresponding to this second identification information is missing in the timing constraint file.

[0097] In another example, a table containing the first identification information and the second identification information can be generated. In this table, match the first identification information and the second identification information. The second identification information is s1 to sn, which are sorted in the table according to the serial number or in the order of traversing the functional modules. Correspondingly, the first identification information in the timing constraint information is x1 to xn, which are sorted in the same sorting method as the second identification information. Normally, if the I / O data in the timing constraint file are all set with timing constraints, then the identification information corresponds one by one. For example, the first identification information corresponding to the second identification information s1 is x1, s2 corresponds to x2, and sn corresponds to xn. If there is a certain xi in the table that does not correspond to the corresponding si, then it is considered that the match of this si fails, and the timing constraint information corresponding to this second identification information xi is missing in the timing constraint file.

[0098] Step b2: In response to any second identification information failing to match the first identification information, determine the I / O data corresponding to this second identification information that fails to match as the first target I / O data.

[0099] In response to any second identification information successfully matching the first identification information, it is considered that the timing constraint information has been set for the I / O data corresponding to this second identification information, and there is no need to correct it anymore.

[0100] Among them, the situation of matching failure may be that the corresponding first identification information cannot be found according to the second identification information corresponding to the I / O data, or the content of the first identification information is inconsistent with the content of the second identification information.

[0101] Step C: In response to the existence of the first target I / O data, determine the timing constraint information of the first target I / O data based on the rated clock cycle corresponding to the clock of the first target I / O data.

[0102] Step D: Obtain the target timing constraint file based on the timing constraint information of the first target I / O data.

[0103] In a specific implementation, after determining that the second identification information with a matching failure is the first target I / O data, set the timing constraint information for the first target I / O data to obtain the target timing constraint file.

[0104] Among them, the target timing constraint file can be generated based on the initial timing constraint file.

[0105] That is, after determining the first target I / O data, write the second identification information corresponding to the first target I / O data into the initial timing constraint file, and set the corresponding timing constraint information for it to obtain the target timing constraint file.

[0106] In addition, the target timing constraint file can also be a newly generated timing constraint file; after the target timing constraint file is generated, use the target timing constraint file and the initial timing constraint file as the timing constraint files input during the synthesis process to perform synthesis on the RTL.

[0107] When setting the timing constraint information for the first target I / O data, it can be that for each determined first target I / O data, set the corresponding timing constraint information for it; in addition, it can also be that after all the first target I / O data are determined, then set the timing constraint information uniformly.

[0108] For the case where all the first target I / O data are determined and then the timing constraint information is set uniformly, exemplarily, first write the second identification information with a matching failure into the target timing constraint file, and set its corresponding I / O timing constraint information to 0.

[0109] After all the first target I / O data are determined, traverse the first target I / O data with the timing constraint information of 0 from the target timing constraint file, and then for each traversed first target I / O data, set the timing constraint information for it.

[0110] Thus, it is possible to determine whether the corresponding I / O data is set with timing constraints according to the I / O timing constraint information corresponding to the second identification information, and uniformly perform timing constraints on the I / O data with the timing constraint information of 0.

[0111] In another embodiment, before determining the timing constraint information of the first target I / O data based on the nominal clock period of the clock corresponding to the first target I / O data in response to the presence of the first target I / O data, the clock corresponding to the first target I / O data and the nominal clock period are parsed from the RTL. When continuing to obtain the clock corresponding to the first target I / O data and the nominal clock period from the RTL, for example, any one of the following M1 or M2 methods can be used.

[0112] M1: Based on the determined second identification information of the first target I / O data, the clock corresponding to the first target I / O data and the nominal clock period are parsed from the RTL.

[0113] The clock period is the basic time unit in an integrated circuit, which can be expressed as the reciprocal of the clock oscillator frequency and is the most basic and smallest time unit in the integrated circuit. It is usually called the clock pulse or T cycle. Within one clock period, a certain functional module in the integrated circuit only completes one most basic operation.

[0114] Among them, the identification information of the clock and the clock period also belong to a part of the constraint information. In an integrated circuit, there may be at least one clock; each clock in the integrated circuit is used to control the timing of the I / O data of each functional module in the integrated circuit. The clock corresponding to the first target I / O data refers to the clock used to control the timing of the first target I / O data. The nominal clock period refers to the inherent clock period of the clock. The clock period corresponding to the first target I / O data may be less than the nominal clock period, may be greater than the nominal clock period, or may be equal to the nominal clock period.

[0115] Exemplarily, the determined second identification information of the first target I / O data includes x2 and x5. Then, according to the second identification information x2 and x5 of the first target I / O data, the clock identification and the nominal clock period corresponding to the second identification information x2 and x5 that match the first target I / O data are found from the RTL.

[0116] M2: Parse the RTL to obtain the clocks corresponding to the I / O data of each functional module in the integrated circuit and the nominal clock periods; based on the determined second identification information of the first target I / O data, screen the clocks corresponding to the first target I / O data and the nominal clock periods from the clocks corresponding to the I / O data of each functional module in the integrated circuit and the nominal clock periods.

[0117] Exemplarily, first determine the clocks and the rated clock cycles corresponding to all the second identification information x1 to xn from the RTL, then determine that the first target I / O data includes x2 and x5, and finally screen out the clocks and the rated clock cycles corresponding to x2 and x5 of the corresponding first target I / O data from the clocks and the rated clock cycles of x1 to xn determined from the RTL.

[0118] After obtaining the clocks and the rated clock cycles corresponding to the first target I / O data, the timing constraint information of the first target I / O data can be generated based on the rated clock cycle of the clock corresponding to the first target I / O data and a preset coefficient.

[0119] Among them, the preset coefficient is a numerical factor set by the designer according to the actual situation, and is used to perform a certain arithmetic operation with the rated clock cycle of the clock corresponding to the first target I / O data to obtain the constraint value of the clock constraint information. The method for determining the timing constraint information based on the rated clock cycle and the preset coefficient includes, but is not limited to: rated clock cycle * preset coefficient, rated clock cycle + preset coefficient, rated clock cycle - preset coefficient, etc., which are not limited here.

[0120] Exemplarily, the rated clock cycle corresponding to the first target I / O data s4 is 10 ns (nanoseconds), the preset coefficient is 0.4, and a multiplication operation is performed, then the constraint value of the first target I / O data is 4 ns.

[0121] The preset value can be set in advance by the designer according to the actual situation and stored in a certain fixed storage space. When responding to the generation of the timing constraint information of the first target I / O data, read the preset value from the fixed storage space and perform subsequent actions.

[0122] The process of setting the constraint value can be completed automatically. After determining the first target I / O data, the constraint value corresponding to the first target I / O data is automatically set by the program execution statement.

[0123] In another embodiment, when obtaining the target timing constraint file based on the timing constraint information of the first target I / O data, any one of the following methods M3 or M4 can be adopted:

[0124] M3: Write the timing constraint information of the first target I / O data into the initial timing constraint file to generate the target timing constraint file.

[0125] Exemplarily, after determining that the constraint values are set for the timing constraint information of the first target I / O data, that is, the constraint value is not 0, write the timing constraint information of the first target I / O data into the initial timing constraint file to generate the target timing constraint file, and perform synthesis on the generated target timing constraint file during synthesis.

[0126] M4: Write another timing constraint file different from the initial timing constraint file based on the timing constraint information of the first target I / O data to generate the target timing constraint file.

[0127] Exemplarily, after determining that the timing constraint information of the first target I / O data has all been set with constraint values, that is, the constraint values are not 0, generate a target timing constraint file different from the initial timing constraint file. During synthesis, synthesize the initial timing constraint file and the target timing constraint file different from the initial timing constraint file together.

[0128] In another embodiment, it is also possible to determine whether there is second target I / O data in the initial timing constraint file that is not included in the integrated circuit based on the second identification information and the initial timing constraint file; in response to the existence of the second target I / O data, delete the timing constraint information of the second target I / O data from the initial timing constraint file.

[0129] Specifically, the second target I / O data is, for example, the I / O data for which the identification information is written incorrectly when the designer configures the constraint information of the I / O data, that is, the I / O data included in the integrated circuit.

[0130] After determining the second target I / O data, deleting the timing constraint information of the second target I / O data from the initial timing constraint file in the initial timing constraint file can improve the maintainability of the timing constraint file.

[0131] Exemplarily, the second identification information is s1 to sn, and the first identification information is x1 to xn. When the I / O data in the timing constraint file is all set correctly, the first identification information and the second identification information are in one-to-one correspondence, that is, s1 corresponds to x1, s2 corresponds to x2, and sn corresponds to xn. If during the actual process, when configuring the timing constraint information for a certain I / O data, the first identification information si corresponding to a certain I / O data is written incorrectly as sj, at this time, determine the I / O data corresponding to the first identification information sj as the second target I / O data. Delete the timing constraint information corresponding to the second identification information si from the initial timing constraint file.

[0132] Following the above S102, the integrated circuit synthesis method provided by the present disclosure implementation further includes:

[0133] S103: Perform circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit.

[0134] In a specific implementation, if the target timing constraint file and the initial timing constraint file are two different files, circuit logic synthesis can be performed based on the target timing constraint file, the initial timing constraint file, and the RTL to obtain the gate-level circuit of the integrated circuit.

[0135] Among them, logic synthesis is one of the steps in the circuit layout generation process, which refers to the process of using tools to convert RTL code into a gate-level circuit. Exemplarily, the process of synthesizing a design starts from reading the RTL code, and through applying timing constraint relationships, a gate-level circuit file is mapped and generated; specifically, it can be divided into: translation, reading in the RTL-level description of the circuit, and translating the language description into corresponding functional modules and the topological structure between the functional modules. The result of this process is to generate the Boolean function expression of the circuit inside the synthesizer without any logic restructuring and optimization; optimization, according to the applied timing and area constraints, performing logic restructuring and optimization on the translation result according to a certain algorithm; mapping, according to the applied timing and area constraints, searching for eligible cells from the target process library to form the logic netlist of the actual circuit.

[0136] See Figure 2 As shown, the embodiments of the present disclosure also provide a flowchart for checking missing I / O constraints and supplementing constraints.

[0137] S201: Obtain the initial timing constraint file SDC before logic synthesis, which contains timing constraint information related to I / O.

[0138] S202: Prepare a timing constraint script, which can be named (extra.sdc). The script contains the check code for I / O constraint integrity and unified constraint, and these contents are common to all sub-modules in the integrated circuit.

[0139] Exemplarily, it is also possible not to prepare the extra.sdc file and directly write the check code in the initial timing constraint file, for example, it can be located after the I / O timing constraint information. Each time synthesis is performed, the check code needs to be written as the SDC content into the corresponding SDC file.

[0140] S203: Parse the RTL through the first parsing instruction included in the timing constraint script to obtain the timing constraint information corresponding to the I / O data of each sub-module of the integrated circuit.

[0141] S204: Parse the RTL through the second parsing instruction included in the timing constraint script to obtain the identification of the clock corresponding to each I / O and the nominal clock period.

[0142] Exemplarily, the identification of the clock and the clock period also belong to a part of the constraint information. There are multiple clocks in the chip, and different I / Os may correspond to different clocks, which is determined according to the actual requirements of the chip. Therefore, based on the RTL, it is necessary to artificially set the clock constraint information to inform the synthesis tool of the required constraint conditions.

[0143] S205: Determine whether timing constraints are set for each I / O through the judgment instruction included in the timing constraint script.

[0144] If timing constraints are artificially set, the constraint value corresponding to the timing constraint information is not 0. If it is found that the constraint values of the timing constraint information corresponding to the missing or wrongly written I / Os are all set to 0.

[0145] Exemplarily, first use the parsing instruction to parse the RTL code to find all the I / Os and their corresponding identifications in it. Secondly, compare them with the identifications corresponding to the I / O data in the initial timing constraint file SDC, and find out the missing or wrong I / O data, and set the constraint value corresponding to the timing constraint information to 0.

[0146] If timing constraints are set, that is, the constraint value corresponding to the I / O timing constraint information is not 0, then ignore this I / O, indicating that this I / O has been artificially set with timing constraints and does not need to be set again; if the constraint value corresponding to the timing constraint information of this I / O is 0, it means that the timing constraints of this I / O are not set, execute the preset statement and set the constraint value corresponding to the I / O timing constraint information according to the clock period corresponding to this I / O.

[0147] Exemplarily, a preset coefficient can be set, and the rated clock period obtained through step S204 is used to determine the clock period corresponding to the problematic I / O, and then the determined clock period is used as the constraint value of the timing constraint information corresponding to the problematic I / O and written into the target timing constraint file.

[0148] S206: Determine all I / Os through the judgment instruction included in the timing constraint script, and uniformly constrain all I / Os without set timing constraints.

[0149] S207: Supplement the I / O data corresponding to the set I / O timing constraint information into the initial SDC file to generate a complete SDC file (target timing constraint file), or alternatively, generate an SDC file (target timing constraint file) and perform synthesis together with the initial SDC file (initial timing constraint file).

[0150] Exemplarily, the initial SDC file needs to delete the ones with wrong names from the initial SDC file to prevent error warnings during synthesis and is also beneficial for later maintenance.

[0151] Those skilled in the art can understand that in the above method of the specific implementation manner, the writing order of each step does not mean a strict execution order and does not constitute any limitation to the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0152] Based on the same inventive concept, the embodiments of the present disclosure also provide an integrated circuit synthesis device corresponding to the integrated circuit synthesis method. Since the principle of solving problems by the device in the embodiments of the present disclosure is similar to the above integrated circuit synthesis method of the embodiments of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0153] Referring to Figure 3 As shown in the figure, it is a schematic diagram of an integrated circuit synthesis device provided by an embodiment of the present disclosure. The device includes: an acquisition module 301, a matching module 302, and a logic synthesis module 303; wherein,

[0154] The acquisition module 301 is configured to acquire an initial timing constraint file of the integrated circuit and the register transfer level circuit RTL of the integrated circuit; the initial timing constraint file includes: timing constraint information corresponding to input / output I / O data of functional modules in the integrated circuit.

[0155] The matching module 302 is configured to perform correction processing on the timing constraint information in the initial timing constraint file based on the RTL to obtain a target timing constraint file.

[0156] The logic synthesis module 303 is configured to perform circuit logic synthesis based on the target timing constraint file and the RTL to obtain a gate-level circuit of the integrated circuit.

[0157] In the embodiments of the present disclosure, before synthesizing the integrated circuit, the timing constraint information in the initial timing constraint file is corrected by using the RTL, so that the timing constraint information of the I / O with omissions or incorrect settings in the initial timing constraint file is corrected, and then the target timing constraint file is used to synthesize the RTL, reducing the situation of excessive synthesis iteration times caused by problems in I / O constraints, improving the synthesis efficiency of the integrated circuit, and reducing costs.

[0158] In an optional implementation manner, the timing constraint information includes: first identification information of the I / O data, a clock name for the clock corresponding to the I / O data, and a clock period corresponding to the I / O data; wherein, the clock corresponding to the I / O data is used to control the clock period of the corresponding I / O data.

[0159] In an alternative embodiment, the apparatus further includes a parsing module 304, and the parsing module 304 is further configured to: parse the RTL to obtain second identification information of I / O data of each functional module in the RTL integrated circuit; the matching module 302 is further configured to: based on the second identification information and the initial timing constraint file, determine whether there is first target I / O data for which timing constraints are not set in the I / O data; in response to the existence of the first target I / O data, determine the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data; and obtain the target timing constraint file based on the timing constraint information of the first target I / O data.

[0160] In an alternative embodiment, the matching module 302 is further configured to: match the second identification information and the first identification information; in response to any second identification information and the first identification information failing to match, determine the I / O data corresponding to the second identification information that fails to match as the first target I / O data.

[0161] In an alternative embodiment, the parsing module 304 is further configured to: based on the second identification information of the determined first target I / O data, parse the clock corresponding to the first target I / O data and the rated clock period from the RTL; or, parse the RTL to obtain the clocks corresponding to the I / O data of each functional module in the integrated circuit and the rated clock periods; and based on the second identification information of the determined first target I / O data, filter the clocks corresponding to the first target I / O data and the rated clock periods from the clocks corresponding to the I / O data of each functional module in the integrated circuit and the rated clock periods.

[0162] In an alternative embodiment, the matching module 302 is further configured to: generate the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data and a preset coefficient.

[0163] In an alternative embodiment, the matching module 302 is further configured to: write the timing constraint information of the first target I / O data into the initial timing constraint file to generate the target timing constraint file.

[0164] In an alternative embodiment, the matching module 302 is further configured to: write the timing constraint information of the target I / O data into another timing constraint file different from the initial timing constraint file to generate the target timing constraint file.

[0165] In an alternative embodiment, the logic synthesis module 303 is further configured to: perform circuit logic synthesis on the basis of the target timing constraint file, the initial timing constraint file, and the RTL to obtain the gate-level circuit of the integrated circuit.

[0166] In an alternative embodiment, the matching module 302 is further configured to: in response to the existence of the second target I / O data, delete the timing constraint information of the second target I / O data from the initial timing constraint file.

[0167] For the description of the processing flow of each module in the device and the interaction flow between the modules, reference may be made to the relevant descriptions in the above method embodiments, which will not be elaborated here.

[0168] The embodiments of the present disclosure further provide a computer device, as Figure 4 shown, which is a schematic structural diagram of the computer device provided by the embodiments of the present disclosure, including:

[0169] a processor 41 and a memory 42; the memory 42 stores machine-readable instructions executable by the processor 41, and the processor 41 is configured to execute the machine-readable instructions stored in the memory 42. When the machine-readable instructions are executed by the processor 41, the processor 41 performs the following steps:

[0170] Obtain an initial timing constraint file of an integrated circuit and the register transfer level circuit RTL of the integrated circuit; the initial timing constraint file includes: timing constraint information obtained by performing timing settings on the output or output I / O data of each functional module in the integrated circuit;

[0171] Based on the RTL, perform correction processing on the timing constraint information in the initial timing constraint file to obtain a target timing constraint file;

[0172] Perform circuit logic synthesis on the basis of the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit.

[0173] The above memory 42 includes an internal memory 421 and an external memory 422; here, the internal memory 421 is also called the main memory, which is used to temporarily store the operation data in the processor 41 and the data exchanged with the external memory 422 such as the hard disk. The processor 41 exchanges data with the external memory 422 through the internal memory 421.

[0174] The specific execution process of the above instructions may refer to the steps of the integrated circuit synthesis method described in the embodiments of the present disclosure, which will not be elaborated here.

[0175] Embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the integrated circuit synthesis method described in the above method embodiments. Wherein, the storage medium may be a volatile or non-volatile computer-readable storage medium.

[0176] Embodiments of the present disclosure also provide a computer program product, which carries program code. The instructions included in the program code can be used to execute the steps of the integrated circuit synthesis method described in the above method embodiments. For details, please refer to the above method embodiments and will not be elaborated here.

[0177] Wherein, the above computer program product can be specifically implemented in a manner of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0178] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here. In several embodiments provided by the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces. The indirect coupling or communication connection of the devices or units may be in an electrical, mechanical or other form.

[0179] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0180] In addition, in each embodiment of the present disclosure, the functional units can be integrated in one processing unit, or each unit exists physically alone, or two or more units are integrated in one unit.

[0181] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present disclosure. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0182] Finally, it should be noted that the above-mentioned embodiments are only specific implementation manners of the present disclosure, used to illustrate the technical solutions of the present disclosure, rather than limiting them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present disclosure can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes, or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An integrated method for an integrated circuit, characterized in that, Including: Obtaining an initial timing constraint file of an integrated circuit and a register transfer level (RTL) circuit of the integrated circuit; The initial timing constraint file includes: timing constraint information obtained by performing timing settings on input / output (I / O) data of each functional module in the integrated circuit; Based on the RTL, performing calibration processing on the timing constraint information in the initial timing constraint file to obtain a target timing constraint file; Based on the target timing constraint file and the RTL, performing circuit logic synthesis to obtain a gate-level circuit of the integrated circuit; The performing calibration processing on the timing constraint information in the initial timing constraint file based on the RTL to obtain a target timing constraint file includes: Parsing the RTL to obtain second identification information of I / O data of each functional module in the RTL integrated circuit; Based on the second identification information and the initial timing constraint file, determining whether there is first target I / O data for which timing constraints are not set in the I / O data; In response to the existence of the first target I / O data, determining timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data; Based on the timing constraint information of the first target I / O data, obtaining the target timing constraint file.

2. The integrated method according to claim 1, wherein The timing constraint information includes: first identification information of the I / O data, a clock name for the clock corresponding to the I / O data, and a clock period corresponding to the I / O data; Wherein, the clock corresponding to the I / O data is used to control the clock period of the corresponding I / O data.

3. The integrated method according to claim 1, wherein The determining whether there is first target I / O data for which timing constraints are not set in the I / O data based on the second identification information and the initial timing constraint file includes: Matching the second identification information and the first identification information of the I / O data; In response to any second identification information and the first identification information failing to match, determining the I / O data corresponding to the second identification information with the matching failure as the first target I / O data.

4. The integrated method according to claim 1 or 3, characterized in that Before the determining the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data in response to the existence of the first target I / O data, it further includes: Based on the determined second identification information of the first target I / O data, parsing the clock corresponding to the first target I / O data and the rated clock period from the RTL; Alternatively, parsing the RTL to obtain the clocks corresponding to the I / O data of each functional module in the integrated circuit and the rated clock periods; based on the determined second identification information of the first target I / O data, screening the clocks corresponding to the first target I / O data and the rated clock periods from the clocks corresponding to the I / O data of each functional module in the integrated circuit and the rated clock periods.

5. The integrated method according to claim 1 or 3, characterized in that The determining the timing constraint information of the first target I / O data based on the rated clock period of the clock corresponding to the first target I / O data includes: Generate the timing constraint information for the first target I / O data based on the nominal clock period corresponding to the clock of the first target I / O data and a preset coefficient.

6. The integrated method according to claim 1 or 3, characterized in that, Obtaining the target timing constraint file based on the timing constraint information for the first target I / O data includes: Writing the timing constraint information for the first target I / O data into the initial timing constraint file to generate the target timing constraint file; and / or Based on the timing constraint information for the first target I / O data, writing another timing constraint file different from the initial timing constraint file to generate the target timing constraint file.

7. The integrated method according to claim 6, characterized in that, Performing circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit includes: Performing circuit logic synthesis based on the target timing constraint file, the initial timing constraint file, and the RTL to obtain the gate-level circuit of the integrated circuit.

8. The integrated method according to claim 6, characterized in that, The method further includes: determining whether there is second target I / O data in the initial timing constraint file that is not included in the integrated circuit based on the second identification information and the initial timing constraint file; In response to the existence of the second target I / O data, deleting the timing constraint information for the second target I / O data from the initial timing constraint file.

9. An integrated device for an integrated circuit, characterized in that, The apparatus includes: An acquisition module, configured to acquire an initial timing constraint file of an integrated circuit and the register transfer level circuit RTL of the integrated circuit; the initial timing constraint file includes: timing constraint information corresponding to the I / O data of the functional modules in the integrated circuit; A matching module, configured to perform correction processing on the timing constraint information in the initial timing constraint file based on the RTL to obtain a target timing constraint file; A logic synthesis module, configured to perform circuit logic synthesis based on the target timing constraint file and the RTL to obtain the gate-level circuit of the integrated circuit; When the matching module is obtaining the target timing constraint file by performing correction processing on the timing constraint information in the initial timing constraint file based on the RTL, it is configured to: Parse the RTL to obtain the second identification information of the I / O data of each functional module in the RTL integrated circuit; Based on the second identification information and the initial timing constraint file, determine whether there is first target I / O data without set timing constraints in the I / O data; In response to the existence of the first target I / O data, determine the timing constraint information for the first target I / O data based on the nominal clock period corresponding to the clock of the first target I / O data; Obtain the target timing constraint file based on the timing constraint information for the first target I / O data.

10. A computer device, characterized in that, Includes: A processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device runs, the processor communicates with the memory through the bus. When the machine-readable instructions are executed by the processor, the steps of the integrated circuit synthesis method according to any one of claims 1 to 8 are executed.

11. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, it executes the steps of the integrated circuit synthesis method according to any one of claims 1 to 8.

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