Power management circuit, system-on-chip device, and power management method

Abstract

The present application provides a power management circuit, a system-on-chip device, and a power management method. A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal based on a status signal and a first power signal from a first power source. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal based on the first power management signal and the status signal.

Description

Technical Field

[0001] The present application relates to the field of circuits, and more particularly to a power management circuit, a system-on-chip device, and a power management method. Background Art

[0002] Dual-rail devices, such as dual-rail static random access memory (SRAM), have different logic circuits operating at different supply voltages. For example, a portion of the SRAM (called the memory peripheral logic) can operate at a lower supply voltage than some of the memory array, another portion of the SRAM (which operates at a higher supply voltage), to reduce dynamic power consumption. This technique allows for lowering the required active power while maintaining adequate performance. However, dual-rail designs suffer from significant cross-domain leakage when the two power supplies are switched on or off. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present application, a circuit is provided, comprising: a power detector configured to output a first power management signal based on a status signal and a first power supply signal from a first power supply, wherein the circuit is configured to operate in different modes in response to the status signal; and a logic circuit configured to output a second power management signal based on the first power management signal and the status signal.

[0004] According to another aspect of an embodiment of the present application, a system-on-chip device is provided, comprising: a first power supply and a second power supply, wherein in a sleep mode, at least one of the first power supply and the second power supply is disabled in response to a status signal; a circuit configured to work with the first power supply and the second power supply; and a power management circuit configured to send a first power management signal to control the circuit, the power management circuit comprising: a power detector configured to generate a first power management signal based on the status signal and a first power signal associated with the first power supply.

[0005] According to another aspect of an embodiment of the present application, a method for power management is provided, comprising: detecting a status signal for indicating a sleep mode of a circuit, the circuit comprising a first domain corresponding to a first power supply and a second domain corresponding to a second power supply, wherein in the sleep mode, one of the first power supply or the second power supply is disabled; generating a first power management signal in response to a first power supply signal and a status signal associated with the first power supply; and outputting an isolation signal based on the first power management signal and the status signal, the isolation signal being used to control isolation between the first domain and the second domain of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a block diagram illustrating a system on a chip (SOC) system according to some embodiments of the present disclosure.

[0008] Figure 2 is a diagram illustrating generation of an isolated signal according to some embodiments of the present disclosure.

[0009] Figure 3 is a diagram illustrating a power detector according to some embodiments of the present disclosure.

[0010] Figure 4 is a diagram showing a first design of a power management circuit according to some embodiments of the disclosure.

[0011] Figure 5 is a diagram showing a second design of a power management circuit in accordance with some embodiments of the present disclosure.

[0012] Figure 6 is a diagram showing a first detailed design of a power detector according to some embodiments of the present disclosure.

[0013] Figure 7 is a diagram showing a second detailed design of a power detector according to some embodiments of the present disclosure.

[0014] Figure 8 is a diagram showing a third detailed design of a power detector according to some embodiments of the present disclosure.

[0015] Figure 9 is a timing diagram illustrating waveforms of a power supply voltage, a power management signal of an SOC system, and a leakage current of a circuit macro according to some embodiments of the present disclosure.

[0016] Figure 10 is a diagram showing a fourth detailed design of a power detector according to some embodiments of the present disclosure.

[0017] Figure 11 is a diagram showing a fifth detailed design of a power detector according to some embodiments of the present disclosure.

[0018] Figure 12 is a diagram showing a sixth detailed design of a power detector according to some embodiments of the present disclosure.

[0019] Figure 13is a diagram showing a seventh detailed design of a power detector according to some embodiments of the present disclosure.

[0020] Figure 14 is a flow chart of an exemplary method of power management for a dual rail device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the description below may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0022] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any term discussed herein) is illustrative only and does not in any way limit the scope and meaning of the present disclosure or any illustrative term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0023] Although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish elements from each other. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0024] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0025] In this document, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0026] Embodiments of the present disclosure are described herein in the context of an exemplary dual-rail device. It will be appreciated that the present disclosure is not limited to the specific circuits and systems illustratively shown and described herein. In this manner, embodiments of the present disclosure provide a power management circuit that can be beneficially used with a variety of memory arrangements and types, such as random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), content addressable memory (CAM), flash memory, register files, and the like. Furthermore, modifications to the embodiments shown within the scope of the present disclosure will be apparent to those skilled in the art in view of the teachings herein.

[0027] In some embodiments, the dual rail device may be an embedded SRAM device, which is popular in high-speed communications, image processing, and system-on-chip (SOC) applications. Figure 1 1 is a block diagram illustrating a system on a chip (SOC) system 100 according to some embodiments of the present disclosure. In some embodiments, the SOC system 100 may be located in a computer or other electronic system. Figure 1 As shown, SOC system 100 includes a circuit macro 110 and a SOC power management circuit (SOCPM) 120 coupled to circuit macro 110. Circuit macro 110 has a circuit macro power management ("macro PM") circuit 112. In some embodiments, circuit macro 110 may be an SRAM having a plurality of memory arrays (typically two-dimensional memory bit cells) configured to store corresponding logic states, i.e., logic high (logic "1") or logic low (logic "0"). Memory bit cells are often arranged in one or more parallel columns.

[0028] The SOC power management circuit 120 is configured to control the power behavior of the circuit macro 110 via one or more power management control signals, such as power on, power off, power state selection, etc. For example, the SOC power management circuit 120 may send one or more power management signals to the circuit macro power management circuit 112 in the circuit macro 110 so that the circuit macro power management circuit 112 may control the circuits in the circuit macro 110 accordingly to achieve appropriate power management.

[0029] The circuit macro 110 on the chip can operate using two independently controlled power supplies 130 and 140. For example, the circuit macro 110 can include a first circuit operating in a first power domain (e.g., a VDDM power domain) and a second circuit operating in a second power domain (e.g., a VDD power domain). In some embodiments, the first circuit is referred to as a VDDM domain circuit, and the second circuit is referred to as a VDD domain circuit.

[0030] In some embodiments, the VDDM domain circuit may be an array of SRAM cells operating at a power supply voltage VDDM, and the VDD domain circuit may be, for example, a memory peripheral logic circuit operating at a power supply voltage VDD lower than the power supply voltage VDDM. The VDD domain circuit and the VDDM domain circuit are interfaced with each other. In some embodiments, the VDDM domain circuit is connected to the VDDM power supply via a corresponding switch controlled by a control signal. The VDD domain circuit is connected to the VDD power supply via another corresponding switch controlled by another control signal. For example, the header switch may be a P-channel metal oxide semiconductor (PMOS) transistor switch. When the header control signal is logic low, the VDDM domain circuit and the VDD domain circuit are coupled to the power supplies VDDM and VDD, respectively. In some other embodiments, different types of switches may be used, such as N-channel metal oxide semiconductor (NMOS) transistor switches. Therefore, when the header control signal is logic high, the VDDM domain circuit and the VDD domain circuit are coupled to the power supplies VDDM and VDD, respectively.

[0031] In some embodiments, circuit macro 110 is structured such that the memory array and wordline driver circuits operate substantially at voltage VDDM, while the data path and control circuitry are configured to operate at voltages VDDM and VDD. Specifically, a portion of the data path and a portion of the control circuitry are configured to operate at voltage VDDM, while the remainder of the data path and the remainder of the control circuitry are configured to operate at a lower voltage, VDD. Therefore, the data path and control circuitry are cross-domain circuits, and undesirable interface leakage currents occur in circuit macro 110 due to DC leakage paths during power-up or during sleep mode. During power-up, the two power supplies (e.g., voltage VDDM and voltage VDD) ramp at different rates. During sleep mode operation, one of the power supplies (e.g., voltage VDDM) floats, resulting in interface leakage currents. To reduce interface leakage currents in cross-domain circuitry in circuit macro 110, SOC power management circuit 120 needs to output one or more power management signals, such as isolation signal ISO, to isolate the interface circuitry between the VDDM power domain and the VDD power domain.

[0032] Figure 2 FIG is a diagram illustrating the generation of an isolation signal ISO according to some embodiments of the present disclosure. Figure 2In the embodiment, the power management circuit 200 is Figure 1 The SOC power management circuit 120 is a part of the SOC system 100 and is configured to generate an isolation signal ISO required for power management of the SOC system 100. Figure 2 As shown, the power management circuit 200 is configured to generate and output an isolation signal ISO according to a state signal (e.g., a state signal SD) and a first power signal of a first power supply (e.g., a power supply voltage VDDM). In some embodiments, when the power management circuit 200 outputs the isolation signal ISO having a logic high value, the isolation of the interface circuit can be enabled to reduce the power supply voltage. Figure 1 Leakage current is shown as a result of DC leakage paths across the circuit domains in the circuit macro 110. In some embodiments, the power management circuit 200 includes a power detector 210 and a logic circuit 220 electrically connected to the power detector 210, which will be discussed in more detail below.

[0033] Figure 3 is a diagram showing some embodiments of the present disclosure. Figure 2 The power detector 210 generates a power management signal PWR_RDYB. Figure 3 As shown, power detector 210 is configured to generate and output a power management signal PWR_RDYB based on a status signal (e.g., status signal SD) and a first power supply signal of a first power supply (e.g., power supply voltage VDDM). The power management signal PWR_RDYB can be used to confirm whether the power supply voltage and status signal SD are at corresponding appropriate levels. In some embodiments, power management signal PWR_RDYB is a power-good negation (bar) signal, which is the inverse of the power-good signal. The power-good signal indicates that the power supply voltages VDD, VDDM, and status signal SD are ready to perform circuit operations in circuit macro 110, such as memory access operations. Alternatively, when power management signal PWR_RDYB is logic high, the power supply voltages and status signal SD are not ready to perform circuit operations in circuit macro 110, such as memory access operations. When power management signal PWR_RDYB is logic low, the power supply voltages and status signal SD are ready to perform circuit operations in circuit macro 110.

[0034] Figure 4 is a diagram showing some embodiments of the present disclosure Figure 2 Schematic diagram of a first design of a power management circuit 200. Figure 4 As shown, the power management circuit 200 includes Figure 31 . The power detector 210 and logic circuit 220 are shown. Logic circuit 220 is coupled to an output terminal of power detector 210 and is configured to receive a power management signal PWR_RDYB and output an isolation signal ISO as a second power management signal based on the received power management signal PWR_RDYB and a status signal SD. As described above, when isolation signal ISO having a logic high value is output from power management circuit 200 to circuit macro 110, isolation of the interface circuit can be enabled to reduce leakage current generated by a DC leakage path of the cross-domain circuit in circuit macro 110.

[0035] exist Figure 4 In an embodiment, logic circuit 220 includes an OR gate logic circuit. A first input terminal of logic circuit 220 is coupled to power detector 210 and configured to receive power management signal PWR_RDYB. A second input terminal of logic circuit 220 is coupled to a corresponding pin and configured to receive status signal SD. An output terminal of logic circuit 220 is configured to output isolation signal ISO.

[0036] Therefore, the power management circuit 200 is configured to output the isolation signal ISO having a logic high value to activate isolation of the interface circuit in response to the state signal SD being logic high or the power management signal PWR_RDYB being logic high.

[0037] Figure 5 is a diagram showing some embodiments of the present disclosure Figure 2 2. A second design of a power management circuit 200 is shown. Figure 4 Compared with the embodiment, Figure 5 The logic circuit 220 in FIG. 2 is coupled to the output terminal of the power detector 210 and is configured to output the isolation signal ISO according to the power management signal PWR_RDY and the state signal SD. Figure 4 In an embodiment, when the power management circuit 200 outputs the isolation signal ISO having a logic high value to the circuit macro 110, isolation of the interface circuit between the VDDM power domain and the VDD power domain in the circuit macro 110 may be enabled to reduce leakage current generated by a DC leakage path of the cross-domain circuit in the circuit macro 110.

[0038] Similar to Figure 3 and Figure 4 The power detector 210, Figure 5 The power detector 210 in the embodiment is also configured to generate and output a power management signal PWR_RDY according to the state signal (e.g., the state signal SD) and the power signal of the first power supply (e.g., the power supply voltage VDDM). The power management signal PWR_RDY is also used to confirm whether the power supply voltage and the state signal SD are at corresponding appropriate levels. Figure 3 and Figure 4 The power management signal PWR_RDYB output by the power detector 210 is compared with the Figure 5 The power management signal PWR_RDY output by the power detector 210 in is a power ready signal. When the power management signal PWR_RDY is logic high, the power supply voltage and the state signal SD are ready to perform circuit operations. When the power management signal PWR_RDY is logic low, the power supply voltage and the state signal SD are not ready to perform circuit operations. Alternatively, the logic values ​​of the power management signal PWR_RDY and the power management signal PWR_RDYB are opposite. In some embodiments, a NOT gate logic circuit can be used to receive the power management signal PWR_RDYB and output a corresponding power management signal PWR_RDY with an opposite logic value, but the present disclosure is not limited thereto. Various circuits can be applied to implement the power management signal PWR_RDY based on the state signal (e.g., the state signal SD) and the power supply signal of the first power supply (e.g., the power supply voltage VDDM).

[0039] exist Figure 5 In the embodiment of FIG. 5 , the logic circuit 220 includes a NOT gate logic circuit 522 and a NAND gate logic circuit 524 coupled to the NOT gate logic circuit 522. The NOT gate logic circuit 522 is configured to receive a state signal (e.g., a state signal SD) and output a control signal SD_B opposite to the state signal.

[0040] A first input terminal of the NAND gate logic circuit 524 is coupled to the power detector 210 and is configured to receive the power management signal PWR_RDY. A second input terminal of the NAND gate logic circuit 524 is coupled to the output terminal of the NOT gate logic circuit 522 and is configured to receive the control signal SD_B. An output terminal of the NAND gate logic circuit 524 is configured to output the isolation signal ISO.

[0041] Therefore, when the state signal SD is logic high, the output signal of the NOT gate logic circuit 522 (e.g., the control signal SD_B) is logic low, which causes the NAND gate logic circuit 524 to output the isolation signal ISO at a logic high value regardless of the value of the power management signal PWR_RDY or the value of the power supply signal (e.g., the power supply voltages VDDM, VDD).

[0042] When the state signal SD is logic low, the output signal (eg, control signal SD_B) of the NOT gate logic circuit 522 is logic high. The NAND gate logic circuit 524 outputs the isolation signal ISO in response to the logic value of the power management signal PWR_RDY.

[0043] If the power management signal PWR_RDY is logic low, the NAND gate logic circuit 524 outputs the isolation signal ISO at logic high, thereby enabling isolation of the interface circuit and reducing cross-domain leakage current. If the power management signal PWR_RDY is also logic high, indicating normal operation, the NAND gate logic circuit 524 outputs the isolation signal ISO at logic low, thereby not enabling isolation.

[0044] Figure 6 is a diagram showing some embodiments of the present disclosure Figure 3 FIG. 2 is a diagram of a detailed design of a power detector 210. In some embodiments, the power detector 210 can be implemented based on the design described herein. Figure 6 As shown, in some embodiments, the power detector 210 includes a comparator circuit 610 , an inverter circuit 620 , and an NMOS transistor 630 .

[0045] The comparator circuit 610 is configured to detect a first power supply signal (e.g., VDDM) and a second power supply signal (e.g., VDD) to output a power management signal PWR_RDYB. The inverter circuit 620 is configured to receive a state signal SD from an input terminal and output the opposite logical value of the state signal SD from an output terminal. An NMOS transistor 630 is coupled between the comparator circuit 610 and a power ground reference, and a control terminal (e.g., gate terminal) of the NMOS transistor 630 is coupled to the output terminal of the inverter circuit 620. Therefore, the NMOS transistor 630 is configured to selectively connect or disconnect the comparator circuit 610 from the power ground terminal based on the state signal SD.

[0046] In other words, the power detector 210 is gated by the state signal SD. Therefore, leakage current due to a floating power supply signal (eg, VDDM) during the sleep phase and transient current occurring during the power-up or power-down phase can be reduced.

[0047] Figure 7 is a diagram showing some embodiments of the present disclosure Figure 3 2. In some embodiments, the power detector 210 can be implemented based on the designs described herein. Figure 7As shown, in some embodiments, the comparator circuit 710 can be or include a Schmitt trigger circuit formed by transistors 712, 714, 716, 718, and 719. A Schmitt trigger circuit is an active circuit that converts an analog input signal (here, the monitored power supply voltage VDDM) into a digital output signal. The circuit maintains its value until the input changes sufficiently to trigger the change. In some embodiments, an inverting Schmitt trigger can be used so that when the input is above a selected threshold, the output is low. When the input is below the selected threshold, the output is high, and when the input is between these two levels, the output maintains its value.

[0048] exist Figure 7 In FIG. 6 , VDDM comparator circuit 710 is implemented as an inverting Schmitt trigger. Comparator circuit 710 includes a transistor stack coupled between VDD and NMOS transistor 630. The transistor stack includes an NMOS transistor 712 and PMOS transistors 714 and 716. The gate terminals of transistors 712, 714, and 716 are coupled to a monitored power supply voltage, which in some embodiments is power supply voltage VDDM. A PMOS transistor 718 is coupled to node 711 between PMOS transistors 714 and 716. The other source / drain terminal of PMOS transistor 718 is coupled to the source / drain terminals of an NMOS transistor 719, whose gate terminal is closely tied to power supply voltage VDD. It should be understood that the power supply voltage "VDD" connected to the gate terminal of NMOS transistor 719 and the "VDD" connected to the source / drain terminals of PMOS transistor 716 have the same logical high value specified by the VDD domain, but do not necessarily originate from the same VDD branch and, therefore, can rise / fall together or independently of each other. The control signal VDDM_on_b is provided at a node 713 , which is located between the NMOS transistor 712 and the PMOS transistor 714 and is associated with the gate terminal of the PMOS transistor 718 .

[0049] When state signal SD is logic low, the other source / drain terminal of NMOS transistor 712 is coupled to power supply ground via NMOS transistor 630, based on the operation of inverter circuit 620 and NMOS transistor 630. Therefore, through circuit operation, when power supply voltage VDD is at its appropriate level and power supply voltage VDDM is not connected, control signal VDDM_on_b is logic high. When power supply voltage VDDM reaches a rising threshold level, control signal VDDM_on_b accordingly transitions to logic low. Furthermore, the Schmitt trigger circuit can provide a rising trigger point that is different from the falling trigger point, and specifically, the rising trigger point is higher than the falling trigger point. That is, the rising trigger point can be specifically set by the inverter stack including NMOS transistor 712, PMOS transistor 714, and PMOS transistor 716. This trigger point is determined by the number of NMOS and PMOS transistors in the stack and their drive strengths, and can be customized accordingly. Other transistors, particularly PMOS transistor 718 and NMOS transistor 719, serve to weaken the drive to PMOS transistors 714 and 716. This lowers the falling trigger point, making it more difficult for control signal VDDM_on_b to switch from low to high. Specifically, when the power supply voltage VDDM drops to the threshold voltage, PMOS transistor 716 turns on first, but PMOS transistor 714 remains off because PMOS transistor 718 and NMOS transistor 719 are on and the voltage at node 711 is at ground. At this point, PMOS transistor 716 and PMOS transistor 718 form a potential divider circuit. Therefore, the voltage at node 711 (e.g., the source terminal of PMOS transistor 714) increases as the power supply voltage VDDM (e.g., the gate terminal of PMOS transistor 714) decreases until PMOS transistor 714 turns on, at which point the falling trigger point is reached. When both PMOS transistors 714 and 716 are on, control signal VDDM_on_b switches from low to high, and PMOS transistor 718 becomes off. In some embodiments, PMOS transistor 718 is referred to as a feedback transistor. Since the impedance of PMOS transistor 716 and PMOS transistor 718 depends on their sizes, the falling trigger point can be properly controlled and lowered to a desired voltage level by selecting the size of PMOS transistor 718 in the Schmitt trigger circuit.

[0050] Comparator circuit 710 effectively reduces leakage current when VDDM rises and falls. In particular, because comparator circuit 710 is a Schmitt trigger circuit, control signal VDDM_on_b (e.g., the output of the Schmitt trigger circuit) remains in its current state until the input rises above a rising trigger point or falls below a falling trigger point. Therefore, when the power supply voltage VDDM includes ripple (e.g., power bounce) during normal operation, comparator circuit 710 avoids leakage current that may be caused by disconnecting power supply VDD from the VDD domain in response to unintended switching of control signal VDDM_on_b.

[0051] The PMOS transistor 720 has one source / drain terminal closely coupled to the power supply voltage VDD, another source / drain terminal coupled to the node 713 , and a gate terminal coupled to the gate terminal of the NMOS transistor 630 .

[0052] When the state signal SD is logic high, the NMOS transistor 630 is turned off, and the other source / drain terminal of the NMOS transistor 712 is disconnected from the power supply ground, according to the operation of the inverter circuit 620 and the NMOS transistor 630. In addition, the PMOS transistor 720 is turned on and pulls up the control signal VDDM_on_b to logic high. Therefore, when the state signal SD is logic high, the power management signal PWR_RDYB is also logic high. In some embodiments, the buffer logic circuit 730 is coupled to the output terminal of the comparator circuit 710 (e.g., node 713) and is configured to output the power management signal PWR_RDYB.

[0053] By operating the above circuit, Figure 7 The power detector 210 may be configured to output the power management signal PWR_RDYB having a logic high value when the state signal SD is logic high or when the monitored power supply voltage VDDM is not turned on.

[0054] Figure 8 is a diagram showing some embodiments of the present disclosure Figure 3 FIG. 2 is an illustration of a third detailed design of a power detector 210. In some embodiments, the power detector 210 can be implemented based on the designs described herein. Figure 8 As shown, in some embodiments, the power detector 210 can implement a comparator circuit by using an inverter circuit 810. The inverter circuit 810 also converts an analog input signal (e.g., the monitored power supply voltage VDDM) into a digital output signal. When the input is above a threshold, the output is low. When the input is below the threshold, the output is high.

[0055] Inverter circuit 810 includes a transistor stack coupled between VDD and NMOS transistor 630. The transistor stack includes a first NMOS transistor 812 and a first PMOS transistor 814. The gate terminals of transistors 812 and 814 are coupled to a monitored supply voltage, which in this embodiment is supply voltage VDDM. A control signal VDDM_on_ is provided at node 816, which is located between NMOS transistor 812 and PMOS transistor 814.

[0056] When state signal SD is logic low, the other source / drain terminal of NMOS transistor 812 is coupled to the power supply ground via NMOS transistor 630, according to the operation of inverter circuit 620 and NMOS transistor 630. Therefore, through circuit operation, when power supply voltage VDD is at its proper level and power supply voltage VDDM is not turned on, control signal VDDM_on_b is logic high. When power supply voltage VDDM reaches a rising threshold level, control signal VDDM_on_b accordingly transitions to logic low.

[0057] When the state signal SD is at a logic high level, the NMOS transistor 630 is turned off according to the operation of the inverter circuit 620 and the NMOS transistor 630, and the other source / drain terminal of the NMOS transistor 812 is disconnected from the power ground. Figure 7 In the embodiment of FIG. 5 , the PMOS transistor 720 is turned on and pulls up the control signal VDDM_on_b to logic high. Therefore, when the state signal SD is logic high, the power management signal PWR_RDYB is also logic high. Figure 8 Zhongyu Figure 7 Components that are the same as or similar to those depicted in are given the same reference numerals, and detailed descriptions thereof are omitted.

[0058] In some other embodiments, the power detector 210 may also be implemented by other comparator circuits, such as various inverter circuits, comparator circuits, or Schmitt trigger comparator circuits. Figure 7 and Figure 8 The circuits shown in FIG. 5 are examples only and are not intended to limit the present disclosure.

[0059] Figure 9 is a diagram showing the power supply voltages VDDM, VDD, Figure 1 The timing diagram 900 of the waveform of the state signal SD and the leakage current of the circuit macro 110 in the SOC system 100 is shown. In particular, Figure 9 Shown with Figure 4 or Figure 5 The time domain of the SOC system 100 of the power management circuit 200 includes Figure 6-8 The power detector 210 is shown in FIG.

[0060] Now let’s discuss the timing of the rise and fall of the power supply voltages VDDM and VDD. Figure 9 As shown, it should be understood that the power supply voltages VDDM and VDD can be powered on or off at different times and independently of each other. The circuit macro 110 is configured to operate in different modes (e.g., normal mode, shutdown mode, or sleep mode) in response to a state signal SD. The state signal SD is a "shutdown" state signal for indicating the sleep mode (or power saving mode) of the circuit. For example, when the circuit macro 110 is in normal mode, in response to a logic high value of the state signal SD, the circuit macro 110 can be switched to sleep mode, and one or more power supply voltages VDDM and VDD can be shut down accordingly to reduce power consumption. Alternatively, in sleep mode, the power supply voltages VDDM and VDD can be disabled in response to the state signal SD. Figure 1 One or more of the power supplies 130 and 140 for providing the power supply voltages VDDM and VDD. In some embodiments, in a sleep mode or a power saving mode, one of the power supplies can be floated to reduce leakage of the SOC system.

[0061] like Figure 9 As shown, during the power-on phase P1 of the SOC system 100 , due to circuit design limitations or design preferences, the supply voltages VDDM, VDD and the SOC state signal SD may not be turned on, and these signals ramp up toward their respective target or steady-state values ​​simultaneously.

[0062] During the power-on phase P1, during the period P11, when the power supply voltage VDD is already at its proper level, the SOC state signal SD is not turned on. However, since isolation between the VDDM domain circuit and the VDD domain circuit is performed based on the logic low value of the power supply voltage VDDM (which results in a logic high value of the power management signal PWR_RDYB and a logic high value of the isolation signal ISO), the asynchronous signal does not cause a large, undesirable interface leakage current between the VDDM domain circuit and the VDD domain circuit. During the period P12 following the period P11, since isolation is performed based on the logic high value of the SOC state signal SD (which also results in a logic high value of the isolation signal ISO), leakage current is also avoided. Therefore, as Figure 9 As shown, using a modified power management design that utilizes a power detector 210 gated by a status signal SD, undesirable transient currents occurring during a power-up or power-down phase (eg, phase P1 ) can be reduced or avoided.

[0063] In the first normal phase P2, both power supply voltages VDD and VDDM are at appropriate levels. The SOC state signal SD is off. Therefore, isolation is not performed. Under normal operation, there is a standby leakage current, but it is not significant.

[0064] After the first normal phase P2, when the SOC state signal SD is turned on to a logic high value, the SOC system 100 enters the sleep phase P3. During the sleep phase P3, one or more power supply voltages VDD and VDDM may also be powered down to reduce leakage current. For example, the power supply voltage VDDM may be disabled and floated. If isolation is not performed, the cross-domain circuits in the circuit macro 110 will have DC leakage paths, resulting in undesirable interface leakage current. Figure 9 As shown, isolation is performed based on the logic high value of the SOC state signal SD in the sleep phase P3. By using the modified power management design of the power detector 210 gated by the state signal SD, the interface leakage current between the VDDM domain circuit and the VDD domain circuit due to the floating power supply voltage VDDM during the sleep phase P3 can be further reduced.

[0065] In some other embodiments, the power detector 210 may be modified by employing a different type of switch (eg, a PMOS transistor switch) to replace the NMOS transistor 630 to selectively connect or disconnect the comparator circuit to the corresponding power reference node.

[0066] Figure 10 is a diagram showing a fourth detailed design of a power detector 210 according to some embodiments of the present disclosure. In some embodiments, the power detector 210 can be implemented based on the design 210 described herein. Figure 10 As shown, in some embodiments, the power detector 210 includes a comparator circuit 1010 and a PMOS transistor 1020 .

[0067] and Figure 6 The power detector 210 in the Figure 10 In the power detector 210 in FIG. 1 , the PMOS transistor 1020 is coupled between the comparator circuit 1010 and the second power supply (e.g., VDD), and the control terminal (e.g., gate terminal) of the PMOS transistor 1020 is coupled to a corresponding pin to receive the state signal SD. Therefore, the PMOS transistor 1020 can be configured to selectively connect or disconnect the comparator circuit 1010 from the second power supply (e.g., VDD) according to the state signal SD. Figure 6 The power detector 210 is also gated by the state signal SD. Therefore, the leakage current generated by the floating power supply signal (eg, VDDM) during the sleep phase and the transient current occurring during the power-on or power-off phase can be reduced.

[0068] Figure 11is a diagram showing a fifth detailed design of a power detector 210 according to some embodiments of the present disclosure. In some embodiments, the power detector 210 can be implemented based on the designs described herein. Figure 11 As shown, in some embodiments, VDDM comparator circuit 1110 may be or include a Schmitt trigger circuit formed by transistors 1112, 1114, 1116, 1118, and 1119. Comparator circuit 1110 includes a transistor stack coupled between power supply ground and PMOS transistor 1020. The transistor stack includes a first NMOS transistor 1112, a first PMOS transistor 1114, and a second PMOS transistor 1116. The gate terminals of transistors 1112, 1114, and 1116 are coupled to the monitored power supply voltage VDDM. PMOS transistor 1118 is coupled to node 1111 between PMOS transistors 1114 and 1116. The other source / drain terminal of PMOS transistor 1118 is coupled to the source / drain terminal of PMOS transistor 1119, whose gate terminal is closely tied to power supply voltage VDD. The control signal VDDM_on_b is provided at a node 1113 , which is located between the NMOS transistor 1112 and the PMOS transistor 1114 and is associated with the gate terminal of the PMOS transistor 1118 .

[0069] When the state signal SD is logic low, the other source / drain terminal of the PMOS transistor 1116 is coupled to the power supply voltage VDD via the PMOS transistor 1020 according to the operation of the PMOS transistor 1020. Therefore, through circuit operation, when the power supply voltage VDD is at its proper level and the power supply voltage VDDM is not turned on, the control signal VDDM_on_b is logic high. When the power supply voltage VDDM reaches the rising threshold level, the control signal VDDM_on_b accordingly transitions to logic low.

[0070] The NMOS transistor 1120 has one source / drain terminal coupled to the node 1113, another source / drain terminal coupled to the power supply ground, and a gate terminal coupled to the gate terminal of the PMOS transistor 1020. Therefore, the NMOS transistor 1120 can be configured to selectively connect or disconnect the output terminal of the comparator circuit 1110 from the power supply ground according to the state signal SD.

[0071] When the status signal SD is logic high, the PMOS transistor 1020 is turned off, and the other source / drain terminal of the PMOS transistor 1116 is disconnected from the power supply voltage VDD. Furthermore, the NMOS transistor 1120 is turned on and pulls the control signal VDDM_on_b down to logic low. In some embodiments, the buffer logic circuit 1130 is coupled to the output terminal of the comparator circuit 1110 (e.g., node 1113) and is configured to output the power management signal PWR_RDYB. Through the above circuit operation, the power detector 210 can be configured to output the power management signal PWR_RDYB having a logic high value when the monitored power supply voltage VDDM is not on.

[0072] In some other embodiments, the power detector 210 may also be implemented by other comparator circuits. For example, the power detector 210 may be or include various inverter circuits, comparator circuits, or Schmitt trigger comparator circuits. Figure 11 The circuit shown in FIG. 1 is merely an example and is not intended to limit the present disclosure.

[0073] Figure 12 is a diagram showing a sixth detailed design of a power detector 210 according to some embodiments of the present disclosure. Figure 12 As shown, in some embodiments, the power detector 210 includes a comparator circuit 1210, a PMOS transistor 1220 coupled between the comparator circuit 1210 and a second power supply (e.g., VDD), an inverter circuit 1230 coupled between the comparator circuit 1210 and a power supply ground reference, and an NMOS transistor 1240. Similar to the above-described embodiments, the comparator circuit 1210 is configured to detect a first power supply signal (e.g., VDDM) and a second power supply signal (e.g., VDD) to output a power management signal PWR_RDYB. The inverter circuit 1230 is configured to receive a state signal SD from an input terminal and output a logic value opposite to the state signal SD from an output terminal.

[0074] A control terminal (eg, gate terminal) of the PMOS transistor 1220 is coupled to a corresponding pin to receive the state signal SD. A control terminal (eg, gate terminal) of the NMOS transistor 1240 is coupled to an output terminal of the inverter circuit 1230 .

[0075] Therefore, both the PMOS transistor 1220 and the NMOS transistor 1240 are configured to selectively connect or disconnect the comparator circuit 1010 to or from the second power supply (e.g., VDD) or the power ground terminal based on the state signal SD. By gating the comparator circuit 1010 from both ends (e.g., the power supply side and the ground side), the leakage current of the power detector 210 can be further reduced. Similar to the above embodiment, the comparator circuit 1210 can be implemented using different types of comparator circuits, such as various inverter circuits, comparator circuits, or Schmitt trigger comparator circuits.

[0076] Figure 13 is a diagram showing a seventh detailed design of a power detector 210 according to some embodiments of the present disclosure. Figure 13 As shown, in some embodiments, the power detector 210 can be Figure 8 The inverter circuit 810 in the embodiment of the present invention realizes the comparator circuit. Figure 8 The power detector 210 is compared to the Figure 13 In the power detector 210, when the state signal SD is logic low, both the PMOS transistor 1220 and the NMOS transistor 1240 are turned on. Therefore, the other source / drain terminal of the PMOS transistor 814 is coupled to the power supply voltage VDD via the PMOS transistor 1220, and the other source / drain terminal of the NMOS transistor 812 is coupled to the power supply ground via the NMOS transistor 1240.

[0077] When the state signal SD is logic high, both the PMOS transistor 1220 and the NMOS transistor 1240 are turned off, and the inverter circuit 810 is disconnected from both the power supply voltage VDD and the power supply ground, and the leakage current is further reduced.

[0078] Figure 14 is a flow chart of an exemplary method 1400 for power management of a dual rail device according to some embodiments of the present disclosure. In some embodiments, the method 1400 includes operations 1410, 1420, and 1430.

[0079] At operation 1410, a status signal indicating a sleep mode of a circuit in a dual-rail device is detected. In some embodiments, in the sleep mode, one of a first power supply or a second power supply in the dual-rail device is disabled.

[0080] At operation 1420 , a first power management signal is generated in response to the status signal and a first power signal associated with the first power source.

[0081] At operation 1430, an isolation signal for controlling isolation between different domains of the circuit is provided as an output based on the first power management signal and the status signal. In some embodiments, isolation is enabled by outputting the isolation signal at a logic high in response to the status signal indicating a sleep mode. In some embodiments, isolation is enabled by outputting the isolation signal at a logic high in response to the first power management signal indicating a power-on state.

[0082] Various example embodiments herein are described in the general context of method steps or processes that can be performed by hardware and / or software. For example, method 1400 can be performed by Figure 3-8 and Figure 10-13 The method disclosed herein may be implemented by one or more circuits shown in , but the present disclosure is not limited thereto. In some embodiments, the method disclosed herein may be implemented in one aspect by a computer program product embodied in a temporary or non-temporary computer-readable medium, including computer-executable instructions, such as program code, executed by a computer in a network environment. The computer-readable medium may include removable and non-removable storage devices, including but not limited to read-only memory (ROM), random access memory (RAM), compact discs (CDs), digital versatile discs (DVDs), and the like.

[0083] The above examples include exemplary operations, but the operations are not necessarily performed in the order shown. Without departing from the spirit and scope of the present disclosure, operations can be appropriately added, replaced, changed in order and / or eliminated.

[0084] By arranging the power detector and utilizing one or more SOC power management signals in the power management circuit to appropriately output an isolation signal, transient leakage current during the power-on or power-off phase and standby leakage current of the power detector during sleep mode can be reduced. In addition, the simple design of the power management circuit has a small impact on the chip area and is suitable for SOC applications.

[0085] In some embodiments, a circuit is disclosed that includes a power detector and a logic circuit. The power detector is configured to output a first power management signal based on a status signal and a first power supply signal from a first power supply. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal based on the first power management signal and the status signal.

[0086] In some embodiments, a system-on-chip device is also disclosed, comprising a first power supply, a second power supply, a circuit, and a power management circuit. In a sleep mode, at least one of the first power supply and the second power supply is disabled in response to a status signal. The circuit is configured to operate with the first power supply and the second power supply. The power management circuit is configured to send a first power management signal to control the circuit. The power management circuit includes a power detector configured to output a first power management signal based on the status signal and a first power signal associated with the first power supply.

[0087] In some embodiments, a method is also disclosed, including: detecting a status signal indicating a sleep mode of a circuit, the circuit including a first domain corresponding to a first power supply and a second domain corresponding to a second power supply, wherein in the sleep mode, one of the first power supply or the second power supply is disabled; generating a first power management signal in response to the status signal and a first power supply signal associated with the first power supply; and outputting an isolation signal based on the first power management signal and the status signal to control isolation between the first domain and the second domain of the circuit.

[0088] Some examples are given below.

[0089] Example 1. A circuit comprising:

[0090] a power detector configured to output a first power management signal based on a status signal and a first power signal from a first power supply, wherein the circuit is configured to operate in a different mode in response to the status signal; and

[0091] A logic circuit is configured to output a second power management signal according to the first power management signal and the status signal.

[0092] Example 2. The circuit of Example 1, wherein the power detector comprises:

[0093] A comparator circuit is configured to detect the first power signal to output a control signal, and the comparator circuit is connected to a second power supply or a power ground terminal.

[0094] Example 3. The circuit of Example 2, wherein the power detector further comprises:

[0095] A transistor is coupled to the comparator circuit and configured to selectively connect or disconnect the comparator circuit from the second power supply according to the status signal.

[0096] Example 4. The circuit of Example 2, wherein the power detector further comprises:

[0097] A transistor is coupled to the comparator circuit and configured to selectively connect or disconnect the comparator circuit from the power supply ground according to the status signal.

[0098] Example 5. The circuit of Example 2, wherein the power detector further comprises:

[0099] A transistor is configured to selectively connect the second power supply to an output terminal of the comparator circuit according to the state signal.

[0100] Example 6. The circuit of Example 2, wherein the power detector further comprises:

[0101] A buffer logic circuit is coupled to the output terminal of the comparator circuit and is configured to output the first power management signal.

[0102] Example 7. The circuit of Example 1, wherein the logic circuit comprises:

[0103] An OR gate includes a first input terminal and a second input terminal, the first input terminal is configured to receive the first power management signal, and the second input terminal is configured to receive the status signal.

[0104] Example 8. The circuit of Example 1, wherein the logic circuit comprises:

[0105] a NOT gate configured to receive the state signal and output a control signal opposite to the state signal; and

[0106] A NAND gate includes a first input terminal and a second input terminal, the first input terminal is configured to receive the first power management signal, and the second input terminal is configured to receive the control signal.

[0107] Example 9. A system-on-chip device comprising:

[0108] a first power source and a second power source, wherein in the sleep mode, at least one of the first power source and the second power source is disabled in response to a status signal;

[0109] circuitry configured to operate with the first and second power supplies; and

[0110] A power management circuit configured to send a first power management signal to control the circuit, the power management circuit comprising:

[0111] A power detector is configured to generate the first power management signal based on the status signal and a first power signal associated with the first power supply.

[0112] Example 10. The system-on-chip device of Example 9, wherein the power management circuit further comprises:

[0113] A logic circuit is configured to output a second power management signal according to the first power management signal and the status signal.

[0114] Example 11. The system-on-chip device of Example 10, wherein the logic circuit comprises an OR gate comprising:

[0115] a first input terminal configured to receive the first power management signal;

[0116] a second input terminal configured to receive the status signal; and

[0117] The output terminal is configured to output the second power management signal.

[0118] Example 12. The system-on-chip device of Example 10, wherein the logic circuit comprises:

[0119] A NOT gate, the NOT gate comprising:

[0120] an input terminal configured to receive the status signal; and

[0121] an output terminal configured to output a control signal opposite to the state signal; and

[0122] A NAND gate, the NAND gate comprising:

[0123] a first input terminal configured to receive the first power management signal;

[0124] a second input terminal connected to the output terminal of the NOT gate; and

[0125] The output terminal is configured to output the second power management signal.

[0126] Example 13. The system-on-chip device of Example 9, wherein the power detector comprises a comparator circuit coupled to the first power supply and the second power supply.

[0127] Example 14. The system-on-chip device of Example 13, wherein the power management circuit further comprises a transistor configured to connect or disconnect the comparator circuit from the second power supply based on the status signal.

[0128] Example 15. The system-on-chip device of Example 13, wherein the power management circuit further comprises a transistor configured to connect or disconnect the comparator circuit to a power ground terminal based on the status signal.

[0129] Example 16. The system-on-chip device of Example 13, wherein the power management circuit further comprises a transistor configured to connect or disconnect the second power supply to or from the output terminal of the comparator circuit according to the status signal.

[0130] Example 17. The system-on-chip device of Example 13, wherein the power detector further comprises a buffer logic circuit coupled to an output terminal of the comparator circuit and configured to output the first power management signal.

[0131] Example 18. A method for power management, comprising:

[0132] detecting a status signal indicating a sleep mode of a circuit, the circuit including a first domain corresponding to a first power supply and a second domain corresponding to a second power supply, wherein one of the first power supply or the second power supply is disabled in the sleep mode;

[0133] generating a first power management signal in response to a first power signal associated with the first power supply and the status signal; and

[0134] An isolation signal is output according to the first power management signal and the status signal, where the isolation signal is used to control isolation between the first domain and the second domain of the circuit.

[0135] Example 19. The method of Example 18, further comprising:

[0136] In response to the status signal indicating the sleep mode, the isolation is enabled by the isolation signal.

[0137] Example 20. The method of Example 18, further comprising:

[0138] The isolation is enabled by the isolation signal in response to the first power management signal indicating a power-on state.

[0139] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit comprising: a power detector configured to output a first power management signal based on a status signal and a first power signal from a first power supply, wherein the circuit is configured to operate in a different mode in response to the status signal; and a logic circuit configured to output a second power management signal according to the first power management signal and the status signal, The power detector includes a comparator circuit configured to detect the first power signal, and the comparator circuit is connected to a second power supply or a power ground terminal.

2. The circuit according to claim 1, wherein The comparator circuit is configured to output the first power management signal.

3. The circuit according to claim 2, wherein The power detector further includes: A transistor is coupled to the comparator circuit and configured to selectively connect or disconnect the comparator circuit from the second power supply according to the status signal.

4. The circuit according to claim 2, wherein The power detector further includes: A transistor is coupled to the comparator circuit and configured to selectively connect or disconnect the comparator circuit from the power supply ground according to the status signal.

5. The circuit according to claim 2, wherein The power detector further includes: A transistor is configured to selectively connect the second power supply to an output terminal of the comparator circuit according to the state signal.

6. The circuit according to claim 2, wherein The power detector further includes: A buffer logic circuit is coupled to the output terminal of the comparator circuit and is configured to output the first power management signal.

7. The circuit according to claim 1, wherein The logic circuit comprises: An OR gate includes a first input terminal and a second input terminal, the first input terminal is configured to receive the first power management signal, and the second input terminal is configured to receive the status signal.

8. The circuit according to claim 1, wherein The logic circuit comprises: a NOT gate configured to receive the state signal and output a control signal opposite to the state signal; and A NAND gate includes a first input terminal and a second input terminal, the first input terminal is configured to receive the first power management signal, and the second input terminal is configured to receive the control signal.

9. A system-on-chip device comprising: a first power source and a second power source, wherein in the sleep mode, at least one of the first power source and the second power source is disabled in response to a status signal; circuitry configured to operate with the first and second power supplies; as well as A power management circuit configured to send a first power management signal to control the circuit, the power management circuit comprising: A power detector is configured to generate the first power management signal based on the status signal and a first power signal associated with the first power supply.

10. The system-on-chip device according to claim 9, wherein: The power management circuit further includes: A logic circuit is configured to output a second power management signal according to the first power management signal and the status signal.

11. The system-on-chip device according to claim 10, wherein: The logic circuit includes an OR gate, and the OR gate includes: a first input terminal configured to receive the first power management signal; a second input terminal configured to receive the status signal; and The output terminal is configured to output the second power management signal.

12. The system-on-chip device according to claim 10, wherein: The logic circuit comprises: A NOT gate, the NOT gate comprising: an input terminal configured to receive the status signal; and an output terminal configured to output a control signal opposite to the state signal; and a NAND gate, the NAND gate comprising: a first input terminal configured to receive the first power management signal; a second input terminal connected to the output terminal of the NOT gate; and The output terminal is configured to output the second power management signal.

13. The system-on-chip device according to claim 9, wherein: The power detector includes a comparator circuit coupled to the first power supply and the second power supply.

14. The system-on-chip device according to claim 13, wherein: The power management circuit further includes a transistor configured to connect or disconnect the comparator circuit from the second power source according to the status signal.

15. The system-on-chip device according to claim 13, wherein: The power management circuit further includes a transistor configured to connect or disconnect the comparator circuit to or from a power ground terminal according to the status signal.

16. The system-on-chip device according to claim 13, wherein: The power management circuit further includes a transistor configured to connect or disconnect the second power source from the output terminal of the comparator circuit according to the status signal. 17 . The system-on-chip device of claim 13 , wherein the power detector further comprises a buffer logic circuit coupled to an output terminal of the comparator circuit and configured to output the first power management signal.

18. A method for power management, comprising: detecting a status signal indicating a sleep mode of a circuit, the circuit including a first domain corresponding to a first power supply and a second domain corresponding to a second power supply, wherein one of the first power supply or the second power supply is disabled in the sleep mode; generating a first power management signal in response to a first power signal associated with the first power source and the status signal; as well as An isolation signal is output according to the first power management signal and the status signal, where the isolation signal is used to control isolation between the first domain and the second domain of the circuit.

19. The method according to claim 18, further comprising: In response to the status signal indicating the sleep mode, the isolation is enabled by the isolation signal.

20. The method of claim 18, further comprising: The isolation is enabled by the isolation signal in response to the first power management signal indicating a power-on state.

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