Memory device and method of operating a memory device

Abstract

Embodiments of the present disclosure relate to a memory device and a method for operating the memory device. A memory device configured to perform a programming operation and a backup operation together includes: a memory block including a main sub-block and a backup block, the main sub-block including selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, program data being programmed in the selected memory cells, and page data included in the program data being backed up in the backup block; a peripheral circuit configured to perform a plurality of programming loops to program the program data in the selected memory cells; and control logic configured to control the peripheral circuit to back up any one of the page data while programming the selected memory cells in a preset programming loop among the plurality of programming loops.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2021-0001550 filed on January 6, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer, smartphone, or tablet. Storage devices include devices that store data on magnetic disks, such as hard disk drives (HDDs), devices that store data on semiconductor memories, such as solid-state drives (SSDs), or memory cards, particularly non-volatile memories.

[0005] A storage device may include a memory device in which data is stored and a memory controller that stores the data in the memory device. Memory devices can be classified as volatile memory and non-volatile memory. Here, non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a memory device may include: a memory block, the memory block including a main sub-block and a backup block, the main sub-block including selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, programming data being programmed in the selected memory cells, and page data included in the programming data being backed up in the backup block; a peripheral circuit configured to perform a plurality of programming loops to program the programming data in the selected memory cells; and control logic configured to control the peripheral circuit to back up any one of the page data while programming the selected memory cells in a preset programming loop among the plurality of programming loops.

[0007] According to an embodiment of the present disclosure, a memory device may include: a memory block including a main sub-block and a backup block, the main sub-block including selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, program data being programmed in the selected memory cells, and page data included in the program data being backed up in the backup block; a peripheral circuit configured to perform a plurality of program loops to program the program data in the selected memory cells; an erase controller configured to control an erase operation on the backup block before the plurality of program loops are performed or after all the plurality of program loops are performed; a program loop counter configured to count the number of times the plurality of program loops are performed; a mode setting unit configured to set a programming mode for programming the program data based on the number of program loops counted by the program loop counter; and a backup execution unit configured to control the peripheral circuit to back up any one of the page data while programming the selected memory cells in a preset program loop among the plurality of program loops.

[0008] According to an embodiment of the present disclosure, a method for operating a memory device includes a memory block, the memory block includes a main sub-block and a backup block, the main sub-block includes selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, programming data is programmed in the selected memory cells, and page data included in the programming data is backed up in the backup block. The method may include: executing a plurality of programming loops to program the programming data in the selected memory cells; and when executing a preset programming loop among the plurality of programming loops, backing up any one of the page data while programming the selected memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a storage device.

[0010] Figure 2 It's a picture Figure 1 Schematic diagram of the structure of a memory device.

[0011] Figure 3 It's a picture Figure 2 Schematic diagram of an embodiment of a memory cell array.

[0012] Figure 4A and Figure 4B is a diagram illustrating a program loop and a process in which memory cells are programmed.

[0013] Figure 5 The diagram shows the configuration of a backup controller.

[0014] Figure 6is a diagram illustrating a backup block and a method for backing up data in the backup block.

[0015] Figure 7 A process of programming selected memory cells when a program operation is performed in a three-level cell method is illustrated.

[0016] Figure 8 Illustrated are threshold voltage distributions of memory cells when backup data is programmed and a method of reading the backup data.

[0017] Figure 9 A section in which a verification operation is performed when backup data is programmed is illustrated.

[0018] Figure 10 The diagram shows the respective Figure 9 Programming loop of the verify operation.

[0019] Figure 11 is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0020] Figure 12 is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0021] Figure 13 It's a picture Figure 1 FIG. 1 is a diagram of another embodiment of a memory controller.

[0022] Figure 14 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0023] Figure 15 is a block diagram illustrating, for example, a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0024] Figure 16 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0025] The specific structural or functional descriptions of the embodiments of the concepts disclosed in this specification or this application are only illustrated for describing the embodiments of the concepts according to the present disclosure. The embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can realize the technical spirit of the present disclosure.

[0027] Embodiments of the present disclosure provide a memory device and a method of operating the memory device, which can reduce time consumed by a backup operation by performing a program operation and a backup operation together.

[0028] According to the present technology, by backing up data in a specific program loop among a plurality of program loops, a backup operation can be performed without separately allocating time for data backup.

[0029] Figure 1 is a block diagram illustrating a storage device and a host.

[0030] refer to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 .

[0031] The storage device 50 may be a device that stores data under the control of the host 300 , such as a cellular phone, smart phone, MP3 player, laptop computer, desktop computer, game console, television, tablet PC, or in-vehicle infotainment system.

[0032] The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices such as an SSD, a multimedia card in the form of MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of SD, mini-SD, and micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0033] The memory device 50 may be manufactured in any of various types of packages. For example, the memory device 50 may be manufactured in any of various types of packages such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer fabrication package (WFP), and wafer stacked package (WSP).

[0034] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data. The memory cell array may include a plurality of memory blocks. Each of the memory blocks may include a plurality of memory cells, and the plurality of memory cells may configure a plurality of pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0035] In one embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a perpendicular NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for the sake of convenience, it is assumed that the memory device 100 is a NAND flash memory.

[0036] The memory device 100 can be implemented as a two-dimensional array structure or a three-dimensional array structure. The three-dimensional array structure is described below as an example, but the present disclosure is not limited to the three-dimensional array structure. The present disclosure can be applied not only to flash memory devices in which the charge storage layer is configured by a conductive floating gate (FG), but also to charge trap flash memories (CTFs) in which the charge storage layer is configured by an insulating film.

[0037] In one embodiment, the memory device 100 may operate in a single-level cell (SLC) method in which one data bit is stored in one memory cell. Alternatively, the memory device 100 may operate in a method in which at least two data bits are stored in one memory cell. For example, the memory device 100 may operate in a multi-level cell (MLC) method in which two data bits are stored in one memory cell, a triple-level cell (TLC) method in which three data bits are stored in one memory cell, or a quad-level cell (QLC) method in which four data bits are stored in one memory cell.

[0038] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access the area selected by the address in the memory cell array. That is, the memory device 100 can perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 can perform a write operation (program operation), a read operation, or an erase operation according to the received command. For example, when a program command is received, the memory device 100 can program data in the area selected by the address. When a read command is received, the memory device 100 can read data from the area selected by the address. When an erase command is received, the memory device 100 can erase the data stored in the area selected by the address.

[0039] In one embodiment, the memory device 100 may include a backup controller 150. When the memory device 100 performs a program operation, the backup controller 150 may back up program data.

[0040] For example, when the memory device 100 performs a programming operation on a selected page among a plurality of pages included in a memory block, the backup controller 150 may back up the program data in the memory cells of the backup block. In this case, the memory cells of the backup block may be memory cells connected to the same selected word line as the memory cells of the selected page. In addition, the data programmed into the memory cells of the backup block may be some of the data to be programmed into the selected page, and may be programmed in a specific programming pulse.

[0041] In one embodiment, the backup controller 150 backs up part or all of the data in a backup block, thereby preventing data loss due to a growing bad block (GBB) occurring during a program operation.

[0042] For example, GBB may occur when a program fail occurs during a program operation on a page of the memory device 100. When GBB occurs, data of other pages in a memory block including the selected page may be lost together.

[0043] When the memory controller 200 controls programming of data through the SLC buffer, some data may be recovered through data stored in the SLC buffer, but the number of pages that can be recovered is limited.

[0044] Therefore, in the present disclosure, a method is proposed in which a memory device 100 includes a selected memory block on which a programming operation is performed and a backup block corresponding to the selected memory block, and when the memory device 100 performs a programming operation on the selected memory block, program data is backed up in the backup block. By backing up the program data in the backup block, even if GBB occurs, data can be restored based on the program data backed up in the backup block.

[0045] The memory controller 200 may control overall operations of the memory device 50 .

[0046] The memory controller 200 may execute firmware when power voltage is applied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 may operate firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0047] In one embodiment, the memory controller 200 may include firmware (not shown) that receives data and a logical block address (LBA) from the host 300 and converts the LBA into a physical block address (PBA) indicating an address of a memory cell in which data included in the memory device 100 is to be stored. In addition, the memory controller 200 may store a logical-physical address mapping table in a buffer memory that configures a mapping relationship between the LBA and the PBA.

[0048] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. according to a request from the host 300. For example, when a program request is received from the host 300, the memory controller 200 can convert the program request into a program command and provide the program command, the PBA, and data to the memory device 100. When a read request is received from the host 300 together with the LBA, the memory controller 200 can change the read request into a read command, select the PBA corresponding to the LBA, and then provide the read command and the PBA to the memory device 100. When an erase request is received from the host 300 together with the LBA, the memory controller 200 can change the erase request into an erase command, select the PBA corresponding to the LBA, and then provide the erase command and the PBA to the memory device 100.

[0049] In one embodiment, the memory controller 200 may generate and transmit program commands, addresses, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0050] In one embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 300 and the buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data used to control the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory and then transmit the data temporarily stored in the buffer memory to the memory device 100.

[0051] In various embodiments, the buffer memory may be used as an operating memory and a cache memory for the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0052] In one embodiment, the buffer memory may be implemented as a dynamic random access memory (DRAM), such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR4 SDRAM, low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, or Rambus dynamic random access memory (RDRAM) or static random access memory (SRAM).

[0053] In various embodiments, the buffer memory may be connected from the outside of the storage device 50. In this case, a volatile memory device connected to the outside of the storage device 50 may be used as the buffer memory.

[0054] In one embodiment, the memory controller 200 may control at least two or more memory devices. In this case, the memory controller 200 may control the memory devices according to an interleaving method to improve operation performance.

[0055] The host 300 may communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0056] Figure 2 It's a picture Figure 1 Schematic diagram of the structure of a memory device.

[0057] refer to Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0058] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz can be connected to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are nonvolatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block can include multiple pages.

[0059] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0060] Each of the memory cells included in the memory cell array 110 may be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC storing four data bits.

[0061] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0062] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0063] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In one embodiment, the row lines RL may also include pipe select lines.

[0064] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0065] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a level higher than the read voltage to unselected word lines.

[0066] In one embodiment, the erase operation of the memory device 100 is performed in memory block units. During the erase operation, the row decoder 121 can select a memory block according to the decoded address. During the erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0067] The voltage generator 122 operates in response to the control of the control logic 130. The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. For example, in response to the operation signal OPSIG, the voltage generator 122 can generate various operation voltages Vop used for program, read, and erase operations. For example, the voltage generator 122 can generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. in response to the control of the control logic 130.

[0068] As an embodiment, the voltage generator 122 may generate the internal power supply voltage by regulating the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0069] As an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

[0070] For example, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage, and may selectively activate the plurality of pumping capacitors in response to the control of the control logic 130 to generate a plurality of voltages.

[0071] The generated plurality of voltages may be supplied to the memory cell array 110 by the row decoder 121 .

[0072] The page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn operate in response to the control of the control logic 130. For example, the first to nth page buffers PB1 to PBn may operate in response to a page buffer control signal PBSIGNALS. For example, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense the voltage or current of the bit lines BL1 to BLn during a read or verify operation.

[0073] For example, during a program operation, when a program voltage is applied to a selected word line, the first to n-th page buffers PB1 to PBn can transmit data DATA received through the input / output circuit 125 to selected memory cells through the first to n-th bit lines BL1 to BLn. The memory cells of the selected page are programmed according to the transmitted data DATA. During a program verification operation, the first to n-th page buffers PB1 to PBn can read page data by sensing a voltage or current received from the selected memory cells through the first to n-th bit lines BL1 to BLn.

[0074] During a read operation, the first to nth page buffers PB1 to PBn read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0075] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or apply an erase voltage.

[0076] The column decoder 124 may transmit data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0077] The input / output circuit 125 can be used to Figure 1 Description Figure 1The memory controller 200 transmits the received command CMD and address ADDR to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0078] The sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT during a read operation or a verification operation and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0079] The control logic 130 may output an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit signal VRYBIT in response to a command CMD and an address ADDR to control the peripheral circuit 120. For example, the control logic 130 may control a read operation of a selected memory block in response to a sub-block read command and address. In addition, the control logic 130 may control an erase operation of a selected sub-block included in a selected memory block in response to a sub-block erase command and address. Furthermore, the control logic 130 may determine whether a verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0080] In one embodiment, the control logic 130 may include a backup controller 150. In another embodiment, the backup controller 150 may be included external to the control logic 130.

[0081] In one embodiment, during a specific programming loop among the programming loops executed when the memory device 100 performs a programming operation, the backup controller 150 may change the programming mode to a backup programming mode. In the backup programming mode, the backup controller 150 may control the memory device 100 so that the programming loop and the backup operation are performed simultaneously. Therefore, while the programming operation is performed on the selected page, some of the data to be programmed in the selected page may be backed up to the backup block.

[0082] Here, when the memory device 100 performs a program operation in the MLC method, the data to be programmed in the selected page may be the least significant bit (LSB) page data and the most significant bit (MSB) page data. When the memory device 100 performs a program operation in the TLC method, the data to be programmed in the selected page may be the least significant bit (LSB) page data, the center significant bit (CSB) page data, and the most significant bit (MSB) page data.

[0083] In one embodiment, the number of backup blocks may be the same as the number of data to be programmed in the selected page. In addition, the data to be backed up in the backup blocks may be programmed in an SLC method.

[0084] In one embodiment, the backup controller 150 may set a read voltage level for reading the backed-up data when programming fails. For example, when the memory device 100 performs a program operation in the TLC method, the backup controller 150 may set a read voltage for reading each of the backed-up LSB page data, CSB page data, and MSB page data.

[0085] Therefore, when a program fail occurs, the backup controller 150 may restore the program data by reading the backed-up data at a preset read voltage, and the memory device 100 may perform a program operation again based on the restored data.

[0086] In one embodiment, the backup controller 150 may erase the backup block before the start of the programming operation or after the completion of the programming operation. For example, after the completion of the programming operation, the backup block may be erased because the backup of the programming data is no longer needed. Alternatively, the backup block may be erased before the start of the programming operation in order to erase the programming data backed up in the previous programming operation at the end of the operation.

[0087] As described above, since the memory device 100 performs a programming operation and the backup controller 150 simultaneously backs up the programming data, the time required for the backup operation can be included in the time consumed by the programming operation. That is, a separate backup programming time for the memory device 100 to back up the programming data may not be consumed. As used herein, the words "simultaneously" and "simultaneously" with respect to occurrences mean that the occurrences occur at overlapping time intervals. For example, if a first occurrence occurs within a first time interval and a second occurrence occurs simultaneously within a second time interval, then the first time interval and the second time interval at least partially overlap with each other, so that there is a time when both the first occurrence and the second occurrence occur.

[0088] As a result, through the above process, the time consumed by the program operation can be shortened.

[0089] Figure 3 It's a picture Figure 2 Schematic diagram of an embodiment of a memory cell array.

[0090] refer to Figure 2 and Figure 3 , Figure 3 It shows Figure 2 1 and 2. A circuit diagram of any one memory block BLKa among a plurality of memory blocks BLK1 to BLKz included in the memory cell array 110.

[0091] A first selection line, a word line, and a second selection line arranged in parallel with each other may be connected to the memory block BLKa. For example, the word lines may be arranged in parallel with each other between the first selection line and the second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0092] For example, the memory block BLKa may include a plurality of strings connected between bit lines BL1 to BLn and source lines SL. The bit lines BL1 to BLn may be connected to the strings separately, and the source line SL may be connected to the strings in common. Since the strings may be configured to be identical to each other, for example, the string ST connected to the first bit line BL1 is specifically described.

[0093] The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST connected in series between a source line SL and a first bit line BL1. One string ST may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include more memory cells F1 to F16 than shown in the figure.

[0094] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings can be connected to the source select line SSL, the gates of the drain select transistors DST can be connected to the drain select line DSL, and the gates of the memory cells F1 to F16 can be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings can be referred to as a physical page PPG. Therefore, the memory block BLKa can include the number of physical pages PPG of the word lines WL1 to WL16.

[0095] One memory cell can store one bit of data. This is commonly referred to as SLC. In this case, one physical page PPG can store one logical page (LPG) of data. One logical page (LPG) of data can include the number of data bits of the memory cells included in one physical page PPG. In addition, one memory cell can store two or more bits of data. This is commonly referred to as MLC. In this case, one physical page PPG can store two or more logical pages (LPG) of data.

[0096] A memory cell storing two or more bits of data in one memory cell is called an MLC. However, recently, as the number of bits of data stored in one memory cell increases, an MLC refers to a memory cell storing two bits of data, a memory cell storing three or more bits of data is called a triple-level cell (TLC), and a memory cell storing four or more bits of data is called a quad-level cell (QLC). In addition, a memory cell storing multiple bits of data has been developed, and the present embodiment can be applied to the memory device 100 storing two or more bits of data.

[0097] In another embodiment, the memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction.

[0098] Figure 4A and Figure 4B is a diagram illustrating a program loop and a process in which memory cells are programmed.

[0099] refer to Figure 4A and Figure 4B , Figure 4A Shows when Figure 2 any one of a plurality of programming loops executed when the memory device 100 performs a programming operation, and Figure 4B FIG. 1 shows a process in which memory cells in an erased state are programmed to a target programmed state. Figure 4B , the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells.

[0100] exist Figure 4A and Figure 4B In, assuming Figure 1 The memory device 100 performs a program operation in an SLC method.

[0101] refer to Figure 4A ,when Figure 2 When the memory device 100 performs a program operation on selected memory cells, a program loop PL may be performed. The program loop PL may include a program pulse applying operation and a verification operation.

[0102] In one embodiment, the program pulse applying operation may be an operation of applying the program voltage Vpgm to the selected word line to which the selected memory cell is connected. That is, Figure 2 The memory device 100 may program selected memory cells by applying a program voltage Vpgm to a selected word line.

[0103] In one embodiment, the verification operation may be an operation of verifying whether the selected memory cell is programmed to the target program state by the program pulse application operation. For example, the verification operation may be an operation of applying a verification voltage Vvfy to the selected word line to which the selected memory cell is connected. That is, whether the selected memory cell is programmed to the target program state may be determined based on data read by applying the verification voltage Vvfy to the selected word line.

[0104] Thereafter, when the verification operation passes, the program loop PL may be terminated, but when the verification operation fails, the next program loop may be executed. The program voltage applied to the selected word line in the next program loop may have a level that is greater than the program voltage Vpgm by a step voltage. That is, the next program loop may be executed in an incremental step pulse programming (ISPP) method.

[0105] After applying a voltage having a level greater than the program voltage Vpgm by a step voltage to the selected word line, whether the selected memory cells are programmed to the target program state may be determined again through a verification operation.

[0106] refer to Figure 4B , Figure 4B It is shown that the threshold voltage distribution of the memory cells shifts when the programming loops are performed sequentially.

[0107] In one embodiment, a plurality of program loops may be performed when a program operation is performed on selected memory cells of the erase state E. At this time, the memory cells of the erase state E may be programmed to a target program state P through various states.

[0108] In one embodiment, when the first program loop PL1 is performed on selected memory cells, the threshold voltage distribution of memory cells in the erase state E may be programmed to the PX1 distribution.

[0109] However, since the first program loop PL1 does not complete programming of erased memory cells, the second program loop PL2 may be performed after the first program loop PL1. When the second program loop PL2 is performed on selected memory cells, the threshold voltage distribution of the memory cells may be changed from PX1 distribution to PX2 distribution.

[0110] Thereafter, in the nth programming loop PLn, the threshold voltage distribution of the selected memory cells may be changed from the PXn-1 distribution to the P distribution. Thus, the selected memory cells may be programmed to the target program state through the first programming loop PL1 to the nth programming loop PLn. In one embodiment, "n" may be a positive integer.

[0111] When a program failure occurs while programming a selected memory cell through the above process, a GBB may occur. When a GBB occurs, data in other pages of the memory block including the selected page may also be lost. Therefore, in preparation for a program failure, the data to be programmed into the selected memory cell can be backed up.

[0112] However, since a separate programming time for backing up data is consumed in order to back up program data, the present disclosure proposes a backup method by backing up program data while performing a program operation without consuming the separate programming time.

[0113] Figure 5 The diagram shows the configuration of a backup controller.

[0114] refer to Figure 5 , Figure 5 The backup controller 150 may include an erase controller 151 , a program loop counter 153 , a mode setting unit 155 , and a backup execution unit 157 .

[0115] In one embodiment, the erase controller 151 may control the erasure of the selected memory block including the selected memory cell and the backup block backing up the program data to be programmed in the selected memory cell. At this time, the backup block and the selected memory block may be connected by the same word line.

[0116] In one embodiment, the erase controller 151 can be Figure 1 The memory controller 200 erases the backup block and the selected memory block after receiving the program command PGM_CMD. That is, before the program data is programmed into the selected memory cells included in the selected memory block, the backup block and the selected memory block may be erased. When receiving the program command PGM_CMD, the erase controller 151 may output an erase request ERASE_REQ for the backup block and the selected memory block, and may erase the backup block and the selected memory block based on the erase request ERASE_REQ.

[0117] In another embodiment, the erase controller 151 can erase the backup block based on the program completion signal PGMC_SIG. Here, the program completion signal PGMC_SIG can be a signal output after the program operation is completed. That is, when the program operation on the selected memory cell is completed, since it is no longer necessary to back up the program data in the backup block, the erase controller 151 can erase the backup block after the program operation is completed for the next programming operation. When the program completion signal PGMC_SIG is received, the erase controller 151 can output an erase request ERASE_REQ for the backup block and the selected memory block, and can erase the backup block and the selected memory block based on the erase request ERASE_REQ.

[0118] In one embodiment, the program loop counter 153 can be used to Figure 1 The memory device 100 counts the number of program loops executed when performing a program operation, and outputs program loop information PGMLOOP_INF based on the counting result. Figure 1 When the memory device 100 performs a program operation on a selected memory cell, a plurality of program loops may be performed, and each time a program loop is performed, the program loop counter 153 may count "1". Figure 1 When three program loops are performed in the memory device 100, the program loop information PGMLOOP_INF may be "3".

[0119] In one embodiment, the mode setting unit 155 may set a programming mode based on the program loop information PGMLOOP_INF received from the program loop counter 153. At this time, the programming mode may be a normal mode or a backup mode. The normal mode may be a programming mode in which a program operation is performed only on selected memory cells, and the backup mode may be a programming mode in which program data is backed up while a program operation is performed on the selected memory cells.

[0120] The mode setting unit 155 can set the programming mode to the backup mode in a specific programming cycle. Figure 1 When the memory device 100 performs a program operation in a TLC method, the program data may be LSB page data, CSB page data, and MSB page data. Therefore, since the data to be backed up is three pieces of data, the mode setting unit 155 may set the program mode to the backup mode so as to back up the above data in three specific program loops. The mode setting unit 155 may set the program mode to the backup mode. Figure 1 The backup mode is set in any specific program loop among a plurality of program loops executed in the memory device 100.

[0121] In one embodiment, the mode setting component 155 may output mode information MODE_INF for setting a mode to the backup execution component 157 .

[0122] In one embodiment, the backup execution component 157 may perform a backup operation based on the mode information MODE_INF received from the mode setting component 155. For example, when the mode information MODE_INF indicates the normal mode, the backup execution component 157 may not operate, and when the mode information MODE_INF indicates the backup mode, the backup execution component 157 may output a backup request BACKUP_REQ.

[0123] Based on the backup request BACKUP_REQ output from the backup execution component 157, Figure 1 The memory device 100 can program the program data in the backup block while programming the selected memory cell. Figure 1 The memory device 100 may back up LSB page data, CSB page data, and MSB page data in a preset specific program loop.

[0124] Figure 6 is a diagram illustrating a backup block and a method of backing up data in the backup block.

[0125] refer to Figure 2 and Figure 6 , Figure 6 Pictured Figure 2 A portion of the first memory block BLK1. Figure 6 In FIG, it is assumed that the first memory block BLK1 is connected to the first to fourth word lines WL1 to WL4 and the first to sixteenth bit lines BL1 to BL16. Figure 6 In the example, one memory cell may exist at a point where one word line and one bit line intersect. The first memory block BLK1 may include a (1_1)th memory block BLK1_1 and first to third backup blocks BLK_BU1 to BLK_BU3 as sub-blocks.

[0126] exist Figure 6 , it is assumed that the first word line WL1 is a selected word line, and the memory cells included in the (1_1)th memory block BLK1_1 (which is a selected memory block among the memory cells connected to the first word line WL1) are selected memory cells on which a programming operation is performed. That is, among the memory cells connected to the first word line WL1, the memory cells respectively connected to the first to fourth bit lines BL1 to BL4 may be selected memory cells. The (1_1)th memory block BLK1_1 may be a main sub-block in which a programming operation is performed.

[0127] exist Figure 6 In, assuming Figure 2 The memory device 100 performs a program operation in a TLC method. Therefore, program data to be programmed in selected memory cells may include LSB page data, CSB page data, and MSB page data.

[0128] As a result, the first memory block BLK1 may include the (1_1)th memory block on which a programming operation is performed, and the first backup blocks BLK_BU1 to the third backup blocks BLK_BU3 in which the program data programmed in the (1_1)th memory block BLK1_1 is backed up. That is, since the number of data that needs to be backed up is three, the backup blocks may be composed of the first backup blocks BLK_BU1 to the third backup blocks BLK_BU3 as three backup blocks. Here, the (1_1)th memory block BLK1_1 and the first backup blocks BLK_BU1 to the third backup blocks BLK_BU3 may be sub-blocks of the first memory block BLK1, and the (1_1)th memory block BLK1_1 and the first backup blocks BLK_BU1 to the third backup blocks BLK_BU3 may be sub-blocks connected to the first word line WL1 to the fourth word line WL4 (i.e., the same word line).

[0129] In one embodiment, a plurality of program loops may be performed on selected memory cells included in the (1_1)th memory block BLK1_1 among memory cells connected to the first word line WL1. Each of the plurality of program loops may include a program pulse applying operation and a verification operation.

[0130] In one embodiment, when a plurality of program loops are performed on selected memory cells, program data may be backed up in memory cells connected to the first word line WL1 among memory cells included in the first to third backup blocks BLK_BU1 to BLK_BU3 in a specific program loop.

[0131] For example, assuming that the backup operation is performed simultaneously with the program operation in the eleventh, thirteenth, and fifteenth programming loops among the plurality of program loops, when the eleventh program loop is performed on the selected memory cells, the MSB page data may be simultaneously programmed in the memory cells connected to the first word line WL1 among the memory cells included in the first backup block BLK_BU1. At this time, in order to program the MSB page data, Figure 5 The backup execution unit 157 may control voltage levels of the fifth to eighth bit lines BL5 to BL8 .

[0132] After simultaneously performing the program operation and the backup operation through the eleventh program loop, the twelfth program loop may be performed. The twelfth program loop may include only an operation of programming selected memory cells without the backup operation.

[0133] When the thirteenth program loop is performed after the twelfth program loop, the CSB page data may be simultaneously programmed in the memory cells connected to the first word line WL1 among the memory cells included in the second backup block BLK_BU2. At this time, in order to program the CSB page data, Figure 5 The backup execution unit 157 may control voltage levels of the ninth to twelfth bit lines BL9 to BL12.

[0134] After simultaneously performing the program operation and the backup operation through the thirteenth program loop, the fourteenth program loop may be performed. The fourteenth program loop may include only an operation of programming selected memory cells without the backup operation.

[0135] When the fifteenth program loop is performed after the fourteenth program loop, the LSB page data may be simultaneously programmed in the memory cells connected to the first word line WL1 among the memory cells included in the third backup block BLK_BU3. At this time, in order to program the LSB page data, Figure 5 The backup execution unit 157 may control voltage levels of the thirteenth to sixteenth bit lines BL13 to BL16.

[0136] As a result, in the eleventh, thirteenth, and fifteenth program loops, since the backup operation is performed together with the program operation, a separate backup operation for backing up program data may not be performed, thereby shortening the time consumed by the program operation.

[0137] Figure 7 A process of programming selected memory cells when a program operation is performed in a TLC method is illustrated.

[0138] refer to Figure 7 , Figure 7 The diagram shows the Figure 2 The threshold voltage distribution of the memory cells is changed by performing a plurality of program loops when the memory device 100 performs a program operation in a TLC method. Figure 7 , the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells.

[0139] In one embodiment, when Figure 2When the memory device 100 performs a programming operation on a selected memory cell, multiple programming loops may be performed. Each of the multiple programming loops may include a program pulse application operation and a verification operation. In each programming loop, a first programming pulse PULSE1 to an nth programming pulse PULSEn may be applied to a selected word line. That is, a program voltage corresponding to the first programming pulse PULSE1 to the nth programming pulse PULSEn, respectively, may be applied to the selected word line. The program voltage may be a voltage for programming the selected memory cell to a target program state, and may increase in a stepped voltage level.

[0140] Therefore, in order to program selected memory cells from the erase state E to the first to seventh program states P1 to P7 , first to nth program pulses PULSE1 to PULSEn may be applied to the selected word line to which the selected memory cells are connected.

[0141] In one embodiment, a program operation may start as a first program pulse PULSE1 is applied to a selected word line. When the first program pulse PULSE1 is applied to the selected word line, a threshold voltage distribution of selected memory cells of an erase state E may increase.

[0142] In one embodiment, as the third program pulse PULSE3 following the second program pulse PULSE2 is applied to the selected word line, memory cells whose target program state is the first program state P1 among the selected memory cells may be programmed to the first program state P1.

[0143] As the fifth programming pulse PULSE5 following the fourth programming pulse PULSE4 is applied to the selected word line, the threshold voltages of the selected memory cells increase, and memory cells whose target programming states are the second programming state P2 among the selected memory cells may be programmed to the second programming state P2.

[0144] Thereafter, as sixth to nth program pulses PULSE6 to PULSEn are sequentially applied to the selected word line, the selected memory cells may be respectively programmed to third to seventh program states P3 to P7 as target program states.

[0145] In the present disclosure, when programming a selected memory cell, a backup operation may be performed in a specific programming loop. For example, the backup operation may be performed in the eleventh, thirteenth, and fifteenth programming loops among a plurality of programming loops performed when programming the selected memory cell.

[0146] refer to Figure 8Changes in threshold voltage distribution of memory cells included in a backup block during a backup operation are described.

[0147] Figure 8 Illustrated are threshold voltage distributions of memory cells when backup data is programmed and a method of reading the backup data.

[0148] refer to Figure 7 and Figure 8 , Figure 8 The diagram shows Figure 7 The process of programming the memory cells of the backup block when the first programming pulse PULSE1, the third programming pulse PULSE3 and the fifth programming pulse PULSE5 are applied to the selected word line. Figure 6 , the backup blocks are composed of first to third backup blocks BLK_BU1 to BLK_BU3, and the first to third backup blocks BLK_BU1 to BLK_BU3 may be sub-blocks connected to first to fourth word lines WL1 to WL4 (ie, the same word line).

[0149] As in Figure 7 Like in Figure 8 In, assuming Figure 2 The memory device 100 performs a programming operation in a TLC method. Therefore, the data to be programmed into the selected memory cell may be the LSB page data, the CSB page data, and the MSB page data. Since three pieces of data are programmed into the selected memory cell, the number of backup blocks may be three.

[0150] In one embodiment, reference Figure 6 , a plurality of program loops may be performed on selected memory cells included in the (1_1)th memory block BLK1_1 among the memory cells connected to the first word line WL1. At this time, a backup operation may be performed on memory cells included in the first to third backup blocks BLK_BU1 to BLK_BU3 among the memory cells connected to the first word line WL1.

[0151] For example, when the first programming pulse PULSE1 is applied to the first word line WL1, the MSB page data can be programmed in the memory cells of the first backup block BLK_BU1 among the memory cells connected to the first word line WL1 using the SLC method. Thereafter, when programming fails, the MSB page data programmed in the first backup block BLK_BU1 can be read using the RM voltage. The RM voltage can be set in advance. The RM voltage can be a read voltage for distinguishing between an erased state and a programmed state of the MSB page data.

[0152] When the third programming pulse PULSE3 is applied to the first word line WL1 after the first programming pulse PULSE1 and the second programming pulse PULSE2 are applied to the first word line WL1, the CSB page data can be programmed in the memory cells of the second backup block BLK_BU2 among the memory cells connected to the first word line WL1 in an SLC method. Thereafter, when programming fails, the CSB page data programmed in the second backup block BLK_BU2 can be read through the RC voltage. The RC voltage can be set in advance. The RC voltage can be a read voltage for distinguishing between the erase state and the program state of the CSB page data. In addition, the level of the RC voltage can be higher than that of the RM voltage.

[0153] After the first to fourth programming pulses PULSE1 to PULSE4 are applied to the first word line WL1, when the fifth programming pulse PULSE5 is applied to the first word line WL1, the LSB page data can be programmed in the memory cells of the third backup block BLK_BU3 among the memory cells connected to the first word line WL1 using the SLC method. Thereafter, when programming fails, the LSB page data programmed in the third backup block BLK_BU3 can be read through the RL voltage. The RL voltage can be set in advance. The RL voltage can be a read voltage for distinguishing between the erased state and the programmed state of the LSB page data. In addition, the level of the RL voltage can be higher than the level of the RC voltage.

[0154] As a result, since the backup operation is performed together with the program operation in a specific program loop among the plurality of program loops, a separate time may not be consumed for the backup operation. Therefore, the time consumed for the program operation is shortened, and all data to be programmed in the selected memory cells included in each of the first to third backup blocks BLK_BU1 to BLK_BU3 can be backed up.

[0155] Figure 9 A section in which a verification operation is performed when backup data is programmed is illustrated.

[0156] refer to Figures 7 to 9 , Figure 9 The diagram shows the reference Figure 7 and Figure 8 The described programming method performs a verification operation in each program loop when performing a program operation on selected memory cells.

[0157] In one embodiment, when Figure 2 The memory device 100 performs a program operation in a TLC method, and a target program state of a selected memory cell may be any one of the first to seventh program states P1 to P7.

[0158] In one embodiment, eleventh to twenty-seventh program loops PL11 to PL27 may be performed to program selected memory cells to a target program state. The eleventh to twenty-seventh program loops PL11 to PL27 may include a program pulse application operation of applying first to seventeenth program pulses PULSE1 to PULSE17 to a selected word line and a verification operation, respectively.

[0159] In one embodiment, when the eleventh program loop PL11 is performed on the selected memory cells, a program pulse application operation in which a first program pulse PULSE1 is applied to the selected word line may be performed. Thereafter, a verification operation may be performed with a first verification voltage Vvfy1 to verify whether the memory cells whose target program states are the first program state P1 are programmed.

[0160] Further, refer to Figure 7 and Figure 8 , the MSB page data among the LSB page data, CSB page data, and MSB page data programmed in the selected memory cells can be programmed in the backup block in the SLC method while performing the eleventh program loop PL11 on the selected memory cells. Therefore, a verification operation can be performed with the first verification voltage Vvfy1 to verify whether the MSB page data is backed up in the backup block.

[0161] In one embodiment, when the twelfth program loop PL12 is performed on the selected memory cells, a program pulse application operation in which the second program pulse PULSE2 is applied to the selected word line may be performed. Thereafter, a verification operation may be performed with the first verification voltage Vvfy1 to verify whether the memory cells whose target program states are the first program state P1 are programmed.

[0162] In one embodiment, when the thirteenth program loop PL13 is performed on the selected memory cells, a program pulse application operation in which a third program pulse PULSE3 is applied to the selected word line may be performed. Unlike the twelfth program loop PL12, in the thirteenth program loop PL13, a verification operation may be performed using the first verification voltage Vvfy1 and the second verification voltage Vvfy2 to verify whether the memory cells whose target program states are the first program state P1 and the second program state P2 are programmed.

[0163] Further, refer to Figure 7 and Figure 8, the CSB page data among the LSB page data, CSB page data, and MSB page data programmed in the selected memory cells can be programmed in the backup block using the SLC method while performing the thirteenth program loop PL13 on the selected memory cells. Therefore, a verification operation can be performed using the second verification voltage Vvfy2 to verify whether the CSB page data is backed up in the backup block.

[0164] In one embodiment, when the fourteenth program loop PL14 is performed on the selected memory cells, a program pulse application operation in which the fourth program pulse PULSE4 is applied to the selected word line may be performed. Thereafter, a verification operation may be performed using the first verification voltage Vvfy1 and the second verification voltage Vvfy2 to verify whether the memory cells whose target program states are the first program state P1 and the second program state P2 are programmed.

[0165] In one embodiment, when the fifteenth program loop PL15 is performed on the selected memory cells, a program pulse application operation in which a fifth program pulse PULSE5 is applied to the selected word line may be performed. Unlike the fourteenth program loop PL14, in the fifteenth program loop PL15, a verification operation may be performed with the first to third verification voltages Vvfy1 to Vvfy3 to verify whether the memory cells whose target program states are the first to third program states P1 to P3 are programmed.

[0166] Further, refer to Figure 7 and Figure 8 , the LSB page data among the LSB page data, CSB page data, and MSB page data programmed in the selected memory cells can be programmed in the backup block using the SLC method while performing the fifteenth program loop PL15 on the selected memory cells. Therefore, a verification operation can be performed using the third verification voltage Vvfy3 to verify whether the LSB page data is backed up in the backup block.

[0167] Through the above verification method, Figure 2 The memory device 100 can verify whether the selected memory cells are programmed to the target program state. In addition, in the eleventh program loop PL11, the thirteenth program loop PL13, and the fifteenth program loop PL15, it can be verified whether the MSB page data, the CSB page data, and the LSB page data are respectively programmed in the backup block.

[0168] Thereafter, when the sixteenth program loop PL16 is performed on the selected memory cell, a verification operation may be performed with the second verification voltage Vvfy2 and the third verification voltage Vvfy3; when the seventeenth program loop PL17 is performed on the selected memory cell, a verification operation may be performed with the second verification voltage Vvfy2 to the fourth verification voltage Vvfy4; when the eighteenth program loop PL18 is performed on the selected memory cell, a verification operation may be performed with the third verification voltage Vvfy3 and the fourth verification voltage Vvfy4; when the nineteenth program loop PL19 is performed on the selected memory cell, a verification operation may be performed with the third verification voltage Vvfy3 to the fifth verification voltage Vvfy5; When the twentieth programming loop PL20 is performed on the selected memory cell, the verification operation can be performed with the fourth verification voltage Vvfy4 and the fifth verification voltage Vvfy5; when the twenty-first programming loop PL21 is performed on the selected memory cell, the verification operation can be performed with the fourth verification voltage Vvfy4 to the sixth verification voltage Vvfy6; when the twenty-second programming loop PL22 is performed on the selected memory cell, the verification operation can be performed with the fifth verification voltage Vvfy5 and the sixth verification voltage Vvfy6; when the twenty-third programming loop PL23 is performed on the selected memory cell, the verification operation can be performed with the fifth verification voltage Vvfy5 to the seventh verification voltage Vvfy7.

[0169] In addition, when each programming loop of the twenty-fourth programming loop PL24 and the twenty-fifth programming loop PL25 is performed on the selected memory cell, the verification operation can be performed with the sixth verification voltage Vvfy6 and the seventh verification voltage Vvfy7; and when each programming loop of the twenty-sixth programming loop PL26 and the twenty-seventh programming loop PL27 is performed on the selected memory cell, the verification operation can be performed with the seventh verification voltage Vvfy7.

[0170] Figure 10 The diagram shows the respective Figure 9 Programming loop of the verify operation.

[0171] refer to Figure 9 and Figure 10 , Figure 10 Pictured Figure 9 Some of the eleventh to twenty-seventh programming loops PL11 to PL27 may include a program pulse applying operation of applying a program pulse to a selected word line and a verification operation. The program pulse applying operation may be an operation of applying a program voltage to the selected word line, and the verification operation may be an operation of applying a verification voltage to the selected word line.

[0172] In one embodiment, an eleventh program loop PL11 may be performed to program selected memory cells. The eleventh program loop PL11 may include a program pulse application operation of applying an eleventh program voltage Vpgm11 to a selected word line and a verification operation of applying a first verification voltage Vvfy1.

[0173] refer to Figure 7 and Figure 8 , the MSB page data among the LSB page data, CSB page data, and MSB page data programmed in the selected memory cells may be programmed in the backup block in the SLC method while performing the eleventh program loop PL11 on the selected memory cells.

[0174] Therefore, in order to verify whether the memory cells whose target program states are the first program state P1 among the selected memory cells in the eleventh program loop PL11 are programmed, a verification operation may be performed with the first verification voltage Vvfy1. In addition, in order to verify whether the MSB page data is programmed in the backup block, a verification operation may be performed with the first verification voltage Vvfy1.

[0175] In one embodiment, a twelfth programming loop PL12 may be performed to program selected memory cells. The twelfth programming loop PL12 may include a program pulse application operation of applying a twelfth programming voltage Vpgm12 to a selected word line and a verification operation of applying a first verification voltage Vvfy1. The twelfth programming voltage Vpgm12 may be a voltage whose level is higher than that of the eleventh programming voltage Vpgm11 by a step voltage. Therefore, in order to verify whether the memory cells whose target program state is the first program state P1 among the selected memory cells are programmed after applying a program pulse in the twelfth programming loop PL12, a verification operation may be performed using the first verification voltage Vvfy1.

[0176] In one embodiment, a thirteenth program loop PL13 may be performed to program selected memory cells. The thirteenth program loop PL13 may include a program pulse application operation of applying a thirteenth program voltage Vpgm13 to a selected word line and a verification operation of applying first and second verification voltages Vvfy1 and Vvfy2.

[0177] refer to Figure 7 and Figure 8 , the CSB page data among the LSB page data, the CSB page data, and the MSB page data programmed in the selected memory cells may be programmed in the backup block in the SLC method while performing the thirteenth program loop PL13 on the selected memory cells.

[0178] Therefore, in order to verify whether the memory cells whose target program states are the first program state P1 and the second program state P2 among the selected memory cells in the thirteenth program loop PL13 are programmed, a verification operation may be performed using the first verification voltage Vvfy1 and the second verification voltage Vvfy2. In addition, in order to verify whether the CSB page data is programmed in the backup block, a verification operation may be performed using the second verification voltage Vvfy2.

[0179] In one embodiment, a fourteenth program loop PL14 may be performed to program selected memory cells. The fourteenth program loop PL14 may include a program pulse application operation of applying a fourteenth program voltage Vpgm14 to a selected word line and a verification operation of applying a first verification voltage Vvfy1 and a second verification voltage Vvfy2. The fourteenth program voltage Vpgm14 may be a voltage whose level is higher than the level of the thirteenth program voltage Vpgm13 by a step voltage. Therefore, in order to verify whether the memory cells whose target program states are the first program state P1 and the second program state P2 among the selected memory cells after applying a program pulse in the fourteenth program loop PL14 are programmed, a verification operation may be performed using the first verification voltage Vvfy1 and the second verification voltage Vvfy2.

[0180] In one embodiment, a fifteenth program loop PL15 may be performed to program selected memory cells. The fifteenth program loop PL15 may include a program pulse application operation of applying a fifteenth program voltage Vpgm15 to a selected word line and a verification operation of applying first to third verification voltages Vvfy1 to Vvfy3.

[0181] refer to Figure 7 and Figure 8 , LSB page data among LSB page data, CSB page data, and MSB page data programmed in selected memory cells may be programmed in the backup block in an SLC method while performing a fifteenth program loop PL15 on the selected memory cells.

[0182] Therefore, in order to verify whether the memory cells whose target program states are the first program state P1 to the third program state P3 among the selected memory cells in the fifteenth programming loop PL15 are programmed, a verification operation may be performed using the first verification voltage Vvfy1 to the third verification voltage Vvfy3. In addition, in order to verify whether the LSB page data is programmed in the backup block, a verification operation may be performed using the third verification voltage Vvfy3.

[0183] In one embodiment, a plurality of program loops may be performed after the fifteenth program loop PL15 to program selected memory cells.

[0184] Figure 11 is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0185] refer to Figure 11 In step S1101, the memory device may receive a program command from a memory controller. In one embodiment, after step S1103, the memory device may program the program data received along with the program command into the selected memory cells in response to the program command. At step S1105, the memory device may perform multiple program loops to program the program data into the selected memory cells. Each of the multiple program loops may include a program pulse application operation and a verification operation.

[0186] In step S1103, the memory device may erase a memory block including selected memory cells for which a plurality of programming cycles are to be performed. In this case, the memory block for which the erase operation is performed may include a primary sub-block and a backup block connected to the primary sub-block via the same word line. The primary sub-block may be a sub-block including memory cells in which program data is to be programmed, and the backup block may be a sub-block including memory cells in which program data is to be backed up. That is, before performing a plurality of programming cycles, the memory device may erase the memory block.

[0187] In another embodiment, step S1103 may be performed after step S1107. That is, after all selected memory cells are programmed to the target program state, the memory block may be erased. However, when step S1103 is performed after step S1107, it is necessary not to erase the data programmed in the selected memory cells, and therefore only the backup blocks among the sub-blocks included in the memory block may be erased.

[0188] In step S1105, the memory device may start a programming loop. The programming loop may include a program pulse application operation and a verification operation. Here, the program pulse application operation may be an operation of applying a program voltage to a selected word line connected to a selected memory cell, and the verification operation may be an operation of verifying whether the selected memory cell is programmed to a target program state by applying a verification voltage to the selected word line.

[0189] In step S1107, the memory device may back up data in backup blocks in a specific program loop. The number of backup blocks and the number of specific program loops may be determined according to the number of data programmed in the selected memory cells.

[0190] For example, when the memory device performs a program operation in the MLC method, since the data programmed in the selected memory cells are LSB page data and MSB page data, the number of backup blocks and the number of specific program loops may be "2." When the memory device performs a program operation in the TLC method, since the data programmed in the selected memory cells are LSB page data, CSB page data, and MSB page data, the number of backup blocks and the number of specific program loops may be "3."

[0191] In one embodiment, when performing a specific program loop, the memory device may be sequentially programmed from MSB page data in an SLC method.

[0192] For example, when the memory device performs a programming operation in the MLC method, after the MSB page data is programmed in a specific programming loop, the LSB page data can be programmed. When the memory device performs a programming operation in the TLC method, after the MSB page data is programmed in a specific programming loop, the CSB page data and the LSB page data can be sequentially programmed.

[0193] Figure 12 is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0194] refer to Figure 12 In step S1201, the memory device may determine whether any one of the preset programming loops has been reached. That is, the memory device may determine whether the order in which the preset programming loops are executed is the order in which the preset programming loops are executed among the multiple programming loops executed when programming the selected memory cell. As used herein, the word "preset" with respect to a parameter, such as one or more preset programming loops and one or more preset backup read voltages, means that the value for the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value for the parameter is determined before the process or algorithm begins. In other embodiments, the value for the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0195] When any one of the preset program loops is not reached (No), the operation may proceed to step S1203 , and when any one of the preset program loops is reached (Yes), the operation may proceed to step S1205 .

[0196] In one embodiment, when any of the preset program loops is not reached (No), the memory device may perform the next program loop in step S1203. At this time, since the preset program loop is not reached, only the program operation on the selected memory cells may be performed without performing a backup operation on the program data.

[0197] After executing the next program loop, the memory device may proceed to step S1201 again to determine whether any one of the preset program loops is reached.

[0198] In one embodiment, when any one of the preset program loops is reached (Yes), the memory device may perform a program loop and backup operation in step S1205. That is, due to reaching any one of the preset program loops, the memory device may back up the program data in the backup block while programming the program data in the selected memory cells.

[0199] At this time, when the memory device performs a program operation in the TLC method, the backed-up data may be any one of LSB page data, CSB page data, and MSB page data.

[0200] In step S1207, the memory device may determine whether the program loop executed in step S1205 is the last program loop among the plurality of program loops. When the program loop executed in step S1205 is not the last program loop among the plurality of program loops (No), the operation may proceed to step S1203 again, and the memory device may execute the next program loop.

[0201] Figure 13 It's a picture Figure 1 FIG. 1 is a diagram of another embodiment of a memory controller.

[0202] The memory controller 1000 is connected to a host and a memory device. The memory controller 1000 is configured to access the memory device in response to a request from the host. For example, the memory controller 1000 is configured to control write, read, erase, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0203] refer to Figure 13 , the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction circuit (ECC) 1030 , a host interface 1040 , a buffer controller (or buffer control circuit) 1050 , a memory interface 1060 , and a bus 1070 .

[0204] The bus 1070 may be configured to provide a channel between components of the memory controller 1000 .

[0205] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host through the host interface 1040 and with a memory device through the memory interface 1060. In addition, the processor 1010 may communicate with the memory buffer 1020 through the buffer controller 1050. The processor 1010 may use the memory buffer 1020 to control the operation of the memory device as an operating memory, a cache memory, or a buffer memory.

[0206] The processor 1010 can perform the functions of the Flash Translation Layer (FTL). The processor 1010 can convert the LBA provided by the host into a PBA through the FTL. The FTL can receive the LBA by using a mapping table and convert the LBA into a PBA. The address mapping method of the Flash Translation Layer includes multiple mapping methods based on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0207] The processor 1010 is configured to randomize data received from the host. For example, the processor 1010 may randomize the data received from the host using a randomization seed. The randomized data is provided to the memory device as data to be stored and is programmed into the memory cell array.

[0208] The processor 1010 may perform randomization and de-randomization through driving software or firmware.

[0209] The memory buffer 1020 may be used as an operating memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0210] The error correction circuit 1030 may perform error correction. The error correction circuit 1030 may perform error correction encoding (ECC encoding) based on data to be written to the memory device via the memory interface 1060. The error correction encoded data may be transmitted to the memory device via the memory interface 1060. The error correction circuit 1030 may perform error correction decoding (ECC decoding) on the data received from the memory device via the memory interface 1060. For example, the error correction circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0211] The host interface 1040 is configured to communicate with an external host under the control of the processor 1010. The host interface 1040 may be configured to perform communication using at least one of various communication methods, such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI Express (PCIe), a non-volatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load-reduced DIMM (LRDIMM).

[0212] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010 .

[0213] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 may transfer commands, addresses, and data with the memory device through a channel.

[0214] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050 .

[0215] For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a nonvolatile memory device (e.g., a read-only memory) provided inside the memory controller 1000. As another example, the processor 1010 may load code from a memory device through the memory interface 1060.

[0216] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus can be separated from each other and do not interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer controller 1050, the error correction circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1202, and the memory interface 1060.

[0217] Figure 14 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0218] refer to Figure 14 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0219] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 is configured to control the read, write, erase, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory device 2200 can be connected to the host. Figure 1 Description Figure 1 The memory device 100 is implemented identically.

[0220] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0221] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device through at least one of various communication standards, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the various communication standards mentioned above.

[0222] For example, the memory device 2200 may be implemented as various nonvolatile memory elements such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0223] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Storage (UFS).

[0224] In one embodiment, the memory device 2200 may perform a plurality of program loops to program program data in selected memory cells. At this time, the memory device 2200 may perform a backup operation together in a specific program loop among the plurality of program loops.

[0225] For example, the memory device 2200 may preset a program loop to be performed together with a backup operation among a plurality of program loops. Thereafter, when the memory device 2200 performs the preset program loop, some program data may be programmed in the backup block while programming the selected memory cells.

[0226] For example, assuming that the memory device 2200 programs selected memory cells using a TLC method, the program data may include LSB page data, CSB page data, and MSB page data. Therefore, when the memory device 2200 performs a preset program loop, while programming the selected memory cells, any one of the LSB page data, CSB page data, and MSB page data may be backed up in a backup block. In this case, the LSB page data, CSB page data, and MSB page data may be programmed in different backup blocks.

[0227] Thereafter, when the memory device 2200 performs a preset program loop again, some program data may be programmed in the backup block while programming the selected memory cells.

[0228] In one embodiment, when a program failure occurs after all program data is programmed in the backup block, the memory device 2200 can recover the program data by reading the data programmed in the backup block. In this case, the memory device 2200 can preset a read voltage for reading the data programmed in the backup block to a level different from a level of a read voltage for distinguishing program states.

[0229] As a result, since the memory device 2200 performs the backup operation together with a specific program loop, a separate time for backing up program data is not consumed, and thus the time consumed by the program operation can be shortened.

[0230] Figure 15 is a block diagram illustrating, for example, a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0231] refer to Figure 15 , an SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 via a signal connector 3001 and receives power PWR via a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0232] In one embodiment, the SSD controller 3210 may perform a reference Figure 1 Described Figure 1 The functions of the memory controller 200 are as follows.

[0233] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0234] The auxiliary power supply device 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply device 3230 can receive power PWR from the host 3100 and charge the power supply. When the power supply from the host 3100 is not smooth, the auxiliary power supply device 3230 can provide power to the SSD 3200. For example, the auxiliary power supply device 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply device 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0235] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0236] In one embodiment, the SSD 3200 may perform a plurality of program loops to program program data in selected memory cells among the memory cells included in each of the plurality of flash memories 3221 to 322n. At this time, the SSD 3200 may perform a backup operation together in a specific program loop among the plurality of program loops.

[0237] For example, the SSD 3200 may preset a program loop to be performed together with a backup operation among a plurality of program loops. Thereafter, when the SSD 3200 performs the preset program loop, some program data may be programmed in the backup block while programming the selected memory cells.

[0238] For example, assuming that the SSD 3200 programs selected memory cells using the TLC method, the program data may include LSB page data, CSB page data, and MSB page data. Therefore, when the SSD 3200 performs a preset program loop, while programming the selected memory cells, any one of the LSB page data, CSB page data, and MSB page data may be backed up in a backup block. In this case, the LSB page data, CSB page data, and MSB page data may be programmed in different backup blocks.

[0239] Thereafter, when the SSD 3200 performs a preset program loop again, some program data may be programmed in the backup block while programming the selected memory cells.

[0240] In one embodiment, when a program failure occurs after all program data has been programmed into the backup block, the SSD 3200 can recover the program data by reading the data programmed into the backup block. In this case, the SSD 3200 can preset a read voltage for reading the data programmed into the backup block to a level different from a level of a read voltage for distinguishing program states.

[0241] As a result, since the SSD 3200 performs the backup operation together with a specific program loop, a separate time for backing up program data is not consumed, and thus the time consumed by the program operation can be shortened.

[0242] Figure 16 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0243] refer to Figure 16 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0244] The application processor 4100 may drive components, an operating system (OS), user programs, and the like included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, and the like that control the components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0245] The memory module 4200 can operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on a package-on-package (POP) and provided as one semiconductor package.

[0246] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and WI-FI. For example, the network module 4300 can be included in the application processor 4100.

[0247] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented as a non-volatile semiconductor memory element, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the storage module 4400 can be provided as a removable storage device (removable drive), such as a memory card, and an external drive of the user system 4000.

[0248] For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be associated with a reference Figure 2 and Figure 3 The memory module 4400 can be used in conjunction with the memory device described in the reference Figure 1 The described storage devices 50 operate identically or similarly.

[0249] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0250] In one embodiment, the memory module 4400 may perform a plurality of program loops to program program data in the selected memory cells. At this time, the memory module 4400 may perform a backup operation together in a specific program loop among the plurality of program loops.

[0251] For example, the memory module 4400 may preset a program loop to be performed together with the backup operation among a plurality of program loops. Thereafter, when the memory module 4400 performs the preset program loop, some program data may be programmed in the backup block while programming the selected memory cells.

[0252] For example, assuming that the memory module 4400 programs selected memory cells using the TLC method, the program data may include LSB page data, CSB page data, and MSB page data. Therefore, when the memory module 4400 performs a preset program loop, while programming the selected memory cells, any one of the LSB page data, CSB page data, and MSB page data may be backed up in a backup block. In this case, the LSB page data, CSB page data, and MSB page data may be programmed in different backup blocks.

[0253] Thereafter, when the memory module 4400 performs a preset program loop again, some program data may be programmed in the backup block while programming the selected memory cells.

[0254] In one embodiment, when a program failure occurs after all program data is programmed in the backup block, the memory module 4400 can recover the program data by reading the data programmed in the backup block. In this case, the memory module 4400 can preset a read voltage for reading the data programmed in the backup block to a level different from a level of a read voltage for distinguishing program states.

[0255] As a result, since the memory module 4400 performs the backup operation together with the specific program loop, a separate time for backing up program data is not consumed, and thus the time consumed by the program operation can be shortened.

Claims

1. A memory device comprising: a memory block including a main sub-block and a backup block, the main sub-block including selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, program data being programmed in the selected memory cells, and page data included in the program data being backed up in the backup block; a peripheral circuit configured to perform a plurality of program loops to program the program data in the selected memory cells; and A control logic is configured to control the peripheral circuit to back up any one of the page data while programming the selected memory cells in a preset program loop among the plurality of program loops. 2 . The memory device of claim 1 , wherein when the selected memory cell is programmed in a three-level cell method, the page data includes least significant bit page data, center significant bit page data, and most significant bit page data. 3 . The memory device of claim 1 , wherein before executing the plurality of program loops, the control logic controls to erase the memory block. 4 . The memory device according to claim 1 , wherein after the plurality of program loops are completed, the control logic controls to erase the backup block.

5. The memory device of claim 1 , wherein the control logic sets a program mode for programming the program data based on whether the preset program loop is reached, and The program mode is any one of a normal mode for performing the plurality of program loops on the selected memory cells and a backup mode for performing a backup operation of backing up any one of the page data while performing the plurality of program loops on the selected memory cells. 6 . The memory device of claim 5 , wherein the control logic sets the program mode to the backup mode in the preset program loop.

7. The memory device according to claim 6, wherein in the backup mode, when a programming voltage is applied to a selected word line to which the selected memory cell is connected, the control logic controls to program any one of the page data into a memory cell connected to the selected word line among the memory cells of the backup block. 8 . The memory device of claim 7 , wherein the control logic controls to program any one of the page data using a single level cell method.

9. The memory device according to claim 7, wherein the control logic controls voltage levels of bit lines respectively connected to memory cells connected to the selected word line among the memory cells of the backup block so that any one of the page data is programmed to the backup block. 10 . The memory device of claim 1 , wherein when programming fails after executing the plurality of program loops, the control logic recovers the program data by reading the page data backed up in the backup block. 11 . The memory device of claim 10 , wherein the control logic reads a preset backup read voltage to read page data.

12. A memory device comprising: a memory block including a main sub-block and a backup block, the main sub-block including selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, program data being programmed in the selected memory cells, and page data included in the program data being backed up in the backup block; a peripheral circuit configured to perform a plurality of program loops to program the program data in the selected memory cells; an erase controller configured to control an erase operation on the backup block before the plurality of program loops are executed or after all the plurality of program loops are executed; a program loop counter configured to count a number of times the plurality of program loops are executed; a mode setting unit configured to set a program mode for programming the program data based on the number of the program loops counted by the program loop counter; and A backup execution unit is configured to control the peripheral circuit to back up any one of the page data while programming the selected memory cells in a preset program loop among the plurality of program loops.

13. The memory device according to claim 12 , wherein the program mode is any one of: a normal mode for executing the plurality of program loops on the selected memory cells, and a backup mode for performing a backup operation of backing up any one of the page data while executing the plurality of program loops on the selected memory cells, and The mode setting part sets the programming mode to the backup mode in the preset programming cycle.

14. The memory device according to claim 13 , wherein in the backup mode, when a program voltage is applied to a selected word line to which the selected memory cell is connected, the backup execution unit controls to program any one of the page data into a memory cell connected to the selected word line among the memory cells of the backup block.

15. The memory device according to claim 14, wherein the backup execution unit controls voltage levels of bit lines respectively connected to memory cells connected to the selected word line among the memory cells of the backup block so that any one of the page data is programmed in the backup block.

16. A method of operating a memory device, the memory device comprising a memory block, the memory block comprising a main sub-block and a backup block, the main sub-block including selected memory cells among a plurality of memory cells respectively connected to a plurality of word lines, program data being programmed in the selected memory cells, and page data included in the program data being backed up in the backup block, the method comprising: performing a plurality of program loops to program the program data in the selected memory cells; as well as When a preset program loop among the plurality of program loops is performed, any one of the page data is backed up while the selected memory cells are being programmed.

17. The method according to claim 16, wherein in backup, when a program voltage is applied to a selected word line to which the selected memory cells are connected, one page data of the page data is programmed in a memory cell connected to the selected word line among the memory cells of the backup block. 18 . The method according to claim 16 , wherein in the backup, any one of the page data is programmed in a single level cell method.

19. The method according to claim 17, wherein in backup, voltage levels of bit lines respectively connected to memory cells connected to the selected word line among the memory cells of the backup block are set so that any one of the page data is programmed in the backup block. 20 . The method of claim 16 , wherein when programming fails after performing the plurality of program loops, the program data is recovered by reading the page data backed up in the backup block using a preset backup read voltage.

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